TWI454910B - Method of operating a memory device, method of reading a digital memory, and memory device thereof - Google Patents

Description

Method for operating memory device, method for reading digital memory and application thereof, and memory device thereof

This invention relates to a flash memory, and more particularly to the reading of a flash memory.

Unit cell serial and multi-bit serial flash memory have become commonplace due to fewer pin counts and simple interfaces. The simplest interface is a Serial Peripheral Interface (SPI). A meta-listing peripheral interface protocol includes a user-supplied 8-bit command, address bytes, and optional dummy bytes for the serial port. The peripheral interface flash memory device, and the serial peripheral interface flash memory device will respond to the user by returning the data. A single 8-bit instruction can identify a read, erase/program, or another suitable operation. For high-performance system applications that require fast read performance, for example, a dual serial peripheral interface (SPI-Dual), a four-string peripheral interface (SPI-Quad), and a Quad Peripheral Interface (QPI) have been developed. The multi-bit serial interface. In the four-column peripheral interface, 8-bit instructions are provided in tandem in a one-bit manner, but all subsequent fields (such as address, selective virtual byte, and data) are in 4 bits. Yuan (4) is completed on a serial basis to improve the reading amount. In the quaternary peripheral interface, all fields (such as 8-bit instructions, addresses, selective virtual bytes, and data) are all done in 4-bit serials. In this way, the quaternary peripheral interface provides 8-bit instructions in two clock cycles, while the four-string peripheral interface requires eight clock cycles. Compared to the serial interface and the four-serial peripheral interface, the quaternary peripheral interface achieves better read performance by reducing the number of clock cycles required to provide read commands. Various multi-bit serial flash interface protocols are described, for example, in U.S. Patent No. 7,558,900.

In order to minimize the delay, different read instructions will be used for different address boundaries, and these different instructions use different numbers of virtual bytes (including mode bytes) depending on the address boundary; see Figure 1 and figure 2. For example, in a four-column peripheral interface, an 8-bit instruction is provided to the flash memory device according to a 1-bit serial interface (eg, by I/O0), but according to a 4-bit (four) interface (eg, borrowing Subsequent interface operations are performed by I/O0-I/O3 (not shown). The command and address will be provided to the serial peripheral interface flash memory device and latched at the "rising edge" of the clock, and the serial peripheral interface flash memory device will provide output at the "falling edge" of the clock. data.

Figure 1 illustrates a four-column peripheral interface instruction called EBh_SPI (or Fast Read Quad Input/Output (Quad I/O)) because it does not impose address restrictions because it falsely locates tuple boundaries. This instruction includes 6 virtual clocks. 2 illustrates a four-string peripheral interface instruction called E7h_SPI (or block read four input/output) that defines the address as a block boundary (A0=0). Since the address boundary restrictions are stated in the instruction, this only needs to include 4 dummy bytes. Therefore, compared to the EBh_SPI instruction, the E7h_SPI instruction provides a higher system read performance after measuring the reduced delay.

Various modes of operation, including a serial peripheral interface supporting multi-bit serial input and output, a four-column peripheral interface, and a fully enhanced tandem peripheral interface mode are described in U.S. Patent No. 7,558,900.

However, some applications require higher system read performance.

The present invention provides a method of operating a memory device, wherein the memory device includes a flash memory cell array for providing an application for reading data via a read command, wherein the application has a bit boundary. The method includes: receiving a read instruction including a start address; configuring a memory device for an address boundary of the application; performing a sequence of sensing operations on the flash memory cell array via the read command (sense operations) ). The sensing operation of the sequence includes: performing a first sensing of the flash memory cell array to obtain an output first data, the first sensing having the first position of the sequence and occurring at the first internal sensing time (sense time) Providing a first data as an output of the memory device; performing a second sensing of the flash memory cell array to obtain an output second data, the second sensing having the second position of the sequence and occurring at the second internal sensing time; The second material is provided as an output of the memory device. In order to improve the read performance, the first internal sensing time and the second internal sensing time may be changed according to the address boundary of the application and the time budgets of the first sensing and the second sensing.

The present invention provides a method of operating a memory device, wherein the memory device comprises a flash memory cell array. This method is used to provide an application of data via a read command. The application has a first address boundary at a first time and a second address boundary at a second time different from the first time. The method includes receiving a first read instruction including a first start address, configuring a memory device for a first address boundary of the application, and performing a first sequence on the flash memory cell array via the first read command Sensing operation; receiving a second read instruction including a second start address; configuring a memory device for a second address boundary of the application; and performing a second sequence on the flash memory cell array via the second read command Induction operation. The first sequence includes: performing a first sensing of the flash memory cell array to obtain an output first data, the first sensing having a first position of the first sequence and occurring at the first internal sensing time; providing the first data as a memory An output of the device; performing a second sensing of the flash memory cell array to obtain an output second data, the second sensing has a second sequence of the first sequence and occurring at the second internal sensing time; and providing the second data as the memory The output of the device, wherein the first internal sensing time and the second internal sensing time are dependent on a first address boundary of the application and a time budget of the first sensing and the second sensing. The second sequence includes: performing a third sensing of the flash memory cell array to obtain an output third data, the third sensing having the first position of the second sequence and occurring at the third internal sensing time; providing the third data as the memory An output of the device; performing a fourth sensing of the flash memory cell array to obtain a fourth data of the output, a fourth sensing having a second position of the second sequence and occurring at the fourth internal sensing time; and providing the fourth data as the memory The output of the device, wherein the third internal sensing time and the fourth internal sensing time are dependent on a second address boundary of the application and a time budget of the third sensing and the fourth sensing.

The present invention provides a method of reading a digital memory in an application, comprising: operating a memory device at a selected one of a plurality of possible operating frequencies of the memory device, the memory device having a plurality of sensing operations The flash memory cell array to be sensed has more than one possible internal sensing time of these sensing operations, which depends on multiple sensing sequences of different address boundary conditions; the configuration instruction is provided according to the selected operating frequency to have read virtual a flash memory device having a parameter number parameter; providing a configuration command to the flash memory device to set an address boundary parameter of the application; providing a read command having a start address to the memory device; and utilizing time The budget receives data from the memory device, the time budget being by reading the virtual byte number parameter and one of the possible internal sensing times corresponding to one of the sensing sequences of the address boundary conditions of the address boundary parameter or Multiple to be determined.

The present invention provides a memory device comprising: a flash memory cell array; an address boundary determination circuit for determining an address boundary from a plurality of different potential address boundaries of a start address of a read command; Determining a circuit circuit coupled to the address boundary determination circuit for determining an internal sensing time sequence corresponding to one of a plurality of different sense sequences of the flash memory cell array, respectively, according to different potential address boundaries; Sensing amplifiers coupled to the internal sensing time determining circuit and the flash memory cell array for performing a plurality of sequential sensing operations on the flash memory cell array according to the plurality of internal sensing times for obtaining from the flash memory cell array Data; and command and control logic coupled to the sense amplifier for providing the obtained data by the output of the memory device.

The present invention provides a memory device comprising: a flash memory cell array; instruction and control logic for determining an address boundary of a start address of a read command, the command and control logic comprising a multiplexer, the multiplexer Inducing an internal sensing time of the flash memory cell array in a sequence of sensing, determining an internal sensing time for at least two sensing sequences based on individual locations of the sensing of the address boundary and the sensing sequence; and a plurality of inductive amplifiers, Coupled with the multiplexer and the flash memory cell array for sensing the flash memory cell array for data acquisition, and the command and control logic is further coupled to the sense amplifier to provide the obtained data by the output of the memory device.

A flash memory device operable under a unit or multi-bit serial protocol can be configured for one or more address boundaries of an application to enable the same address boundary configurable read instruction, regardless of What is the boundary of one or more addresses of the application. The least significant bits (LSBs) of the start address of the read instruction, such as the address boundary configurable (ABC), or by the address boundary parameter that can be specified in the previous configuration command, The flash memory device can be automatically configured for the address boundary of the application. Depending on the address boundary configuration, the internal sensing time of the flash memory device can be optimized, thereby improving the performance of the flash memory device for a memory device that uses a fixed internal sensing time to sense the memory. Depending on the address boundary of the application and the desired flash memory device operating frequency, the user can specify or configure the number of virtual bytes of the read command in advance. In most applications, the flash memory device operates at a fixed frequency and the address boundaries are fixed to a byte, a block, or a double word, so the user only needs to specify or configure the number of virtual bytes at a time. . However, for those applications where the address boundary changes or the operating frequency of the flash memory device changes, the number of virtual byte groups can also be changed, so the user can specify or configure the address boundary configurable (ABC) read command in advance. It may have to be specified or configured again. Therefore, the number of dummy bytes of the read command can be minimized and the internal sensing time can be optimized to improve the read performance of the flash memory device, so as to allow higher flash memory device operation for the address boundary of the application. frequency.

The term "flash memory device" as used in this patent application means any type of memory device including any memory structure such as a reverse or gate (NOR), a NAND, or any combination thereof. Any type of flash memory cell, either alone or in combination with any other type of memory cell in any other type of memory structure. The term "address boundary configurable (ABC) read instruction" means a read instruction that is not restricted by any particular address boundary condition, so that the flash memory device can be configured for different address boundaries and does not have to Change the read command.

The term "internal sensing time" refers to the time required by the flash memory device to sense a group of flash bits. The internal sensing time can be expressed in a variety of clock cycles T _cc . In many types of flash memory devices, some flash bits (e.g., 32 bits) are simultaneously sensed in groups to achieve better read performance. The flash memory device is capable of dynamically adjusting its internal sensing time based on the address boundary of the address provided by the address boundary configurable (ABC) read command and the sensed position of the sensing sequence.

3 is an example of how to operate a flash memory device with configurable internal sensing time to complete an address boundary configurable (ABC) read operation 20, and FIG. 4 is how such a flash memory device processes bits. An example of an address boundary configurable (ABC) read instruction 30. In implementing a particular application, the user can select the operating frequency of the flash memory device from the range of frequencies supported by the flash memory device (block 21) and can also identify the type of address boundary used by the application (block twenty two). Depending on the operating frequency and the type of address boundary, the user can determine the minimum number of virtual bytes required by the address boundary configurable (ABC) read instruction (block 23). The technique for establishing the number of virtual bytes is to issue a configuration command to the flash memory device before receiving the address boundary configurable (ABC) read command. When processed in the flash memory device in accordance with the procedure illustrated in Figure 4, an address boundary configurable (ABC) read command can then be issued (block 24). The data required by the (BBC) configurable (ABC) instruction is received (block 25) and can be read as needed (block 26-yes). If the application requires a different address boundary, then a new address boundary can be specified (block 27-y, block 22). If the user wants to operate the flash memory device at a different frequency, the frequency can be specified (block 28-y, block 21). When the read operation ends (block 26 - no, block 27 - no, and block 28 - no), other operations can continue to be processed (block 29).

Referring to FIG. 4, when the flash memory device receives an address boundary configurable (ABC) read command, the flash memory device will check the address field of the address boundary configurable (ABC) read command. The type of address boundary is identified (block 31), from which the internal sensing time that best fits the address boundary can be determined (block 32). On the other hand, an address boundary can be specified in the configuration command (not shown) issued earlier than the address boundary configurable (ABC) read command to the flash memory device, thereby determining the optimal internal sensing. Time (block 32). The flash bit block is then sensed (block 33) and the data is provided (block 34). Although FIG. 4 illustrates the provision of data after an induction and prior to the next sensing, the data may also be provided during the next sensing. Subsequent sensing operations occur (block 35-no, block 32, block 33, block 34) until the end of the reading (block 35-Yes). Although the address boundary is determined by the address of the address boundary configurable (ABC) read command (block 31) and the entire read operation period is maintained, the internal sensing time can be changed according to the sensed position of the sense sequence. . The internal sensing time may be the same during the entire read operation or during a partial read operation, in which case the act of determining the internal sensing time will not be performed (block 32). Other operations can continue to be processed (block 36).

FIG. 5 illustrates an example of an address boundary configurable (ABC) read command EBh_QPI based on an address boundary and an "internal sensing time" configuration of the sensing sequence. The internal sensing time can be configured by the configuration instruction or the address boundary of the starting address (eg, byte, block, double word), which can be read by the address boundary configurable (ABC) The least significant bit of the starting address is identified. The read command EBh_QPI can cause different internal sensing times to improve read performance. One suitable way to determine the internal sensing time based on the least significant bit of the starting address is to compute using appropriate logic circuitry, where the calculation is based on the least significant bit of the address and the sensing sequence. Another suitable way to determine the internal sensing time is a look-up table with multiple stored values (ie, multiple storage sensing times), where the least significant bit and the sensing sequence are selected from the lookup table based on the address. The appropriate value (ie the appropriate induction time). Another suitable way to determine the internal sensing time is by the multiplexer selecting from among the predetermined and internally available internal sensing times that can be selected based on the least significant bit of the address and the sensing sequence.

Although the first and subsequent internal sensing times may be the same, the subsequent sensing time may have to be greater than the first sensing time under actual considerations. This is because, in effect, the flash memory device encounters more noise during subsequent sensing operations due to output switching. Conversely, the flash memory device does not encounter such noise during the first sensing period because it does not output a switch. Because of this noise and other design considerations during subsequent sensing, it is preferable to make the subsequent sensing time greater than the first sensing time; see also Figure 7.

Various time budgets are evident in Figure 5. The time budget can take into account the first sense, the second sense, and the spacing therebetween. The ends of the first sense and the second sense occur, respectively, after approximately 8/4/8 clock cycles have elapsed after 8 virtual clocks have been sent to the address boundary 40/50/60. This is because the data of the second inductive group flash memory cell (32 bits) is output starting at 2/4/8 clock cycles after 8 virtual clocks have been issued. Due to this consideration, the budget of the "combined first sensing time and second sensing time" (as shown in FIG. 5) is 9.5T _cc /11.5T _cc /15.5T _cc , respectively, where T _cc is the clock cycle. This budget also includes the interval between the first sensing time and the second sensing time (no sense time). In general, the time budget can be regarded as the "number of virtual clocks" plus "the number of clocks required to output the first sensing data" minus half the clock. Taking two virtual clocks as an example, this budget will be 3.5T _cc /5.5T _cc /9.5T _cc for the byte/word/double word boundary, respectively. Taking four virtual clocks as an example, this budget will be 5.5T _cc /7.5T _cc /11.5T _cc for the byte/word/double word boundary, respectively. Taking six virtual clocks as an example, this budget will be 7.5T _cc /9.5T _cc /13.5T _cc for the byte/word/double word boundary, respectively. Taking eight virtual clocks as an example, this budget will be 9.5T _cc /11.5T _cc /13.5T _cc for the byte/word/double word boundary (see Figure 5). The above illustrates that different address boundaries have different budgets. In general, the budget for the double-word boundary is greater than the budget for the block boundary, and the budget for the block boundary is greater than the budget for the byte boundary, so that the higher the number of virtual bytes can be enabled for the same number of virtual bytes. The operation of the frequency, or the number of smaller virtual tuples can be used for operations of the same frequency.

Due to various design choices, it is not possible to achieve address-border configurable (ABC) read instruction improvements in all flash memory designs or for all combinations of dummy byte and boundary conditions. Potential. Moreover, the "first internal sensing time and the second internal sensing time" budget is particularly divided into the first internal sensing time and the second internal sensing time based on design choices and other considerations such as noise. As shown in Figure 5 and Figure 7, the budget of 9.5T _cc /11.5T _cc /15.5T _cc is divided into 4.5T _cc /4.5T _cc /6.5T _cc for the first internal sensing time and time split for the second internal sensing time. Into 4.5T _cc /5.5T _cc /6.5T _cc . The first internal sensing time and the second internal sensing time do not accurately reach the above budget because some time (0.5T _{cc /} 1.5T _{cc /} 2.5T _cc ) is allocated to the first internal sensing time and the second internal sensing time. The interval between. The interval will be distributed between any two consecutive senses (eg, between the first sense and the second sense) to provide time for internal address changes, voltage charging, and voltage discharge, and the like. Therefore, this interval allows for a preparation time before the next sensing operation.

Figure 6 shows an example of how to use a multiplexer to determine the appropriate internal sensing time. In this case, the multiplexer is taken as an example, but it can also be designed as other suitable logic circuits and used to generate or select the internal sensing time according to the least significant bit and the sensing sequence of the address. Multiplexer 58 is selected via select logic 59 between six different sensing times X1, Y1, Z1, X2, Y2, and Z2. The least significant bit of the logical evaluation address is selected along with the sensed position of the sense sequence, and an input selection signal is provided to the multiplexer 58 based on the evaluation result to select an appropriate internal sensing time. Therefore, the read performance depends on the start address and the sense sequence.

Referring to Figures 5 and 6, a set of sensing times is as follows. The first internal sensing time can be selected from the sensing time X1 of the byte boundary, the sensing time Y1 of the block boundary, and the sensing time Z1 of the double word boundary. The selection logic 59 generates a first selection signal to the multiplexer 58 according to the least significant bit of the address and the sensed position of the sensing sequence to select the first internal sensing time from the sensing times X1, Y1, and Z1, that is, the first A sensing operation. The selection logic 59 further generates a subsequent selection signal to the multiplexer 58 according to the least significant bit of the address and the sensing sequence to select all subsequent internal sensing times from the sensing times X2, Y2, and Z2, that is, to continue the first All sensing of the sensing operation.

The signal waveform and its associated internal sensing time series as shown in Figure 5 apply to the quaternary peripheral interface. In the quaternary peripheral interface, all interfaces (eg, 8-bit instructions, addresses, selective dummy bytes, and data) are done on a 4-bit basis. In this way, the quaternary peripheral interface can provide 8-bit instructions in two clock cycles, as shown in FIG. When receiving an address boundary configurable (ABC) read command, address, and dummy byte, the flash memory device begins to send output data to the user. As shown, the command and address are latched on the rising edge of the clock, and the flash memory device sends the output data at the falling edge of the clock.

The signal waveform of the internal sensing time and its associated sequence are depicted as a byte boundary condition 40, a block boundary condition 50, and a double word boundary condition 60, respectively. The signal waveform shown contains eight virtual clocks. The first byte data 42 of the sense sequence of the byte boundary condition 40 outputs only two clocks, thereby reducing the time budget available for the first internal sensing time and the second internal sensing time. The reduced budget imposes a limit on the maximum clock frequency of the flash memory device. The first two byte data 52 of the sensing sequence of the block boundary condition 50 outputs four clocks, thereby reducing the time budget available for the first internal sensing time and the second internal sensing time, but the reduced budget is less than the bit. The sensing sequence of the group boundary condition 40. The first four byte data 62 of the sensing sequence of the double word boundary condition 60 outputs eight clocks, which provide a large time budget for the first internal sensing time and the second internal sensing time. During the first sensing operation, when the sensing operation of the flash bit (eg, 4-byte) of the same size group is completed internally, the flash memory is decoded for the byte/word/double word address boundary instance. The body device sends only the last byte, the last two bytes, and all four bytes as outputs. For all address boundaries 40, 50, and 60, the data will be sequentially sensed and then output in a continuous 32-bit (4-byte) group with eight clocks per group. However, the internal sensing time from the byte boundary to the block boundary to the double word boundary is usually gradually increased, so that the double word boundary has the best read performance, followed by the block boundary, and finally the worst read. Take the byte boundary of the performance. This adjustable internal sensing time based on user applications (such as address boundaries) provides different and optimal read performance.

The number of virtual byte groups can be configured to the flash memory device by the user issuing appropriate instructions. Although a virtual byte may be a "don't care" byte (such as input data 1 or invalid 0), the term "dummy Bytes" as used herein may include, for example, mode bits. Auxiliary byte of the group (Mode bytes). When all other conditions are the same, reducing the number of virtual bytes can improve system read performance. The number of virtual bytes can be set using any suitable instruction, and this instruction can be used in particular to set the number of virtual bytes, or can include configuring address boundaries, and setting up, for example, burst read with wrap An additional read parameter for the number of bytes of the wrap length of the instruction. The number of virtual bytes, along with the value of the least significant bit of the address and the sensing sequence, also changes the budget for the first internal sensing time and subsequent internal sensing time. The number of virtual bytes can be configured only once before all read operations of the application, or can be configured any number of times during the application.

7 is a table showing examples of maximum operating frequencies for various address boundaries, number of sensing sequences, and number of virtual clocks. As shown, the number of virtual bytes can have a preset value when powered up, such as 2 virtual bytes, but can be manually configured at any time by issuing appropriate instructions (configured before any read commands are issued) Once, or configured from time to time during the application, it becomes 4, 6, 8, or other number of virtual bytes. The configuration shown in the table of Figure 7 is only an example, and many different variations can be used to achieve a similar degree of optimization. For the sake of explanation, it is assumed that the minimum time requirement for induction of a particular flash memory device of interest is 35 nanoseconds. For this 35 nanosecond demand, the induction time with multiple clock cycles T _cc shown in this table can be converted to the maximum operating frequency. For the sake of simplicity, it is further assumed that the maximum operating frequency is the lower of the first sensing operating frequency and the subsequent sensing operating frequency (indicated by a double asterisk in the table of Figure 7). In fact, guard bands greater than 10 megahertz (MHz) can be added due to noise and other considerations. As shown in the table of Figure 7, the two virtual clocks are suitable for applications of approximately 30 MHz (T _cc = 33 (ns)) regardless of their address boundaries. Four virtual clocks are suitable for byte address boundary applications of approximately 50 MHz (T _cc = 20 (ns)) and are suitable for 80 MHz (T _cc = 12 (ns)) block and double word address boundary application. Six virtual clocks are suitable for byte address boundary applications of 80 megahertz MHz (T _cc = 12 (ns)) and are suitable for block addresses up to approximately 104 MHz (T _cc = 10 (ns)) And double word address boundary application. Eight virtual clocks are suitable for byte and block address boundary applications up to approximately 104 MHz (T _cc = 10 (ns)) and are suitable for up to approximately 166 MHz when operating frequency is available (T _cc = 6 (ns) ) The double word address boundary application.

It should be noted that the maximum operating frequency is discussed in this discussion with various virtual clock instances, and other limitations due to the logic block design are not considered. Although the maximum operating frequency of many flash memory devices is currently limited to about 104 MHz, the current 166 MHz clock rate is not available, and the eight virtual clock instances are currently less practical, but the maximum operating frequency is expected. It will continue to increase so that eight virtual clock instances can be expected to be of practical value in the future. Now, four virtual clock instances and six virtual clock instances have the most practical value.

An example of improving read performance is as follows. For designs that are not optimized for address boundaries, rate performance may be based on a byte (ie, the slowest), regardless of the fact that the address boundary of the application may be a block or a doubleword, or Use six virtual bytes. However, if the design is optimized for a double-word boundary, then four virtual clock instances with tunable can be used to provide superior read performance. Therefore, for the design of optimized address boundaries, the same read instruction with six dummy bytes can be read in 80 megahertz (MHz) clocks in applications with byte address boundaries. Taking a flash memory device, in another application with a double word address boundary, the same read command with four dummy bytes can be used to read the flash memory device with a clock of 80 megahertz . This provides great flexibility for only one read instruction (ie, address boundary configurable (ABC) read instructions). For example, when implementing an application of eight virtual clock instances, there would be no need to use another read instruction for eight virtual clock instances.

Another example of read performance improvement is as follows. Referring to the eight virtual clock instances, the internal sensing time of 6.5×T _cc for the double-word boundary application (designed for address boundary optimization) may be greater than the use of the benefits of no address optimization. The internal sensing time of 4.5 × T _cc is about 40%. In an addressless design, the internal sensing time is usually based on a byte, regardless of whether the address boundary is a block or a double block boundary.

Another example of read performance improvement is as follows. For address-free read commands, the maximum read frequency of the flash memory device is 30 MHz for 2 virtual clocks, 50 MHz for 4 virtual clocks, 80 MHz for 6 virtual clocks, and 8 virtual times. 104MHz pulse. However, for a read command having a double word boundary limit, the maximum read frequency of the flash memory device is 30 MHz for 2 virtual clocks, 80 MHz for 4 virtual clocks, 104 MHz for 6 virtual clocks, and 10 virtual clocks of 104MHz. In applications with double-word address boundary constraints, the improvement in read performance is clearly visible for four virtual clock instances and six virtual clock instances.

8 is a block diagram of a flash memory device architecture suitable for performing address boundary configurable (ABC) read instructions. Many other types of flash memory devices can be modified in accordance with what is described herein to perform address boundary configurable (ABC) read instructions. The flash memory cell array 78 is provided with an address by a column decoding circuit 77 and a row decoding circuit 75. The latter includes a 256-bit page buffer for writing to the flash memory cell array 78 and for reading flash memory. The thirty-two sense amplifiers of the cell array 78 belong to the block. Corresponding to the state register 70, the protection logic 77 is written to avoid writing to the flash memory cell array 78 in certain cases. The command and control logic 71 controls the high voltage generator 72 and the page address latch and counter 73 for controlling the column decode circuit 77. The instruction and control logic 71 also controls a byte address latch and counter 74 for controlling the row decoding circuit 75. The instruction and control logic 71 includes four input/output pins IO0-IO3, a serial clock input pin CLK, and a wafer select input pin/CS.

As shown, the multiplexer 79 is disposed in the command and control logic 71 for providing an internal sense time control signal to the block 75 of the thirty-two sense amplifiers. The logic selected is accomplished by instruction and control logic 71. All thirty-two sense amplifiers can be used regardless of the address boundary.

The flash memory device of Figure 8 supports serial peripheral interface (SPI) and quaternary peripheral interface operations, including standard serial peripheral interface (SPI) instructions, dual serial peripheral interface instructions, four serial peripheral interface instructions, and four Meta peripheral interface instructions. The device will support quad-peripheral interface (QPI) operation when switching from the standard/dual/quad serial interface mode to the quad peripheral interface (QPI) mode using the "Enable QPI (38h)" command. This device can be switched back to the standard / dual / quad series peripheral interface mode using the "Disable QPI (FFh)" command.

Although the flash memory device of FIG. 8 only uses the address boundary configurable read command in the quaternary peripheral interface mode, the address boundary configurable read command can be used in a mode different from the quaternary peripheral interface. For example, various serial peripheral interface modes. The addressable boundary configurable read commands may include a fast read four input/output (EBh_QPI) quaternary peripheral interface (QPI) mode instruction, a fast read (0Bh_QPI) quaternary peripheral interface (QPI) mode instruction. And the package burst read (0Ch_QPI) instruction. The number of virtual clocks can be configured as 2, 4, 6, or 8 by the "Set Read Parameters (C0h)" command. Similar address boundary configurable instructions support four serial peripheral interface modes.

The invention and its applications and advantages are described herein with reference to the accompanying drawings, however, this description is not intended to limit the invention, and the scope of the invention is defined by the scope of the claims. The embodiments disclosed herein may be changed and modified, and the actual replacement and equivalents of the various elements of the embodiments will be apparent to those skilled in the art. Also, the specific numerical values given herein are for illustrative purposes only and may vary as needed. Various values in a range that are referenced will include all values within the range. These and other variations and modifications of the embodiments disclosed herein may be made without departing from the scope of the invention.

20, 21, 22, 23, 24, 25, 26, 27, 28, 29. . . step

30, 31, 32, 33, 34, 35, 36. . . step

40. . . Byte boundary condition

42. . . The first byte of the sense sequence

44. . . The second byte of the sensing sequence

46. . . The third byte of the sense sequence

50. . . Block boundary condition

52. . . The first double byte of the sensing sequence

54. . . The second double byte of the sensing sequence

56. . . The third double byte of the sensing sequence

58,79. . . Multiplexer (MUX)

59. . . Selection logic

60. . . Double word boundary condition

62. . . The first four bytes of the sensing sequence

64. . . The second quaternion of the sensing sequence

66. . . The third octet of the sensing sequence

70. . . Status register

71. . . Instruction and control logic

72. . . High voltage generator

73. . . Page address latch and counter

74. . . Byte address latch and counter

75. . . Row decoding circuit

76. . . Write control logic

77. . . Column decoding circuit

78. . . Flash memory cell array

CLK. . . Serial clock input pin

/CS. . . Chip selection input pin

IO0, IO1, IO2, IO3. . . Input/output pin

X1, X2. . . Sensing time of the byte boundary

Y1, Y2. . . Sensing time of the word boundary

Z1, Z2. . . Induction time of double word boundary

Figure 1 is a waveform diagram of a command signal.

Figure 2 is a waveform diagram of another command signal.

3 is a flow diagram of a read operation with configurable address boundaries.

4 is a flow diagram of a read command configurable by a flash memory device processing address boundary.

Figure 5 is a waveform diagram of an instruction with various address boundaries and its associated internal sensing timing.

6 is a block diagram of an implementation of a multiplexer circuit for selecting an induction time.

Figure 7 is a table of internal sensing timings and the number of appropriate virtual clocks for various address boundary conditions and operating frequencies.

Figure 8 is a circuit diagram showing the structure of a flash memory device.

30, 31, 32, 33, 34, 35, 36. . . step

Claims (15)

A method of operating a memory device, wherein the memory device comprises a flash memory cell array, the method of operating the memory device provides an application of data via a read command, wherein the application has a bit boundary, the memory device The operating method includes: receiving a read instruction including a start address; configuring the memory device for the address boundary of the application; and performing a sequence of sensing operations on the flash memory cell array via the read command The sequence includes: performing a first sensing of the flash memory cell array to obtain an output first data, the first sensing having a first location of the sequence and occurring at a first internal sensing time; providing the first data as An output of the memory device; performing a second sensing of the flash memory cell array to obtain an output second data, the second sensing having a second position of the sequence and occurring at a second internal sensing time; and providing the first The second data is used as an output of the memory device, wherein in order to improve the read performance, the address boundary and the first sensing and the Two induction time budget to change the first sensing time and the second inner sensing time internal. The method of operating the memory device of claim 1, wherein the first internal sensing time and the second internal sensing time are changed according to the first sensing and the second sensing individual positions of the sequence. The method of operating the memory device of claim 1, wherein the sequence further comprises: performing third sensing of the flash memory cell array to obtain an output third data, the third sensing having the sequence a third location and occurring at a third internal sensing time; and providing the third data as an output of the memory device. The method of operating a memory device according to claim 3, wherein the first internal sensing time is less than or equal to the second internal sensing time and the third internal sensing time. The method of operating a memory device according to claim 4, wherein the second internal sensing time and the third internal sensing time are equal or unequal. The method of operating a memory device according to claim 1, wherein the configuring step comprises configuring the memory according to the address boundary of the application according to one or more least significant bits of the start address. Device. The method of operating the memory device of claim 1, further comprising: receiving a configuration command, the configuration command comprising an address boundary parameter, before the step of receiving the read command, wherein the configuring step comprises The address boundary parameter configures the memory device for the address boundary of the application. The operating method of the memory device of claim 1, further comprising: receiving a configuration command including the virtual clock number parameter before the step of receiving the read command; and according to the virtual clock The number parameter configures the memory device to insert a virtual clock when the read command is received. A method of operating a memory device, wherein the memory device comprises a flash memory cell array, the method of operation of the memory device providing an application of data via a read command, wherein the application has a first address boundary at a first time And having a second address boundary at a second time different from the first time, the method of operating the memory device includes: receiving a first read instruction including a first start address; the first for the application Addressing the memory device; performing a first sequence of sensing operations on the flash memory cell array via the read command, the first sequence comprising: performing a first sensing of the flash memory cell array to obtain an output First information, the first sensing has a first position of the first sequence and occurs at a first internal sensing time; providing the first data as an output of the memory device; performing a second of the flash memory cell array Sensing to obtain a second data of the output, the second sensing having a second position of the first sequence and occurring at a second internal sensing time; and providing the second data as The output of the memory device, wherein the first internal sensing time and the second internal sensing time are dependent on the first address boundary of the application and the time budget of the first sensing and the second sensing; the receiving includes the second a second read command of the start address; configuring the memory device for the second address boundary of the application; and performing a second sequence of sensing operations on the flash memory cell array via the second read command, The second sequence includes: performing third sensing of the flash memory cell array to obtain an output third data, the third sensing having a first position of the second sequence and occurring at a third internal sensing time; providing the The third data is used as an output of the memory device; performing a fourth sensing of the flash memory cell array to obtain an output fourth data, the fourth sensing having the second position of the second sequence and occurring in the fourth internal sensing And providing the fourth data as an output of the memory device, wherein the third internal sensing time and the fourth internal sensing time are dependent on the second address boundary of the application The third induction time budget and the fourth induction. The method of operating a memory device according to claim 9, wherein the step of configuring the memory device for the first address boundary of the application comprises one or more according to the first start address The least significant bit configures the memory device for the first address boundary of the application; and the step of configuring the memory device for the second address boundary of the application includes the second start bit The one or more least significant bits of the address configure the memory device for the second address boundary of the application. The operating method of the memory device of claim 9, further comprising: receiving the first configuration instruction, the first configuration instruction including the first address boundary parameter, before receiving the step of the first read instruction The step of configuring the memory device for the first address boundary of the application includes configuring the memory device for the first address boundary of the application based on the first address boundary parameter; and receiving Receiving, by the second read instruction, the second configuration instruction, the second configuration instruction includes a second address boundary parameter; wherein the step of configuring the memory device for the second address boundary of the application comprises The memory device is configured for the second address boundary of the application based on the second address boundary parameter. The operating method of the memory device of claim 9, further comprising: receiving a first configuration instruction, the first configuration instruction including a virtual clock number parameter, before receiving the step of the first read instruction; Configuring the memory device to insert a virtual clock into the first read command according to the virtual clock number parameter; receiving a second configuration command prior to the step of receiving the first read command, the second configuration command including a virtual clock number parameter; and configuring the memory device to insert a virtual clock into the second read command based on the virtual clock number parameter. A method of reading a digital memory, comprising: operating a memory device by selecting a selected one of a plurality of possible operating frequencies of the memory device, the memory device having a sensitivity in a plurality of sensing operations The flash memory cell array further has a plurality of internal sensing times of the sensing operations, which are dependent on a plurality of sensing sequences of different address boundary conditions; providing configuration instructions to the read virtual byte according to the selected operating frequency a flash memory device of a number parameter; providing configuration instructions to the flash memory device to set an address boundary parameter of the application; providing a read command having a start address to the memory device; and utilizing time The budget receives data from the memory device, the time budget being by the read virtual byte number parameter and the one of the sensing sequences corresponding to the address boundary condition of the address boundary parameter One or more of these internal sensing times are determined. A memory device includes: a flash memory cell array; an address boundary determining circuit for determining an address boundary from a plurality of different potential address boundaries of a start address of the read command; an internal sensing time determining circuit, And the address boundary determining circuit is coupled to determine an internal sensing time sequence corresponding to one of the plurality of different sensing sequences of the flash memory cell array according to the different potential address boundaries; a plurality of inductive amplifiers, And the internal sensing time determining circuit and the flash memory cell array are coupled to perform the plurality of sequential sensing operations on the flash memory cell array according to the plurality of internal sensing times to obtain from the flash memory cell array Data and instructions and control logic coupled to the sense amplifiers for providing the obtained data by the output of the memory device. A memory device includes: a flash memory cell array; instruction and control logic for determining an address boundary of a start address of a read command, the command and control logic including a multiplexer for selecting Sensing the internal sensing time of the flash memory cell array in a sequence of sensing, and determining the internal sensing time for the at least two sensing sequences according to the address boundary and the sensed individual positions of the sensing sequences; And a plurality of sense amplifiers coupled to the multiplexer and the flash memory cell array for sensing the flash memory cell array for obtaining data, and the command and control logic is further coupled to the sense amplifiers for The output of the memory device provides the obtained data.