JP3985614B2 - Automatic identification method of serial memory - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to a serial memory.Address lengthThe present invention relates to an automatic type discrimination method.
[0002]
[Prior art]
In recent years, due to advances in semiconductor technology, the capacity of memories mounted on electronic devices such as portable terminals has been increasing. In addition, it is well known that a memory having a serial interface that can easily cope with downsizing is often used because the number of input / output ports is small.
[0003]
FIG. 14A shows a block diagram of a general serial memory.
14A, it is known that a general serial memory includes at least four ports DI (input), Do (output), Cs (chip select), and SK (serial clock).
Here, the DI port is a port for inputting a write command, a read command, and a series of serial data for designating an address, and Do is a port for outputting serial data read from the memory.
[0004]
Further, Cs is a port for making the memory accessible. Normally, by setting Cs to the Lo level, the memory becomes active, and data can be written or read. . Further, SK is a port for inputting a serial clock, and after Cs is set from Hi to Lo level, the serial clock is input to perform predetermined writing and reading.
[0005]
FIGS. 14B and 14C show a read timing chart and a write timing chart of the serial memory, respectively. As shown in FIG. 14B, at the time of reading, a read command and a read address are given to the DI port as a series of serial data, and serial clock data synchronized therewith is given to the SK port. Then, read data corresponding to the read address is output in synchronization with the serial clock signal.
[0006]
On the other hand, as shown in FIG. 14C, at the time of writing, Cs is once set from Hi to Lo, and a write command, a write address and write data are given as a series of serial data from the DI port. When Cs is changed from Lo → Hi level, writing is executed.
[0007]
Generally, various memory sizes are prepared for serial memories mounted on electronic devices, but only the bit length of the read (write) address differs depending on the memory size. Accordingly, if only the bit length of the address is changed according to the corresponding memory size, it is possible to cope with various memory sizes. Further, in Japanese Patent Laid-Open No. 2000-122921, even if the mounted memory size is unknown, the start of serial data given to the DI port and the timing of read data output from the Do port differ depending on the memory size. A method of automatically recognizing the memory size using the synthesizer has been proposed.
[0008]
[Problems to be solved by the invention]
However, the memory size automatic recognition method proposed in Japanese Patent Application Laid-Open No. 2000-122921 has the following problems. That is, in the conventional automatic memory size recognition method, when a read command and a read address of a predetermined bit are given to a DI port of an unknown memory, a response bit (Lo level) is added to the head of read data output from the Do port. The change of the read data head from Hi level to Lo level (response bit) is detected, and the memory size is determined by the time difference between the read command head and the detected response bit. It is supposed to be. For this reason, for example, this automatic recognition method cannot be applied to a serial memory having a generally well-known interface such as an SPI (Serial Peripheral Interface) to which no response bit is added.
[0009]
In addition, in order to detect a change from the Hi level to the Lo level at the beginning of the read data, the output voltage of the port must be fixed at the Hi level in a state where the data is uncertain before the Do port outputs the response bit. There is a problem that the number of parts increases because a pull-up resistor to the power source must be added to the port.
The present invention has been made to solve the above problems, and an object of the present invention is to provide a memory size automatic determination method that can also be used for an SPI type serial memory.
[0010]
[Means for Solving the Problems]
  In order to solve the above-mentioned object, the invention according to claim 1 of the serial memory automatic determination method according to the present invention accesses an unknown serial memory andAddress length typeIs a method of automatically determiningThe first byteWrite command1 byte data (0 or multiple of 4) from the 2nd byte to the 4th byte is set differentlyA processing step of giving a pre-write fixed bit string of a predetermined bit length to the serial memory and performing a pre-write process;The first byteRead commandThe second byte data is the same value as that of the pre-write fixed bit string, and the third byte data is set to a value different from that of the pre-write fixed bit string.A processing step of applying a first read fixed bit string having a predetermined bit length to the serial memory to perform a first read process, and extracting first determination data from the data read in the first read processThe address length type is determined by the value of the first determination data.First determination processing step for determiningWhen,
WithIt is comprised as follows.
  Therefore, this configuration has an unknown memory size.(Address length type)It has the effect of giving basic processing for discriminating between the two.
[0011]
  The invention according to claim 2 according to the present invention is the invention according to claim 1,Further, the read command is included in the first byte, the data in the second byte and the third byte are set to the same values as those in the pre-write standard bit string, and the fourth byte data is in the pre-write standard bit string. A second reading fixed bit string having a predetermined bit length set to a value different from the above is provided to the serial memory to perform a second reading process, and second determination data is extracted from the data read in the second reading process And a second determination processing step for determining the address length type based on the value of the second determination data.Is.
[0012]
  Furthermore, the invention according to claim 3 according to the present invention isClaim 1LeaveIn the first determination processing step, it is determined whether there are three types of 8 or 9 bit address type, 10 to 16 bit address type, or 17 to 24 bit address type (including failure time).It is comprised as follows.
[0013]
  The invention of claim 4 relating to the present invention isClaim 2LeaveIn the second determination processing step, it is determined whether it is a 17 to 24 bit address type or a failure.It is comprised as follows.
[0014]
  The invention according to claim 5 relating to the present invention isClaim 1LeaveThe third byte data of the first read fixed bit string is a value obtained by adding 01h to the third byte data of the pre-write fixed bit string.It is a configuration.
[0015]
  The invention according to claim 6 relating to the present invention isClaim 2LeaveThe fourth byte data of the second read fixed bit string is a value obtained by adding 01h to the fourth byte data of the pre-write fixed bit string.It is a configuration.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described in detail based on illustrated embodiments.
FIG. 1 is a flowchart showing processing steps of a serial memory automatic discrimination method according to the present invention. The serial memory described here is assumed to conform to the SPI (Serial Peripheral Interface), but the input / output ports of the memory and the access timing are basically the same as those shown in FIG. Omitted. The flowchart in FIG. 1 describes a processing program executed by the CPU, and it is assumed that each port of the serial memory is accessed via a general-purpose port provided in the CPU.
[0017]
Hereinafter, the processing procedure of the flowchart shown in FIG. 1 will be described.
First, the overall flow of the flowchart of FIG. 1 will be described. In this processing procedure, a predetermined bit string for writing having a predetermined length, which will be described later, is specified together with a plurality of addresses in the pre-writing process 1 and written to an unknown serial memory. Then, when the written data is read by the first reading process 2 and 2 bytes of 2 addresses (assuming that 1 address = 1 byte) are determined by the first determination process 3, the unknown serial memory has 8 and 9 It is classified into bit type, 16-bit type and others.
[0018]
Further, for those which are determined to be neither 8-, 9-bit, nor 16-bit types, in the second determination reading process 4, another address different from the address specified in the first reading process 2 is specified. Data is read out. Of these, 2 bytes of data for 2 addresses are determined in the second determination processing 5 to determine whether the data is a 24-bit type or a defective product, and the processing flow ends.
[0019]
Therefore, before describing each processing step, the data structure and page writing (reading) of an SPI-compliant serial memory will be described. Generally, the concept of a page is used for an SPI-compliant serial memory. This will be explained using an 8-bit or 9-bit memory as an example.
FIGS. 2A and 2B show the data structure of a memory having an 8-bit address and a 9-bit address. In FIG. 2, for example, in the memory of 8-bit address (a), the address can be specified from 00h to FFh, and data of 256 bytes in total of D1 to D256 (each data is in units of 1 byte) can be stored. it can.
[0020]
Here, a group of several bytes of each data is called one page. Normally, one page generally has a page size that is a multiple of 4 such as 4, 8, 16, 32, and 256 bytes depending on the memory size, and therefore, it is described here as 4 bytes / page.
Therefore, if it is 4 bytes / page, an 8-bit address memory has a data structure of 64 pages.
[0021]
In addition, the 9-bit address memory shown in FIG. 2B can specify addresses 00h to 1FFh, can store 512 bytes of D1 to D512, and has a 128-page data structure.
Here, when data is written to the memory, a write command and an address are input from the DI (input) port in FIG. 14, and subsequently, write data is continuously input for 4 bytes. Then, the write data is continuously written in the same page one byte at a time starting from the address. For example, in the case of an 8-bit address memory, if the address is specified as 00h and then D1 to D4 are input as 4 bytes of data, each byte of D1 to D4 is successively written to addresses 00h to 03h. It is.
[0022]
However, continuous writing of data across the next page is prohibited.
For example, even if address 00h is specified and 5 bytes of D1 to D5 are subsequently specified, D1 to D4 are written to 00h to 03h, and then D5 is written to the next address 04h, but the process proceeds to the next page. I can't. Therefore, it returns to the top address 00h of the same page, and D1 written earlier is overwritten with D5.
[0023]
On the other hand, in the case of reading, an address is input together with a read command, and then dummy data for a necessary byte is input. Then, data is continuously read out byte by byte in synchronization with the inputted dummy data in the order of consecutive addresses from the address. In the case of reading, if dummy data is added, it is possible to read continuously regardless of the page. Here, the dummy data may be any data.
[0024]
Now, the pre-writing process 1 of FIG. 1 will be described in detail below.
First, FIG. 3A shows a fixed bit string for pre-writing including a write command input from the DI port.
The first command (1) is data that specifies writing, and is usually given as 1-byte data. For the upper 5 bits, each bit is set to 0, and the lower 3 bits are set to bits corresponding to writing. Yes. Further, a series of data (2) to (7) is input following the 1-byte write command (1).
Here, 00h is 1-byte all-zero data (hexadecimal display), and “T”, “P”, “R”, “D”, and “G” indicate a 1-byte code of each character. (Hereinafter, when the address, data, or character code is expressed in hexadecimal notation, for example, 1Fh is suffixed with h.)
Further, when inputting the pre-written fixed bit string, predetermined signals are given to the Cs port and the SK port shown in FIG. 14, but the description thereof will be omitted below for the sake of simplicity. .
[0025]
Now, when the pre-programmed fixed bit string including the write command shown in FIG. 3A is input to the 8-bit address memory, 1 byte (8 bits) of (2) following the command (1) is recognized as an address. Therefore, the following 5 bytes (3) to (7) are processed as write data.
However, for the reason described above, writing cannot be performed across the first and second pages. Accordingly, as shown in FIG. 3B, “T”, “P”, “R”, and “D” are sequentially written to the addresses 00h to 03h of the first page, and the data D1 at the address 00h is further changed from “T” to “G”. "G", "P", "R", and "D" are stored in the addresses 00h to 03h, respectively.
[0026]
On the other hand, when the pre-programmed fixed bit string is input to the 9-bit address memory, the 5th bit (set to 0 here) from the beginning of the command (1) is interpreted as the most significant address, and the subsequent 1 byte is the lower order. Since it is interpreted as an 8-bit address, “G”, “P”, “R”, and “D” are stored in the addresses from 000h to 003h as shown in FIG. The
[0027]
Further, FIG. 5A and FIG. 5B show the result of inputting the pre-programmed fixed bit string to the memory having the 16-bit address. In this case, data 00h “T” of 2 bytes (2) and (3) following the command (1) is decoded as an address, and 4 bytes of (4) to (7) are processed as write data. Here, since the 1-byte character code of “T” is 54h, the 16-bit address is recognized as 0054h. As a result, data “P”, “R”, “D”, and “G” are stored in the addresses 0054h to 0057h, respectively. Even if the memory has a 10-15 bit address, the memory reads address information for each byte and decodes only the necessary number of address bits, so that the write results are exactly the same.
[0028]
  6A and 6B show the result of inputting the pre-programmed fixed bit string to the memory having a 24-bit address. In this example, the write command (1) is followed by (2) to(4)Three bytes 00h, “T”, “P” are decoded as addresses, and three bytes (5) to (7) are processed as write data. Here, since the character codes of “T” and “P” are 54h and 50h, respectively, “R”, “D”, and “G” are written in the addresses 005450h to 005452h, respectively. Even if the target memory has an address of 17 to 23 bits, the memory reads address information for each byte and decodes only the necessary number of address bits, so that the write results are exactly the same. Become.
[0029]
The example of the pre-write process has been described above. However, in the example of the pre-write process in the 8-, 9-bit address memory, only the data written at the head address is different when the page unit exceeds 4 bytes. The results in this case are shown in FIGS.
Note that in the pre-writing described above, the write address is determined as 00h, “T” (= 54h), and “P” (= 50h) for the second to fourth bytes from the beginning of the pre-programmed fixed bit string. is doing. At this time, when the first and second read processing described later is executed, each byte for determining the address is written so that the data is sequentially written from the top of the page so as not to read the data across the pages. Each is set to be 0 or a multiple of 4.
The pre-writing process 1 has been described above.
[0030]
Next, the first reading process in FIG. 1 will be described. When reading data from the target serial memory, first, 5 bytes of the first read fixed bit string including the read command is input to the DI (input) port of the serial memory. Then, data is output from the Do (output) port of the target serial memory, but the output data differs depending on the type of the target serial memory. The mechanism will be described below. FIG. 8 illustrates the first read result when the target serial memory is assumed to be an 8- or 9-bit address type. 8A shows an example in which one page has 4 bytes, and FIG. 8B shows an example in which one page has 8 bytes or more.
[0031]
As shown in FIG. 8A, 4 bytes of serial data (2) to (5) are input following a 1 byte read command (1) from DI (input). Here, for (3) “U” (= 55h) of the first read fixed bit string, 01h is set to 54h with respect to (3) “T” (= 54h) of the above-described fixed bit string for pre-writing. Set to the added value.
Then, when the target serial memory has an 8-bit address, the 1-byte data 00h of (2) following the command (1) is recognized as an address, and 3 bytes of (3) to (5) are recognized as dummy data. Alternatively, when the target serial memory has a 9-bit address, the total 9 bits of the fifth bit (set to 0) and (2) of the command (1) are recognized as the address 000h, and (3) to (5) 3 Bytes are recognized as dummy data.
[0032]
Here, the dummy data is arbitrary data to be added in order to continuously read data following the address 00h (000h), and here corresponds to 3 bytes of (3) to (5), The data at addresses 00h to 02h (000h to 002h) shown in FIGS. 3 and 4 are continuously read, and “G”, “P”, and “R” are output from the Do port of the target serial memory. Note that the output of the Do port is indefinite and data is not determined until an address for the necessary bits is input.
On the other hand, as shown in FIG. 8B, when the target serial memory is an 8 and 9-bit address type and one page has 8 bytes or more, the addresses 00h to 02h (000h) shown in FIGS. ... 002h) is read, and “T”, “P”, and “R” are output from the Do port of the target serial memory.
[0033]
When the target memory is a 16-bit address type, as shown in FIG. 9A, 2 bytes of (2) and (3) following the command (1) are recognized as the address 0055h, and (4 ) (5) is recognized as dummy data. Accordingly, the data “R” and “D” at the addresses 0055h and 0056h illustrated in FIG. 5 are output from the Do port of the target serial memory. At this time, it should be noted that the read start address is incremented by one with respect to the prewrite start address.
[0034]
When the target memory is a 24-bit address type, as shown in FIG. 9B, 3 bytes of (2), (3), and (4) following the command (1) are recognized as an address 005500h ( 5) is recognized as dummy data.
Note that the address 005500h is different from the address (see FIG. 6) specified in the pre-write, so that it is not known what data is stored here, so-called data is “undefined” It has become.
Here, the data portion corresponding to (4) and (5) output at the third and fourth bytes after the command (1) is given is called first determination data, and is used for the next first determination processing. Use. The first read process 2 for each memory type has been described above.
[0035]
Next, the first determination process 3 in FIG. 1 will be described.
In this processing step, first determination data is extracted based on the data read in the first reading process 2 described above. As a result of the first reading process 2, the target serial memory type is classified into one of the tables shown in FIG. 10 according to the order of the first determination data.
When the first determination data is in the order of “P” and “R”, the target serial memory is determined to be an 8- or 9-bit address type. When the first determination data is in the order of “R” and “D”, the target serial memory is determined to be a 16-bit address type (10 to 16-bit address). If the first determination data is “indefinite” or “indefinite”, that is, other than the above grouping order, the target serial memory is determined as a 24-bit address type (17 to 24-bit address) or a defective product. Note that although 2 bytes are extracted as the first determination data, the processing speed may be improved by extracting 1 byte.
The first determination process 3 has been described above.
[0036]
Next, the second reading process 4 in FIG. 1 will be described.
As a result of the first determination process 3 described above, for a target determined to be a 24-bit address type (17 to 24-bit address) or a defective product, it is determined whether or not it is a defective product after this processing step. It has become.
Therefore, first, as shown in FIG. 11, the 6-byte second read fixed bit string (1) to (6) including the read command is input to the DI port of the target memory.
Here, 1 byte of (1) is a read command, and the following 3 bytes of (2) 00h, (3) “T”, (4) “Q” are recognized as address 005451h (5) (6 ) Is recognized as dummy data.
[0037]
However, (2) and (3) of the second read fixed bit string are set to be the same as 00h and “T” of (2) and (3) of the pre-write fixed bit string described above. 2 (4) of the regular bit string for reading is set to be 51h obtained by adding 01h to 50h, corresponding to (4) “P” (= 50h) of the regular bit string for pre-writing described above. is there.
Then, if the target memory is a 24-bit address type, “D” and “G” are output from the Do port in synchronization with the dummy data of (5) and (6). (See Figure 6)
If the target memory is a faulty product, “undefined” and “undefined” other than the “D” and “G” grouping order.
[0038]
Here, the data portion corresponding to (5) and (6) output at the 4th and 5th bytes after the command (1) is given is called second determination data, and is used for the next second determination processing. Use. Even if the target memory is an 8-, 9-bit address type or a 16-bit address type (10 to 16-bit address), the last two bytes output from the Do port must be “R” “D”. Note that there is no possibility of determining a 24-bit address type as an 8- or 9-bit type (see FIG. 12). The second read process result has been described above.
[0039]
Next, the second determination process in FIG. 1 will be described.
In this processing step, second determination data is extracted based on the data read in the second reading process described above. As a result of the second reading process, the target serial memory type is classified into one of the tables shown in FIG. 13 according to the second determination data set. When the second determination data is “D” or “G”, the target serial memory can be specified as a 24-bit address type (17 to 24-bit address).
When the second determination data is “indefinite” or “indefinite”, that is, other than the pair of “D” and “G”, it can be determined as a defective product. Here, although the second determination data is 2 bytes, this may be 1 byte to improve the processing speed.
[0040]
In the embodiment described above, it is assumed that the target serial memory assigns an address in units of 1 byte, but an address such as AT25F512 manufactured by Atmel is 16 bits, but the address is There is a rare type that must be given 3 bytes. In such a case, it is determined as a 24-bit type. The following description is supplemented for such an example.
[0041]
For example, a description will be given by taking as an example a type in which an address is 13 bits but an address for 3 bytes must be given. This type of memory recognizes (decodes) only the lower 13 bits of the given 3-byte address.
Therefore, when the data shown in FIG. 6 is written in advance writing, only the lower 13 bits of the designated head address 005450h are decoded (only addresses 000000h to 001FFFh can be specified in the address range). "R", "D", and "G" are written in addresses 001450h to 001452h.
[0042]
On the other hand, when the first reading process 2 is performed, data is read from 005500h. However, for the same reason as described above, the address is interpreted as 001500h, and data is read therefrom. Accordingly, at this time, the first determination data is “indefinite” and “indefinite”, and the target memory is determined as a 24-bit address type or a defective product.
[0043]
However, when the second reading process is subsequently performed, data is read from the addresses 005451h and 005452h. For the same reason, the addresses are interpreted as 001451h and 001452h, and data is read therefrom.
Therefore, the second determination data is “D” and “G”, and the target memory is determined to be a 24-bit type as shown in the determination table of FIG. Therefore, even if the effective address length is short, paying attention to the number of bytes to which the address is assigned, all current memories are 8-, 9-bit address type, 16-bit address type or 24-bit address. It can be classified into any of the types.
[0044]
In the above, all the process steps in FIG. 1 were demonstrated.
It should be noted that the bit string after the second byte excluding the command for the pre-programmed fixed bit string input to the DI port of the target serial memory is 00h, “T”, “P”, “R”, “D”, “G”. It is not limited and other combinations may be used. For example, after writing data in an arbitrary page in the pre-write process 1, each of the second to fourth bytes of the bit string is read so that the data in the same page is read when the first and second read processes are executed. The byte may be set to be any type of * 0h, * 4h, * 8h, and * Ch so as to be 0 or a multiple of 4. (However, * is 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, or F)
[0045]
At this time, the third byte of the first read fixed bit string (the first byte of (3) in FIG. 8A) is the third byte of the pre-written fixed bit string (corresponding to “T” = 54h). The code is set to a value obtained by adding 01h (corresponding to “U” = 55h in this embodiment), and the fourth byte of the second read fixed bit string (1 byte of (4) in FIG. 11) Is set so that 01h is added to the character code of the fourth byte (corresponding to “P” = 50h) of the pre-programmed fixed bit string (corresponding to “Q” = 51h in this embodiment). Any combination is possible.
That is, if it is set to be any type of * 1h, * 5h, * 9h, * Dh obtained by adding 01h to any of the above-mentioned * 0h, * 4h, * 8h, * Ch If the target serial memory has a page configuration that is a multiple of 4, data is not read across pages in the first and second read processing, and therefore, the same determination as in the above-described embodiment can be made.
[0046]
In addition, since the certainty of determination is higher when the extracted first determination data and second determination data have different character codes, each byte after the second byte of the pre-written fixed bit string is different from each other. It is better to set as follows.
[0047]
As described above, according to the simple processing steps shown in FIG. 1, an SPI-compliant serial memory can be easily classified into any of 8, 9-bit address type, 16-bit address type, and 24-bit address type. It is. In addition, since the target memory does not need to include a specific response bit in the data output of the Do port, the memory type can be determined without being affected by the indeterminate state of the port appearing in the Do port, and the Do port pull Up resistance can be eliminated.
[0048]
【The invention's effect】
A method for automatically recognizing a memory size of a serial memory according to any one of claims 1 to 4 according to the present invention, wherein a predetermined bit string for pre-writing is given to an unknown serial memory, pre-writing processing is performed, and the pre-writing processing is executed. Thereafter, a first reading process and a second reading process are performed, and first determination data and second determination data are extracted from the first and second read data, and the first determination data and the second determination data are extracted. Since the unknown memory type is determined based on the set order of the determination data, the invention according to claim 5 according to the present invention has the first determination data and the second determination data at least 1 byte, respectively. Even if the memory type does not have a response bit added to the read data, it can easily determine the memory type easily. Sosu remarkable effects to provide a method.
[Brief description of the drawings]
FIG. 1 is a processing flowchart of a memory type automatic discrimination method according to the present invention.
FIG. 2 is a data structure of an 8- or 9-bit address type.
FIG. 3 shows an example of a pre-write result of an 8-bit address type (4 bytes / page)
[Fig. 4] Example of 9-bit address type pre-write result
FIG. 5 shows an example of a 16-bit address type pre-write result.
FIG. 6 shows an example of a 24-bit address type pre-write result.
[Fig. 7] Pre-write result of 8- and 9-bit type address type (8 bytes / page)
FIG. 8 shows an example of a first read processing result of an 8-, 9-bit address type.
FIG. 9 shows an example of a first read processing result of a 16-bit address type or a 24-bit address type.
FIG. 10 is a combination example of first determination data.
FIG. 11 shows an example of a second read processing result of a 24-bit address type.
FIG. 12 shows an example of a second read processing result of an 8-, 9-bit address type or a 16-address type.
FIG. 13 is a combination example of first determination data and second determination data.
FIG. 14 is a block diagram of a serial memory and an access timing chart;
[Explanation of symbols]
1 ... Pre-writing process
2 ... First reading process
3. First determination process
4. Second reading process
5 ... Second determination process

Claims (6)

A method of accessing an unknown serial memory and automatically determining the type of address length of the serial memory,
A serial bit string for pre-writing with a predetermined bit length in which each 1-byte data (0 or multiples of 4) from the 2nd byte to the 4th byte is set differently , including the write command in the first byte. Processing steps for giving pre-write processing to the memory;
The first byte contains a read command and the second byte data is set to the same value as that of the pre-write fixed bit string, and the third byte data is set to a value different from that of the pre-write fixed bit string. A processing step of supplying a first read fixed bit string having a predetermined bit length to the serial memory and performing a first read process;
A first determination processing step of extracting first determination data from the data read in the first read processing and determining an address length type based on a value of the first determination data ;
A method for automatically determining serial memory, comprising: Further, the read command is included in the first byte, the data in the second byte and the third byte are set to the same values as those in the pre-write standard bit string, and the fourth byte data is in the pre-write standard bit string. A processing step of giving a second read fixed bit string having a predetermined bit length set to a value different from that to the serial memory and performing a second read process;
A second determination processing step of extracting second determination data from the data read in the second read processing and determining an address length type based on a value of the second determination data;
Automatic discrimination method of the serial memory according to claim 1, comprising the. In the first determination processing step, it is determined whether there are three types of 8 or 9 bit address type, 10 to 16 bit address type, or 17 to 24 bit address type (including failure time). The serial memory automatic determination method according to claim 1. 3. The serial memory automatic determination method according to claim 2, wherein the second determination processing step determines whether the address type is a 17 to 24 bit address type or a failure. 2. The serial number according to claim 1, wherein the third byte data of the first read fixed bit string is a value obtained by adding 01h to the third byte data of the pre-write fixed bit string. Automatic memory detection method. 3. The serial memory according to claim 2, wherein the fourth byte data of the second read fixed bit string is a value obtained by adding 01h to the fourth byte data of the pre-write fixed bit string. Automatic determination method.

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