JPS6331827B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a pattern recognition device, in particular, performs time-division matching processing in divided information units when matching feature extraction information of a recognition target pattern with dictionary information of a standard feature pattern. Therefore, the present invention relates to a pattern recognition device that sequentially inputs both dictionary information in sub-block units read from a dictionary memory in which dictionary information is stored and corresponding divided feature extraction information to a matching circuit. .

In conventional pattern recognition devices, the entire amount of feature extraction information regarding a certain feature extracted from the recognition target pattern and the entire amount of dictionary information corresponding thereto are input to a matching circuit, and the input is performed at once. A matching processing method is used to determine whether or not the information matches. Since all the feature extraction information and dictionary information for a certain feature are input at once and the matching process is executed, the capacity of the matching circuit becomes large, and the number of data lines for inputting the information also increases. It has many drawbacks.

The present invention aims to solve the above-mentioned drawbacks, and the dictionary information of standard feature patterns is divided into sub-blocks, stored in a dictionary memory and read out, and features extracted from the corresponding recognition target pattern are obtained. The extracted information is also divided and read separately, and input switching control is performed to sequentially input both pieces of information to the matching circuit, and matching processing is performed in a time-sharing manner, thereby reducing the capacity of the matching circuit and reducing the number of data lines. The purpose is to increase the speed of the matching process. Therefore, in the pattern recognition device of the present invention, the dictionary information of each standard feature pattern is composed of a plurality of divided dictionary information divided into predetermined information units, and a block address is assigned to each dictionary information, and the dictionary information is divided into the divided dictionary information. A dictionary memory is stored by assigning an address within the block, and dictionary information is read out from the dictionary memory in each divided sub-block unit.At the same time, a recognition target corresponding to the dictionary information in the read sub-block unit is read out. A matching control circuit that reads pattern feature extraction information using the in-block address of the dictionary information read out in sub-block units, and matches the dictionary information and feature extraction information in divided information units. In a pattern recognition device equipped with a matching circuit, the matching control circuit determines the current block address when the sub-block division dictionary information input to the matching circuit matches the corresponding division feature extraction information. The first counter increments the block address when there is a mismatch, whereas the address in the block is initialized when both the inputs of the matching circuit do not match. a second counter that increments an intra-block address in a sub-block other than the final sub-block when the inputs match; and the second counter that generates a count of the intra-block address for reading out the final sub-block.
When the count number of the counter matches the count number of the final sub-block set in advance, the counting function of the second counter is stopped, and the recognition target pattern of the feature extraction information and the standard feature pattern of the dictionary information It is equipped with a comparator circuit that generates a strobe signal indicating that the matching has been achieved, and according to instructions from the matching control circuit, the sub-
The present invention is characterized in that the divided dictionary information for each block and the corresponding divided feature extraction information are sequentially introduced into the matching circuit. This will be explained below with reference to the drawings.

Figure 1 is an explanatory diagram illustrating an example in which dictionary information of standard feature patterns is stored in a divided state in dictionary memory, and Figure 2 explains how to read divided dictionary information stored in dictionary memory. An explanatory diagram to
Fig. 3 shows the configuration of an embodiment of the pattern recognition device of the present invention, and Fig. 4 shows a timer diagram for explaining the control function.
The chart diagram and FIG. 5 each show the configuration of an embodiment of the matching control circuit.

FIG. 1 is an explanatory diagram in which, for example, 16 types (A to P) of dictionary information (block information) are stored in the dictionary memory, where 1 is the memory, 2 is the address, and 3#1 is the memory.
3#16 to 3#16 are the dictionary information of the first sub-block in the dictionary information of the 1st block to the 16th block, and 4#1 to 4#16 are the second sub-blocks.
Dictionary information of the block, 5#1 to 5#16 are the dictionary information of the third sub-block, 6#1 to 6#16 are the dictionary information of the fourth sub-block, and 7 to 10 are the dictionary information of the 1st to 16th sub-block. block address specifying one of the block units, 1
1 to 14 represent intra-block addresses specifying sub-blocks within the block unit.
Note that the dictionary information of the sub-blocks described above corresponds to the divided dictionary information referred to in the present invention.

As described above, the dictionary information A of standard feature patterns is stored with each of the first to sixteenth blocks divided into sub-blocks. Therefore, the information of the first block of the standard feature pattern, that is, the dictionary information A, is accessed by the addresses "000000", "010000", "100000", and "110000".
Similarly, the information of the 16th block, that is, the dictionary information P, is accessed using the addresses "001111", "011111", "101111", and "111111".

FIG. 2 is an explanatory diagram for explaining how to read the divided dictionary information stored in the dictionary memory, in which block address C (n bits) specifies a block,
For example, the block address "0000" of n = 4 bits specifies the dictionary information A of the first block in Fig. 1, and the block address b (m bits)
specifies a sub-block, that is, m=2 bits, for example, intra-block address "01" specifies dictionary information A-2 of the second sub-block.

FIG. 3 shows the configuration of an embodiment of the pattern recognition device of the present invention, in which reference numeral 15 is a setting circuit, 16 is a matching control circuit, 17 is a dictionary memory, 18 is a feature extraction section, 19 is a result output circuit, and 20 represents a matching circuit.

The setting circuit 15 is a circuit for appropriately accumulating dictionary information inputted from an input medium such as a paper tape or a floppy disk, and writing the information contents into the dictionary memory 17, and the address at the time of setting is a block in the dictionary memory 17. Block for specifying units
Address C (n bits) and intra-block address b specifying a sub-block within the block unit.
(m bits) and the total (m+n) bits of the address are treated as one unit. Note that writing from the setting circuit 15 to the dictionary memory 17 is performed through the w-bit write line a.

In the matching control circuit 16, a timing signal i is sent from the feature extraction unit 18 to inform that the feature extraction has been completed.
That is, when receiving the recognition start signal, the address information of the above-mentioned intra-block address b and block address c is controlled. For example, by fixing the address information of block address c that specifies a block and incrementing block address b of block address n bits, the match output h will output "match" for all addresses in the block. At this time, it is determined that there is a match for the block specified by the block address c, and a strobe signal g is sent from the matching control circuit 16 to the result output circuit 19. On the other hand, while changing the address b in the block, the match output h is "mismatch".
When , the block address c is incremented by +1, and the intra-block address b is initialized, that is, once set to all "0", and then the intra-block address b is changed.

As shown in FIG. 1 described above, the dictionary memory 17 stores, for example, the first to sixteenth blocks.

The feature extractor 18 extracts a maximum of t×2 ^m bits of features, and when the extraction is finished, outputs a timing signal i to the matching control circuit 16 to start recognition. The feature extraction information e of t bits corresponding to the dictionary information divided into sub-blocks read from the dictionary memory 17 according to the intra-block address b is selected from the feature extraction section 18 and sent to the matching circuit 20 via the feature line. sent to.

When the result output circuit 19 receives the strobe signal g indicating that matching has been achieved from the matching control circuit 16, it selects the category described in the dictionary information d output from the last sub-block in the dictionary memory 17. The information d' bit is latched, and the above d' bit is output as the output of the recognition result. By decoding the d' bit, the category of the character to be recognized is determined.

The matching circuit 20 uses the t-bit feature extraction information e from the feature extraction section 18 and the sub-data from the dictionary memory 17.
Block information d is input in corresponding combinations, and the state of "match" or "mismatch" is determined and an output signal h is output. The matching circuit 2
0 is input to match the sub-block information d and the corresponding feature extraction information e, so the capacity of the matching circuit 20 is smaller than when matching is done for the entire block. Therefore, the number of data lines can be reduced.

It is now assumed that dictionary information is stored in the dictionary memory 17 from, for example, a paper tape by the setting circuit 15, as shown in FIG. When the timing signal i (recognition start) is input to the matching control circuit 16 from the feature extracting section 18, the dictionary memory 17 sets the block address c as "00" and the block address b as "0000", that is, "000000". Access by address. The dictionary information of sub-block A-1 is read out from the dictionary memory 17 and inputted to the matching circuit 20. On the other hand, since the feature extraction section 18 selects the feature extraction information e-1 corresponding to the sub-block and inputs it to the matching circuit 20, it is checked whether the two match, and if they "match", A coincidence output h is output and input to the matching control circuit 16. The matching control circuit 16 increments the block address c by +1 and accesses the dictionary memory 17 with the address "01", that is, "010000". As a result, the dictionary information of sub-block A-2 is read from the dictionary memory 17 and inputted to the matching circuit 20.
The same address "010000" is also supplied. Feature extraction information e-2 corresponding to sub-block A-2 is input from the feature extraction unit 21 to the matching circuit 20 and checked, and if it is a "match", the matching output h is sent to the matching circuit 16 as explained above. is input.
Then, the intra-block address c is further incremented by +1 step. On the other hand, if the matching circuit 20 cannot find a match, the matching control circuit 16
The address b is incremented by +1 to "0001" and at the same time, the address c within the block is initialized, that is, returned to the address "00". The dictionary memory 17 is accessed using the address "000001" thus obtained. As a result, the dictionary information of sub-block B-1 is read from the dictionary memory 17 and inputted to the matching circuit. At the same time, the feature extraction information e-1 is selected from the feature extraction section 18 and input to the matching circuit 20. Thereafter, when the output h is "match", the block address b is fixed and the intra-block address c is incremented by +1. Further, when the output h is "unmatched", as explained above, the block address b is incremented by +1 and at the same time, the intra-block address c is initialized.

For example, the dictionary information of sub-block B-4 whose intra-block address b is "11" and block address c is "0001" and the corresponding feature extraction information e-4 selected from the feature extraction section 18, When there is a “match” in the matching circuit 20, the matching output h is input to the matching control circuit 16. When the matching output h of the "match" is input, the matching control circuit 16 issues a strobe signal g to the result output circuit 19 assuming that all matches have been achieved. Category information d' is written in the dictionary information of sub-block B-4 read at the address "110001", and when the strobe signal g is input to the result output circuit 19, the above information d' is written. Latch. Then, the strobe signal j and the recognition result are outputted to the result output circuit 19.
A character code corresponding to the feature extraction information extracted from the feature extraction unit 18 is obtained. Character recognition is performed by decoding the character code.

Figure 4 is a time chart for explaining the control function.
An example is illustrated. For example, for dictionary information A, the figure shows a match when sub-block 1, that is, A-1 dictionary information, and feature extraction information e-1, and a mismatch when sub-block 2, that is, A-2 dictionary information, and feature extraction information e-2. For dictionary information B, sub-block 1, that is, B-1 dictionary information, and feature extraction information e-1 indicate a mismatch, and for dictionary information C, sub-blocks 1 to 4, that is, C-1 to C-4. Dictionary information, feature extraction information e-1 or e-
FIG. 4 is a time chart showing that each of the four cases is in agreement.

The shaded area in the figure indicates insufficient output or don't care, and the matching output h indicates a match, and the ○/fail indicates a mismatch. Note that _Tc represents the period of the clock φ, _TAC represents the access time of the dictionary memory, _TDM represents the delay time of the matching circuit, and _TDF represents the delay time of the characteristic output e from the address b within the block.

To briefly explain the time chart in the same figure, when timing signal i is received, clock #1
In this case, the dictionary information A-1 and the feature extraction information e-1 of the first sub-block are output at the address "000000", but the matching output h is a match. Clock #3
At this time, the intra-block address b advances by +1 and a match is checked in the second sub-block, but the match output h indicates that there is no match.
When clock #4, block address c is +1
Address b within the incremented block indicates that it is being initialized. At this time, the coincidence output h of the first sub-block indicates a mismatch. At clock #5, the block address c further increments by +1, but the coincidence output h of the first sub-block shows a coincidence. Clock #6, #7, #8
The intra-block addresses b are each incremented by +1, and the match outputs h in the second to fourth sub-blocks all indicate a match. Therefore, at the next clock #10, a strobe signal g is generated indicating that a match has been achieved.

FIG. 5 shows the configuration of an embodiment of the matching control circuit, in which 21 and 22 are inverters, 23 is a NOR circuit, 24, 29, and 32 are AND circuits, and 25, 26
is a counter, 27 is a comparison circuit, 28 is a comparator, 3
0 and 31 represent D-type flip-flops, respectively. The symbols b, c, g, h, and i correspond to those in FIG. 3, and φ represents a clock signal.

The counter 25 is the dictionary memory 17 in FIG.
The counter 25 is a counter that generates a sub-block address, and upon receiving a signal indicating that the coincidence output h is "non-coincidence", the counter 25 increments by +1.

The counter 26 is the dictionary memory 17 in FIG.
When the counter generates the address within the block, the address within the block is initialized upon receiving a signal indicating that the match output h is a "mismatch", that is, the previous count is cleared, and the match output h is a "match".
When receiving a signal indicating , the address within the block is incremented by +1 in sub-blocks other than the final sub-block.

The comparison circuit 27 stops the counting function of the counter 26 when the preset count number 2 ^m -1 of the final sub-block matches the count number of the counter 26, and also matches the feature extraction information with the dictionary information. A strobe signal is generated to indicate that the voltage has been removed.

The timing signal i, that is, the recognition starter signal is sent to the counter 25 via the inverter 22 and to the NOR circuit 2.
3, the counters 26 are cleared respectively, and the count number becomes zero. When the match output h reaches a high level indicating "match", the inverter 21
The count enable (CE) of the counter 25 becomes low level through the counter 25, and even if the clock φ is input to the counter 25, the counter 25 will not count. Therefore, its output c, ie the block address c, remains fixed. On the other hand, the output of the comparator 28 is always at a low level, and since its output is input to the AND circuit 26, the high level signal of the coincidence output h passes through the AND circuit 26 to enable the count of the counter 26. (CE) to high level. Therefore, when the clock φ is input, the counter 26 increments by +1, and its output b side, that is, the address b in the block changes.

When the coincidence output h reaches a low level indicating "mismatch", the counter 25 enters a count waiting state and is activated by the input of the clock φ.
advances by +1 and changes the block address c. On the other hand, the low level signal of the coincidence output h causes the count enable (CE) of the counter 26 to go to low level via the AND circuit 24, thereby causing a state in which counting is excluded. Then, the counter 26 is cleared via the inverter 21 and the NOR circuit 23, and the intra-block address b is initialized.

When high-level signals indicating "match" are sequentially inputted from the match outputs h, the counter 26 counts the number of match outputs h, sequentially varies the intra-block address b, and the comparator 2 in the comparison circuit 27
The count number is also input to 8. The count number of the final sub-block address 2 ^m -1 is set in advance in the comparator 28, and the counter 26
When the count ^number from
Output on 4,29. As a result, the counting function of the counter 26 is stopped and a high level signal is input to the D-type flip-flop 30 via the AND circuit 29. When the clock φ is input to the D-type flip-flop 30, a high-level signal from its output Q is input to the D-type flip-flop 31 at the next stage and also to the AND circuit 32. The other inputs of 32 are at high level since the output of D-type flip-flop 31 is at high level, and accordingly, the output g of AND circuit 32 outputs a high level signal. That is, a strobe signal is generated. When the next clock φ is input to the D-type flip-flops 30 and 31, the output Q becomes low level, and therefore the AND circuit 3
The output g of No. 2 also returns to low level.

In this way, the matching control circuit 16 in FIG. 3 receives the matching output h from the matching circuit 20 and the timing signal i from the feature extraction section, and controls the reading of the respective information from the dictionary memory 17 and the feature extraction section 18. Strobe signal g to the result output circuit 19
Send.

As explained above, according to the present invention, the dictionary information of the standard feature pattern is read out from the dictionary memory in sub-block units, and the feature extraction information extracted from the corresponding recognition target pattern is also read out in divided information units. Time-division matching processing becomes possible by performing input switching control to sequentially input both information to the reading and matching circuits. Then, it becomes possible to reduce the capacity of the matching circuit, reduce the number of data lines, and increase the speed of matching processing.

[Brief explanation of the drawing]

Figure 1 is an explanatory diagram illustrating an example in which dictionary information of standard feature patterns is stored in a divided state in dictionary memory, and Figure 2 explains how to read divided dictionary information stored in dictionary memory. An explanatory diagram to
Fig. 3 shows the configuration of an embodiment of the pattern recognition device of the present invention, and Fig. 4 shows a timer diagram for explaining the control function.
The chart diagram and FIG. 5 each show the configuration of an embodiment of the matching control circuit. In the figure, 1 is memory, 2 is address, 3#1 to 3#16, 4#1 to 4#16, 5#1 to 5#16, 6#1 to 6#16 are sub-block dictionary information, 7 to 10 are 1st to 16th
block/block specifying one of the block units.
Addresses 11 to 14 are intra-block addresses specifying sub-blocks within the block unit, 1
5 is a setting circuit, 16 is a matching control circuit, 17 is a dictionary memory, 18 is a feature extraction section, 19 is a result output circuit, 20 is a matching circuit, 25 and 26 are counters, 2
7 represents a comparison circuit, 28 a comparator, and 30 and 31 a D-type flip-flop.

Claims (1)

[Scope of Claims] 1. The dictionary information of each standard feature pattern is composed of a plurality of divided dictionary information divided into predetermined information units, and a block address is assigned to each dictionary information and the divided dictionary information is divided into blocks. By assigning an address and reading the dictionary information from the stored dictionary memory in each divided sub-block unit, the recognition target pattern corresponding to the read dictionary information in the sub-block unit is read out from the dictionary memory. A matching control circuit that reads the feature extraction information using the address within the block of the dictionary information read out in sub-block units, and a matching circuit that matches the dictionary information and the feature extraction information in divided information units. In the pattern recognition device, the matching control circuit maintains the current block address as it is when the sub-block division dictionary information input to the matching circuit matches the corresponding division feature extraction information. In contrast, the first counter increments the block address when there is a mismatch, and the first counter increments the block address when there is a mismatch, and the first counter increments the block address when there is a mismatch. a second counter that increments an intra-block address in a sub-block other than the final sub-block when there is a match; and a second counter that generates a count of the intra-block address for reading the final sub-block.
When the count number of the counter matches the count number of the final sub-block set in advance, the counting function of the second counter is stopped, and the recognition target pattern of the feature extraction information and the standard feature pattern of the dictionary information It is equipped with a comparator circuit that generates a strobe signal indicating that the matching has been achieved, and according to instructions from the matching control circuit, the sub-
A pattern recognition device characterized in that divided dictionary information for each block and corresponding divided feature extraction information are sequentially introduced into the matching circuit.