JPH0728783A - Method and circuit for stopping dsp - Google Patents

Abstract

PURPOSE:To resolve the trouble that input/output of serial data which stops program development of a digital signal processor DSP is broken halfway at the time of this program development. CONSTITUTION:The circuit, which stops execution of a program in a DSP 1 to which parallel data is inputted after conversion to serial, data and from which serial data to be converted to parallel data is outputted, is provided with a shift register 11 which shifts the parallel clock or synchronization of parallel data by the serial clock for that of serial data, a differential circuit 12 which differentiates the shift register output, and a counting circuit 13 which counts the output of the differential circuit, and execution of the program is stopped based on the counted value of the counting circuit 13.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a DSP (Digital Signal Pro
cessor), and more specifically, it relates to a method of stopping the execution of a program useful in the development of a DSP program and a stop circuit used for the execution.

[0002]

2. Description of the Related Art FIG. 1 is a block diagram of a peripheral circuit of a DSP disclosed in a title "Floating Point Digital Signal Processing LSI FDSP-4 Debug System" of "National Convention of Semiconductor and Materials Division, Institute of Electronics, Information and Communication Engineers, 1987". It is a figure. In the figure, 1 is D
The parallel data, which is SP and is transmitted via a data bus (not shown), is temporarily stored in the serial input memory 4, where it is converted into serial data and input to the DSP 1. The data generated in the DSP 1 is output in the form of serial data and temporarily stored in the serial output memory 5, where it is converted into parallel data and sent to the data bus. A serial oscillator 7 and a synchronization signal generator 8 are provided to perform such input / output. The serial oscillator 7 generates a serial clock for synchronizing serial data, and is supplied to both memories 4 and 5 and is also supplied to the synchronization signal generator 8. The synchronizing signal generator 8 is composed of a frequency divider (8 frequency divider in the case of 8 bits) according to the number of bits of parallel data, and gives the frequency division output to both memories 4 and 5 as a parallel clock for parallel data. .

Reference numeral 2 is a program memory for storing a program to be executed by the DSP 1.
A program address is given from DSP 1, and the program data read from the corresponding address is input to DSP 1. Reference numeral 9 is an execution stop controller provided to control the execution stop of the program, and includes an OR gate 91 and a D flip-flop 92. The OR gate 91 receives the output of the stop address memory 3 and the Q output of the D flip-flop 92 as two inputs, and the output of the OR gate 91 is the D flip-flop.
It has 92 D inputs.

The CK terminal of the D flip-flop 92 has a DSP 1
The clock provided for reading the program is supplied from the programming oscillator 6. D flip-flop 92
Q output of is supplied to DSP 1 as an execute / stop signal.
That is, the DSP 1 executes the program and stops in response to "0" / "1" of the Q output. CLR of D flip-flop 92
An execution command signal for causing DSP 1 to execute a program is given to the terminal. DSP for stop address memory 3
Write "1" to the address of the program where you want to stop 1, and set "0" to other addresses.

To execute the program, an execution command signal is input and the D flip-flop 92 of the execution stop controller 9 is reset. Then the Q output becomes "0" and the DSP
1 sequentially outputs the program address, thereby executing the program read from the program memory 2.
The program address is also input to the stop address memory 3, but when it becomes an address storing "1", the data read from the stop address memory 3 becomes "1", which is D through the OR gate 91. The Q output applied to the flip-flop 92 becomes "1", and the program execution of the DSP 1 is stopped. When the execution command signal is input as necessary, the D flip-flop 92 is reset and the program execution is restarted.

[0006]

During the above operation, the serial oscillator 7 and the serial clock output from the synchronizing signal generator 8 are not synchronized with the parallel clock and the program clock output from the program oscillator 6. Q output of D flip-flop 92 becomes "1" and DS
When P1 is stopped, serial data input / output may be in progress. In such a case, correct data input / output has not been performed, which causes a problem in resuming execution of the subsequent program.

The present invention has been made in view of the above problems, and is related to the input / output of serial data.
It is an object of the present invention to provide a DSP stop method and a stop circuit in which the DSP does not stop even if serial data input / output is incomplete by stopping P.

[0008]

A method of stopping a DSP according to the present invention is a method of stopping execution of a program in a DSP in which serial data to be converted from parallel data or serial data to be converted into parallel data is input / output. The number of input / output times of serial data is counted, and when the number of times has reached a predetermined number, the execution of the program is stopped.

The stop circuit of the DSP according to the present invention is a DS for converting parallel data into serial data and inputting it, and outputting serial data to be converted into parallel data.
In a circuit for stopping the execution of the program in P, a shift register that shifts a parallel clock for synchronizing parallel data with a serial clock for synchronizing serial data, a differentiating circuit that differentiates the shift register output, and a differentiating circuit of the differentiating circuit. A counting circuit for counting the outputs, and the program execution is stopped based on the count value of the counting circuit.

[0010]

By setting the required number of serial data input / output circuits in advance, the execution of the program is stopped at the required stage. Regarding the operation of the stop circuit, the parallel clock is shifted in the shift register by the serial clock. Therefore, the output is a signal indicating that one unit (for example, one word) of serial data has been input / output. The differentiating circuit falls (or rises) the output.
Is cut out and counted by a counting circuit. When this count reaches the set value, a signal is issued to stop the DSP.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings showing the embodiments. FIG. 2 is a block diagram showing an embodiment of the present invention, which can selectively perform the method according to the present invention and the conventional method described with reference to FIG. In the figure, 1 is DS
The parallel data P, which has been transmitted via a data bus (not shown), is temporarily stored in the serial input memory 4, where it is converted into serial data and input to the DSP 1. The data generated in the DSP 1 is output in the form of serial data and temporarily stored in the serial output memory 5, where it is converted into parallel data and sent to the data bus. A serial oscillator 7 and a synchronization signal generator 8 are provided to perform such input / output. The serial oscillator 7 generates a serial clock for synchronizing serial data, and is supplied to both memories 4 and 5 and is also supplied to the synchronization signal generator 8. The synchronizing signal generator 8 is composed of a frequency divider (8 frequency divider in the case of 8 bits) according to the number of bits of parallel data, and gives the frequency division output to both memories 4 and 5 as a parallel clock for parallel data. .

2 is a program memory for storing a program to be executed by the DSP 1.
A program address is given from DSP 1, and the program data read from the corresponding address is input to DSP 1. Reference numeral 9 is an execution stop controller provided to control the execution stop of the program, and includes an OR gate 91 and a D flip-flop 92. OR gate 91 is selector 10
2 and the Q output of the D flip-flop 92 are two inputs, and the output of the OR gate 91 is the D input of the D flip-flop 92.

The DSP 1 is connected to the CK terminal of the D flip-flop 92.
A program clock provided for reading the program is provided from the programming oscillator 6. The Q output of the D flip-flop 92 is given to the DSP 1 as an execute / stop signal. That is, the DSP corresponds to "0" / "1" of the Q output.
1 executes the program and stops. An execution command signal for causing the DSP 1 to execute a program is given to the CLR terminal of the D flip-flop 92. The stop address memory 3 contains the address of the program where you want to stop the DSP 1.
Write "1" and set other addresses to "0". The output of the stop address memory 3 is one input of the selector 10.

The parallel clock output from the synchronizing signal generating circuit 8 is input to the shift register 11. The shift register 11 has a number of stages corresponding to the number of bits of parallel data, and uses a serial oscillator 7 as a shift clock.
The serial clock output by is supplied. The output of the shift register 11 is input to the differentiating circuit 12. The differentiating circuit 12 has a structure for cutting out the trailing edge of the output of the shift register 11 (it may be the trailing edge depending on the form of the signal), and is formed by cascading D flip-flops 12a and 12b. . The output of the shift register 11 becomes the D input of the D flip-flop 12a in the preceding stage, and its Q output is the D in the latter stage.
It is the D input of the flip-flop 12b. The program clock output from the programming oscillator 6 is applied to the CK terminals of both D flip-flops 12a and 12b. Q output of D flip-flop 12a and D flip-flop 12b
The Q-bar output of the AND circuit constitutes a differentiation circuit 12 together with these.
It has two inputs to the gate 12c, and the output of the AND gate 12c is given to the counting circuit 13 as the output of the differentiating circuit 12. The counting circuit 13 includes a counter 13a having a preset function and an AND
It has a gate 13b. The preset value is given to terminal IN.

The output of the differentiating circuit 12 is given to the enable terminal EN of the counter 13a, and the program clock output from the program oscillator 6 is given to the CLK terminal as the counting target of the counter 13a. All bits of the count output of the counter 13a are input to the AND gate 13b.
The output of the gate 13b is the other input of the selector 10. As in the conventional case, the selector 10 is provided with a selection signal for selecting whether the DSP 1 is stopped or the DSP 1 is stopped by the output of the counting circuit 13 according to the output content of the stop address memory 3, and accordingly the stop address is used. The input from the memory 3 or the counting circuit 13 is selectively output.

The above operation will be described with reference to the time chart of FIG. The numbers in the circles in FIG. 3 correspond to the numbers in the circles in FIG. Further, the times of ◯ 1 to ◯ 4 and ◯ 5 to ◯ 11 are different, and the latter is displayed enlarged about 1000 times as compared with the former. Since the illustrated example has 8 bits, the serial clock ◯ 1 becomes a parallel clock ◯ 2 divided by eight. One cycle of this parallel clock, that is, 8 pulses of serial clock, 8 bits of serial data ○ 3
Input or output to P 1. The parallel clock is output from here after being delayed by 8 pulses of the serial clock by the shift register 11 (∘4).

◯ 5 to ◯ 11 in FIG. 3 show the operation after such shift register 11 output ◯ 4 is input. When the program clock ○ 5 is input to the differentiating circuit 12, the D flip-flop 12a outputs the shift register 11 ○ 4
The Q output ○ 6 becomes "1". Then, with a delay of one program clock, this Q output is read into the D flip-flop 12b, and its Q bar output ○ 7 turns to "0". Then, the output 8 of the AND gate 12c becomes a differential output having a width of one pulse of the program clock. In other words, "1" for one pulse width of the program clock is the shift register
It is cut out at the trailing edge of the 11th output. This is the counting circuit 13
The counter 13a is enabled and the program clock input to the CLK pin is counted up.

In other words, the counter 13a is incremented when input / output of one unit of parallel data is performed. If the counter 13a has an 8-bit structure and it is desired to stop the DSP 1 by inputting / outputting parallel data of 4 units (4 words), 255-4 = 251 is preset in the counter. Then, the contents of the counter 13a change like ○ 9, and
When it becomes 5, all output bits become "1" and AND
The output 13 of the gate 13b becomes "1" and is input to the D flip-flop 92 via the selector 10 and the OR gate 91, and the DSP 1 is stopped by the Q output 11 (= "1"). When the output of the stop address memory 3 is used, the same operation as the conventional one is performed.

[0019]

As described above, according to the present invention, the DSP program execution can be stopped in association with the input / output of serial data regardless of the change of the program address. It is stopped, input / output becomes incomplete, and there is no inconvenience when resuming program execution. Therefore, unnecessary work such as performing data input / output again is not required, and the work efficiency in DSP program development is improved. In addition, reliability is improved because incomplete data is not used.

[Brief description of drawings]

FIG. 1 is a block diagram of a peripheral circuit of a conventional DSP.

FIG. 2 is a block diagram of a peripheral circuit of a DSP of the present invention.

FIG. 3 is a time chart thereof.

[Explanation of symbols]

 1 DSP 7 Serial oscillator 8 Synchronous signal generator 9 Execution stop controller 11 Shift register 12 Differentiator circuit 13 Counting circuit

Claims (2)

[Claims] 1. Serial data to be converted from parallel data or to be converted into parallel data is input / output.
A method of stopping the execution of a program in DSP (1), characterized in that the number of input / output times of serial data is counted, and when the number of times reaches a predetermined number, the execution of the program is stopped. 2. A circuit for stopping the execution of a program in a DSP (1) which converts parallel data into serial data and inputs the serial data, and outputs serial data which should be converted into parallel data. A shift register (11) that shifts a clock with a serial clock for synchronizing serial data, a differentiation circuit (12) that differentiates the output of the shift register, and a counting circuit (13) that counts the output of the differentiation circuit , The counting circuit (13)
And a stop circuit for stopping the execution of the program based on the count value of.