JP3829906B2 - Microcomputer with built-in EEPROM interface - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention belongs to the technical field of microcomputers, and more specifically, to the technical field of microcomputers incorporating an interface suitable for serial communication with an EEPROM.
[0002]
[Prior art]
In data communication between a microcomputer and another device, either a parallel communication method or a serial communication method is roughly classified into one of two methods. In general, serial communication enables communication between a microcomputer and other devices with a few signal lines, so communication with much fewer signal lines than parallel communication is possible, and packaging and wiring are easy. There is an advantage of becoming.
[0003]
Normally, as shown in FIG. 4, when serial communication is performed between a conventional microcomputer 1 ′ and another device 2 ′ (various memories other than EEPROM and other microcomputers), a serial clock terminal, Communication is performed via the data transmission terminal and the data reception terminal. The serial synchronous communication resource used at this time is a clock synchronous serial interface built in the microcomputer, and data input and output are performed with a half clock shift from each other. That is, as shown in FIG. 5 and FIG. 6, the output from the data transmission terminal starts at one timing of the rising and falling edges of the pulsed clock signal, and conversely the data at the other timing. Reading at the receiving terminal is performed. Such a normal serial communication system is called an SPI (serial parallel interface) communication system.
[0004]
4 to 6, CSN is a chip select terminal (terminal or signal, hereinafter the same), SCK is a serial clock terminal, CTX is a data transmission terminal, CRX is a data reception terminal, and CBUSY is a communication busy terminal. . As for the signal input / output at these terminals, CSN, SCK, and CTX are port outputs, and the remaining CRX and CBUSY are port inputs as viewed from the conventional microcomputer 1 ′ on the master side. Note that LSB / MSB at the right ends of FIGS. 5 and 6 means that data communication is possible with either LSB first or MSB first. 5 and 6 are the same as each other except that the serial clock signal timing of SCK is reversed.
[0005]
On the other hand, when serial communication is performed between a conventional ordinary microcomputer and EEPROM without special communication hardware, communication is performed while controlling existing port resources with communication software. That is, the signal value of each port corresponding to CS (BUSY), SK (CSK), DO, and DI is directly controlled to 0 or 1 by communication software. While the serial communication with the EEPROM is performed in this way, the CPU of the microcomputer is completely involved in processing of the communication software, and thus cannot perform other processes. However, if you interrupt other processing and try to perform parallel processing in a time-sharing manner, you will have to divide the communication for one time and divide it into multiple times for serial communication. The required time becomes longer. Therefore, it is inconvenient because it cannot communicate with the EEPROM at high speed in parallel with other processing.
[0006]
Not only that, but it is clear that the communication method with the EEPROM differs from the above SPI communication method in data input / output timing, so the SPI method serial interface normally built in the microcomputer should be applied as it is. Is not easy. However, since the EEPROM communication protocol has already been established as an industry standard, the interface resources of the microcomputer must be adapted to the EEPROM mode. Therefore, as described above, a large interface control software is prepared on the microcomputer side for serial communication with the EEPROM, and the data transmission / reception timing of the microcomputer is controlled by the software.
[0007]
[Problems to be solved by the invention]
In the prior art described above, since the input / output control with the EEPROM is performed by the software of the microcomputer as described above, there is a disadvantage that the code size of the software for controlling the EEPROM interface becomes large. Then, there is a disadvantage that a large ROM capacity is required to store the software. In addition, since the code size of the software is large, the CPU processing time is not a little consumed for the arithmetic processing, and the CPU cannot perform other processing during that time.
[0008]
Accordingly, it is an object of the present invention to provide a microcomputer with a built-in EEPROM interface that prevents the increase in cost while reducing the code size of the software for controlling the EEPROM interface and reducing the CPU load required for communication with the EEPROM.
[0009]
[Means for Solving the Problems]
In order to solve the above problems, the inventors have invented the following means.
[0010]
That is, the inventors need only slightly modify the hardware configuration for SPI so that the data input from the data receiving terminal is delayed by a half step with respect to the data output from the data transmitting terminal. Discovered. As a result, communication at the timing of the EEPROM mode is basically possible by slightly modifying the communication hardware that is standardly equipped with the microcomputer having the serial interface, and the first means is invented. It came to. Furthermore, the second means and the third means were invented for the purpose of complementing the first means. Then, a microcomputer having all the requirements of the first means, the second means, and the third means is made on a trial basis, a communication test with the EEPROM is performed, and it is confirmed that the microcomputer functions perfectly. Completed.
[0011]
(First means)
The first means of the present invention is the microcomputer with built-in EEPROM interface according to claim 1.
[0012]
In this means, the EEPROM interface of the microcomputer has a transmission / reception circuit that performs transmission from the data transmission terminal and reception at the data reception terminal when the serial clock signal falls. This transmission / reception circuit synchronizes data input / output timing in hardware, eliminating the need for timing adjustment software, and greatly simplifying software that waits for output data and reads and processes input data It becomes. That is, the code size of the interface software for communication with the EEPROM can be significantly reduced by slightly modifying the interface hardware for the normal SPI mode.
[0013]
Therefore, the capacity of the ROM for storing the software becomes small, the processing time of the software is greatly shortened, and serial communication between the microcomputer and the EEPROM in a short time becomes possible. Not only that, but the CPU time required for the calculation processing of the software is very small, so the CPU time allocated for communication with the EEPROM is greatly reduced, and the CPU can immediately start other processing. . That is, the serial communication is almost entirely left to the EEPROM interface, and the CPU of the microcomputer can process other tasks while performing the serial communication with the EEPROM.
[0014]
Further, since the interface hardware is slightly modified and the ROM capacity for storing the interface software for the EEPROM mode is small, the cost is hardly increased. On the contrary, there is a possibility that even the cost can be reduced by the reduction in the interface software development cost and the ROM capacity.
[0015]
Furthermore, as described above, the configuration of the interface hardware in this means is only slightly different from that of the normal SPI communication system, so it is easy to use the interface hardware also as an SPI. . Even if they are shared, the cost increase is slight, so from the viewpoint of the versatility of the microcomputer, it is desirable to use a microcomputer equipped with SPI / EEPROM interface hardware.
[0016]
Therefore, according to the microcomputer with built-in EEPROM interface of this means, the code size of the EEPROM serial interface control software can be greatly reduced while preventing an increase in cost. As a result, not only the ROM capacity required for storing the software is reduced, but also communication with the EEPROM can be performed in a short time, and the CPU can be used more effectively.
[0017]
(Second means)
The second means of the present invention is the microcomputer with a built-in EEPROM interface according to claim 2.
[0018]
In this means, the EEPROM interface has a dummy clock signal generation circuit for generating a dummy clock signal after the serial clock signal is completed so that the final signal from the EEPROM can be received at the data reception terminal.
[0019]
When the microcomputer reads data from the EEPROM, the last one bit of the read data is sent later from the last serial clock signal in the EEPROM interface in which the normal SPI interface is modified. Therefore, if only the normal serial clock signal is referred to, the last one bit may be missed. Therefore, in this means, after the serial clock signal is finished, the dummy clock signal generation circuit generates the dummy clock signal inside the EEPROM interface, so that the last one bit sent from the EEPROM can be reliably received. ing. As a result, the microcomputer according to this means can receive the data without being read out until the last bit of the read data sent from the EEPROM.
[0020]
Therefore, according to the present means, in addition to the effect of the first means described above, the last one bit of the received data sent from the EEPROM is reliably received even if the hardware modification from the SPI interface is slight. The effect is that you will be able to.
[0021]
(Third means)
The third means of the present invention is the microcomputer with built-in EEPROM interface according to claim 3.
[0022]
In the present means, the EEPROM interface includes idle reading means for idle reading of the first half of the signals received at the data reception terminal, and dummy data added to the transmission data from the data transmission terminal to add the data length of the transmission data. Transmission data generating means capable of adjusting the transmission data.
[0023]
That is, since the normal SPI interface performs data transmission / reception in parallel, the EEPROM interface with a modified SPI interface may cause the following two problems.
[0024]
First, while the microcomputer sends instructions and addresses to the EEPROM, the EEPROM interface of the microcomputer may read the potential applied to the data reception terminal as significant data. Therefore, in this means, an empty reading means is provided in the EEPROM interface, so that a meaningless signal in the first half of signals received at the data receiving terminal is read empty and discarded. As a result, the microcomputer of this means can surely prevent the inconvenience that the meaningless potential applied to the data receiving terminal is read as significant data from the EEPROM.
[0025]
Second, at the time of reading data from the EEPROM, if the potential from the data transmission terminal is indefinite in the EEPROM interface of the microcomputer, there is a possibility that some trouble will occur in the operation of the EEPROM. Therefore, in this means, by providing an appropriate transmission data generation means in the EEPROM interface of the microcomputer, it is possible to add harmless dummy data to the transmission data from the data transmission terminal and appropriately adjust the data length of the transmission data. I can do it. As a result, even when data is read from the EEPROM, a signal sent from the data transmission terminal to the EEPROM becomes harmless, and malfunction of the EEPROM is reliably prevented.
[0026]
In addition, in normal SPI, the length of data that can be transmitted and received is usually limited to 8 bits or 16 bits, but the data length is freed by the transmission data generation means. In other words, by adjusting the transmission data length by adding dummy data to the transmission data in accordance with the length of data to be transmitted / received to / from the EEPROM, data having a length other than 8 bits or 16 bits can be transmitted / received. become.
[0027]
Explaining in more detail with an example, when reading data from the EEPROM, the transmission data from the microcomputer is configured as [dummy data] + [transmission data] + [dummy data of the reception data length], and the desired reception data. Sent to the length. Conversely, when data is written to the EEPROM, transmission data from the microcomputer is transmitted according to a desired transmission data length with a configuration of [dummy data] + [transmission data]. As a result, since the data length of transmission / reception can be set to a desired length, the degree of freedom regarding the data length increases in communication with the EEPROM.
[0028]
Therefore, according to this means, in addition to the effects of the first means or the second means described above, the following two effects are produced even if the hardware modification from the SPI interface is slight. That is, first, the data length of transmission / reception can be set to a desired length, so that there is an effect that the degree of freedom regarding the data length is increased. Next, data transmission / reception with the EEPROM can be performed with higher reliability. There is an effect of becoming.
[0029]
(Fourth means)
The fourth means of the present invention is the microcomputer with built-in EEPROM interface according to claim 4.
[0030]
In this means, since the hardware of the EEPROM interface also serves as the hardware of the SPI (serial parallel interface), the function of the interface hardware is simple and the functions are enhanced. Here, the configuration of the interface hardware of the first means described above is only slightly different from that of the normal SPI communication system, so it is technically easy to use the interface hardware also as an SPI. It is. And even if it is shared, there is an advantage that the versatility of the microcomputer increases because the cost increase is slight.
[0031]
Therefore, according to this means, there is an effect that the versatility of the microcomputer can be improved with a slight increase in cost.
[0032]
DETAILED DESCRIPTION OF THE INVENTION
The embodiments of the microcomputer with built-in EEPROM interface according to the present invention will be described clearly and sufficiently in the following examples so that a person skilled in the art can understand the embodiments.
[0033]
[Example 1]
(Configuration of Example 1)
As shown in FIG. 1, the microcomputer 1 with a built-in EEPROM interface as the first embodiment of the present invention is a one-chip microcomputer, and is connected to the EEPROM 2 by at least four signal lines. These four conducting wires are a communication busy signal line BUSY, a serial clock signal line SCK, a data output signal line DO, and a data input signal line DI in order from the top in the figure. The microcomputer 1 of this embodiment has a communication busy terminal 1b, a serial clock terminal 1c, a data transmission terminal 1d, and a data reception terminal 1e, and the above-described signal lines are connected to these terminals.
[0034]
The microcomputer 1 of the present embodiment incorporates an EEPROM interface 10 that can exchange data with the EEPROM 2 through these terminals 1b to 1e. The EEPROM interface 10 has a configuration obtained by slightly modifying a normal SPI, and includes a transmission / reception circuit 11, a dummy clock signal generation circuit 12, an idle reading unit 13, and a transmission data generation unit 14, unlike the normal SPI. Here, the three signals BUSY, SCK, and DO are port outputs of the EEPROM interface 10, and only one remaining signal DI is a port input of the EEPROM interface 10. Note that the EEPROM interface 10 is configured to be used as a normal SPI.
[0035]
As shown in FIG. 2 and FIG. 3, the transmission / reception circuit 11 is a circuit that performs transmission from the data transmission terminal 1d and reception at the data reception terminal 1e when the serial clock signal SCK falls. The transmission / reception circuit 11 is configured as hardware as a part of the integrated circuit of the microcomputer 1, and does not impose a load on the CPU and has a very high processing speed.
[0036]
The dummy clock signal generation circuit 12 receives an internal dummy clock signal after the serial clock signal SCK is completed, as shown at the right end of FIG. 3, so that the data reception terminal 1e can receive the final signal D0 from the EEPROM 2. This is a circuit to be generated. The dummy clock signal generation circuit 12 is also configured as hardware as a part of the integrated circuit of the microcomputer 1, and does not apply a load to the CPU. The dummy clock signal generation circuit 12 is configured as a part of the transmission / reception circuit 11.
[0037]
As shown in the left half of FIG. 3, the idle reading means 13 is software-configured means for idlely reading a meaningless signal in the first half of the signal DI received at the data receiving terminal 1e. On the other hand, the transmission data generation means 14 can adjust the data length of the transmission data DO by adding dummy data to the transmission data DO from the data transmission terminal 1d, as shown in the upper right part of FIGS. It is configured by software. The software of the idle reading means 13 and the transmission data generating means 14 is stored in the RAM or ROM of the microcomputer 1 and is processed by the CPU.
[0038]
(Operation of Example 1)
Since the microcomputer 1 with built-in EEPROM interface of the present embodiment is configured as described above, it exhibits the following operations.
[0039]
As shown in FIGS. 2 and 3, the transmission / reception circuit 11 transmits the transmission data DO from the data transmission terminal 1d and receives the reception data DI at the data reception terminal 1e when the serial clock signal SCK falls. Has an effect. Therefore, when communicating with the EEPROM 2, unlike the prior art, interface control software processed by the CPU is unnecessary, and data transmission / reception is processed at high speed by hardware.
[0040]
Further, as shown in the left half of FIG. 3, the idle reading means 13 idle-reads the first half of the meaningless signal including the reception data DI received at the data receiving terminal 1e when data is read from the EEPROM 2. Has the effect of That is, the meaningless signal in the first half of the signals received at the data receiving terminal 1e is read idle and discarded, so that the meaningless potential applied to the data receiving terminal 1e is read as significant data from the EEPROM 2. There is no inconvenience.
[0041]
On the other hand, the transmission data generating means 14 adds the harmless dummy data consisting mainly of zero to the transmission data DO from the data transmission terminal 1d as shown in the upper sequence of FIGS. Has the effect of adjusting the length. As a result, not only the data length of the transmission data DO can be adjusted, but also the malfunction of the EEPROM is surely prevented.
[0042]
Further, as shown at the right end of FIG. 3, the dummy clock signal generation circuit 12 has a function of generating a dummy clock signal inside the transmission / reception circuit 11 after the serial clock signal SCK is completed. As a result, the final signal D0 from the EEPROM 2 that comes after the last pulse of the serial clock signal SCK is reliably received by the data receiving terminal 1e, and the last one bit of the received data DI is not read out.
[0043]
(Effect of Example 1)
The microcomputer 1 according to the present embodiment is configured as described above and has the above-described functions, and thus has the following effects.
[0044]
First, since the data input / output timing is synchronized in hardware by the transmission / reception circuit 11, the interface control software of the prior art becomes unnecessary, and the interface software is greatly simplified. That is, the code size of the interface software for communication with the EEPROM 2 can be significantly reduced by slightly modifying the normal SPI interface hardware.
[0045]
Therefore, the ROM capacity for storing the software can be reduced. In addition, the processing time of the software is greatly shortened, and serial communication between the microcomputer 1 and the EEPROM 2 can be performed in a short time. Further, since the CPU time required for the calculation processing of the software is very small, the CPU time allocated for communication with the EEPROM 2 is greatly reduced, and the CPU can immediately start other processing. is there. That is, there is an effect that the CPU of the microcomputer 1 can process other tasks while serial communication with the EEPROM 2 is almost entirely left to the EEPROM interface.
[0046]
Secondly, the interface hardware from the conventional SPI is slightly modified and the ROM capacity for storing the interface software for the EEPROM mode is small, so that the cost is hardly increased. Rather, there is an effect that the cost is reduced by the reduction of the development cost of the interface software and the ROM capacity.
[0047]
As described above in detail, according to the microcomputer 1 with built-in EEPROM interface of the present embodiment, the code size of the EEPROM serial interface control software can be significantly reduced while preventing an increase in cost. As a result, not only the ROM capacity required for storing the software is reduced, but also communication with the EEPROM can be performed in a short time, and the CPU can be used more effectively. In addition, the transmission / reception data length can be set to a desired length, and the degree of freedom regarding the data length is also increased.
[Brief description of the drawings]
FIG. 1 is a schematic diagram showing a configuration of a microcomputer as Example 1. FIG. 2 is a signal timing chart at the time of data writing in Example 1. FIG. 3 is a signal timing chart at the time of data reading in Example 1. Fig. 4 Schematic diagram showing connection of clock synchronous serial interface [Fig. 5] Timing chart of clock synchronous serial interface [Fig. 6] Timing chart of clock synchronous serial interface [Explanation of symbols]
1: Microcomputer with built-in EEPROM interface 10: EEPROM interface (also used as SPI)
11: Transmission / reception circuit 12: Dummy clock signal generation circuit 13: Empty reading means 14: Transmission data generation means 1b: Communication busy terminal 1c: Serial clock terminal 1d: Data transmission terminal 1e: Data reception terminal 2: EEPROM
1 ': Conventional microcomputer (master side)
2 ': Other device (slave side)

Claims (3)

A microcomputer having a communication busy terminal, a serial clock terminal, a data transmission terminal, and a data reception terminal and having an EEPROM interface capable of transferring data by serial communication with the EEPROM,
The EEPROM interface modifies the interface hardware for normal SPI mode so that the data input from the data receiving terminal is delayed by a half step with respect to the data output from the data transmitting terminal, and the serial clock signal rises. A transmission / reception circuit that performs transmission from the data transmission terminal and reception at the data reception terminal at the time of falling , and the serial clock signal ends so that the final signal from the EEPROM can be received at the data reception terminal After having a dummy clock signal generation circuit that generates an internal dummy clock signal different from the serial clock signal,
The serial clock signal is output to the EEPROM only while a busy signal is output from the communication busy terminal .
Microcomputer with built-in EEPROM interface. The EEPROM interface includes idle reading means for idle reading of the first half of the signals received at the data reception terminal, and dummy data is added to the transmission data from the data transmission terminal to add the data length of the transmission data. Transmission data generating means capable of adjusting the
The microcomputer with a built-in EEPROM interface according to claim 1. The hardware of the EEPROM interface also serves as the hardware of SPI (serial parallel interface),
The microcomputer with a built-in EEPROM interface according to any one of claims 1 and 2.

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