JP2001027991A - Serial data communicating method with multiple slave cpus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a serial data communicating method with multiple slave CPUs which saves input/output ports of a CPU and enables many slave CPUs to be connected. SOLUTION: A master CPU 4 sends a slave address to a slave CPU 1, which once receiving the slave address, starts a timer. The master CPU 4 after waiting for a time T sends the slave address again to the slave CPU 1, which when receiving the slave address again for longer than a time TL within a time TH, sets ACK data in a transmitting buffer to make transmission ready; when the master CPU 4 sends the slave address again after waiting for the time T, the slave CPU 1 sends slave ACK data, so that a serial data communication is made between the master CPU 4 and slave CPU 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plurality of slave CPU
System that performs serial communication with the
The present invention relates to a serial communication having a plurality of slave CPUs in which a transmission interval from a slave CPU is switched so that the slave CPU can determine and recognize whether data transmitted from the master CPU is data or a slave address.

[0002]

2. Description of the Related Art Conventionally, a system for performing serial data communication with a plurality of slave CPUs by a data transmission / reception clock from a master CPU is configured as shown in FIG. 3, for example. In FIG. 3, a plurality (in FIG. 3,
One master CPU 4 is used for three slave CPUs 1 to 3 (illustrating three cases). This one
In the serial data communication method in which serial communication is performed by a data transmission / reception clock signal from the master CPUs 4, when one master CPU 4 selects the slave CPUs 1 to 3, the REQ signal for the selection is set to REQ.
From signal output terminals REQ1m to REQ3m to REQ signal input terminals REQ1s to REQ of slave CPUs 1 to 3, respectively.
3s.

Next, the slave CPUs 1 to 3
ACK for recognizing REQ signal transmitted from PU 4 and responding to master CPU 4 that communication is ready.
The signal is sent to the ACK signal output terminals AC of the slave CPUs 1-3.
The signal is transmitted from K1s to ACK3s to the ACK signal input terminals ACK1m to ACK3m of the master CPU 4. Along with this,
The master CPU 4 transmits a clock signal from the clock signal output terminal SCKm to the clock signal input terminals SCK1s to SCK3s of the slave CPUs 1 to 3, and uses the clock signal to transmit serial communication data output from the master CPU 4 from the data output terminal SO to the slave CPUs 1 to 3. 3 data input terminals SI1s to SI3s. Slave C
The data output of the serial communication of the PUs 1 to 3 is output together with the clock signal for data transmission together with the data output terminals SO1s to SO3.
s to the data input terminal SI of the master CPU 4.

As described above, in the conventional serial data communication method, the REQ signal for the master CPU 4 to select the slave CPUs 1 to 3 and the
The master CP recognizes the Q signal and indicates that communication is ready.
An ACK signal to send to U4 was needed.

As an approximation technique, for example, Japanese Patent Application Laid-Open No. 02-47755 discloses a main CPU and a sub-CP.
When performing serial data communication with U,
After the serial clock output from the PU to the sub CPU outputs an “H” signal for a first predetermined time T or more, a serial clock pulse for a plurality of bits is output at a second predetermined time T
The serial data that is generated within 2 and is output from the main CPU to the sub CPU in synchronization with the serial clock pulse signal is used as address data, and the communication direction, contents and number of subsequent communication data are determined by the address data. Is disclosed.

[0006]

However, the conventional serial communication method requires the same number of REQ signals and ACK signals as the number of slave CPUs. There is a problem that is spent for.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and has a plurality of slave CPUs in which the signal lines of the REQ signal and the ACK signal are eliminated, and the input / output port of the CPU can be effectively used for other controls. It is an object of the present invention to provide a serial data communication method having the following.

[0008]

In order to achieve the above object, a serial data communication method having a plurality of slave CPUs according to the present invention provides a method of serial communication from one master CPU to a plurality of slave CPUs by a data transmission / reception clock signal. Communication interval when transmitting and receiving a slave address transmitted from the master CPU to the serial data line in place of the REQ signal and ACK data transmitted from the slave CPU to the master CPU in place of the ACK signal Is performed in a processing step at an interval different from the communication interval during normal data transmission and reception. Therefore, the slave CPU receives the slave address transmitted from the master CPU,
Since the communication interval when the ACK data transmitted from the slave CPU to the master CPU is received by the master CPU is different from the communication interval at the time of normal data transmission and reception, R
The signal lines for the EQ signal and the ACK signal are eliminated, and the input / output port of the CPU can be used effectively for other controls.

[0009]

Next, an embodiment of a serial data communication method having a plurality of slave CPUs according to the present invention will be described with reference to the drawings. FIG. 1 shows one master CPU applied to a first embodiment of a serial data communication method having a plurality of slave CPUs according to the present invention.
FIG. 3 is a block diagram showing a configuration of a serial communication system for performing serial communication with a plurality of slave CPUs using a data transmission / reception clock signal.

The serial communication system shown in FIG.
3 of slave CPUs 1-3 as a plurality of slave CPUs
FIG. 7 illustrates a case where a number is used. One master CPU 4 is used for the three slave CPUs 1 to 3, and the serial communication data output terminal SO, data input terminal SI, and clock signal output terminal SCK are connected to the master CP.
U4 is connected to slave CPUs 1-3 connected in parallel.

That is, data output from the data output terminal SO of the master CPU 4 can be input to each of the data input terminals SI1 to SI3 of the three slave CPUs 1 to 3, respectively. Further, data outputs from the data output terminals SO1 to SO3 of the three slave CPUs 1 to 3 are input to the data input terminal SI of the master CPU 4, respectively. From the clock signal output terminal SCK of the master CPU 4 to the clock signal input terminals S of the three slave CPUs 1 to 3
A clock signal is input to CK1 to SCK3.

Next, a plurality of slaves C according to the present invention are provided by the serial communication system configured as described above.
The operation of the first embodiment of the serial data communication method having a PU will be described with reference to the flowchart of FIG. In this description, among the three slave CPUs 1 to 3, a procedure for performing serial data communication between the master CPU 4 and the slave CPU 1 on behalf of the slave CPU 1 will be described with reference to the flowchart of FIG. Will be explained.

FIG. 2 is a flowchart showing a communication processing flow in the CPU. Although not shown in FIG. 2, the flowchart of the slave CPU 2 and the slave CPU 3 is basically the same as that of the slave CPU 1, and the address of the slave CPU 1 is set to the address of the slave CPU 2 and the address of the slave CPU 3.
ACK data of the slave CPU2 and ACK data of the slave CPU3.

When communication starts and the master CPU 4 communicates with the slave CPU 1, the master CPU 4
The second slave address is transmitted on the serial data line (step A1). By transmitting the first slave address, the slave CPU 1 performs a reception interrupt process (step A2), and when the slave CPU 1 receives the first slave address (step A).
3), the slave CPU 1 starts a timer (step A4). At this time, the slave CPU 2 and the slave CPU 3 determine that their slave addresses have not been selected, and end the receiving operation.

If the master CPU 1 has not received the next data from the master CPU 4 since the start of the timer (step A5), and the elapsed time of the timer is not within TH (that is, the timer value> TH), (Step A6), the processes of Step A5 and Step A6 are repeated. In this state, the master CPU 4
If no ACK data has been received from the slave CPU 1 (step A7), the process waits for a time T within the set time of the timer (step A8), and returns to the process of step A1 again. Is transmitted to the slave CPU 12 through the serial data line.

In the slave CPU 1, when the second slave address is received again within the time TL and the time TH within the elapsed time from the start of the timer (step A9), a transmission (not shown) in the slave CPU 1 is performed. By setting the ACK data of the slave CPU 1 in the buffer, the slave CPU 1
4 is set in a transmission permission state (step A10). Note that each time of the timer at this time is TL <T <TH.

Next, the slave CPU 1
ACK data is transmitted to U4 (step A1)
1) and receiving the ACK data (step A7), the master CPU 4 performs serial data communication with the slave CPU 1 (step A12). Similarly, the slave CPU 1
Serial data communication is performed with U4 (step A1).
3). Thus, instead of the REQ signal, the master CP
U4 sends a slave address on the serial data line, and slave CPU1 sends A instead of an ACK signal.
Since the communication interval when transmitting and receiving CK data is set to be different from the interval when transmitting and receiving normal data, signal lines for the REQ signal and the ACK signal can be eliminated. Therefore, the input / output port to each CPU can be effectively used for other control and the like.

As described above, during the serial data communication between the master CPU 4 and the slave CPU 1, the master CP
Even if the same data as the slave address of the slave CPU 2 or the slave address of the slave CPU 3 is transmitted from U4, the slave CPU 2 or the slave C
PU3 does not start communicating with the master CPU. When the master CPU 4 communicates with the slave CPU 2, the slave address and the ACK data of the slave CPU 2 are used. When the master CPU 4 communicates with the slave CPU 3,
Slave address of slave CPU3 and slave CPU
By using the ACK data of No. 3, communication can be performed in the same manner as in the case where communication is performed between the master CPU 4 and the slave CPU 1. It is to be noted that the present invention is not limited to the above-described embodiment, and it is obvious that the embodiment can be appropriately modified within the scope of the technical idea of the present invention.

[0019]

As described above, according to the present invention, when serial data communication is performed between a master CPU and a plurality of slave CPUs, a signal is transmitted from the master CPU to a serial data line instead of the REQ signal. Since the communication interval when transmitting and receiving ACK data transmitted from the slave CPU as a substitute for the slave address and the ACK signal is different from the communication interval during normal data transmission and reception, a plurality of slave CPUs are provided. Since the REQ signal and the ACK signal are not used in the serial signal, even if the number of slave CPUs is increased, the number of input / output ports of the CPUs to be used can be reduced and many slave CPUs can be connected.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a serial communication system applied to a first embodiment of a serial data communication method having a plurality of slave CPUs according to the present invention.

FIG. 2 is a flowchart showing a communication processing flow between a master CPU and a slave CPU for describing an operation of a first embodiment of a serial data communication method having a plurality of slave CPUs according to the present invention.

FIG. 3 is a block diagram showing a configuration of a conventional serial data communication system to which a serial data communication method having a plurality of slave CPUs is applied.

[Explanation of symbols]

1-3 slave CPU, 4 master CPU, S
I, SI1 to SI3 ... data input terminals, SO, SO1
SO3: Data output terminal, SCK: Clock signal output terminal, SCK1 to SCK3: Clock signal input terminal.

Claims (3)

[Claims] 1. A system for performing serial communication from one master CPU to a plurality of slave CPUs using a data transmission / reception clock signal, wherein: a slave address transmitted from the master CPU to a serial data line instead of a REQ signal;
Instead of the signal, the slave CPU sends the master CP
A serial data communication method having a plurality of slave CPUs, wherein the communication interval when transmitting and receiving ACK data transmitted to the U is set to a different interval from the communication interval during normal data transmission and reception. . 2. The processing step includes: a first step of starting a timer when a first slave address transmitted from the master CPU confirms that the first slave address is a slave address to itself by a predetermined slave CPU; When the predetermined slave CPU receives the second slave address transmitted by the master CPU within a second set time later than the first set time after the elapse of the first set time, the predetermined slave CPU becomes the master CPU.
A second step of transmitting the first ACK data to the transmission permission state and transmitting the third slave address transmitted by the master CPU after the lapse of the second set time to the predetermined slave CPU.
When the master CPU receives and transmits the first ACK data to the master CPU, the master CPU
3. The serial data communication method having a plurality of slave CPUs according to claim 1, further comprising: a third step of performing data communication with U. 3. When the timer is started, the predetermined slave CPUs, other than the predetermined slave CPU, determine that their slave addresses have not been selected and end the receiving operation. 3. The serial data communication method having a plurality of slave CPUs according to claim 2, wherein: