JP5448795B2 - 情報処理装置又は情報処理方法 - Google Patents

情報処理装置又は情報処理方法 Download PDF

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Publication number
JP5448795B2
JP5448795B2 JP2009295616A JP2009295616A JP5448795B2 JP 5448795 B2 JP5448795 B2 JP 5448795B2 JP 2009295616 A JP2009295616 A JP 2009295616A JP 2009295616 A JP2009295616 A JP 2009295616A JP 5448795 B2 JP5448795 B2 JP 5448795B2
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JP
Japan
Prior art keywords
data
external device
reception
clock
unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2009295616A
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English (en)
Japanese (ja)
Other versions
JP2011135530A5 (https=
JP2011135530A (ja
Inventor
昭好 桃井
浩一 森下
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP2009295616A priority Critical patent/JP5448795B2/ja
Application filed by Canon Inc filed Critical Canon Inc
Priority to PCT/JP2010/007404 priority patent/WO2011077706A1/en
Priority to EP10838945.3A priority patent/EP2517396B1/en
Priority to CN201080058942.5A priority patent/CN102696196B/zh
Priority to US13/518,321 priority patent/US9479326B2/en
Priority to KR1020127018694A priority patent/KR101453176B1/ko
Publication of JP2011135530A publication Critical patent/JP2011135530A/ja
Publication of JP2011135530A5 publication Critical patent/JP2011135530A5/ja
Application granted granted Critical
Publication of JP5448795B2 publication Critical patent/JP5448795B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0091—Transmitter details
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/0033—Correction by delay
    • H04L7/0037—Delay of clock signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Program-control systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/10—Arrangements for initial synchronisation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP2009295616A 2009-12-25 2009-12-25 情報処理装置又は情報処理方法 Expired - Fee Related JP5448795B2 (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP2009295616A JP5448795B2 (ja) 2009-12-25 2009-12-25 情報処理装置又は情報処理方法
EP10838945.3A EP2517396B1 (en) 2009-12-25 2010-12-21 Information processing apparatus or information processing method
CN201080058942.5A CN102696196B (zh) 2009-12-25 2010-12-21 信息处理设备或信息处理方法
US13/518,321 US9479326B2 (en) 2009-12-25 2010-12-21 Information processing apparatus or information processing method
PCT/JP2010/007404 WO2011077706A1 (en) 2009-12-25 2010-12-21 Information processing apparatus or information processing method
KR1020127018694A KR101453176B1 (ko) 2009-12-25 2010-12-21 정보 처리 장치 또는 정보 처리 방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009295616A JP5448795B2 (ja) 2009-12-25 2009-12-25 情報処理装置又は情報処理方法

Publications (3)

Publication Number Publication Date
JP2011135530A JP2011135530A (ja) 2011-07-07
JP2011135530A5 JP2011135530A5 (https=) 2013-02-14
JP5448795B2 true JP5448795B2 (ja) 2014-03-19

Family

ID=44195260

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009295616A Expired - Fee Related JP5448795B2 (ja) 2009-12-25 2009-12-25 情報処理装置又は情報処理方法

Country Status (6)

Country Link
US (1) US9479326B2 (https=)
EP (1) EP2517396B1 (https=)
JP (1) JP5448795B2 (https=)
KR (1) KR101453176B1 (https=)
CN (1) CN102696196B (https=)
WO (1) WO2011077706A1 (https=)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10552169B2 (en) 2017-03-17 2020-02-04 Sandisk Technologies Llc On-die signal calibration

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4384307A (en) * 1979-08-28 1983-05-17 Inteq, Inc. Facsimile communications interface adapter
JPS59173839A (ja) * 1983-03-22 1984-10-02 Matsushita Electric Ind Co Ltd 直列デ−タ転送回路
JP3157029B2 (ja) 1992-02-28 2001-04-16 沖電気工業株式会社 データ受信装置
JP3367009B2 (ja) 1995-08-31 2003-01-14 京セラ株式会社 プリンタ装置における同期式データ伝送方式
US5922076A (en) 1997-09-16 1999-07-13 Analog Devices, Inc. Clocking scheme for digital signal processor system
JP3173457B2 (ja) 1998-03-23 2001-06-04 日本電気株式会社 データ通信装置
US6757347B1 (en) 2000-04-28 2004-06-29 Hewlett-Packard Development Company, L.P. Source synchronous link with data and clock signals having the same electrical characteristics
US6735709B1 (en) 2000-11-09 2004-05-11 Micron Technology, Inc. Method of timing calibration using slower data rate pattern
JP2002247141A (ja) 2001-02-21 2002-08-30 Aisin Seiki Co Ltd シリアル通信装置
US6922789B2 (en) * 2001-09-21 2005-07-26 International Business Machines Corporation Apparatus and method for recalibrating a source-synchronous pipelined self-timed bus interface
CN100412749C (zh) 2004-10-21 2008-08-20 威盛电子股份有限公司 存储器信号定时调校方法与相关装置
DE102005019041B4 (de) * 2005-04-23 2009-04-16 Qimonda Ag Halbleiterspeicher und Verfahren zur Anpassung der Phasenbeziehung zwischen einem Taktsignal und Strobe-Signal bei der Übernahme von zu übertragenden Schreibdaten
CN101416437A (zh) 2006-04-05 2009-04-22 松下电器产业株式会社 可移动存储装置、相位同步方法、相位同步程序、其记录介质及主机终端
KR101228270B1 (ko) * 2006-05-01 2013-01-30 주식회사 아도반테스토 시험 장치 및 시험 방법
US8024599B2 (en) 2007-03-08 2011-09-20 Sandisk Il Ltd Bias and random delay cancellation
JP5188287B2 (ja) * 2008-06-25 2013-04-24 ルネサスエレクトロニクス株式会社 通信装置
KR100942953B1 (ko) 2008-06-30 2010-02-17 주식회사 하이닉스반도체 데이터 전달 회로 및 그를 포함하는 반도체 메모리 장치
EP2351037A4 (en) * 2009-01-12 2011-12-28 Rambus Inc MESOCHRONIC SIGNALING SYSTEM WITH CORE ACTIVE SYNCHRONIZATION

Also Published As

Publication number Publication date
US9479326B2 (en) 2016-10-25
CN102696196B (zh) 2015-04-01
KR20120094956A (ko) 2012-08-27
EP2517396A4 (en) 2017-12-27
EP2517396A1 (en) 2012-10-31
JP2011135530A (ja) 2011-07-07
EP2517396B1 (en) 2018-10-10
KR101453176B1 (ko) 2014-10-22
CN102696196A (zh) 2012-09-26
WO2011077706A1 (en) 2011-06-30
US20120259438A1 (en) 2012-10-11

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