JP5448324B2 - Dll回路及びこれを備える半導体装置、並びに、データ処理システム - Google Patents
Dll回路及びこれを備える半導体装置、並びに、データ処理システム Download PDFInfo
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- JP5448324B2 JP5448324B2 JP2007275470A JP2007275470A JP5448324B2 JP 5448324 B2 JP5448324 B2 JP 5448324B2 JP 2007275470 A JP2007275470 A JP 2007275470A JP 2007275470 A JP2007275470 A JP 2007275470A JP 5448324 B2 JP5448324 B2 JP 5448324B2
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- circuit
- clock
- adjustment
- determination signal
- dll
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- 239000004065 semiconductor Substances 0.000 title claims description 24
- 230000000630 rising effect Effects 0.000 claims description 38
- 230000001934 delay Effects 0.000 claims description 5
- 230000003111 delayed effect Effects 0.000 description 12
- 239000011295 pitch Substances 0.000 description 11
- 238000010586 diagram Methods 0.000 description 8
- 230000008034 disappearance Effects 0.000 description 7
- 230000001360 synchronised effect Effects 0.000 description 6
- 230000006870 function Effects 0.000 description 3
- 230000004044 response Effects 0.000 description 2
- 238000010348 incorporation Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0818—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter comprising coarse and fine delay or phase-shifting means
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
Landscapes
- Dram (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Pulse Circuits (AREA)
Description
11 クロック端子
12 アドレス端子
13 コマンド端子
14 データ入出力端子
20 メモリセルアレイ
30 コントローラ
40 出力バッファ
50 入力バッファ
100 DLL回路
105 入力レシーバ
110 位相判定部
111,112 位相判定回路
120 調整部
121,122 カウンタ回路
123,124 遅延回路
123a,124a 粗調回路
123b,124b 微調回路
130 再生回路
140 レプリカバッファ
150 停止回路
1000 データ処理システム
1100 システムバス
1200 データプロセッサ
1400 ストレージデバイス
1500 I/Oデバイス
1600 ROM
Claims (8)
- 第1のクロックの立ち上がりエッジと第2のクロックの立ち上がりエッジの位相を比較することにより、第1の判定信号を生成する第1の位相判定回路と、
前記第1のクロックの立ち下がりエッジと前記第2のクロックの立ち下がりエッジの位相を比較することにより、第2の判定信号を生成する第2の位相判定回路と、
前記第1の判定信号に基づいて、第3のクロックのアクティブエッジの位置を調整する第1の調整回路と、
前記第2の判定信号に基づいて、第4のクロックのアクティブエッジの位置を調整する第2の調整回路と、
前記第3及び第4のクロックに基づいて前記第2のクロックを生成するクロック生成回路と、
前記第1の判定信号に基づく前記第3のクロックのアクティブエッジの調整方向と、前記第2の判定信号に基づく前記第4のクロックのアクティブエッジの調整方向とが互いに逆方向であることに応答して、前記第1の調整回路による調整動作及び前記第2の調整回路による調整動作のいずれか一方を停止させる停止回路とを備えることを特徴とするDLL回路。 - 前記第1の調整回路は、前記第1の判定信号に基づいてカウント値が更新される第1のカウンタ回路と、前記第1のカウンタ回路のカウント値に基づいて前記第3のクロックを遅延させる第1の遅延回路とを含み、
前記第2の調整回路は、前記第2の判定信号に基づいてカウント値が更新される第2のカウンタ回路と、前記第2のカウンタ回路のカウント値に基づいて前記第4のクロックを遅延させる第2の遅延回路とを含むことを特徴とする請求項1に記載のDLL回路。 - 前記第1の遅延回路は、相対的に調整幅の大きい第1の粗調回路と、相対的に調整幅の小さい第1の微調回路とを含み、
前記第2の遅延回路は、相対的に調整幅の大きい第2の粗調回路と、相対的に調整幅の小さい第2の微調回路とを含み、
前記停止回路は、前記第1の粗調回路による調整動作及び前記第2の粗調回路による調整動作のいずれか一方を停止させることを特徴とする請求項2に記載のDLL回路。 - 前記クロック生成回路は、前記第3及び第4のクロックに基づいて第5のクロックを生成する再生回路と、前記第5のクロックを遅延させることにより前記第2のクロックを生成するレプリカバッファとを含むことを特徴とする請求項1乃至3のいずれか一項に記載のDLL回路。
- 前記第5のクロックは、データを外部に出力するための出力バッファの動作タイミングを定めるものであり、前記レプリカバッファは、前記出力バッファと同じ回路構成を有していることを特徴とする請求項4に記載のDLL回路。
- 前記第1のクロックが外部クロックであることを特徴とする請求項1乃至5のいずれか一項に記載のDLL回路。
- 外部から供給される前記第1のクロックに同期してデータを出力する半導体装置であって、請求項5に記載のDLL回路と、前記第5のクロックに同期してデータを出力する出力バッファとを備えることを特徴とする半導体装置。
- 請求項7に記載の半導体装置を備えるデータ処理システム。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007275470A JP5448324B2 (ja) | 2007-10-23 | 2007-10-23 | Dll回路及びこれを備える半導体装置、並びに、データ処理システム |
US12/289,137 US7755401B2 (en) | 2007-10-23 | 2008-10-21 | Semiconductor device including DLL circuit, and data processing system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007275470A JP5448324B2 (ja) | 2007-10-23 | 2007-10-23 | Dll回路及びこれを備える半導体装置、並びに、データ処理システム |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2009105657A JP2009105657A (ja) | 2009-05-14 |
JP5448324B2 true JP5448324B2 (ja) | 2014-03-19 |
Family
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Family Applications (1)
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JP2007275470A Expired - Fee Related JP5448324B2 (ja) | 2007-10-23 | 2007-10-23 | Dll回路及びこれを備える半導体装置、並びに、データ処理システム |
Country Status (2)
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US (1) | US7755401B2 (ja) |
JP (1) | JP5448324B2 (ja) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011061457A (ja) * | 2009-09-09 | 2011-03-24 | Elpida Memory Inc | クロック生成回路及びこれを備える半導体装置並びにデータ処理システム |
JP2011199617A (ja) * | 2010-03-19 | 2011-10-06 | Elpida Memory Inc | クロック生成回路及びこれを備える半導体装置、並びに、クロック信号の生成方法 |
US8604850B2 (en) * | 2011-03-29 | 2013-12-10 | Micron Technology, Inc. | Measurement initialization circuitry |
KR20150105994A (ko) * | 2013-01-16 | 2015-09-18 | 피에스4 뤽스코 에스.에이.알.엘. | 출력 신호 생성 장치, 반도체 장치 및 출력 신호 생성 방법 |
US9325491B2 (en) * | 2014-04-15 | 2016-04-26 | Triquint Semiconductor, Inc. | Clock generation circuit with dual phase-locked loops |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100366618B1 (ko) * | 2000-03-31 | 2003-01-09 | 삼성전자 주식회사 | 클럭 신호의 듀티 사이클을 보정하는 지연 동기 루프 회로및 지연 동기 방법 |
JP3404369B2 (ja) * | 2000-09-26 | 2003-05-06 | エヌイーシーマイクロシステム株式会社 | Dll回路 |
KR100401522B1 (ko) * | 2001-09-20 | 2003-10-17 | 주식회사 하이닉스반도체 | 듀티 보정 회로 |
US6605969B2 (en) * | 2001-10-09 | 2003-08-12 | Micron Technology, Inc. | Method and circuit for adjusting the timing of ouput data based on an operational mode of output drivers |
US6777990B2 (en) * | 2002-03-19 | 2004-08-17 | Infineon Technologies Ag | Delay lock loop having an edge detector and fixed delay |
KR100515071B1 (ko) * | 2003-04-29 | 2005-09-16 | 주식회사 하이닉스반도체 | 디엘엘 장치 |
KR100631166B1 (ko) * | 2003-05-31 | 2006-10-02 | 주식회사 하이닉스반도체 | 지연고정 시간을 줄인 레지스터 제어 지연고정루프 |
JP3859624B2 (ja) * | 2003-07-31 | 2006-12-20 | エルピーダメモリ株式会社 | 遅延回路と遅延同期ループ装置 |
KR100578232B1 (ko) * | 2003-10-30 | 2006-05-12 | 주식회사 하이닉스반도체 | 지연 고정 루프 |
KR100696957B1 (ko) * | 2005-03-31 | 2007-03-20 | 주식회사 하이닉스반도체 | 클럭 듀티 조정 회로, 이를 이용한 지연 고정 루프 회로 및그 방법 |
KR100810070B1 (ko) * | 2005-09-29 | 2008-03-06 | 주식회사 하이닉스반도체 | 지연고정루프 |
KR100776906B1 (ko) * | 2006-02-16 | 2007-11-19 | 주식회사 하이닉스반도체 | 파워다운 모드 동안 주기적으로 락킹 동작을 실행하는기능을 가지는 dll 및 그 락킹 동작 방법 |
JP2007243735A (ja) | 2006-03-09 | 2007-09-20 | Elpida Memory Inc | Dll回路及びそれを備えた半導体装置 |
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2007
- 2007-10-23 JP JP2007275470A patent/JP5448324B2/ja not_active Expired - Fee Related
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2008
- 2008-10-21 US US12/289,137 patent/US7755401B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
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US7755401B2 (en) | 2010-07-13 |
JP2009105657A (ja) | 2009-05-14 |
US20090102527A1 (en) | 2009-04-23 |
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