JP5440221B2 - Manufacturing method of laminated structure of semiconductor device - Google Patents

Description

The present invention relates to a three-dimensional integrated circuit device, in which electrical connection between upper and lower circuit boards is performed by metal filling by bottom-up plating in through-holes instead of bumps and bonding electrodes. the method for producing a laminated structure.

  Conventionally, in a semiconductor integrated circuit, the degree of integration per chip has been improved by a fine processing technique of a semiconductor element. However, with the increase in power consumption due to the miniaturization of elements and the increase in chip area due to the increase in functionality, it has become difficult to improve the performance of semiconductor integrated circuits only with the microfabrication technology. In addition, manufacturing costs and capital investment are also rising.

Against this background, in recent years, three-dimensional integration technology has attracted attention as a semiconductor integration technology that does not rely on microfabrication technology. The three-dimensional integration technique is an integration technique in which various semiconductor integrated circuit substrates (semiconductor devices) are stacked in the thickness direction (longitudinal direction) and the circuits of each layer are electrically connected by wiring. An integrated circuit using this technique is called a three-dimensional integrated circuit. Three-dimensional integrated circuits enable "miniaturization", "high speed", "high integration (high density)", "high parallelism", and "low power consumption" of integrated circuits. because it can integrate produced in different substrate materials and processes elements, conventional S ystem o n C hip (hereinafter, referred to as SoC) than technology also allows the realization of "low cost" and "multifunctional" chips .

As a technology for stacking chips and substrates, a stacking method that allows through-electrodes (Through Silicon Via (TSV) and Die Side Via (DSV)) and bonding electrodes to be formed on the substrate and allows the layers to be multilayered while interconnecting each substrate. Has been proposed (see, for example, Patent Documents 1 and 2).
The characteristics of the structure obtained by this laminating method are as follows: (1) Bonding electrodes are provided at both ends of the substrate on which the through electrodes are formed in advance, and the bonding electrodes between the substrates are bonded to each other to connect the circuits of the respective substrates to each other. And (2) filling the gap between the substrates with an underfill material to reinforce the strength of the laminate and protect it from the external environment.

  Also, without using bonding electrodes, the metal (Cu) wiring exposed on the surface of the flat semiconductor substrate and the insulating film are activated and directly bonded to ensure the bonding between chips and the conduction between the chips in a lump. Has also been proposed (see, for example, Patent Documents 3 and 4).

Japanese Patent Laid-Open No. 11-261001 JP 2001-326326 A JP 2000-299379 A JP 2002-26123 A

However, the techniques relating to the three-dimensional integrated circuit device described in Patent Documents 1 and 2 have the following problems.
As a first problem, it is difficult to reduce the resistance of the wiring connecting the substrates.
That is, the through wiring of the prior art is composed of a through electrode and a bonding electrode. Therefore, the resistance of the through wiring includes not only the resistance of the through electrode material and the resistance of the connecting electrode material but also the contact resistance at the interface between the through electrode and the connecting electrode and between the connecting electrode and the connecting electrode. . For the same reason, degradation of transmission characteristics at the interface between different materials and electromigration resistance are reduced. Furthermore, when the through electrodes are formed at a higher density, the characteristic deterioration cannot be ignored.

As a second problem, it is difficult to reduce the manufacturing cost in the lamination process.
That is, for example, firstly, a process of forming a buried wiring for a through electrode is performed, secondly, a process of forming a bonding electrode on the surface of the semiconductor substrate, and thirdly, a process of pasting bonding electrodes together Fourth, the step of injecting the underfill material is performed, fifth, the step of thinning the substrate to cue the bottom of the through electrode, and sixth, the second step at the bottom of the through electrode In consideration of the structure of stacking by repeating the third to sixth steps, the above-mentioned steps are also subdivided into fine steps. By accumulating the process yield, the yield of the finally obtained product is lowered.

  In addition, even if a bonding failure occurs in the bonding electrode, this bonding failure is not found until completion. Therefore, it is necessary to design the electrode for inter-substrate interconnection in advance with redundancy, and therefore the design cost is reduced. As a result of the increase and the increase in chip size, the chip share per wafer is reduced.

As a third problem, it is difficult to miniaturize wiring.
This is because the bonding electrode used in the prior art is not miniaturized.
Further, in the techniques described in Patent Documents 3 and 4, since dishing of Cu occurs during chemical mechanical polishing (CMP) used for planarizing the substrate surface, it is possible to secure the bonding and conduction collectively. It has become difficult.

A fourth problem is that when a stacked substrate is defective, it is difficult to remove the defective substrate when it is desired to replace the defective substrate.
That is, in the three-dimensional integrated circuit, the substrate of each layer is firmly bonded by the bump and the underfill resin, but in this case, the substrate cannot be removed. There is a structure in which chips are joined only with solder bumps as a partly removable structure, but it is necessary to heat and remove the stacked chips one by one from the top, and there is residue in the pad part after removing the bumps There are problems such as the possibility of remaining and the surface after removal being uneven.

The present invention has been made in order to solve such problems, and its object is to provide a method for producing a laminated structure of a semiconductor device comprising a three-dimensional integrated circuit device structure having a seamless through wiring.

The laminated structure of the semiconductor device of the present invention is
A semiconductor substrate having a semiconductor element and a wiring group connected to the semiconductor element;
A through electrode provided in a thickness direction of the semiconductor substrate;
A recess provided on one of the front and back surfaces of the semiconductor substrate;
Relocation wiring provided in the recess and electrically connected to the through electrode and extending in one surface direction of the front and back surfaces, and
A semiconductor device in which one of the through electrode and the rearrangement wiring is connected to at least a part of the wiring group is stacked in a plurality of layers,
The side opposite to the rearrangement wiring of the through electrode in one of the semiconductor devices stacked vertically and the rearrangement wiring in the other semiconductor device are formed continuously, and The through electrode in the one semiconductor device and the through electrode connected to the rearrangement wiring in the other semiconductor device are formed at different positions in a plan view.

According to the stacked structure of the semiconductor device, the side opposite to the rearrangement wiring of the through electrode in one semiconductor device among the semiconductor devices stacked one above the other and the rearrangement wiring in the other semiconductor device are continuous. Thus, the through electrode in one semiconductor device and the rearrangement wiring in the other semiconductor device are formed seamlessly. Therefore, the resistance is sufficiently reduced not only between the through electrode in the same semiconductor device and the rearrangement wiring electrically connected thereto, but also between the through electrode connected between different semiconductor devices and the rearrangement wiring. Will be.
Therefore, the resistance of the through wiring can be reduced, and the transmission characteristics and electromigration resistance can be improved.
In addition, since there is no bonding electrode, it is possible to miniaturize the through wiring composed of the through electrode only by miniaturizing the through electrode.

In the laminated structure of the semiconductor device,
The one semiconductor device and / or the other semiconductor device is provided with a plurality of sets of through electrodes and rearrangement wirings electrically connected thereto,
The one semiconductor device and / or the other semiconductor device is provided with a set of through-electrodes that are independent of each other without being continuous and a relocation wiring that is electrically connected thereto. It may be.

  In this way, a part of the semiconductor element in one semiconductor device and a part of the semiconductor element in the other semiconductor device are operated together by a combination of the through electrode and the rearrangement wiring that are continuous between these semiconductor devices. In addition, the other part of the semiconductor element in one semiconductor device and the other part of the semiconductor element in the other semiconductor device can be connected to the through-electrodes that are independent of each other without being continuous between these semiconductor devices. It becomes possible to operate independently by the combination with the placement and routing.

In the laminated structure of the semiconductor device,
The semiconductor devices stacked above and below may be directly continuous only between the through electrode and the rearrangement wiring that are continuous between them.
In this way, when a defect occurs in one of the stacked semiconductor devices, the defective semiconductor device can be easily obtained by removing only one of the directly connected through electrode and rearrangement wiring. Can be exchanged.

In the laminated structure of the semiconductor device,
The recess is provided at a position spaced from the through electrode,
The rearrangement wiring in the recess may be electrically connected to the through electrode through at least a part of the wiring in the wiring group.
If it does in this way, it will become possible to design the formation position of a crevice more freely.

The method for manufacturing a laminated structure of a semiconductor device of the present invention includes:
Providing a first semiconductor substrate having a semiconductor element and a wiring group connected to the semiconductor element;
Forming a first through hole penetrating in the thickness direction in the first semiconductor substrate;
Forming a first recess on one of the front and back surfaces of the first semiconductor substrate;
Providing a first recess-side conductive layer for energization in the first recess;
Providing a first surface-side conductive layer for energization on the other side of the front and back surfaces of the first semiconductor substrate;
Using the first surface side conductive layer and the first recess side conductive layer as a seed layer, a first through electrode is formed in the first through hole, and the front and back surfaces are formed in the first recess. Forming a rearrangement wiring extending in one of the surface directions,
In the step of forming the first through hole or the step of forming the first recess, a manufacturing process of the first semiconductor device in which at least a part of the wirings in the wiring group is exposed;
Preparing a second semiconductor substrate having a semiconductor element and a wiring group connected to the semiconductor element;
Passing through the second semiconductor substrate in the thickness direction and forming a second through hole; and
Forming a second recess on one side of the front and back surfaces of the second semiconductor substrate;
Forming a second recess-side conductive layer for energization in the second recess,
In the step of forming the second through hole or the step of forming the second recess, a manufacturing process of the second semiconductor device in which at least a part of the wirings in the wiring group is exposed;
The second semiconductor device manufactured in the manufacturing process of the second semiconductor device is placed on the first rearrangement wiring of the first semiconductor device on the first semiconductor device manufactured in the manufacturing process of the first semiconductor device. Laminating the second through hole so that the second through hole is in a different position from the first through hole in a plan view.
Using the first rearrangement wiring and the second recess side conductive layer as a seed layer, a second through electrode is formed in the second through hole, and the front and back surfaces are formed in the second recess. Forming a rearrangement wiring extending in one surface direction.

According to this method for manufacturing a laminated structure of a semiconductor device, the process can be shortened, and thereby the yield of the lamination process can be improved.
In other words, in the past, for example, the seven steps of lamination process (through hole formation → metal (conductor) filling → wafer grinding (for exposing the bottom of the through hole) → bump formation → bump bonding → underfill resin bonding → back metallization) In this manufacturing method, the number of steps can basically be reduced to (through-hole formation → stacking → plating metal filling). Thereby, it becomes possible to improve the yield by a lamination process.

  Further, the connection state between the semiconductor devices of the through wiring composed of the through electrode and the rearrangement wiring can also be determined from the plating filling condition, and replating can be performed when the plating growth is poor. Therefore, the area of the redundant circuit portion on the semiconductor substrate can be reduced, or the circuit function itself can be simplified. Thereby, it becomes possible to suppress an increase in design cost and chip manufacturing cost.

Furthermore, by adopting the bottom-up plating method, it is possible to fill the through hole with a metal material without forming selectivity in the plating solution, and to form a metal wiring without a void. . Thereby, it is possible to reduce the cost for forming the through wiring. Naturally, even if the semiconductor substrate including the through hole is made thinner, the metal material is filled into the fine (high aspect) through hole only by plating as in the conventionally known multilayer wiring forming process without using a CVD apparatus. It is also possible to follow.
Further, since the semiconductor devices are joined in a region other than the through wiring, a joining process for only this portion can be arbitrarily selected. Naturally, since the through wiring is formed after the bonding between the semiconductor devices, it is possible to suppress the bonding failure of the conductor region.

In the method for manufacturing a laminated structure of the semiconductor device,
In the first semiconductor device and / or the second semiconductor device, a plurality of sets of through electrodes and rearrangement wirings electrically connected thereto are provided,
The first semiconductor device and / or the second semiconductor device may be provided with a set of penetrating electrodes that are independent without being continuous between the semiconductor devices and a relocation wiring electrically connected thereto. Good.

  According to this configuration, a part of the semiconductor element in the first semiconductor device and a part of the semiconductor element in the second semiconductor device operate together by a set of the through electrode and the rearrangement wiring that are continuous between these semiconductor devices. In addition, the other part of the semiconductor element in the first semiconductor device and the other part of the semiconductor element in the second semiconductor device are connected to the through-electrodes that are independent without being continuous between these semiconductor devices. It becomes possible to operate independently by the combination with the placement and routing.

In the method for manufacturing a laminated structure of the semiconductor device,
You may make it make the said 1st semiconductor device and 2nd semiconductor device laminated | stacked up and down directly continue only between the penetration electrode and rearrangement wiring which continue between these.
In this way, when a defect occurs in one of the stacked semiconductor devices, the defective semiconductor device can be easily obtained by removing only one of the directly connected through electrode and rearrangement wiring. Can be exchanged.

  According to the present invention, it is possible to improve the reliability of the through wiring composed of the through electrode and the rearrangement wiring of the laminated structure that becomes a three-dimensional integrated circuit, and to greatly simplify the lamination process. Furthermore, it is possible to repair defective chips.

1 is a cross-sectional structure diagram of a semiconductor device as a basic configuration of the present invention. FIG. 2 shows a cross-sectional structure in a main process step of the semiconductor device manufacturing method shown in FIG. FIG. 2 shows a cross-sectional structure in a main process step of the semiconductor device manufacturing method shown in FIG. FIG. 6 is a cross-sectional structure diagram illustrating a modification of the semiconductor device illustrated in FIG. 1. FIG. 10 is a cross-sectional structure diagram illustrating another modification of the semiconductor device illustrated in FIG. 1. It is a section construction figure of a 1st embodiment of a layered structure of the present invention. FIG. 7 shows a cross-sectional structure in a main process step of the manufacturing method of the laminated structure shown in FIG. 6 in order of processes. FIG. 7 is a cross-sectional structure diagram illustrating a modified example of the laminated structure illustrated in FIG. 6. It is sectional structure drawing of 2nd Embodiment of the laminated structure of this invention. The cross-sectional structure in the main process step of the manufacturing method of the laminated structure shown in FIG. 9 is shown in process order. FIG. 10 is a cross-sectional structure diagram illustrating a modified example of the laminated structure illustrated in FIG. 9. It is sectional drawing of 3rd Embodiment of the laminated structure of this invention, and process drawing for demonstrating replacement | exchange with a non-defective board | substrate when there exists a defective board | substrate in a laminated structure. FIG. 13 is a cross-sectional structure diagram illustrating a modified example of the multilayer structure illustrated in FIG. FIG. 13 is a cross-sectional structure diagram illustrating another modification of the laminated structure illustrated in FIG. FIG. 13 is a cross-sectional structure diagram illustrating another modification of the laminated structure illustrated in FIG.

Hereinafter, the present invention will be described in detail with reference to the drawings. In each drawing used for the following description, the scale of each member is appropriately changed to make each member a recognizable size.
"Basic configuration and manufacturing process"
First, a basic configuration and a manufacturing process of a laminated structure of a semiconductor device according to the present invention will be described.
FIG. 1 is a cross-sectional structure diagram of a semiconductor device as a basic configuration of the present invention. 2 and 3 show the cross-sectional structures in the main process steps of the semiconductor device manufacturing method shown in FIG.

As shown in FIG. 1, a semiconductor device 1 that is a basic configuration of the present invention includes a semiconductor substrate 11, a multilayer wiring layer 12 formed on the semiconductor substrate 11, and a through wiring 5. is there.
The semiconductor substrate 11 is made of a silicon substrate on which a semiconductor element (not shown) is formed. The multilayer wiring layer 12 is formed by forming a wiring group composed of a plurality of wirings 13 that are electrically connected to the semiconductor element, and covering these wirings 13 with an insulating film.

The through wiring 5 is formed in the semiconductor substrate 11 and the multilayer wiring layer 12 through the thickness direction thereof. The through wiring 5 includes a through electrode 6 formed in the semiconductor substrate 11 and the multilayer wiring layer 12 and a rearrangement wiring 7 formed in the surface layer portion of the multilayer wiring layer 12. That is, the through electrode 6 is formed in the through hole 8 formed through the semiconductor substrate 11 and the multilayer wiring layer 12 in the thickness direction, and the rearrangement wiring 7 is formed on the surface layer portion of the multilayer wiring layer 12. It is formed in the recess 9 formed in the above.

The recess 9 is formed to extend in the surface direction on the surface of the multilayer wiring layer 12, and communicates with the through hole 8 at a part thereof. Under such a configuration, the through electrode 6 and the rearrangement wiring 7 are continuously formed. The rearrangement wiring 7 is formed in the multilayer wiring layer 12 so as to be connected to a part of the wirings 13 in the wiring group. Therefore, the through wiring 5 is electrically connected to a semiconductor element connected to the wiring 13.
An insulating film 14 is formed on the back surface of the semiconductor substrate 11, that is, the surface opposite to the multilayer wiring layer 12 and the inner surface of the through hole 8 in the semiconductor substrate 11.

In order to manufacture such a semiconductor device 1, first, a semiconductor substrate 11 having a multilayer wiring layer 12 formed on one surface (front surface) as shown in FIG. 2A is prepared.
Next, as shown in FIG. 2B, the back surface side of the semiconductor substrate 11 is etched to form a hole 8a.
Next, as shown in FIG. 2C, an insulating film (oxide film) 14 is formed on the back surface of the semiconductor substrate 11 and in the hole 8a by a thermal oxidation method or the like.

Next, as shown in FIG. 2D, a recess 9 is formed in the surface layer portion of the multilayer wiring layer 12 by etching or the like. At this time, in this example, the wiring 13 which is a part of the wiring group is exposed in the recess 9.
Next, as shown in FIG. 2 (e), a recess-side conductive layer 15 is formed on the surface of the multilayer wiring layer 12 and the inner surface of the recess 9. At this time, the recess-side conductive layer 15 is also formed on the wiring 13 exposed in the recess 9.

Next, as shown in FIG. 2 (f), the multilayer wiring layer 12 is etched to form a hole that allows the hole 8 a to communicate with the recess 9, thereby forming a through hole 8 that communicates with the recess 9. To do.
Next, as shown in FIG. 3G, the support substrate 17 having the surface-side conductive layer 16 for filling the plating metal is disposed on the back surface of the semiconductor substrate 11, and the surface-side conductive layer 16 is in contact with the semiconductor substrate 11. Paste. For this attachment, an attachment layer (not shown) or the like patterned so as to remove at least a portion corresponding to the through hole 8 is used.

  Next, the semiconductor substrate 11 is immersed in a plating solution (not shown), and a plating electrode disposed so as to be opposed to each other is used, and the surface-side conductive layer 16 is energized as a seed layer, thereby bottom-up plating. I do. Thereby, as shown in FIG. 3H, the metal material 5a (for example, copper) is sequentially filled from the back surface side of the semiconductor substrate 11 toward the multilayer wiring layer 12 side.

  Then, when the filling of the plating metal by bottom-up plating proceeds and reaches the recess-side conductive layer 15 in the recess 9 formed in the multilayer wiring layer 12, the recess-side conductive layer 15 is also energized as a seed layer. As shown in FIG. 3I, the concave portion 9 is also filled with the metal material 5a. Thereby, a continuous through wiring layer is formed from the inside of the through hole 8 to the inside of the recess 9. Note that, as described above, the wiring 13 that is a part of the wiring group is exposed in the recess 9, so that the exposed wiring 13 becomes conductive to the metal material 5 a filled in the recess 9.

Next, as shown in FIG. 3 (j), the excess metal material 5 a on the surface side of the multilayer wiring layer 12 is removed by chemical mechanical polishing (CMP), and the surface of the multilayer wiring layer 12 at a portion excluding the recess 9. To expose.
Thereafter, as shown in FIG. 3 (k), the support substrate 17 is removed from the back surface of the semiconductor substrate 11. Thereby, the through wiring 5 is obtained which penetrates from the back surface of the semiconductor substrate 11 to the surface side of the multilayer wiring layer 12 and further extends and rewires on the surface side in the surface direction (lateral direction). That is, the through wiring 5 including the through electrode 6 and the rearrangement wiring 7 is formed, whereby the semiconductor device 1 shown in FIG. 1 is obtained.

Note that the semiconductor device serving as the basic configuration of the present invention can have various configurations other than the configuration shown in FIG.
For example, in FIGS. 1, 3 (j), and 3 (k), the rearrangement wiring 7 is formed so as to fill the entire recess 9, but the bottom and side portions of the recess 9 are not filled without filling the entire recess 9. Only the rearrangement wiring 7 may be formed.

Further, as shown in FIG. 4, the direction of the semiconductor substrate 11 is turned upside down, the recess 9 is formed on the back surface (upper surface) side of the semiconductor substrate 11, the rearrangement wiring 7 is formed therein, and the surface of the multilayer wiring layer 12 is formed. One end surface of the through electrode 6 may be exposed on the (lower surface). In that case, the penetrating electrode 6 side is connected to a part of the wirings 13 in the wiring group.
In the present invention, the insulating film 14 formed on the semiconductor substrate 11 can also be regarded as a part of the semiconductor substrate 11. Therefore, instead of forming the recess 9 on the back surface (upper surface) side of the semiconductor substrate 11 as shown in FIG. 4, the recess 9 is formed in the insulating film 14 located on the back surface side of the semiconductor substrate 11. In addition, the rearrangement wiring 7 may be formed.

  Further, as shown in FIG. 5, the recess 9 formed in the multilayer wiring layer 12 can be formed at a position separated from the through electrode 6, that is, not communicated with the through hole 8. In that case, the rearrangement wiring 7 in the recess 9 may be electrically connected to the through electrode 6 through at least a part of the wirings 13 in the wiring group in the multilayer wiring layer 12. By configuring in this way, the formation position of the recess 9 can be designed more freely.

“First Embodiment”
Next, a first embodiment of a stacked structure of a semiconductor device according to the present invention will be described.
FIG. 6 is a cross-sectional structure diagram of the first embodiment of the laminated structure. FIG. 7 shows a cross-sectional structure in a main process step in the order of steps in the method for manufacturing the laminated structure shown in FIG. In the following, an example in which the semiconductor devices 1 having the configuration shown in FIG. 1 are stacked in two stages and stacked as shown in FIGS. 6 and 7 will be described. However, the semiconductor devices 1 may be stacked in three or more stages. Of course.

As shown in FIG. 6, the stacked structure 20 of the present embodiment is formed by stacking the second semiconductor device 1B having the configuration shown in FIG. 1 on the first semiconductor device 1A having the configuration shown in FIG. A first semiconductor device 1A and a second semiconductor device 1B are stacked one above the other.
In particular, the rearrangement wiring 7 in the through wiring 5 of the first semiconductor device 1A and the through electrode 6 in the through wiring 5 of the second semiconductor device 1B are formed continuously and seamlessly. Further, the through electrodes 6 in the first semiconductor device 1A and the through electrodes 6 in the second semiconductor device 1B are formed and arranged at different positions in plan view.
The first semiconductor device 1A and the second semiconductor device 1B may be the same or different in the outer diameter of the through electrode 6, the thickness of the semiconductor substrate 11, the circuit configuration, and the like.

  In order to manufacture such a laminated structure 20, first, as shown in FIG. 7A, the upper surface (on the multilayer wiring layer 12 side) of the first semiconductor device 1A in the state shown in FIG. The lower surface (the back surface of the semiconductor substrate 11) of the second semiconductor device 10B in the state shown in FIG. At that time, the lower opening of the through hole 8 of the second semiconductor device 10B is positioned on the rearrangement wiring 7 of the first semiconductor device 1A and not on the through electrode 6 of the first semiconductor device 1A. Perform alignment.

  Next, this laminated body is immersed in a plating solution (not shown) having the same composition as that of the formation of the first semiconductor device 1A, and bottom-up plating is performed using plating electrodes arranged to face each other. Then, since the through wiring 5 has already been formed in the first semiconductor device 1A, and the surface side conductive layer 16 is joined at the bottom thereof, by energizing the surface side conductive layer 16 in this state, As shown in FIG. 7B, the metal material 5a is sequentially filled from the back surface side of the second semiconductor device 1B to the multilayer wiring layer 12 side as shown in FIG. can do. When the metal material 5a is filled in this way, particularly the portion where the metal material 5a is added is substantially seamless and formed in a continuous state.

  When the filling of the plating metal by bottom-up plating proceeds and reaches the concave side conductive layer 15 in the concave portion 9 formed in the multilayer wiring layer 12 of the second semiconductor device 10B, the concave side conductive layer 15 is also seeded. By energizing as a layer, the recess 9 is filled with the metal material 5a as shown in FIG. Thereby, a continuous through wiring layer is formed from the inside of the through hole 8 to the inside of the recess 9. As shown in FIG. 7A, the wiring 13 which is a part of the wiring group is exposed in the recess 9, so that the exposed wiring 13 is formed on the metal material 5a filled in the recess 9. It becomes conductive.

Next, as shown in FIG. 7D, excess metal material on the surface side of the multilayer wiring layer 12 is removed by chemical mechanical polishing (CMP), and the surface of the multilayer wiring layer 12 in a portion excluding the concave portion 9 is removed. Expose. Thus, the second semiconductor device 10B becomes the semiconductor device 1B having the basic configuration shown in FIG.
Thereafter, as shown in FIG. 7E, the support substrate 17 is removed from the back surface of the first semiconductor device 1A. Thereby, the stacked structure 20 of the semiconductor device shown in FIG. 6 obtained by stacking the second semiconductor device 1B on the first semiconductor device 1A is obtained.

  In the laminated structure 20 obtained in this way, the side opposite to the rearrangement wiring of the through electrode 6 in the second semiconductor device 1B among the semiconductor devices 1A and 1B laminated vertically, the first Since the rearrangement wiring 7 in the semiconductor device 1A is continuously formed of the same metal material without a seam, the through electrode 6 in the second semiconductor device 1B and the rearrangement wiring 7 in the first semiconductor device 1A are joined together. It will be formed without.

Accordingly, not only between the through electrode 6 in the same semiconductor device 1 and the rearrangement wiring 7 electrically connected thereto, but also between the through electrode 6 and the rearrangement wiring 7 connected between different semiconductor devices 1A and 1B. In this case, the resistance is sufficiently reduced.
Therefore, the resistance of the through wiring 5 can be reduced, and the transmission characteristics and electromigration resistance can be improved.
Further, since there is no bonding electrode, the through wiring 5 made of the through electrode 6 can be miniaturized only by reducing the diameter of the through electrode 6.

  Moreover, in such a manufacturing method of the laminated structure 20, the process can be shortened, and thereby the yield of the lamination process can be improved. In other words, in the past, for example, the seven steps of lamination process (through hole formation → metal (conductor) filling → wafer grinding (for exposing the bottom of the through hole) → bump formation → bump bonding → underfill resin bonding → back metallization) In the method of this embodiment, the number of steps can be basically reduced to (through-hole formation → stacking → plating metal filling). Thereby, the yield by a lamination process can be improved.

  Moreover, the connection state between the semiconductor devices 1A and 1B of the through wiring 5 composed of the through electrode 6 and the rearrangement wiring 7 can also be determined from the plating filling condition, and replating can be performed when the plating growth is poor. . Therefore, the area of the redundant circuit portion on the semiconductor substrate 11 can be reduced, or the circuit function itself can be simplified. Thereby, an increase in design cost and chip manufacturing cost can be suppressed.

Furthermore, by adopting the bottom-up plating method, it is possible to fill the through hole 8 with a metal material without giving selectivity to the plating solution, and there is no void in the metal wiring (rearrangement wiring 7). ) Can be formed. Thereby, the cost concerning formation of the penetration wiring 5 can be reduced. Naturally, even if the semiconductor substrate 11 including the through hole 8 is made thinner, a metal material can be formed into the fine (high aspect) through hole 8 only by plating as in a conventionally known multilayer wiring formation process without using a CVD apparatus. Can also be filled.
Further, since the semiconductor devices 1A and 1B are joined in a region other than the through wiring 5, the joining process of only this portion can be arbitrarily selected. Naturally, since the through wiring 5 of the upper second semiconductor device 1B is formed after the bonding between the semiconductor devices 1A and 1B, it is possible to suppress the bonding failure of the conductor region.

  Note that the bonding between the semiconductor devices 1A and 1B described in the manufacturing process is a bonding between the semiconductor devices 1A and 1B facing each other at the time of stacking and a plane other than the place where the through wiring 5 is formed. Attached. At this time, as a pasting method, a known method such as direct bonding, adhesion, or close contact may be employed.

Specifically, in the case of direct bonding, the insulating layers whose surfaces are activated are directly bonded to each other.
In the bonding method, various bonding materials and metal materials are formed on only one substrate (device) or both substrates (devices) on the corresponding plane of the semiconductor devices 1A and 1B excluding the position of the through wiring 5. Alternatively, it is also possible to adopt a method such as bonding (diffusion bonding) at a predetermined bonding temperature, vacuum degree, and pressure with an adhesive sheet sandwiched therebetween.

  In the adhesion method, in the corresponding plane of the semiconductor devices 1A and 1B excluding the position of the through wiring 5, the planes are brought into direct contact with each other, or an adhesion layer is formed on only one substrate or both substrates, or is adhered. In addition, it is possible to employ a method of pressing and adhering in a normal temperature, normal pressure, or vacuum with a close contact sheet interposed therebetween. For this reason, it is needless to say that a method is selected that can suppress the seepage between the substrates (devices) when the plated metal material is filled. The selection of these methods can be appropriately selected in consideration of the required strength of the laminated structure or the ease of repair (replacement of defective substrates after lamination).

  For the semiconductor devices 1A and 1B shown in FIG. 6 and FIG. 7, the cross-sectional structure shown in FIG. 1 and the manufacturing process shown in FIG. 2 and FIG. 3 are referred to. Needless to say, the structure of 1B may be replaced with the structure shown in FIGS. In addition, FIG. 6 shows a stacked structure in which two layers are stacked. However, as described above, three or more layers can be stacked in the same manner.

  Furthermore, in the present embodiment, the metal material of the through wiring 5 of the upper second semiconductor device 1B may be different from the metal material of the through wiring 5 of the lower first semiconductor device 1A. In that case, as shown in FIG. 8, before the second semiconductor substrate 1B (10B) is stacked, at least the second semiconductor substrate 1B (10B) penetrates on the surface of the rearrangement wiring 7 of the first semiconductor substrate 1A. A seed layer 18 made of a metal material to be embedded in the second semiconductor device 1B is formed in advance on a portion corresponding to the bottom of the hole 8 by using a method such as a CVD method, a sputter film formation method, or a vapor deposition method. Further, a recess-side conductive layer (not shown) made of the same kind of metal material is also formed as a seed layer in the recess 9 of the second semiconductor device 1B.

  Thereafter, the same metal material as that of the seed layer 18 is filled in the through holes 8 and the recesses 9 in the same manner as in the manufacturing process shown in FIG. 7, so that the through wiring of the first semiconductor device 1A as shown in FIG. The through wiring 5 can be formed in the second semiconductor device 1 </ b> B with a metal material different from 5 in a state of being continuously connected to the through wiring 5 seamlessly.

“Second Embodiment”
Next, a second embodiment of the laminated structure of the semiconductor device according to the present invention will be described.
FIG. 9 is a cross-sectional structure diagram of the second embodiment of the laminated structure. FIG. 10 shows a cross-sectional structure in a main process step in the order of steps in the method for manufacturing the laminated structure shown in FIG. Hereinafter, as illustrated in FIGS. 9 and 10, an example in which the semiconductor devices having the configuration illustrated in FIG. 1 are stacked and stacked in four stages will be described.

  As shown in FIG. 9, the stacked structure 30 of the present embodiment has a second semiconductor device 1D, a third semiconductor device 1E, and a fourth semiconductor device on the first semiconductor device 1C having the configuration shown in FIG. 1F is sequentially laminated, and the second laminated structure 20B is similarly laminated on the first laminated structure 20A corresponding to the first embodiment having the configuration shown in FIG.

  In this laminated structure 30, a plurality of through wirings 5 each including the through electrode 6 and the rearrangement wiring 7 electrically connected thereto are provided in each of the first semiconductor device 1C to the fourth semiconductor device 1F. It is provided one by one. Further, between some of the semiconductor devices, in the embodiment shown in FIG. 9, between the second semiconductor device 1D and the third semiconductor device 1E, that is, between the first stacked structure 20A and the second stacked structure 20B. In between, a set of penetrating wirings 5A and 5B arranged independently without being continuous with each other is provided.

  In the second stacked structure 20B, the through-electrodes 6 and 6 are directly connected between the third semiconductor device 1E and the fourth semiconductor device 1F without the rearrangement wiring 7 therebetween. Two sets are formed. However, if these continuous wirings 6 and 6 are regarded as one through electrode, these wirings 5C are one through wiring independent by this through electrode and the rearrangement wiring 7 formed in the fourth semiconductor device 1F. 5 can be considered.

  In order to manufacture such a laminated structure 30, first, as shown in FIG. 10 (a), the upper surface of the laminated structure 20A in the state shown in FIG. 7 (d) (the second semiconductor device 1D). The second laminated structure 20B in which the metal filling is performed only partially is attached to the surface of the multilayer wiring layer 12 side. Specifically, the portion where the wiring 5C is formed, that is, the portion formed by the continuous through holes 8 and 8 and the concave portion 9 for forming the wiring 5C is not filled with metal, and the first stacked body 20A is not filled. The through wiring 5B provided independently of the through wiring 5A without being continuous is filled with metal in advance to finish its formation.

Then, as shown in FIG. 10A, the through wiring 5B is not continuous (connected) to each rearrangement wiring 7 of the first laminated structure 20A, and the through hole 8 for forming the wiring 5C is formed. Alignment is performed so that the lower opening is positioned on the rearrangement wiring 7 of the first stacked structure 20A (second semiconductor device 1D).

  Next, this laminated body is immersed in a plating solution (not shown) having the same composition as that for forming the first laminated structure 20A, and bottom-up plating is performed using plating electrodes arranged to face each other. . Then, since the through wiring 5 is already formed in the first stacked structure 20A, and the surface side conductive layer 16 is joined at the bottom thereof, by energizing the surface side conductive layer 16 in this state, Using the surface of the rearrangement wiring 7 of the through wiring 5 that is conductive to the electrode as an electrode, the metal material is sequentially applied from the back surface side of the second laminated structure 20B to the multilayer wiring layer 12 side as shown in FIG. 10B. Can be filled. When the metal material is filled in this way, particularly in the portion where the metal material is added, there is substantially no seam, and the continuous wiring 5C is obtained.

  When the filling of the plating metal by bottom-up plating proceeds and reaches the concave side conductive layer 15 in the concave portion 9 formed in the multilayer wiring layer 12 of the fourth semiconductor device 1F, the concave side conductive layer 15 is also seeded. By energizing as a layer, the recess 9 is filled with a metal material as shown in FIG. Thereby, a continuous wiring (through wiring) layer is formed from the inside of the through hole 8 of the third semiconductor device 1E through the inside of the through hole 8 of the fourth semiconductor device 1F and into the recess 9. Note that, as shown in FIG. 10A, the wiring 13 that is a part of the wiring group is exposed in the recess 9, so that the exposed wiring 13 is electrically connected to the metal material filled in the recess 9. To come.

Next, as shown in FIG. 10B, the excess metal material on the surface side of the multilayer wiring layer 12 is removed by chemical mechanical polishing (CMP), and the surface of the multilayer wiring layer 12 in a portion excluding the recess 9 is removed. Expose. Thereby, the fourth semiconductor device 1F becomes a semiconductor device having the basic configuration shown in FIG.
Thereafter, as shown in FIG. 10C, the support substrate 17 is removed from the back surface of the first semiconductor device 1C. As a result, the second semiconductor device 1D, the third semiconductor device 1E, and the fourth semiconductor device 1F are sequentially stacked on the first semiconductor device 1C. Therefore, the second stacked structure 20B is formed on the first stacked structure 20A. As a result, a laminated structure 30 is obtained.

In the laminated structure 30 thus obtained and the manufacturing method thereof, in addition to the operational effects obtained by the laminated structure 20 and the manufacturing method of the first embodiment, the following operational effects are obtained. It is done.
That is, according to the stacked structure 30 and the manufacturing method thereof, a part of the semiconductor elements in the first integrated structure 20A and a part of the semiconductor elements in the second integrated structure 20B are combined with each other. 20B can be operated together by a set of through wirings 5 including continuous through electrodes and rearrangement wirings between 20B, the other part of the semiconductor element in the first integrated structure 20A, and the semiconductor in the second integrated structure 20B. The other part of the element can be independently operated by a set of wirings 5C which are independent without being continuous between the integrated structures 20A and 20B. Therefore, the design freedom of the laminated structure 30 can be increased.

Note that the bonding between the integrated structures 20A and 20B and the method thereof described in the manufacturing process can be the same as in the case of the first embodiment.
For the semiconductor devices 1C to 1F shown in FIG. 9 and FIG. 10, the cross-sectional structure shown in FIG. 1 and the manufacturing process shown in FIG. 2 and FIG. 3 were referred to. The structure of ˜1F can be replaced with the structure shown in FIGS. 9 shows a stacked structure in which the semiconductor devices 1 are stacked in four stages, it is needless to say that the semiconductor devices 1 can be stacked in two, three, or five or more stages.

  Furthermore, as this 2nd Embodiment, the diameter of some penetration wiring 5D may differ from the diameter of the other penetration wiring 5 like the laminated structure 31 shown, for example in FIG. In that case, for example, for the laminated structure 20B, a through-wiring manufacturing process is performed separately, and in particular, by forming a plurality of types of inner diameters of the through holes 8, a three-dimensional integrated circuit device having through-wirings with different diameters ( A laminated structure 30) can be realized. Further, one rearrangement wiring 7 may be connected to the plurality of through electrodes 6.

“Third Embodiment”
Next, a third embodiment of the laminated structure of the semiconductor device according to the present invention will be described.
FIG. 12A is a cross-sectional structure diagram of the third embodiment of the laminated structure. 12A to 12E are diagrams illustrating steps for explaining replacement with a non-defective substrate when a defective substrate is present in the stacked structure shown in FIG. 12A.

The laminated structure 40 of the third embodiment shown in FIG. 12A is different from the laminated structure 20 shown in FIG. 6 between the first semiconductor device 1A and the second semiconductor device 1B. It is a point which is directly connected only between the through electrode 6 and the rearrangement wiring 7 which are continuous between them without being attached to each other by direct bonding, adhesion, close contact or the like. .

  That is, the multilayer structure 40 is formed in the through wiring 5 of the first semiconductor device 1A without directly attaching the multilayer wiring layer 12 of the first semiconductor device 1A and the semiconductor substrate 11 of the second semiconductor device 1B. Only between the rearrangement wiring 7 and the through electrode 6 in the through wiring 5 of the second semiconductor device 1B is directly continuous. Therefore, in this laminated structure 40, the first semiconductor device 1A and the second semiconductor device 1B are directly continuous only by using the through wirings 5 and 5 that are continuous to each other as pillars. .

In the laminated structure 40 having such a configuration, when a defect occurs in one of the stacked semiconductor devices, it is only necessary to remove one of the continuous through electrode and the rearrangement wiring. It is possible to easily replace the semiconductor device in which this occurs.
Hereinafter, a method for replacing a defective substrate when a defect occurs in the upper second semiconductor device 1B among the stacked semiconductor devices will be described.

In the stacked structure 40 shown in FIG. 12A, when it is confirmed that the second semiconductor device 1B on the upper side is defective, first, as shown in FIG. (2) The through wiring 5 (rearrangement wiring 7 and through electrode 6 ) of the semiconductor device 1B is completely removed by etching. Then, since the first semiconductor device 1A and the second semiconductor device 1B are continuous with each other only through wirings 5 and 5, the bonding strength of each other is sufficiently weakened by removing one of the through wirings 5. .

Next, as shown in FIG. 12C, the second semiconductor device 1B is removed from the first semiconductor device 1A.
Subsequently, as shown in FIG. 12D, a new non-defective semiconductor device 1G is placed on the first semiconductor device 1A and pasted as necessary. At that time, alignment is performed so that the lower opening of the through hole 8 of the semiconductor device 1G is located on the rearrangement wiring 7 of the first semiconductor device 1A and not on the through electrode 6 of the first semiconductor device 1A. This is performed in the same manner as in the case shown in FIG.

  Next, this laminated body is immersed in a plating solution (not shown) having the same composition as that of the formation of the first semiconductor device 1A, and bottom-up plating is performed using plating electrodes arranged to face each other. As a result, the metal material 5a is filled in the same manner as shown in FIG. 7D, and is continuously connected to the through wiring 5 (rearrangement wiring 7) of the first semiconductor device 1A as shown in FIG. 12E. In this state, the through wiring 5 is formed in the semiconductor device 1G.

Thereafter, by removing the support substrate 17 from the back surface of the first semiconductor device 1A, a new stacked structure 20 (40) of the semiconductor device formed by stacking the semiconductor device 1G on the first semiconductor device 1A is obtained.
Even when the defect is not the upper second semiconductor device 1B but the lower first semiconductor device 1A, the first semiconductor device 1B is removed from the first semiconductor device 1A in the same process, and then the first After exchanging the semiconductor device 1A with a non-defective product, the steps shown in FIGS. 12D and 12E are performed to obtain a new stacked structure 20 (40) of the semiconductor device made of the non-defective product.

  Therefore, according to the stacked structure 40 shown in FIG. 12A, when a defect occurs in one of the stacked semiconductor devices, one of the directly connected through electrode and rearrangement wiring is removed. It is possible to easily replace the defective semiconductor device.

  In the present embodiment, for example, as shown in FIG. 13, by disposing the adhesion layer 41 or the adhesion sheet 41 between the semiconductor devices 1A and 1B, absorption of unevenness on the opposing planes of the semiconductor devices 1A and 1B, Prevention of mixing of the plating solution between apparatuses, reinforcement of apparatus connection strength, and the like can be realized.

Further, as shown in FIG. 14, the through wiring 5 on the second semiconductor device 1 </ b> B side (upper side) extends below the bottom surface of the semiconductor substrate 11 and has a cylindrical shape in which a through hole is formed only in the periphery thereof. An adhesive layer 42 may be formed, and the adhesive layer 42 may be bonded to the rearrangement wiring 7 of the first semiconductor device 1A.
In such a configuration, when a defective semiconductor device is replaced, the metal material of all portions of the rearrangement wiring 7 of the lower first semiconductor device 1A bonded to the adhesive layer 42 is removed. Thus, the second semiconductor device 1B can be easily removed from the first semiconductor device 1A.

Moreover, as shown in FIG. 15, it is good also as a structure which formed the contact bonding layer 43 as an insulating film in the inner wall face of the through-hole 8 of the 2nd semiconductor device 1B. In the case of such a configuration, the second semiconductor device 1B before filling the through hole 8 and the recess 9 with the metal material is brought into close contact with the first semiconductor device 1A, and then an insulating film is formed on the inner wall surface of the through hole 8. The adhesive layer 43 is formed. As a result, the second semiconductor device 1B before being filled with the metal material can be temporarily connected on the first semiconductor device 1A without forming a gap.
Further, when replacing a defective semiconductor device, in the same way as in the case shown in FIG. 14, the metal of all the portions of the rearrangement wiring 7 of the lower first semiconductor device 1A bonded to the adhesive layer 43 is used. By removing the material, the second semiconductor device 1B can be easily removed from the first semiconductor device 1A.

  The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the present invention.

DESCRIPTION OF SYMBOLS 1, 1C, 1D, 1E, 1F, 1G ... Semiconductor substrate, 1A ... 1st semiconductor device, 1B ... 2nd semiconductor device, 5 ... Through electrode, 6 ... Through electrode, 7 ... Rearrangement wiring, 8 ... Through-hole, DESCRIPTION OF SYMBOLS 9 ... Concave part, 11 ... Semiconductor substrate, 12 ... Multilayer wiring layer, 13 ... Wiring, 14 ... Insulating film, 15 ... Concave side conductive layer, 16 ... Surface side conductive layer, 17 ... Support substrate, 18 ... Seed layer, 20 ... Laminated structure, 20A ... first laminated structure, 20B ... second laminated structure, 30, 31, 40 ... laminated structure

Claims (3)

Providing a first semiconductor substrate having a semiconductor element and a wiring group connected to the semiconductor element;
Forming a first through hole penetrating in the thickness direction in the first semiconductor substrate;
Forming a first recess on one of the front and back surfaces of the first semiconductor substrate;
Providing a first recess-side conductive layer for energization in the first recess;
Providing a first surface-side conductive layer for energization on the other side of the front and back surfaces of the first semiconductor substrate;
Using the first surface side conductive layer and the first recess side conductive layer as a seed layer, a first through electrode is formed in the first through hole, and the front and back surfaces are formed in the first recess. Forming a rearrangement wiring extending in one of the surface directions,
In the step of forming the first through hole or the step of forming the first recess, a manufacturing process of the first semiconductor device in which at least a part of the wirings in the wiring group is exposed;
Preparing a second semiconductor substrate having a semiconductor element and a wiring group connected to the semiconductor element;
Passing through the second semiconductor substrate in the thickness direction and forming a second through hole; and
Forming a second recess on one side of the front and back surfaces of the second semiconductor substrate;
Forming a second recess-side conductive layer for energization in the second recess,
In the step of forming the second through hole or the step of forming the second recess, a manufacturing process of the second semiconductor device in which at least a part of the wirings in the wiring group is exposed;
The second semiconductor device manufactured in the manufacturing process of the second semiconductor device is placed on the first rearrangement wiring of the first semiconductor device on the first semiconductor device manufactured in the manufacturing process of the first semiconductor device. Laminating the second through hole so that the second through hole is in a different position from the first through hole in a plan view.
Using the first rearrangement wiring and the second recess side conductive layer as a seed layer, a second through electrode is formed in the second through hole, and the front and back surfaces are formed in the second recess. And a step of forming a rearrangement wiring extending in one surface direction. A method of manufacturing a laminated structure of a semiconductor device, comprising: In the manufacturing method of the laminated structure of the semiconductor device of Claim 1 ,
In the first semiconductor device and / or the second semiconductor device, a plurality of sets of through electrodes and rearrangement wirings electrically connected thereto are provided,
Providing the first semiconductor device and / or the second semiconductor device with a set of through electrodes that are independent of each other without being continuous between the semiconductor devices and a relocation wiring electrically connected thereto. A method for manufacturing a laminated structure of a semiconductor device. In the manufacturing method of the laminated structure of the semiconductor device of Claim 1 or 2 ,
A stacked structure of a semiconductor device, wherein the first semiconductor device and the second semiconductor device stacked vertically are directly continuous only between a through electrode and a rearrangement wiring that are continuous between the first semiconductor device and the second semiconductor device. Manufacturing method.

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