CN109192747A - The forming method of imaging sensor - Google Patents
The forming method of imaging sensor Download PDFInfo
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- CN109192747A CN109192747A CN201811284091.0A CN201811284091A CN109192747A CN 109192747 A CN109192747 A CN 109192747A CN 201811284091 A CN201811284091 A CN 201811284091A CN 109192747 A CN109192747 A CN 109192747A
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- 238000003384 imaging method Methods 0.000 title claims abstract description 32
- 238000000034 method Methods 0.000 title claims abstract description 26
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- 239000000758 substrate Substances 0.000 claims abstract description 96
- 239000004065 semiconductor Substances 0.000 claims abstract description 86
- 238000005530 etching Methods 0.000 claims abstract description 55
- 229910052751 metal Inorganic materials 0.000 claims abstract description 54
- 239000002184 metal Substances 0.000 claims abstract description 54
- 239000011229 interlayer Substances 0.000 claims abstract description 26
- 239000010703 silicon Substances 0.000 claims abstract description 26
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 26
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 25
- 239000011241 protective layer Substances 0.000 claims description 22
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 20
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 12
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 11
- 239000000463 material Substances 0.000 claims description 9
- 239000004020 conductor Substances 0.000 claims description 8
- 239000000377 silicon dioxide Substances 0.000 claims description 8
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical group CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 5
- 238000003475 lamination Methods 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- 239000004411 aluminium Substances 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
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- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
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- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/1469—Assemblies, i.e. hybrid integration
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14634—Assemblies, i.e. Hybrid structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14636—Interconnect structures
Abstract
A kind of forming method of imaging sensor, comprising: provide pixel semiconductor substrate, the front of the pixel semiconductor substrate has dielectric layer；Pixel metal interconnection structure is formed on the surface of the dielectric layer, the pixel metal interconnection structure includes at least pixel interlayer dielectric layer；The pixel interlayer dielectric layer is performed etching to form first groove, the first groove exposes a part of surface of the dielectric layer；The front of the pixel semiconductor substrate is bonded with the front of logic wafer, the front face surface of the logic wafer has logic top wire, and the opening of the first groove is towards a part of the logic top wire；From the back side of the pixel semiconductor substrate, the pixel semiconductor substrate and the dielectric layer are performed etching to form second groove, the second groove is connected to first groove.The present invention program can mitigate the surface of pixel wafer and the etching injury of silicon substrate, mitigate dark current problem.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors more particularly to a kind of forming methods of imaging sensor.
Background technique
Imaging sensor is the core component of picture pick-up device, realizes image taking function by converting optical signals into electric signal
Energy.By taking cmos image sensor (CMOS Image Sensors, CIS) device as an example, due to its tool
There is the advantages of low-power consumption and high s/n ratio, therefore is widely applied in various fields.
3 dimension stacking-type (3D-Stack) CIS are developed, to support the demand to higher quality image.Specifically,
3D-Stack CIS can make logic wafer and pixel wafer respectively, so by the logic wafer front with
And the front bonding of the pixel wafer, since pixel portion and logic circuitry portions are mutually indepedent, high image quality can be directed to
Demand pixel portion is optimized, logic circuitry portions are optimized for high performance demand.
It in specific implementation, can be using through-silicon-via (Through Silicon Via, TSV) technology in logic crystalline substance
It is respectively formed metal interconnection structure in round and pixel wafer, and then carries out vertical conducting between wafer, is met between wafer
Interconnection function.
However, in the existing technique for forming TSV, need to carry out multiple etching from the back side of the pixel wafer to patrolling
The top wire for collecting wafer is easy to damage the backside surface of pixel wafer, and damage in multiple etching around etching ditch
The silicon substrate of slot is easy to produce dark current problem when serious, influence the device quality of imaging sensor.
Summary of the invention
The technical problem to be solved by the present invention is to provide a kind of forming methods of imaging sensor, can mitigate pixel wafer
The etching injury of surface and silicon substrate mitigates dark current problem, improves the device quality of imaging sensor.
In order to solve the above technical problems, the embodiment of the present invention provides a kind of forming method of imaging sensor, comprising: provide
The front of pixel semiconductor substrate, the pixel semiconductor substrate has dielectric layer；Pixel is formed on the surface of the dielectric layer
Metal interconnection structure, the pixel metal interconnection structure include at least pixel interlayer dielectric layer；To the pixel interlayer dielectric layer
It performs etching to form first groove, the first groove exposes a part of surface of the dielectric layer；By the pixel half
The front of conductor substrate is bonded with the front of logic wafer, and the front face surface of the logic wafer has logic top-level metallic
Line, the opening of the first groove is towards a part of the logic top wire；From the back of the pixel semiconductor substrate
Face performs etching the pixel semiconductor substrate and the dielectric layer to form second groove, the second groove and the
The connection of one groove.
Optionally, the forming method of the imaging sensor further include: to the second groove and the first groove
Interior filling conductive material, to form through silicon via conducting structure.
Optionally, the conductive material is selected from: copper, aluminium and titanium.
Optionally, the pixel metal interconnection structure further includes a plurality of pixel bonding layer metal wire；It is situated between to the pixel interlayer
It includes: to carry out to the pixel interlayer dielectric layer between adjacent pixel bonding layer metal wire that matter layer, which is performed etching to form first groove,
Etching, so that the first groove exposes a part of the pixel bonding layer metal wire.
Optionally, from the back side of the pixel semiconductor substrate, to the pixel semiconductor substrate and the dielectric layer
Performing etching to form second groove includes: the backside surface formation protective layer in the pixel semiconductor substrate；Described in etching
Protective layer and the pixel semiconductor substrate, to form initial trench, the position of the initial trench and the first groove
Position there is corresponding relationship, and expose a part of surface of the dielectric layer；Oxide layer is formed, the oxide layer covers institute
State the surface of protective layer and the filling initial trench；The oxide layer in the initial trench is etched, and is etched described initial
Groove towards dielectric layer, to form the second groove.
Optionally, the protective layer and the pixel semiconductor substrate are etched, includes: described to form initial trench
The surface of protective layer forms patterned first mask layer；Using first mask layer as exposure mask, etch the protective layer and
The pixel semiconductor substrate, to form the initial trench.
Optionally, etch the oxide layer in the initial trench, and etch the initial trench towards dielectric layer, with
Forming the second groove includes: to form patterned second mask layer on the surface of the oxide layer；With second exposure mask
Layer be exposure mask, etch the oxide layer in the initial trench, and etch the initial trench towards dielectric layer, to be formed
State second groove.
Optionally, the material of the protective layer is selected from: silica and silicon nitride.
Optionally, the material of the oxide layer is TEOS.
Optionally, the dielectric layer is selected from: the lamination of silica and silicon nitride, silicon oxide layer, silicon nitride layer.
Compared with prior art, the technical solution of the embodiment of the present invention has the advantages that
In embodiments of the present invention, pixel semiconductor substrate is provided, the front of the pixel semiconductor substrate has medium
Layer；Pixel metal interconnection structure is formed on the surface of the dielectric layer, the pixel metal interconnection structure includes at least pixel layer
Between dielectric layer；The pixel interlayer dielectric layer is performed etching to form first groove, the first groove, which exposes, to be given an account of
A part of surface of matter layer；The front of the pixel semiconductor substrate is bonded with the front of logic wafer, the logic
The front face surface of wafer has logic top wire, and the opening of the first groove is towards the one of the logic top wire
Part；From the back side of the pixel semiconductor substrate, to the pixel semiconductor substrate and the dielectric layer perform etching with
Second groove is formed, the second groove is connected to first groove.It using the above scheme, can be by the pixel semiconductor
The front of substrate forms first groove, and the front of the pixel semiconductor substrate and the front of logic wafer are then carried out key
It closes, and then forms second groove from the back side of the pixel semiconductor substrate, the second groove is connected to first groove, compares
In in the prior art, entire groove is performed etching from the back side of the pixel semiconductor substrate, is easy to damage in multiple etching
Hurt the backside surface of pixel wafer, and damage surrounds the silicon substrate of etching groove, it, can be with using the scheme of the embodiment of the present invention
A part is etched respectively in the front and back of the pixel semiconductor substrate, to mitigate surface and the silicon lining of pixel wafer
The etching injury at bottom mitigates dark current problem, improves the device quality of imaging sensor.
Further, in embodiments of the present invention, the pixel metal interconnection structure further includes a plurality of pixel bonding layer metal wire,
Pixel interlayer dielectric layer between adjacent pixel bonding layer metal wire is performed etching so that the first groove expose it is described
A part of pixel bonding layer metal wire can make the through silicon via conducting structure connected pixel bonding layer metal wire to be formed and logic top
Layer metal wire, is better achieved between wafer and carries out vertical conducting, preferably meet the interconnection function between wafer.
Detailed description of the invention
Fig. 1 to Fig. 9 is the corresponding device profile knot of each step in a kind of forming method of imaging sensor in the prior art
Structure schematic diagram；
Figure 10 is a kind of flow chart of the forming method of imaging sensor in the embodiment of the present invention；
Figure 11 to Figure 17 is the corresponding device of each step in a kind of forming method of imaging sensor in the embodiment of the present invention
The schematic diagram of the section structure.
Specific embodiment
In the prior art, metal interconnection structure is respectively formed in logic wafer and pixel wafer using TSV technology, into
And vertical conducting is carried out between wafer, meet the interconnection function between wafer, however needs from the back side of the pixel wafer
The top wire for carrying out multiple etching to logic wafer is easy to damage the backside surface of pixel wafer in multiple etching, with
And damage surrounds the silicon substrate of etching groove, and dark current problem is easy to produce when serious, influences the device quality of imaging sensor.
Fig. 1 to Fig. 9 is the corresponding device profile knot of each step in a kind of forming method of imaging sensor in the prior art
Structure schematic diagram.
Referring to Fig.1, pixel semiconductor substrate 100 is provided, forms dielectric layer in the front of the pixel semiconductor substrate 100
101, pixel metal interconnection structure is formed on the surface of the dielectric layer 101, in the surface shape of the pixel metal interconnection structure
At bonded layer 105.
Wherein, the pixel metal interconnection structure may include pixel interlayer dielectric layer 102, a plurality of pixel bonding layer metal wire
103 and a plurality of pixel top wire 104.It is understood that the pixel metal interconnection structure can also include one layer
Or multilayer pixel metallic intermediate layer line.
Referring to Fig. 2, logic wafer is provided.
Wherein, the logic wafer may include logic semiconductor substrate 110, in the logic semiconductor substrate 110
Front is formed with logical media layer 111, forms logic metal interconnection structure on the surface of the logical media layer 111.
Wherein, the logic metal interconnection structure may include logic interlayer dielectric layer 112, a plurality of logic bonding layer metal wire
113 and a plurality of logic top wire 114.It is understood that the logic metal interconnection structure can also include one layer
Or multilayer logic metallic intermediate layer line.
Referring to Fig. 3, the front of the pixel semiconductor substrate 100 is bonded with the front of logic wafer, is then existed
The backside surface of pixel semiconductor substrate 100 forms protective layer 120.
Specifically, being bonded for the pixel semiconductor substrate 100 and logic wafer can be realized by bonded layer 105.
Referring to Fig. 4, patterned first mask layer 161 is formed on the surface of the protective layer 120, with first exposure mask
Layer 161 is exposure mask, the protective layer 120 and the pixel semiconductor substrate 100 is etched, to form initial trench.
Wherein, the initial trench exposes a part of surface of the dielectric layer 101, namely with the dielectric layer 101
For stop-layer (Stop layer), the initial trench is performed etching.
It should be pointed out that the extending direction of the initial trench is directed toward the logic top wire 114 of logic wafer, from
And after metal material being filled in the initial trench, knot is connected in the through silicon via for forming connection logic top wire 114
Structure.
Referring to Fig. 5, oxide layer 130 is formed, the oxide layer 130 covers described in the surface of the protective layer 120 and filling
Initial trench.
In specific implementation, the oxide layer 130 can side wall namely pixel semiconductor substrate 100 to initial trench
It is protected.
Referring to Fig. 6, patterned second mask layer 162 is formed on the surface of the oxide layer 130, with second exposure mask
Layer 162 is exposure mask, the oxide layer 130 in the initial trench is etched, to form second groove.
In specific implementation, a part of the oxide layer 130 is remained with around the second groove, thus realization pair
The protection of pixel semiconductor substrate 100.
It is exposure mask with the oxide layer 130, in a manner of Self-aligned etching, to adjacent pixel bonding layer metal wire referring to Fig. 7
Pixel interlayer dielectric layer 102 between 103 performs etching.
In specific implementation, the first groove exposes a part of the pixel bonding layer metal wire 103, thus filling out
After entering metal material, the through silicon via conducting structure of connection pixel bonding layer metal wire 103 is formed.
In another embodiment specific implementation mode, additional mask layer can also be used for exposure mask, to pixel interlayer dielectric layer
102 perform etching.
Referring to Fig. 8, patterned third mask layer 163, the third mask layer are formed on the surface of the oxide layer 130
163 cover the side wall of second grooves and have certain thickness, are exposure mask with the third mask layer 163, etching pixel interlayer is situated between
Matter layer 102 and bonded layer 105, to form third groove.
The present inventor has found after study, shown in Fig. 8 to pixel interlayer dielectric layer 102 and bonded layer
It is more demanding to the protective effect of the oxide layer 130 since etching depth is deeper in 105 the step of performing etching, it is easy hair
The case where life damages the backside surface of pixel wafer, and damage surrounds the silicon substrate of etching groove.
Referring to Fig. 9, conductive material is filled into the third groove, to form through silicon via conducting structure 180.
The present inventor also found that in the prior art, entire groove is from the pixel semiconductor after study
The back side of substrate performs etching, and etching number is more, is easy to damage the backside surface of pixel wafer in multiple etching, and
Damage surrounds the silicon substrate of etching groove, and dark current problem is easy to produce when serious, influences the device quality of imaging sensor.
In embodiments of the present invention, pixel semiconductor substrate is provided, the front of the pixel semiconductor substrate has medium
Layer；Pixel metal interconnection structure is formed on the surface of the dielectric layer, the pixel metal interconnection structure includes at least pixel layer
Between dielectric layer；The pixel interlayer dielectric layer is performed etching to form first groove, the first groove, which exposes, to be given an account of
A part of surface of matter layer；The front of the pixel semiconductor substrate is bonded with the front of logic wafer, the logic
The front face surface of wafer has logic top wire, and the opening of the first groove is towards the one of the logic top wire
Part；From the back side of the pixel semiconductor substrate, to the pixel semiconductor substrate and the dielectric layer perform etching with
Second groove is formed, the second groove is connected to first groove.It using the above scheme, can be by the pixel semiconductor
The front of substrate forms first groove, and the front of the pixel semiconductor substrate and the front of logic wafer are then carried out key
It closes, and then forms second groove from the back side of the pixel semiconductor substrate, the second groove is connected to first groove, compares
In in the prior art, entire groove is performed etching from the back side of the pixel semiconductor substrate, is easy to damage in multiple etching
Hurt the backside surface of pixel wafer, and damage surrounds the silicon substrate of etching groove, it, can be with using the scheme of the embodiment of the present invention
A part is etched respectively in the front and back of the pixel semiconductor substrate, to mitigate surface and the silicon lining of pixel wafer
The etching injury at bottom mitigates dark current problem, improves the device quality of imaging sensor.
It is understandable to enable above-mentioned purpose of the invention, feature and beneficial effect to become apparent, with reference to the accompanying drawing to this
The specific embodiment of invention is described in detail.
0, Figure 10 is a kind of flow chart of the forming method of imaging sensor in the embodiment of the present invention referring to Fig.1.The figure
As the forming method of sensor may include step S21 to step S25:
Step S21: providing pixel semiconductor substrate, and the front of the pixel semiconductor substrate has dielectric layer；
Step S22: pixel metal interconnection structure is formed on the surface of the dielectric layer, the pixel metal interconnection structure is extremely
It less include pixel interlayer dielectric layer；
Step S23: the pixel interlayer dielectric layer is performed etching to form first groove, the first groove exposes
A part of surface of the dielectric layer；
Step S24: the front of the pixel semiconductor substrate is bonded with the front of logic wafer, the logic is brilliant
Round front face surface has logic top wire, and the opening of the first groove is towards one of the logic top wire
Point；
Step S25: from the back side of the pixel semiconductor substrate, to the pixel semiconductor substrate and the dielectric layer
It performs etching to form second groove, the second groove is connected to first groove.
Above-mentioned each step is illustrated below with reference to Figure 11 to Figure 17.
Figure 11 to Figure 17 is the corresponding device of each step in a kind of forming method of imaging sensor in the embodiment of the present invention
The schematic diagram of the section structure.
Referring to Fig.1 1, pixel semiconductor substrate 200 is provided, the front of the pixel semiconductor substrate 200 has dielectric layer
201, pixel metal interconnection structure is formed on the surface of the dielectric layer 201, in the surface shape of the pixel metal interconnection structure
At bonded layer 205, patterned first mask layer 261 is formed on the surface of the bonded layer 205, with first mask layer
261 be exposure mask, the bonded layer 205 and the pixel semiconductor substrate 200 is etched, to form initial trench 241.
Wherein, the pixel metal interconnection structure may include pixel interlayer dielectric layer 202, a plurality of pixel bonding layer metal wire
203 and a plurality of pixel top wire 204.It is understood that the pixel metal interconnection structure can also include one layer
Or multilayer pixel metallic intermediate layer line.
In specific implementation, the pixel semiconductor substrate 200 can be silicon substrate or the pixel semiconductor substrate
200 material can also be the materials appropriate applied to imaging sensor such as germanium, SiGe, silicon carbide, GaAs or gallium indium
Material, it is preferable that the pixel semiconductor substrate 200, which can be grown, epitaxial layer (Epitaxy layer, Epi layer), may be used also
Think the semiconductor substrate being lightly doped.
Further, the dielectric layer 201 can be lamination, silicon oxide layer, the silicon nitride layer of silica and silicon nitride.
Wherein, the silica for example can be SiO2, the silicon nitride for example can be Si3N4。
The pixel interlayer dielectric layer 202 can be lamination, silicon oxide layer, the silicon nitride layer of silica and silicon nitride.
The material of the bonded layer 205 can be silica.
Further, performing etching to the pixel interlayer dielectric layer 202 can wrap the step of first groove 241 with being formed
It includes: the pixel interlayer dielectric layer 202 between adjacent pixel bonding layer metal wire 203 being performed etching, so that the first groove
241 expose a part of the pixel bonding layer metal wire 203.
In embodiments of the present invention, by making first groove 241 expose one of the pixel bonding layer metal wire 203
Point, after filling metal material in the first groove 241, the through silicon via conducting structure connected pixel bonding layer of formation
Metal wire 203 and logic top wire 214, are better achieved between wafer and carry out vertical conducting, preferably meet wafer
Between interconnection function.
Referring to Fig.1 2, logic wafer is provided.
Wherein, the logic wafer may include logic semiconductor substrate 210, in the logic semiconductor substrate 210
Front is formed with logical media layer 211, forms logic metal interconnection structure on the surface of the logical media layer 211.
Wherein, the logic metal interconnection structure may include logic interlayer dielectric layer 212, a plurality of logic bonding layer metal wire
213 and a plurality of logic top wire 214.It is understood that the logic metal interconnection structure can also include one layer
Or multilayer logic metallic intermediate layer line.
More contents in relation to logic semiconductor substrate 210, logical media layer 211, logic interlayer dielectric layer 212, please join
According to above and pixel semiconductor substrate shown in fig. 1 and the semiconductor devices of formation.
Referring to Fig.1 3, the front of the pixel semiconductor substrate 200 is bonded with the front of logic wafer, is then existed
The backside surface of pixel semiconductor substrate 200 forms protective layer 220, and the opening of the first groove 241 is towards the logic top
A part of layer metal wire 214.
Specifically, being bonded for the pixel semiconductor substrate 200 and logic wafer can be realized by bonded layer 205.
In embodiments of the present invention, by making the opening of the first groove 241 towards the logic top wire 214
A part, after metal material being filled in the first groove 241, formed connection logic top wire 214 silicon
Through-hole conducting structure.
Referring to Fig.1 4, patterned second mask layer 262 is formed on the surface of the protective layer 220, is covered with described second
Film layer 262 is exposure mask, the protective layer 220 and the pixel semiconductor substrate 200 is etched, to form initial trench 245.
Wherein, the position of the initial trench 245 and the position of the first groove 241 have corresponding relationship, and exposure
A part of surface of the dielectric layer 201 out, namely with the dielectric layer 201 be stop-layer, the initial trench 245 is carried out
Etching.
It should be pointed out that dielectric layer 201 is separated between the initial trench 245 and the first groove 241, rear
After a part of continuous etching removal dielectric layer 201, metal material can be filled in the trench, to form through silicon via conducting structure,
Therefore, the position of the initial trench 245 and the position of the first groove 241 should be on the basis of removing dielectric layer 201
It can communicate.
Referring to Fig.1 5, oxide layer 230 is formed, the oxide layer 230 covers described in the surface of the protective layer 220 and filling
Initial trench 245.
In specific implementation, the oxide layer 230 can side wall namely pixel semiconductor substrate to initial trench 245
200 are protected.
Wherein, the material of the oxide layer 230 can be ethyl orthosilicate (TEOS), since the step side of TEOS is coating
Better performances can preferably protect initial trench 245.
Referring to Fig.1 6, patterned third mask layer 263 is formed on the surface of the oxide layer 230, is covered with the third
Film layer 263 be exposure mask, etch the oxide layer 230 in the initial trench 245, and etch the initial trench 245 towards
Dielectric layer 201, to form second groove 242, the second groove 242 is connected to first groove 241.
Wherein, the third mask layer 263 covers the side wall of the initial trench 245 and has certain thickness, to make
The width for obtaining the second groove 242 can be less than the width of the initial trench 245.
It should be pointed out that in embodiments of the present invention, first groove 241 and second groove 242 have it is multiple, it is described
Second groove 242 is connected to corresponding first groove 241.
In specific implementation, a part of the oxide layer 230 is remained with around the second groove 242, thus real
Now to the protection of pixel semiconductor substrate 200.
Referring to Fig.1 7, conductive material is filled into the second groove 242 and the first groove 241, it is logical to form silicon
Hole conducting structure 280.
In specific implementation, the conductive material can be selected from: copper, aluminium and titanium, to realize the through silicon via conducting knot
The conducting function of structure 280.
In embodiments of the present invention, first groove 241 is formed by the front in the pixel semiconductor substrate 200, so
The front of the pixel semiconductor substrate 200 is bonded with the front of logic wafer afterwards, and then from the pixel semiconductor
The back side of substrate 200 forms second groove 242, and the second groove 242 is connected to first groove 241, compared with the prior art
In, entire groove is performed etching from the back side of the pixel semiconductor substrate, is easy to damage pixel wafer in multiple etching
Backside surface, and damage can be in the pixel using the scheme of the embodiment of the present invention around the silicon substrate of etching groove
The front and back of semiconductor substrate 200 etches a part respectively, to mitigate the surface of pixel wafer and the quarter of silicon substrate
Deteriorate wound, mitigates dark current problem, improve the device quality of imaging sensor.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (10)
1. a kind of forming method of imaging sensor characterized by comprising
Pixel semiconductor substrate is provided, the front of the pixel semiconductor substrate has dielectric layer；
Pixel metal interconnection structure is formed on the surface of the dielectric layer, the pixel metal interconnection structure includes at least pixel layer
Between dielectric layer；
The pixel interlayer dielectric layer is performed etching to form first groove, the first groove exposes the dielectric layer
A part of surface；
The front of the pixel semiconductor substrate is bonded with the front of logic wafer, the front face surface of the logic wafer
With logic top wire, the opening of the first groove is towards a part of the logic top wire；
From the back side of the pixel semiconductor substrate, the pixel semiconductor substrate and the dielectric layer are performed etching with shape
At second groove, the second groove is connected to first groove.
2. the forming method of imaging sensor according to claim 1, which is characterized in that further include:
Conductive material is filled into the second groove and the first groove, to form through silicon via conducting structure.
3. the forming method of imaging sensor according to claim 2, which is characterized in that the conductive material is selected from: copper,
Aluminium and titanium.
4. the forming method of imaging sensor according to claim 1, which is characterized in that the pixel metal interconnection structure
It further include a plurality of pixel bonding layer metal wire；
The pixel interlayer dielectric layer is performed etching to form first groove and include:
Pixel interlayer dielectric layer between adjacent pixel bonding layer metal wire is performed etching, so that the first groove exposes
A part of the pixel bonding layer metal wire.
5. the forming method of imaging sensor according to claim 1, which is characterized in that from the pixel semiconductor substrate
The back side, the pixel semiconductor substrate and the dielectric layer are performed etching to form second groove and include:
Protective layer is formed in the backside surface of the pixel semiconductor substrate；
Etch the protective layer and the pixel semiconductor substrate, to form initial trench, the position of the initial trench with
The position of the first groove has corresponding relationship, and exposes a part of surface of the dielectric layer；
Oxide layer is formed, the oxide layer covers the surface of the protective layer and the filling initial trench；
Etch the oxide layer in the initial trench, and etch the initial trench towards dielectric layer, to form described
Two grooves.
6. the forming method of imaging sensor according to claim 5, which is characterized in that etch the protective layer and institute
Pixel semiconductor substrate is stated, includes: to form initial trench
Patterned first mask layer is formed on the surface of the protective layer；
Using first mask layer as exposure mask, the protective layer and the pixel semiconductor substrate are etched, it is described first to be formed
Beginning groove.
7. the forming method of imaging sensor according to claim 5, which is characterized in that etch in the initial trench
Oxide layer, and etch the initial trench towards dielectric layer, include: to form the second groove
Patterned second mask layer is formed on the surface of the oxide layer；
Using second mask layer as exposure mask, the oxide layer in the initial trench is etched, and etches the initial trench face
To dielectric layer, to form the second groove.
8. the forming method of imaging sensor according to claim 5, which is characterized in that the material of the protective layer selects
From: silica and silicon nitride.
9. the forming method of imaging sensor according to claim 5, which is characterized in that the material of the oxide layer is
TEOS。
10. the forming method of imaging sensor according to claim 1, which is characterized in that the dielectric layer is selected from: oxidation
The lamination of silicon and silicon nitride, silicon oxide layer, silicon nitride layer.
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| CN111834285A (en) * | 2020-07-20 | 2020-10-27 | 武汉新芯集成电路制造有限公司 | Semiconductor device and method for manufacturing the same |
| WO2021208078A1 (en) * | 2020-04-17 | 2021-10-21 | 华为技术有限公司 | Semiconductor structure and manufacturing method therefor |
| CN111834285B (en) * | 2020-07-20 | 2024-05-17 | 武汉新芯集成电路制造有限公司 | Semiconductor device and method for manufacturing the same |
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| CN107046043A (en) * | 2015-12-29 | 2017-08-15 | 台湾积体电路制造股份有限公司 | Stacking substrat structure with interlayer cross tie part |
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| WO2021208078A1 (en) * | 2020-04-17 | 2021-10-21 | 华为技术有限公司 | Semiconductor structure and manufacturing method therefor |
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Application publication date: 20190111 |