JP5433154B2 - 半導体装置の作製方法 - Google Patents
半導体装置の作製方法 Download PDFInfo
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- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
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- H01L27/1285—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor using control of the annealing or irradiation parameters, e.g. using different scanning direction or intensity for different transistors
Description
図1および図2を用いて、本実施の形態では、第1のバッファ膜、第1の半導体膜、第2のバッファ膜、および光吸収膜を基板上に形成し、光吸収膜および第2のバッファ膜を通過させて第1の半導体膜にレーザ光を照射することで、第1の半導体膜に結晶性半導体を形成する方法を説明する。
(1)非晶質シリコン膜の表面に、数nm程度の単体金属、金属化合物または合金の薄膜をスパッタ法や蒸着法で形成する方法。
(2)単体金属、金属化合物または合金と、溶媒との混合物をスピンコート法、印刷法等で非晶質シリコン膜の上面に塗布する方法。この方法では、溶媒中に金属化合物等が溶解していても、溶解せずに分散していてもよい。
本発明の結晶化方法を用いて形成された結晶性半導体膜を用いて、様々な半導体装置を作製することができる。本発明の結晶化方法では、厚さ50nm以下の非単結晶半導体膜を歩留まり良く作製することが可能になる。よって、ゲート幅が1μm以下に微細化しても、短チャネル効果が抑制されたトランジスタを形成することができる。本実施の形態では、図3〜図5を用いて、実施の形態1で説明したレーザ結晶化によって形成された結晶性半導体を用いた半導体装置の作製方法を説明する。
11 酸化窒化シリコン膜
12 酸化窒化シリコン膜
13 非晶質シリコン膜
14 酸化窒化シリコン膜
15 非晶質シリコン膜
16 レーザ光
23 結晶性シリコン
25 結晶性シリコン
100 基板
101 第1のバッファ膜(第1の絶縁膜)
102 第1の半導体膜
103 第2のバッファ膜(第2の絶縁膜)
104、104’ 光吸収膜(第2の半導体膜)
105 レーザ光
106 液相の半導体
107 液相の光吸収膜
105 レーザ光
108 結晶性半導体
120 基板
121 第1のバッファ膜
122 第1の半導体膜
123 第2のバッファ膜
124 光吸収膜
128 結晶性半導体
131 マスク
132 第1の不純物領域
133 導電膜
134、135 第1の導電膜
138、139 第1の絶縁膜
140、141 結晶性半導体膜
142〜145 第2の不純物領域
146 チャネル形成領域
147 第2の絶縁膜
148〜150 第2の導電膜
152 薄膜トランジスタ
153 容量素子
160 第1の絶縁膜
161、162 結晶性半導体膜
163 第2の絶縁膜
164、165 第1の導電膜
166〜169 不純物領域
170、171 チャネル形成領域
173 第3の絶縁膜
174〜177 第2の導電膜
178 第1の薄膜トランジスタ
179 第2の薄膜トランジスタ
180 ガラス基板
181 絶縁膜
182 非晶質シリコン膜
183 絶縁膜
184 非晶質シリコン膜
185 レーザ光
186、187 液相のシリコン
188 結晶性シリコン
189 結晶性シリコン
200a 窒化タンタル膜
200b タングステン膜
201〜203 半導体層
201c〜203c チャネル形成領域
204 酸化窒化シリコン膜
205〜208 ゲート電極
209〜215 高濃度不純物領域
216〜223 低濃度不純物領域
225 nチャネル型薄膜トランジスタ
226 pチャネル型薄膜トランジスタ
227 nチャネル型薄膜トランジスタ
231 酸化シリコン膜
232 窒化シリコン膜
233 酸化シリコン膜
234〜239 配線
240 接続端子
241 酸化窒化シリコン膜
242 第1の画素電極
243 配向膜
244 導電層
251 ガラス基板
252 着色層
253 第2の画素電極
254 配向膜
255 液晶層
256 スペーサ
257 シール材
258 液晶素子
261 異方性導電膜
262 FPC
263 端子部
264 駆動回路部
265 画素部
300 層間絶縁膜
301 nチャネル型薄膜トランジスタ
302 pチャネル型薄膜トランジスタ
303 pチャネル型薄膜トランジスタ
311 端子部
312 駆動回路部
313 画素部
314 接続端子
315 層間絶縁膜
316 第1の電極層
317 有機絶縁物膜
318 発光物質を含む層
319 第2の電極層
320 導電層
321 発光素子
322 保護膜
323 シール材
324 封止基板
325 空間
326 異方性導電層
327 FPC
351 本体
352〜354 表示部
355 本体
356 表示部
357 本体
358 表示部
359 本体
360 表示部
361 本体
362 表示部
400 半導体装置
401 アンテナ部
402 電源部
403 ロジック部
411 アンテナ
421 整流回路
422 保持容量
423 定電圧回路
431 復調回路
432 クロック生成・補正回路
433 判定回路
434 メモリコントローラ
435 変調回路
436 変調用抵抗
437 符号化回路
438 マスクROM
441 高耐圧型薄膜トランジスタ
442 コンデンサ
443 nチャネル型薄膜トランジスタ
444 pチャネル型薄膜トランジスタ
R1〜R4 レジスト
500 ガラス基板
501 剥離膜
501a 第1層
501b 第2層
501c 第3層
502 絶縁膜
502a 第1層
502b 第2層
503 非晶質シリコン膜
504 絶縁膜
505 非晶質シリコン膜
507 結晶性シリコン
508 結晶性シリコン
509 結晶性シリコン
511〜513 半導体層
511c〜513c チャネル形成領域
515 絶縁膜
516 n型不純物領域
521〜524 第1導電膜
525〜528 n型低濃度不純物領域
529、530 p型高濃度不純物領域
531〜534 絶縁層
536〜541 n型高濃度不純物領域
542〜545 n型低濃度不純物領域
546 n型不純物領域
550 キャップ絶縁膜
551 第1層間絶縁膜
552〜563 第2導電膜
565 第2層間絶縁膜
566 第3導電膜
567 第3層間絶縁膜
568 第4導電膜
570 素子形成層
571 絶縁膜
572 支持基材
573 可撓性基板
Claims (3)
- 基板上に第1のバッファ膜を形成し、
前記第1のバッファ膜上に第1の半導体膜を形成し、
前記第1の半導体膜上に第2のバッファ膜を形成し、
前記第2のバッファ膜上に光吸収膜を形成し、
前記光吸収膜の上方からレーザ光を照射して、前記第1の半導体膜を結晶性半導体膜にする半導体装置の作製方法であって、
前記光吸収膜は、非晶質シリコンまたは微結晶のシリコン、非晶質または微結晶のゲルマニウム、非晶質または微結晶のシリコンゲルマニウム(SixGe1−x、0<x<1)であり、
前記光吸収膜の厚さは、30nm以上200nm以下(200nmを除く)であり、
前記第1の半導体膜の厚さは、50nm以下であり、
前記レーザ光の照射により、前記光吸収膜が固相から液相になるまでの間、前記光吸収膜が前記レーザ光を透過し、
前記レーザ光が、前記光吸収膜及び前記第1の半導体膜に照射され、前記光吸収膜及び前記第1の半導体膜が完全溶融し、液相の光吸収膜及び液相の第1の半導体膜になり、
前記液相の光吸収膜は前記レーザ光の反射率が上昇し、前記レーザ光を透過しなくなり、前記液相の光吸収膜からの熱伝導により前記第1の半導体膜が加熱された後、前記第1の半導体膜が固化して前記結晶性半導体膜になることを特徴とする半導体装置の作製方法。 - 請求項1において、
前記第1のバッファ膜は絶縁膜であることを特徴とする半導体装置の作製方法。 - 請求項1または請求項2において、
前記第2のバッファ膜は絶縁膜であることを特徴とする半導体装置の作製方法。
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JP2008235875A5 JP2008235875A5 (ja) | 2011-03-10 |
JP5433154B2 true JP5433154B2 (ja) | 2014-03-05 |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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JP7216025B2 (ja) | 2017-06-09 | 2023-01-31 | コーニンクレッカ フィリップス エヌ ヴェ | 少なくとも2つのアタッチメントを備えるヘアケアデバイス |
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Publication number | Priority date | Publication date | Assignee | Title |
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US20100037820A1 (en) * | 2008-08-13 | 2010-02-18 | Synos Technology, Inc. | Vapor Deposition Reactor |
US8475591B2 (en) * | 2008-08-15 | 2013-07-02 | Varian Semiconductor Equipment Associates, Inc. | Method of controlling a thickness of a sheet formed from a melt |
WO2010095901A2 (en) | 2009-02-23 | 2010-08-26 | Synos Technology, Inc. | Method for forming thin film using radicals generated by plasma |
JP5969216B2 (ja) * | 2011-02-11 | 2016-08-17 | 株式会社半導体エネルギー研究所 | 発光素子、表示装置、照明装置、及びこれらの作製方法 |
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JPH07106246A (ja) * | 1993-09-30 | 1995-04-21 | Kyocera Corp | 多結晶シリコン薄膜の形成方法 |
JP2002050764A (ja) * | 2000-08-02 | 2002-02-15 | Matsushita Electric Ind Co Ltd | 薄膜トランジスタ、アレイ基板、液晶表示装置、有機el表示装置およびその製造方法 |
JP2003178979A (ja) | 2001-08-30 | 2003-06-27 | Semiconductor Energy Lab Co Ltd | 半導体装置の作製方法 |
TWI282126B (en) | 2001-08-30 | 2007-06-01 | Semiconductor Energy Lab | Method for manufacturing semiconductor device |
JP2003168646A (ja) * | 2001-12-04 | 2003-06-13 | Sanyo Electric Co Ltd | 半導体装置の製造方法 |
JP2004134773A (ja) | 2002-09-18 | 2004-04-30 | Sanyo Electric Co Ltd | 半導体装置の製造方法 |
TWI253179B (en) | 2002-09-18 | 2006-04-11 | Sanyo Electric Co | Method for making a semiconductor device |
JP4577114B2 (ja) * | 2005-06-23 | 2010-11-10 | ソニー株式会社 | 薄膜トランジスタの製造方法および表示装置の製造方法 |
WO2007046290A1 (en) | 2005-10-18 | 2007-04-26 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
US8278739B2 (en) | 2006-03-20 | 2012-10-02 | Semiconductor Energy Laboratory Co., Ltd. | Crystalline semiconductor film, semiconductor device, and method for manufacturing thereof |
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JP7216025B2 (ja) | 2017-06-09 | 2023-01-31 | コーニンクレッカ フィリップス エヌ ヴェ | 少なくとも2つのアタッチメントを備えるヘアケアデバイス |
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