JP5432367B2 - 書込み検証を使用した符号のエラーフロア軽減 - Google Patents
書込み検証を使用した符号のエラーフロア軽減 Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
- G11B20/1833—Error detection or correction; Testing, e.g. of drop-outs by adding special lists or symbols to the coded information
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1105—Decoding
- H03M13/1108—Hard decision decoding, e.g. bit flipping, modified or weighted bit flipping
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1105—Decoding
- H03M13/1142—Decoding using trapping sets
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/45—Soft decoding, i.e. using symbol reliability information
- H03M13/451—Soft decoding, i.e. using symbol reliability information using a set of candidate code words, e.g. ordered statistics decoding [OSD]
- H03M13/453—Soft decoding, i.e. using symbol reliability information using a set of candidate code words, e.g. ordered statistics decoding [OSD] wherein the candidate code words are obtained by an algebraic decoder, e.g. Chase decoding
- H03M13/455—Soft decoding, i.e. using symbol reliability information using a set of candidate code words, e.g. ordered statistics decoding [OSD] wherein the candidate code words are obtained by an algebraic decoder, e.g. Chase decoding using a set of erasure patterns or successive erasure decoding, e.g. generalized minimum distance [GMD] decoding
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
- G11B20/1816—Testing
- G11B2020/1823—Testing wherein a flag is set when errors are detected or qualified
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
- G11B20/1833—Error detection or correction; Testing, e.g. of drop-outs by adding special lists or symbols to the coded information
- G11B2020/185—Error detection or correction; Testing, e.g. of drop-outs by adding special lists or symbols to the coded information using an low density parity check [LDPC] code
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B2220/00—Record carriers by type
- G11B2220/20—Disc-shaped record carriers
- G11B2220/25—Disc-shaped record carriers characterised in that the disc is based on a specific recording technology
- G11B2220/2508—Magnetic discs
- G11B2220/2516—Hard disks
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B2220/00—Record carriers by type
- G11B2220/60—Solid state media
- G11B2220/61—Solid state media wherein solid state memory is used for storing A/V content
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Description
コードワード108を作成するために、LDPCエンコーダ106は、情報ワード104のビットに、LDPC符号によって指定されたいくつかのパリティビットを付加する。情報ワード104内のビットの数はKとして示される。符号化コードワード内のビットは可変ビットとして知られており、それらの可変ビットの数はNとして示される。従って、パリティビットの数はN−Kによって与えられる。
特定のLDPC符号は、パリティチェック行列、又はH行列、或いは単にHとして知られている1及び0の2次元行列によって定義される。Hは、LDPCエンコーダ及びデコーダの両方によってアプリオリに知られている。Hは、N個の列及びN−K個の行、即ち、コードワードのビットごとに1つの列及びパリティビットごとに1つの行を備える。H内の各1は、列のコードワードビットと行のパリティビットとの間の関連を表す。例えば、Hの第3の行、第7の列にある1は、第3のパリティチェックビットがコードワードの第7のビットに関連することを意味する。チェックビットの値とそのチェックビットに関連する全ての可変ビットの合計モジュロ2は0であるはずである。典型的なLDPC符号の定義特性は、Hが「疎」である、即ち、Hの要素がほとんど0であり、1が比較的少ないことである。
図3は、図1のデコーダ114によって使用されるLDPC復号方法300の流れ図である。復号方法300の核心は、確率伝搬法と呼ばれる反復二相メッセージパッシングアルゴリズムである。確率伝搬法はタナーグラフを使用して説明されることが可能である。
ベクトル
シンドロームチェック306又は314を通ることは、ベクトル
従って、有効なベクトル
ベクトル
LDPCデコーダのビットエラーレート(BER)は、復号ビットが誤った値を有する確率を表す。従って、例えば、10−9のBERを有するデコーダは、平均して、10億復号ビットごとに1つの誤りビットを生成することになる。DCCWに収束するためのLDPC復号セッションの失敗はデコーダのBERに寄与する。
Claims (10)
- 元の符号化コードワードを記憶媒体に記憶するための機械実装方法であって、
(a)前記元の符号化コードワードを、書き込まれた符号化コードワードとして前記記憶媒体に書き込むステップ、
(b)前記記憶媒体から前記書き込まれた符号化コードワードを読み出すことによりチャネル出力コードワードを生成するステップ、
(c)前記書き込まれた符号化コードワード内の1つ以上の誤りビットの第1のセットを識別するために、前記チャネル出力コードワードに基づいて前記元の符号化コードワードを派生コードワードと比較するステップ、
(d)前記第1のセット内の1つ以上の誤りビットを選択することにより前記書き込まれた符号化コードワード内の1つ以上の誤りビットの第2のセットを生成するステップ、
及び
(e)前記記憶媒体に、前記第2のセット内の前記1つ以上の誤りビットに対応する誤りビット情報を書き込むステップであって、前記誤りビット情報は、前記書き込まれた符号化コードワードのための一意の識別子及び前記第2のセット内の前記1つ以上の誤りビットのための添字を備えるステップ
を備える方法。 - 請求項1記載の方法であって、元の符号化コードワードは低密度パリティチェックコードワードである、方法。
- 請求項1記載の方法であって、ステップ(c)は、前記チャネル出力コードワードに対する復号を実行して前記派生コードワードを生成するステップをさらに備える、方法。
- 請求項1記載の方法であって、
(f)前記記憶媒体から前記書き込まれた符号化コードワードを読み出すことによりデコーダ入力コードワードを生成するステップ、
(g)前記デコーダ入力コードワードに対する復号を実行して、復号コードワードを生成するステップ、並びに
(h)復号コードワードが、復号された正しいコードワードでない場合は、
(h1)前記記憶媒体から前記誤りビット情報を読み出すステップ、
(h2)前記誤りビット情報に基づいて、修正コードワードを生成するステップ、及び
(h3)前記修正コードワードに対してさらなる処理を実行するステップ
をさらに備える方法。 - 請求項1記載の方法であって、ステップ(d)は、
(d1)前記第1のセット内の1つ以上の誤りビットを選択するステップ、
(d2)前記1つ以上の選択された誤りビットに基づいて修正コードワードを生成するステップ、
(d3)前記修正コードワードに対する復号を実行して候補復号コードワードを生成するステップ、
(d4)前記候補復号コードワードが復号された正しいコードワードであるかどうかを判定するステップ、
(d5)前記候補復号コードワードが前記復号された正しいコードワードである場合は、前記1つ以上の選択された誤りビットに基づいて前記第2のセットを生成するステップ、及び
(d6)前記候補復号コードワードが前記復号された正しいコードワードでない場合は、前記第1のセット内に別の1つ以上の選択された誤りビットがないかステップ(d1)〜(d4)を繰り返すステップ
を備える、方法。 - 記憶媒体に記憶されている書き込まれた符号化コードワードのための復号コードワードを生成するための機械実装方法であって、前記書き込まれた符号化コードワードは1つ以上の誤りビットを有し、
(a)前記記憶媒体から前記書き込まれた符号化コードワードを読み出すことによりチャネル出力コードワードを生成するステップ、
(b)前記チャネル出力コードワードに基づいて派生コードワードを生成するステップ、
(c)前記記憶媒体から誤りビット情報を読み出すステップであって、前記誤りビット情報は前記書き込まれた符号化コードワード内の1つ以上の誤りビットに対応し、前記誤りビット情報は、前記書き込まれた符号化コードワードのための一意の識別子及び前記書き込まれた符号化コードワード内の1つ以上の誤りビットのための添字を備えるステップ、
(d)前記誤りビット情報に基づいて修正コードワードを生成するステップ、及び
(e)前記修正コードワードに対する処理を実行して前記復号コードワードを生成するステップ
を備える方法。 - 請求項6記載の方法であって、前記書き込まれた符号化コードワードは低密度パリティチェックコードワードである、方法。
- 請求項6記載の方法であって、ステップ(b)は、
(b1)前記チャネル出力コードワードに対する復号を実行して前記派生コードワードを生成するステップ、及び
(b2)前記派生コードワードが復号された正しいコードワードではないと判定するステップ
を備える、方法。 - 請求項6記載の方法であって、ステップ(e)は、
(e1)前記誤りビット情報が前記書き込まれた符号化コードワード内の前記誤りビットの全てに対応するか否かを判定するステップ、
(e2)前記誤りビット情報が前記書き込まれた符号化コードワード内の前記誤りビットの全てに対応する場合は、前記修正コードワードに対してシンドロームチェック及び巡回冗長検査(CRC)のうちの1つ以上を実行するステップ、及び
(e3)前記誤りビット情報が前記書き込まれた符号化コードワード内の前記誤りビットの全てには対応しない場合は、前記修正コードワードに対して復号を実行するステップを備える、方法。 - 請求項6記載の方法であって、前記誤りビット情報は、
前記誤りビット情報が前記書き込まれた符号化コードワード内の前記誤りビットの全てに対応するかどうかの表示
をさらに備える、方法。
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PCT/US2009/041215 WO2010123493A1 (en) | 2009-04-21 | 2009-04-21 | Error-floor mitigation of codes using write verification |
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JP2012525062A JP2012525062A (ja) | 2012-10-18 |
JP2012525062A5 JP2012525062A5 (ja) | 2013-06-27 |
JP5432367B2 true JP5432367B2 (ja) | 2014-03-05 |
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US (1) | US8484535B2 (ja) |
EP (1) | EP2307960B1 (ja) |
JP (1) | JP5432367B2 (ja) |
KR (1) | KR101321487B1 (ja) |
CN (1) | CN102077173B (ja) |
TW (1) | TWI411912B (ja) |
WO (1) | WO2010123493A1 (ja) |
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US20120030539A1 (en) | 2012-02-02 |
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