JP5419395B2 - Semiconductor device manufacturing method, semiconductor device, and MOS transistor - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor device having an element isolation trench. Further, the present invention relates to a semi-conductor device and a MOS-type transistor.

  LOCOS (LOCal Oxidation of Silicon) type element isolation, which has been conventionally used as an element isolation method, has a problem that the element isolation characteristics deteriorate due to bird's beaks and thinning as the element becomes finer. It became a hindrance. A trench type element isolation method developed to solve this problem uses a method of filling a trench formed in a substrate with an insulating film such as a silicon oxide film, thereby eliminating the problems of bird's beak and thinning.

  However, the active region in which a transistor is formed with the miniaturization of the element, that is, the influence of variations in processing of the gate width of the transistor is affected by LSI (Large Scale Integrated Circuit), particularly flash memory and SRAM (Static Random Access Memory) used in narrow channel transistors. ) Is causing a decrease in the memory operating margin.

  As a technique for improving the processing accuracy of the active region, a processing flow shown in FIG. 5 is introduced. This processing flow has steps S301 to S307 and S311 to S313.

  Hereinafter, steps S301 to S307 and S311 to S313 will be described with reference to FIGS. 6A to 6I.

  First, in step S301, a silicon substrate 301 shown in FIG. 6A is prepared.

  Next, in step S302, a silicon oxide film 302 having a thickness of 2 to 20 nm, for example, 10 nm is formed on the surface of the silicon substrate 301 by thermal oxidation. Then, a silicon nitride film 303 having a thickness of 50 nm to 200 nm, for example, a thickness of 100 nm is formed on the surface of the silicon oxide film 302 by LPCVD (low pressure chemical vapor deposition).

  Next, in step S303, a resist film is applied on the surface of the silicon nitride film 303, and then exposed and developed to form a resist pattern 304 shown in FIG. 6B. The resist pattern 304 is formed on an element formation region (active region), and the opening defines an element isolation region.

  Next, in step S304, the silicon nitride film 303 and the silicon oxide film 302 are etched using the resist pattern 304 as an etching mask to obtain the silicon nitride film 303a and the silicon oxide film 302a shown in FIG. 6C. Thereafter, the resist pattern 304 is removed to obtain the state shown in FIG. 6D.

  Next, in step S305, the width W of the defined element isolation region is measured from above the substrate.

  A SEM (scanning electron microscope) is used for the measurement, and the measured value of the width W is recorded in step S311 so that it can be compared with the design reference value. From this measured value, a machining condition change value is calculated in step S312. Then, in step S313, the processing condition change value is reflected in a condition setting for performing a photo process (S303) for forming a processing mask or an etching process (S304) for processing.

  On the other hand, the finished product is obtained by etching the silicon substrate 301 in step S306 to obtain a silicon substrate 301a in which element isolation trenches 341 are formed as shown in FIG. 6E. The element isolation trench 341 has a depth of 160 to 500 nm, for example, 300 nm.

  Next, as shown in FIG. 6F, after a trench surface oxide film 306 is formed on the bottom and side surfaces of the element isolation trench 341, an element isolation buried insulating film 308 shown in FIG. 6G is formed. A part of the element isolation embedded insulating film 308 is embedded in the element isolation trench 341.

  Next, as shown in FIG. 6H, a surface flattening step such as polishing is performed to obtain an element isolation buried insulating film 308a.

  Next, as shown in FIG. 6H, the silicon nitride film 303a is removed by immersion in heated phosphoric acid, and the silicon oxide film 302a is removed by wet etching. Thereby, a buried insulating film 308b for element isolation is obtained.

  Next, an element is formed in step S307. More specifically, as shown in FIG. 6I, a MOS (Metal Oxide Semiconductor) transistor is formed in each of the two active regions formed in FIG. 6H. The gate length direction of the one MOS transistor is just perpendicular to the gate length direction of the other MOS transistor. In FIG. 6I, 310 is a gate insulating film, 311 is a gate electrode, 312 is a gate spacer, 313 is a source / drain portion, 314 is an interlayer film, 315 is a contact plug, and 316 is a wiring.

  By the way, in the MOS transistor formed on the right side in FIG. 6I, the silicon nitride film 303a is removed and the silicon oxide film 302a is removed by wet etching, so that the portion shown by A, that is, the side portion of the element isolation trench 341 is obtained. Is not covered with the trench surface oxide film 306a or the element isolation buried insulating film 308a. That is, the trench surface oxide film 306 and the element isolation buried insulating film 308 near the surface of the active region of the MOS transistor are removed by wet etching.

  As a result, in the MOS transistor, there is a problem that a short circuit or a leak occurs between the gate electrode 111 and the silicon substrate 301a at a portion indicated by α.

  In order to solve such a problem, in the above processing flow, in step S305, the width W of the defined element isolation region is measured from above the substrate, and the measured value of the width W is used to perform the next photo process ( S303) or the etching process (S304) is modified. That is, the process that causes the measured value of the width W to deviate from the specified value is corrected.

  However, in the above processing flow, the shift in the width W is reflected in the product in which the next photo process (S303) or the etching process (S304) is performed, but for the product having the shifted width W. Since this is not reflected, this product will have variations in properties. Or since the said product becomes outside a specification, the following process processing was not implemented but had to be discarded.

An object of the present invention is to reduce variations in process treatment is to provide a manufacturing how the semiconductor device can be manufactured with less variation semiconductor device by improving the machining accuracy of the semiconductor substrate.

  Another object of the present invention is to provide a semiconductor device and a MOS transistor manufactured by the method for manufacturing a semiconductor device.

In order to solve the above problems, a method for manufacturing a semiconductor device of the present invention includes:
Preparing a semiconductor substrate;
Forming a first insulating film made of a material different from the first insulating film on the surface of the semiconductor substrate;
Forming a second insulating film on the surface of the first insulating film;
Forming a photoresist having a window for forming an element isolation trench on the surface of the second insulating film;
Using the photoresist as a mask, removing a part of the second insulating film to form an opening in the second insulating film to expose a part of the surface of the first insulating film When,
After removing the photoresist, measuring the width of the adjacent portion adjacent to the opening with respect to the second insulating film in which the opening is formed, as viewed from the surface side of the semiconductor substrate;
Calculating the difference between the measurement value of the width of the adjacent portion and the design reference value;
The film thickness calculated from the above difference is applied to the third film covering a part of the first insulating film exposed from the opening and the side surface and surface of the second insulating film in which the opening is formed. forming by a thickness adjusted to have,
Etching is performed so as to leave a part of the third film covering the side surface of the second insulating film in which the opening is formed, thereby forming a side wall protective film made of a part of the third film. Process,
Using the second insulating film in which the opening is formed and the side wall protective film as a mask, the first insulating film and a part of the semiconductor substrate are etched to form the element isolation on the semiconductor substrate. And a step of forming a trench.

  According to the method of manufacturing a semiconductor device having the above-described configuration, the first insulating film and the second insulating film in which the opening is formed and the sidewall protective film that covers the side surface of the second insulating film are used as a mask. By etching a part of the semiconductor substrate, an element isolation trench is formed in the semiconductor substrate. Since this side wall protective film is formed of a part of the third film formed by adjusting the film thickness in accordance with the measured value of the width of the adjacent portion adjacent to the opening, it is possible to reduce variations in process processing. Here, the process process is a process for forming a film to be a mask for forming an element isolation trench.

  Therefore, the processing accuracy of the semiconductor substrate can be improved, and an element isolation trench having a desired shape can be accurately formed in the semiconductor substrate.

  As a result, even when a plurality of the semiconductor devices are manufactured, the shape of the element isolation trenches of each semiconductor device can be made substantially the same, and the variation in performance among the plurality of semiconductor devices can be reduced.

A method for manufacturing a semiconductor device of the present invention includes:
Preparing a semiconductor substrate;
Forming a first insulating film on the surface of the semiconductor substrate;
Forming a second insulating film on the surface of the first insulating film;
Forming a photoresist having a window for forming an element isolation trench on the surface of the second insulating film;
By using the photoresist as a mask, the second insulating film and a part of the first insulating film are removed, whereby the second insulating film and the first insulating film are formed on the surface of the semiconductor substrate. Forming an opening exposing a portion;
After removing the photoresist, measuring the width of the adjacent portion adjacent to the opening with respect to the second insulating film in which the opening is formed, as viewed from the surface side of the semiconductor substrate;
Calculating the difference between the measurement value of the width of the adjacent portion and the design reference value;
First covering the part of the semiconductor substrate exposed from the opening, the side surface of the first insulating film in which the opening is formed, and the side surface and surface of the second insulating film in which the opening is formed. The step of adjusting the film thickness to have the film thickness calculated from the above difference ,
Etching so that a part of the third film covering the side surface of the first insulating film in which the opening is formed and the side surface of the second insulating film in which the opening is formed remain. Forming a sidewall protective film comprising a part of the third film;
Forming a trench for element isolation in the semiconductor substrate by etching a part of the semiconductor substrate using the second insulating film in which the opening is formed and the sidewall protective film as a mask; It is characterized by having prepared.

  According to the method for manufacturing a semiconductor device having the above-described structure, the second insulating film in which the opening is formed and the sidewall protective film that covers the side surfaces of the first and second insulating films are used as masks. By etching the portion, an element isolation trench is formed in the semiconductor substrate. Since this side wall protective film is formed of a part of the third film formed by adjusting the film thickness in accordance with the measured value of the width of the adjacent portion adjacent to the opening, it is possible to reduce variations in process processing. Here, the process process is a process for forming a film to be a mask for forming an element isolation trench.

  Therefore, the processing accuracy of the semiconductor substrate can be improved, and an element isolation trench having a desired shape can be accurately formed in the semiconductor substrate.

  As a result, even when a plurality of the semiconductor devices are manufactured, the shape of the element isolation trenches of each semiconductor device can be made substantially the same, and the variation in performance among the plurality of semiconductor devices can be reduced.

In one embodiment of a method for manufacturing a semiconductor device,
After removing the photoresist, the method includes a step of measuring the width of the adjacent portion adjacent to the opening with respect to the first insulating film in which the opening is formed, as viewed from the surface side of the semiconductor substrate.

  According to the method of manufacturing the semiconductor device of the above embodiment, after removing the photoresist, the width of the adjacent portion adjacent to the opening with respect to the first insulating film in which the opening is formed is increased from the surface side of the semiconductor substrate. Since it measures by seeing, it can measure easily in the middle of a manufacturing process using SEM (scanning electron microscope).

In one embodiment of a method for manufacturing a semiconductor device,
The third film is any one of a silicon oxide film, a silicon nitride film, a SiON film, and a polysilicon film.

  According to the method of manufacturing a semiconductor device of the above embodiment, since any one of the silicon oxide film, silicon nitride film, SiON film, and polysilicon film is the third film, it is easy in the LSI manufacturing process. Can be selectively removed from the silicon substrate.

In one embodiment of a method for manufacturing a semiconductor device,
The film thickness of the third film is 5 to 50 nm.

  According to the method for manufacturing a semiconductor device of the above embodiment, since the thickness of the third film is 5 to 50 nm, the variation in the active region due to the process variation can be sufficiently corrected.

In one embodiment of a method for manufacturing a semiconductor device,
The third film is formed by chemical vapor deposition.

  According to the method for manufacturing a semiconductor device of the above embodiment, since the third film is formed by chemical vapor deposition, a film having a uniform thickness on the surface of the silicon substrate, the surface of the second insulating film, and the side surface. Can be formed.

In one embodiment of a method for manufacturing a semiconductor device,
The second insulating film is a silicon nitride film. According to the method of manufacturing a semiconductor device of the above embodiment, the second insulating film is a silicon nitride film, which can be easily used in the LSI manufacturing process. It is a material and can be selectively removed with respect to the silicon oxide film.

The semiconductor device of the present invention is
A semiconductor device manufactured using the method for manufacturing a semiconductor device of the present invention,
A semiconductor substrate having the element isolation trench and an active region defined by the element isolation trench;
A buried insulating film buried in the element isolation trench;
A gate insulating film formed on the active region;
A gate electrode formed on the gate insulating film,
The buried insulating film covers the entire sidewall of the element isolation trench.

  According to the semiconductor device having the above configuration, since the buried insulating film covers the entire side wall of the element isolation trench, the gate insulating film and the gate electrode can be prevented from coming into contact with the side wall of the element isolation trench. .

  Therefore, it is possible to prevent a short circuit and a leak from occurring between the gate electrode and the silicon substrate.

The MOS transistor of the present invention is
A MOS transistor manufactured using the method for manufacturing a semiconductor device of the present invention,
A semiconductor substrate having the element isolation trench and an active region defined by the element isolation trench;
A buried insulating film buried in the element isolation trench;
A gate insulating film formed on the active region;
A gate electrode formed on the gate insulating film,
The buried insulating film covers the entire sidewall of the element isolation trench.

  According to the MOS transistor having the above configuration, since the buried insulating film covers the entire sidewall of the element isolation trench, the gate insulating film and the gate electrode can be prevented from contacting the sidewall of the element isolation trench. it can.

  Therefore, it is possible to prevent a short circuit and a leak from occurring between the gate electrode and the silicon substrate.

  According to the present invention, the width of the active region of the LSI using the element isolation trench, that is, the variation in the gate width of the transistor can be reduced from lot to lot or from wafer to wafer. And a transistor having stable characteristics with no fluctuation in threshold voltage can be provided, thereby contributing to stabilization of the circuit operation of the LSI.

  Hereinafter, an embodiment of the present invention will be described using a processing flow diagram and schematic cross-sectional views of each process.

(First embodiment)
FIG. 1 is a diagram showing a process flow of the method for manufacturing a CMOS transistor according to the first embodiment of the present invention. This processing flow has steps S101 to S109 and S111 to S113.

  Hereinafter, steps S101 to S109 and S111 to S113 will be described with reference to FIGS. 2A to 2K.

  First, in step S101, the silicon substrate 101 shown in FIG. 2A is prepared.

  Next, in step S102, a silicon oxide film 102 having a thickness of 2 to 20 nm, for example, a thickness of 10 nm is formed on the surface of the silicon substrate 101 by thermal oxidation. Then, a silicon nitride film 103 having a thickness of 50 nm to 200 nm, for example, a thickness of 100 nm is formed on the silicon oxide film 102 by LPCVD. The silicon substrate 101 is an example of a semiconductor substrate, the silicon oxide film 102 is an example of a first insulating film, and the silicon nitride film 103 is an example of a second insulating film.

  Next, in step S103, a resist film is applied on the surface of the silicon nitride film 103, and exposed and developed, thereby forming a resist pattern 104 having a window 120 as shown in FIG. 2B. The resist pattern 104 is formed on an element formation region (active region), and the window portion 120 defines an element isolation region. That is, the window 120 is formed so as to overlap with a region to be an element isolation region. The resist pattern 104 is an example of a photoresist.

  Next, in step S104, the silicon nitride film 103 and the silicon oxide film 102 are etched. Thereby, as shown in FIG. 2C, an opening 130 is formed in the silicon nitride film 103 a, and a part of the silicon oxide film 102 is exposed from the opening 130. Thereafter, the resist pattern 104 is removed to obtain the state shown in FIG. 2D.

  Next, in step S <b> 105, the width A of the adjacent portion 131 adjacent to the opening portion 130 with respect to the silicon nitride film 103 a in which the opening portion 130 is formed is measured as viewed from the surface side of the silicon substrate 101.

  A SEM (scanning electron microscope) is used for the measurement, and the measured value of the width A is recorded in step S111 so that it can be compared with the design reference value. From this measurement value, a film thickness setting value is calculated in step S112. In step S113, the film thickness set value is set to a target film thickness in a third film formation step (S106) described later. The recording in step S111 is not limited as long as it can be used when forming the third film later.

  The calculation method of the film thickness set value will be described in more detail. First, the difference between the measured value of the width A and the design reference value is obtained. If this difference is outside the specified range (10 nm at the most), the target film thickness of the third film is changed. That is, if the difference is large, the target film thickness of the third film is increased. Conversely, if the difference is small, the target film thickness of the third film is decreased. Change the film thickness. At this time, it is preferable that the changed film thickness is a value obtained by multiplying the difference between the measured value of the width A and the design reference value by 0.8 to 1.5.

  Next, in step S106, as shown in FIG. 2E, an oxide film 105 as an example of a third film is formed by LPCVD. The oxide film 105 covers a part of the silicon oxide film 102 exposed from the opening 130 and the side surface of the silicon nitride film 103a. The oxide film 105 is also an example of a correction insulating film.

  Here, as the thickness B of the oxide film 105 increases, the area covered with the element isolation buried insulating film 108, which will be described later, increases on the surface of the silicon substrate 101 serving as the channel region of the transistor (see FIG. 2H). On the other hand, when the film thickness B of the oxide film 105 is reduced, a side surface of a later-described element isolation trench 141 may be exposed from the element isolation buried insulating film 108 (see FIG. 2J). The side surface of the element isolation trench 141 becomes a part of the channel region of the transistor. For this reason, the exposure of the side surface of the element isolation trench 141 causes a rapid change in transistor characteristics such as a threshold voltage and a drain current.

  In order to avoid such a rapid change in transistor characteristics, accurately control the gate width, and reduce the variation in transistor characteristics, the minimum value of the film thickness B of the oxide film 105 is the value after the transistor formation shown in FIG. 2K. In this cross-sectional view, it is necessary to make a selection in such a range that the entire side surface of the element isolation trench 141 is covered with the element isolation buried insulating film 108. Further, since the minimum value of the film thickness B of the oxide film 105 varies depending on the combination of subsequent processes, it is necessary to select an optimum value in a timely manner. In this embodiment, the oxide film 105 is also used as an example of the third film and the correction insulating film. However, a film made of an appropriate material in consideration of film thickness control and subsequent processing conditions is used as the third film, It may also be used as an example of a correction insulating film. That is, the third film and the correction insulating film are not limited to the oxide film 105. Examples of the third film include a silicon oxide film and a silicon nitride film.

  Next, in step S107, the oxide film 105 in contact with the surface of the silicon nitride film 103a and the oxide film 105 in contact with the surface of the silicon oxide film 102 are made anisotropic by RIE (reactive ion etching). Etch under strong conditions. As a result, as shown in FIG. 2F, a sidewall-like sidewall protective film 105a is formed so as to cover the sidewall of the silicon nitride film 103a. At this time, a part of the silicon oxide film 102 shown in FIG. 2E is exposed.

  Next, in step S108, the silicon oxide film 102 and a part of the silicon substrate 101 are etched to form the silicon substrate 101a having the element isolation trench 141 and the silicon oxide film 102a as shown in FIG. 2F. can get. At this time, the element isolation trench 141 is formed to have a depth of 160 to 500 nm, for example, 300 nm.

  When the element isolation trench 141 is formed, the width becomes smaller than the width C (width A + 2 × film thickness B) of the active region due to loss at the time of etching, but as described above, the width A is smaller than the design reference value. In contrast, the thickness B is increased, and conversely, when the width A is larger than the design reference value, the adjustment is performed to decrease B, so that fluctuation of the width C can be prevented. As a result, since the gate width of the transistor is formed stably, variation in transistor characteristics, in particular, drain current of a transistor having a narrow channel width can be reduced.

  Next, as shown in FIG. 2G, after the trench surface oxide film 106 is formed on the bottom and side surfaces of the element isolation trench 141, the element isolation buried insulating film 108 shown in FIG. 2H is formed. A part of the element isolation buried insulating film 108 is buried in the element isolation trench 141.

  Next, as shown in FIG. 2I, a surface flattening step by polishing or the like is performed to obtain an element isolation buried insulating film 108a.

  Next, as shown in FIG. 2J, the silicon nitride film 103a is removed by immersion in heated phosphoric acid, and the silicon oxide film 102a is removed by wet etching. As a result, the element isolation buried insulating film 108b is obtained.

  Next, an element is formed in step S109. More specifically, as shown in FIG. 2K, a gate insulating film 110 and a gate electrode 111 are formed in accordance with a normal complementary metal oxide semiconductor (CMOS) LSI process. Prior to the formation of the gate insulating film 110, impurities may be introduced into the silicon substrate 101a to form wells in the silicon substrate 101a. Further, after forming gate spacers 112 on both sides of the gate electrode 111, source / drain portions 113 are formed on the silicon substrate 101a. Then, an interlayer film 114, contact plugs 115, and wirings 116 are formed.

  According to the manufacturing method of this embodiment, even if the silicon nitride film 103a is removed and the silicon oxide film 102a is removed by wet etching, as shown in FIG. 2J, the element isolation trench is separated from the element isolation buried insulating film 108b. Part of 141 is not exposed.

  Therefore, it is possible to prevent the occurrence of a short circuit or leakage between the gate electrode 111 and the silicon substrate 101.

  Further, the sidewall protective film 105a is formed of a part of the oxide film 105 formed by adjusting the film thickness in accordance with the measured value of the width A of the adjacent portion 131 adjacent to the opening 130. Can be reduced.

  Therefore, the processing accuracy of the silicon substrate 101a can be improved, and the element isolation trench 141 having a desired shape can be accurately formed in the silicon substrate 101a.

  As a result, even if a plurality of CMOS transistors are manufactured by using the above manufacturing method, the shape of the element isolation trench of each CMOS transistor is made substantially the same, and the variation in performance among the plurality of CMOS transistors is reduced. be able to.

(Second Embodiment)
FIG. 3 is a diagram showing a processing flow of the semiconductor device manufacturing method according to the second embodiment of the present invention. This processing flow has steps S201 to S209 and S211 to S213.

  Hereinafter, steps S201 to S209 and S211 to S213 will be described with reference to FIGS. 4A to 4K.

  First, in step S201, the silicon substrate 101 shown in FIG. 4A is prepared.

  Next, in step S202, a silicon oxide film 102 having a thickness of 2 to 20 nm, for example, a thickness of 10 nm is formed on the surface of the silicon substrate 101 by thermal oxidation. Then, a silicon nitride film 103 having a thickness of 50 nm to 200 nm, for example, a thickness of 100 nm is formed on the silicon oxide film 102 by LPCVD. The silicon substrate 101 is an example of a semiconductor substrate, the silicon oxide film 102 is an example of a first insulating film, and the silicon nitride film 103 is an example of a second insulating film.

  Next, in step S203, a resist film is applied on the surface of the silicon nitride film 103 and exposed and developed to form a resist pattern 104 having a window 120 as shown in FIG. 4B. The resist pattern 104 is formed on an element formation region (active region), and the window portion 120 defines an element isolation region. That is, the window 120 is formed so as to overlap with a region to be an element isolation region. The resist pattern 104 is an example of a photoresist.

  Next, in step S204, the silicon nitride film 103 and the silicon oxide film 102 are etched. As a result, as shown in FIG. 4C, an opening 230 is formed in the silicon nitride film 103 a and the silicon oxide film 102 b, and a part of the silicon substrate 101 is exposed from the opening 230. Thereafter, the resist pattern 104 is removed to obtain the state shown in FIG. 4D.

  Next, in step S205, the width A of the adjacent portion 131 adjacent to the opening 230 with respect to the silicon nitride film 103a in which the opening 230 is formed is measured as viewed from the surface side of the silicon substrate 101.

  A SEM (scanning electron microscope) is used for the measurement, and the measured value of the width A is recorded in step S211 so that it can be compared with the design reference value. From this measurement value, a film thickness setting value is calculated in step S212. In step S213, the film thickness set value is set to a target film thickness in a third film formation step (S206) described later. The recording in step S211 is not particularly limited as long as it can be used when a third film is formed later.

  The calculation method of the film thickness set value will be described in more detail. First, the difference between the measured value of the width A and the design reference value is obtained. If this difference is outside the specified range (10 nm at the most), the target film thickness of the third film is changed. That is, if the difference is large, the target film thickness of the third film is increased. Conversely, if the difference is small, the target film thickness of the third film is decreased. Change the film thickness. At this time, it is preferable that the changed film thickness is a value obtained by multiplying the difference between the measured value of the width A and the design reference value by 0.8 to 1.5.

  Next, in step S206, as shown in FIG. 4E, an oxide film 105 as an example of a third film is formed by the LPCVD method. The oxide film 105 covers a part of the silicon substrate 101 exposed from the opening 230 and the side surfaces of the silicon nitride film 103a and the silicon oxide film 102b. The oxide film 105 is also an example of a correction insulating film.

  Here, as the film thickness B of the oxide film 105 increases, the area covered with the element isolation buried insulating film 108 described later increases on the surface of the silicon substrate 101 which becomes the channel area of the transistor (see FIG. 4H). On the other hand, when the film thickness B of the oxide film 105 is reduced, a side surface of an element isolation trench 141 described later may be exposed from the element isolation buried insulating film 108 (see FIG. 4J). The side surface of the element isolation trench 141 becomes a part of the channel region of the transistor. For this reason, the exposure of the side surface of the element isolation trench 141 causes a rapid change in transistor characteristics such as a threshold voltage and a drain current.

  In order to avoid such a rapid change in transistor characteristics, accurately control the gate width, and reduce the variation in transistor characteristics, the minimum value of the film thickness B of the oxide film 105 is the value after the transistor formation shown in FIG. 4K. In this cross-sectional view, it is necessary to make a selection in such a range that the entire side surface of the element isolation trench 141 is covered with the element isolation buried insulating film 108. Further, since the minimum value of the film thickness B of the oxide film 105 varies depending on the combination of subsequent processes, it is necessary to select an optimum value in a timely manner. In this embodiment, the oxide film 105 is also used as an example of the third film and the correction insulating film. However, a film made of an appropriate material in consideration of film thickness control and subsequent processing conditions is used as the third film, It may also be used as an example of a correction insulating film. That is, the third film and the correction insulating film are not limited to the oxide film 105. Examples of the third film include a silicon oxide film and a silicon nitride film.

  Next, in step S207, the oxide film 105 in contact with the surface of the silicon nitride film 103a and the oxide film 105 in contact with the surface of the silicon substrate 101 are etched under strongly anisotropic conditions by the RIE method. As a result, as shown in FIG. 4F, a sidewall-like sidewall protective film 105b is formed so as to cover the sidewall of the silicon nitride film 103a. At this time, a part of the silicon substrate 101 shown in FIG. 4E is exposed.

  Next, in step S208, a part of the silicon substrate 101 is etched to obtain a silicon substrate 101a having element isolation trenches 141 as shown in FIG. 4F. At this time, the element isolation trench 141 is formed to have a depth of 160 to 500 nm, for example, 300 nm.

  When the element isolation trench 141 is formed, the width becomes smaller than the width C (width A + 2 × film thickness B) of the active region due to loss at the time of etching, but as described above, the width A is smaller than the design reference value. In contrast, the thickness B is increased, and conversely, when the width A is larger than the design reference value, the adjustment is performed to decrease B, so that fluctuation of the width C can be prevented. As a result, since the gate width of the transistor is formed stably, variation in transistor characteristics, in particular, drain current of a transistor having a narrow channel width can be reduced.

  Next, as shown in FIG. 4G, after the trench surface oxide film 106 is formed on the bottom and side surfaces of the element isolation trench 141, the element isolation buried insulating film 108 shown in FIG. 4H is formed. A part of the element isolation buried insulating film 108 is buried in the element isolation trench 141.

  Next, as shown in FIG. 4I, a surface flattening step such as polishing is performed to obtain a buried insulating film 108c for element isolation.

  Next, as shown in FIG. 4J, the silicon nitride film 103a is removed by immersion in heated phosphoric acid, and the silicon oxide film 102b is removed by wet etching. Thereby, a buried insulating film 108d for element isolation is obtained.

  Next, in step S209, an element is formed. More specifically, as shown in FIG. 4K, a gate insulating film 110 and a gate electrode 111 are formed according to a normal CMOS LSI process. Prior to the formation of the gate insulating film 110, impurities may be introduced into the silicon substrate 101a to form wells in the silicon substrate 101a. Further, after forming gate spacers 112 on both sides of the gate electrode 111, source / drain portions 113 are formed on the silicon substrate 101a. Then, an interlayer film 114, contact plugs 115, and wirings 116 are formed.

  According to the manufacturing method of this embodiment, even if the silicon nitride film 103a is removed and the silicon oxide film 102b is removed by wet etching, as shown in FIG. 4J, the element isolation trench 108d is removed from the element isolation buried insulating film 108d. Part of 141 is not exposed.

  Therefore, it is possible to prevent the occurrence of a short circuit or leakage between the gate electrode 111 and the silicon substrate 101.

  Further, the sidewall protective film 105b is formed of a part of the oxide film 105 formed by adjusting the film thickness according to the measured value of the width A of the adjacent portion 131 adjacent to the opening 230, so that variations in process processing are reduced. Can be reduced.

  Therefore, the processing accuracy of the silicon substrate 101a can be improved, and the element isolation trench 141 having a desired shape can be accurately formed in the silicon substrate 101a.

  As a result, even if a plurality of CMOS transistors are manufactured by using the above manufacturing method, the shape of the element isolation trench of each CMOS transistor is made substantially the same, and the variation in performance among the plurality of CMOS transistors is reduced. be able to.

  In the second embodiment, in step S201, the width A of the adjacent portion 131 adjacent to the opening 230 with respect to the silicon nitride film 103a is measured as viewed from the front surface side of the silicon substrate 101, but with respect to the silicon nitride film 103a. The width A of the adjacent portion 131 adjacent to the opening 230 is measured when viewed from the surface side of the silicon substrate 101, and the width of the adjacent portion adjacent to the opening 230 with respect to the silicon oxide film 102b is also measured on the surface side of the silicon substrate 101. You may measure from the point of view. In this case, the target film thickness in step S213 may be set from the width A of the adjacent portion 131 of the silicon nitride film 103a and the width of the adjacent portion of the silicon oxide film 102b. The target film thickness of the oxide film 105 is obtained in advance by using an electrical or physical method to obtain a correlation between the execution gate width of the transistor and the oxide film 105, and by using the correlation equation, the execution gate width of the desired transistor is obtained. Select a film thickness such that

  In the first and second embodiments, the CMOS transistor is manufactured by using the present invention. However, for example, a MOS transistor may be manufactured by using the present invention, or an element isolation trench is provided. The semiconductor device may be manufactured.

  Although the invention made by the present inventor has been specifically described based on the first and second embodiments, the present invention is not limited to the first and second embodiments, and departs from the gist thereof. Various changes can be made without departing from the scope.

FIG. 1 is a process flow diagram of a CMOS transistor manufacturing method according to the first embodiment of the present invention. FIG. 2A is a schematic cross-sectional view of one manufacturing process of the CMOS transistor of the first embodiment. FIG. 2B is a schematic cross-sectional view of one manufacturing process of the CMOS transistor of the first embodiment. FIG. 2C is a schematic cross-sectional view of one manufacturing process of the CMOS transistor of the first embodiment. FIG. 2D is a schematic cross-sectional view of one manufacturing process of the CMOS transistor of the first embodiment. FIG. 2E is a schematic cross-sectional view of one manufacturing process of the CMOS transistor of the first embodiment. FIG. 2F is a schematic cross-sectional view of one manufacturing process of the CMOS transistor of the first embodiment. FIG. 2G is a schematic cross-sectional view of one manufacturing process of the CMOS transistor of the first embodiment. FIG. 2H is a schematic cross-sectional view of one manufacturing process of the CMOS transistor of the first embodiment. FIG. 2I is a schematic cross-sectional view of one manufacturing process of the CMOS transistor of the first embodiment. FIG. 2J is a schematic cross-sectional view of one manufacturing process of the CMOS transistor of the first embodiment. FIG. 2K is a schematic cross-sectional view of one manufacturing process of the CMOS transistor of the first embodiment. FIG. 3 is a process flow diagram of the CMOS transistor manufacturing method according to the second embodiment of the present invention. FIG. 4A is a schematic cross-sectional view of one manufacturing process of the CMOS transistor of the second embodiment. FIG. 4B is a schematic cross-sectional view of one manufacturing process of the CMOS transistor of the second embodiment. FIG. 4C is a schematic cross-sectional view of one manufacturing process of the CMOS transistor of the second embodiment. FIG. 4D is a schematic cross-sectional view of one manufacturing process of the CMOS transistor of the second embodiment. FIG. 4E is a schematic cross-sectional view of one manufacturing process of the CMOS transistor of the second embodiment. FIG. 4F is a schematic cross-sectional view of one manufacturing process of the CMOS transistor of the second embodiment. FIG. 4G is a schematic cross-sectional view of one manufacturing process of the CMOS transistor of the second embodiment. FIG. 4H is a schematic cross-sectional view of one manufacturing process of the CMOS transistor of the second embodiment. FIG. 4I is a schematic cross-sectional view of one manufacturing process of the CMOS transistor of the second embodiment. FIG. 4J is a schematic cross-sectional view of one manufacturing process of the CMOS transistor of the second embodiment. FIG. 4K is a schematic cross-sectional view of one manufacturing process of the CMOS transistor of the second embodiment. FIG. 5 is a process flow diagram of a CMOS transistor manufacturing method for explaining the problem of the present invention. FIG. 6A is a schematic cross-sectional view of one manufacturing process of a CMOS transistor for explaining the problem of the present invention . FIG. 6B is a schematic cross-sectional view of one manufacturing process of the CMOS transistor for explaining the problem of the present invention . FIG. 6C is a schematic cross-sectional view of one manufacturing process of the CMOS transistor for explaining the problem of the present invention . FIG. 6D is a schematic cross-sectional view of one manufacturing process of the CMOS transistor for explaining the problem of the present invention . FIG. 6E is a schematic cross-sectional view of one manufacturing process of the CMOS transistor for explaining the problem of the present invention . FIG. 6F is a schematic cross-sectional view of one manufacturing process of the CMOS transistor for explaining the problem of the present invention . FIG. 6G is a schematic cross-sectional view of one manufacturing process of the CMOS transistor for explaining the problem of the present invention . FIG. 6H is a schematic cross-sectional view of one manufacturing process of the CMOS transistor for explaining the problem of the present invention . FIG. 6I is a schematic cross section of one manufacturing process of a CMOS transistor for explaining the problem of the present invention .

101, 101a Silicon substrate 102, 102a, 102b Silicon oxide film 103, 103a Silicon nitride film 104 Resist pattern 105 Oxide film 105a, 105b Side wall protective film 108, 108a, 108b, 108c, 108d Embedded isolation film 120 for element isolation Window part 130 , 230 Opening 131 Adjacent part

Claims (9)

Preparing a semiconductor substrate;
Forming a first insulating film on the surface of the semiconductor substrate;
Forming a second insulating film made of a material different from the first insulating film on the surface of the first insulating film;
Forming a photoresist having a window for forming an element isolation trench on the surface of the second insulating film;
Using the photoresist as a mask, removing a part of the second insulating film to form an opening in the second insulating film to expose a part of the surface of the first insulating film When,
After removing the photoresist, measuring the width of the adjacent portion adjacent to the opening with respect to the second insulating film in which the opening is formed, as viewed from the surface side of the semiconductor substrate;
Calculating the difference between the measurement value of the width of the adjacent portion and the design reference value;
The film thickness calculated from the above difference is applied to the third film covering a part of the first insulating film exposed from the opening and the side surface and surface of the second insulating film in which the opening is formed. forming by a thickness adjusted to have,
Etching is performed so as to leave a part of the third film covering the side surface of the second insulating film in which the opening is formed, thereby forming a side wall protective film made of a part of the third film. Process,
Using the second insulating film in which the opening is formed and the side wall protective film as a mask, the first insulating film and a part of the semiconductor substrate are etched to form the element isolation on the semiconductor substrate. A method for manufacturing a semiconductor device, comprising: forming a trench. Preparing a semiconductor substrate;
Forming a first insulating film on the surface of the semiconductor substrate;
Forming a second insulating film on the surface of the first insulating film;
Forming a photoresist having a window for forming an element isolation trench on the surface of the second insulating film;
By using the photoresist as a mask, the second insulating film and a part of the first insulating film are removed, whereby the second insulating film and the first insulating film are formed on the surface of the semiconductor substrate. Forming an opening exposing a portion;
After removing the photoresist, measuring the width of the adjacent portion adjacent to the opening with respect to the second insulating film in which the opening is formed, as viewed from the surface side of the semiconductor substrate;
Calculating the difference between the measurement value of the width of the adjacent portion and the design reference value;
First covering the part of the semiconductor substrate exposed from the opening, the side surface of the first insulating film in which the opening is formed, and the side surface and surface of the second insulating film in which the opening is formed. The step of adjusting the film thickness to have the film thickness calculated from the above difference ,
Etching so that a part of the third film covering the side surface of the first insulating film in which the opening is formed and the side surface of the second insulating film in which the opening is formed remain. Forming a sidewall protective film comprising a part of the third film;
Forming a trench for element isolation in the semiconductor substrate by etching a part of the semiconductor substrate using the second insulating film in which the opening is formed and the sidewall protective film as a mask; A method for manufacturing a semiconductor device, comprising: In the manufacturing method of the semiconductor device according to claim 2,
A step of measuring the width of the adjacent portion adjacent to the opening with respect to the first insulating film in which the opening is formed after removing the photoresist, as viewed from the surface side of the semiconductor substrate; A method of manufacturing a semiconductor device. In the manufacturing method of the semiconductor device according to any one of claims 1 to 3,
The method of manufacturing a semiconductor device, wherein the third film is any one of a silicon oxide film, a silicon nitride film, a SiON film, and a polysilicon film. In the manufacturing method of the semiconductor device according to any one of claims 1 to 4,
The method of manufacturing a semiconductor device, wherein the thickness of the third film is 5 to 50 nm. In the manufacturing method of the semiconductor device according to any one of claims 1 to 5,
The method of manufacturing a semiconductor device, wherein the third film is formed by a chemical vapor deposition method. In the manufacturing method of the semiconductor device according to any one of claims 1 to 6,
A method of manufacturing a semiconductor device, wherein the second insulating film is a silicon nitride film. A semiconductor device manufactured using the method for manufacturing a semiconductor device according to any one of claims 1 to 7,
A semiconductor substrate having the element isolation trench and an active region defined by the element isolation trench;
A buried insulating film buried in the element isolation trench;
A gate insulating film formed on the active region;
A gate electrode formed on the gate insulating film,
The semiconductor device, wherein the buried insulating film covers the entire sidewall of the element isolation trench. A MOS transistor manufactured using the method for manufacturing a semiconductor device according to claim 1,
A semiconductor substrate having the element isolation trench and an active region defined by the element isolation trench;
A buried insulating film buried in the element isolation trench;
A gate insulating film formed on the active region;
A gate electrode formed on the gate insulating film,
The MOS transistor according to claim 1, wherein the buried insulating film covers the entire sidewall of the element isolation trench.

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