JP2008042045A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device which improves an yield compared with a conventional device. <P>SOLUTION: The method of manufacturing the semiconductor device is provided with a process of forming mask films 21 and 22 on a semiconductor substrate positioned in an element area for forming an element separation film 2, a process of measuring sizes of mask films 21 and 22 a process of calculating a thermal oxidation amount for forming the element separation film 2 based on the difference of a measured size from the design size of the mask films 21 and 22, and a process of forming the element separation film 2 by thermal oxidation of the semiconductor substrate 1 with the mask films 21 and 22 as a mask according to the calculated thermal oxidation amount. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, which can improve the yield as compared with the prior art.

  FIG. 10 is a cross-sectional view for explaining the method for manufacturing a semiconductor device according to the first conventional example. First, the element isolation film 102 is formed on the silicon substrate 100 to isolate the element region from other regions. Next, a gate oxide film 103 is formed on the silicon substrate 100 located in the element region, and then a gate electrode 104 is formed on the gate oxide film 103. Next, two low-concentration impurity regions 106 and two pocket regions 106 a are formed, and the sidewall of the gate electrode 104 is covered with a sidewall 105. Next, two impurity regions 107 to be a source and a drain are formed. Thereby, a transistor is formed (see, for example, Patent Document 1).

  In the first conventional example, after each step, the dimension of the member formed in each step is measured, and it is inspected whether the measurement result is within the reference range. Further, it is inspected whether the performance of the finally formed transistor satisfies the standard.

  FIG. 11 is a cross-sectional view for explaining a method for manufacturing a semiconductor device according to a second conventional example. First, an element isolation film 102 is formed on the silicon substrate 100, and a polysilicon film is further formed on the element isolation film 102. Next, a resist pattern is formed on the polysilicon film, and the polysilicon film is selectively removed by etching the polysilicon film using the resist pattern as a mask. As a result, a polysilicon resistor 112 is formed on the element isolation film 102. Thereafter, impurities are introduced into the polysilicon resistor 112.

JP 2000-040747 A (FIG. 1, paragraphs 7 to 14)

  As described above, when manufacturing a semiconductor device, it is inspected that the performance of the finally formed transistor satisfies the standard. For example, even if the dimensions of individual components are within the standard range, if the dimensions of multiple components deviate significantly from the design values, the performance degradation due to these deviations overlaps, resulting in the transistor performance being the standard. May not be satisfied.

  In addition, since the resistance element is used in an analog circuit, it is necessary to strictly manage the resistance value. For this reason, in order to increase the yield of a semiconductor device having a resistance element, it is necessary to reduce the variation in resistance value.

  The present invention has been made in consideration of the above-described circumstances, and an object of the present invention is to provide a method of manufacturing a semiconductor device capable of improving the yield as compared with the prior art.

In order to solve the above problems, a method of manufacturing a semiconductor device according to the present invention includes a step of forming a mask film on a semiconductor substrate located in an element region in order to form an element isolation film;
Measuring the width of the mask film;
Calculating a thermal oxidation amount for forming an element isolation film based on a difference in measurement width with respect to a design width of the mask film;
Forming a device isolation film on the semiconductor substrate by thermally oxidizing the semiconductor substrate using the mask film as a mask according to the calculated thermal oxidation amount.

  According to this method of manufacturing a semiconductor device, the amount of thermal oxidation of the element isolation film can be adjusted according to the width of the mask film, and the size of the bird's beak can be adjusted. Therefore, the variation in the width of the element region can be reduced, the variation in the characteristics of the semiconductor device can be reduced, and the yield of the semiconductor device can be improved.

Another method of manufacturing a semiconductor device according to the present invention includes a step of forming an element isolation film on a semiconductor substrate,
Measuring a width of an element region of the semiconductor substrate separated by the element isolation film;
Forming a sacrificial thermal oxide film on a semiconductor substrate located in the element region;
Calculating an etching amount when removing the sacrificial thermal oxide film based on a difference in measurement width with respect to a design width of the element region;
Etching the sacrificial thermal oxide film and removing the surface layer of the element isolation film by performing etching according to the calculated etching amount.

  According to this method of manufacturing a semiconductor device, since the etching amount of the sacrificial thermal oxide film and the element isolation film is adjusted according to the width of the element region, the variation in the width of the element region can be reduced. . Therefore, variation in characteristics of the semiconductor device can be reduced and the yield of the semiconductor device can be improved.

Another method of manufacturing a semiconductor device according to the present invention includes a step of forming an element isolation film on a semiconductor substrate,
Measuring a width of an element region of the semiconductor substrate separated by the element isolation film;
Forming a gate insulating film on the semiconductor substrate located in the element region;
Forming a semiconductor film on the gate insulating film and the element isolation film;
Forming a photoresist film on the semiconductor film;
Calculating an exposure amount of the photoresist film based on a difference in measurement width with respect to a design width of the element region;
Forming a resist pattern located on the semiconductor film by exposing the photoresist film in accordance with the calculated exposure amount and then developing the photoresist film; and
Forming a gate electrode by etching the semiconductor film using the resist pattern as a mask.

  According to this method for manufacturing a semiconductor device, the exposure amount when the resist pattern is formed can be adjusted according to the dimensions of the element region, and the width of the gate electrode can be adjusted. Therefore, variation in characteristics of the semiconductor device can be reduced and the yield of the semiconductor device can be improved. Note that the step of calculating the exposure amount may be performed at any timing as long as the width of the element region is measured and before the resist pattern is formed.

Another method of manufacturing a semiconductor device according to the present invention includes a step of forming a gate insulating film of a transistor on each of the first and second semiconductor substrates;
Measuring the thickness of the gate insulating film of the first semiconductor substrate;
The amount of impurities introduced into the pocket region or LDD region formed below the gate insulating film of the second semiconductor substrate based on the difference in the measured film thickness of the gate insulating film with respect to the design film thickness of the gate insulating film Calculating
And introducing an impurity into the pocket region or the LDD region of the second semiconductor substrate according to the calculated impurity amount.

Another method of manufacturing a semiconductor device according to the present invention includes a step of forming a gate insulating film of a transistor on a semiconductor substrate,
Measuring the thickness of the gate insulating film;
Calculating an impurity amount to be introduced into a pocket region or an LDD region located below the gate insulating film based on a difference in measured film thickness with respect to a design film thickness of the gate insulating film;
Introducing impurities into the pocket region or the LDD region according to the calculated amount of impurities.

  According to these semiconductor device manufacturing methods, the amount of impurities introduced into the pocket region or the LDD region is adjusted by the thickness of the gate insulating film. Therefore, variation in threshold voltage of transistors can be reduced and yield of semiconductor devices can be improved.

Another method of manufacturing a semiconductor device according to the present invention includes a step of forming a gate insulating film of a transistor on a semiconductor substrate on each of the first and second semiconductor substrates,
Measuring a thickness of the gate insulating film formed on the first semiconductor substrate;

Forming a semiconductor film on the gate insulating film of the second semiconductor substrate;
Forming a photoresist film on the semiconductor film;
Calculating an exposure amount of the photoresist film based on a difference in measured film thickness with respect to a design film thickness of the gate insulating film;
Forming a resist pattern located on the semiconductor film by exposing the photoresist film in accordance with the calculated exposure amount and then developing the photoresist film; and
Forming a gate electrode on the second semiconductor substrate by etching the semiconductor film using the resist pattern as a mask.

Another method of manufacturing a semiconductor device according to the present invention includes a step of forming a gate insulating film of a transistor on a semiconductor substrate,
Measuring the thickness of the gate insulating film;
Forming a semiconductor film on the gate insulating film;
Forming a photoresist film on the semiconductor film;
Calculating an exposure amount of the photoresist film based on a difference in measured film thickness with respect to a design film thickness of the gate insulating film;
Forming a resist pattern located on the semiconductor film by exposing the photoresist film in accordance with the calculated exposure amount and then developing the photoresist film; and
Forming a gate electrode by etching the semiconductor film using the resist pattern as a mask.

  According to these semiconductor device manufacturing methods, the width of the gate electrode is adjusted by the thickness of the gate insulating film. Therefore, variation in threshold voltage of transistors can be reduced and yield of semiconductor devices can be improved. Note that the step of calculating the exposure amount may be performed at any timing after the film thickness of the gate insulating film is measured and before the resist pattern is formed.

Another method of manufacturing a semiconductor device according to the present invention includes a step of forming a gate insulating film of a transistor on each of the first and second semiconductor substrates;
Measuring a thickness of the gate insulating film formed on the first semiconductor substrate;
Calculating a film thickness of an insulating film serving as a sidewall of a gate electrode formed on the second semiconductor substrate based on a difference in measured film thickness with respect to a design film thickness of the gate insulating film;
Forming a gate electrode on the gate insulating film of the second semiconductor substrate;
Forming an insulating film having the calculated film thickness on and around the gate electrode;
Etching back the insulating film to form a sidewall on the side wall of the gate electrode;
Forming two impurity regions serving as a source and a drain in the semiconductor substrate by introducing impurities into the semiconductor substrate using the gate electrode and the sidewall as a mask.

Another method of manufacturing a semiconductor device according to the present invention includes a step of forming a gate insulating film of a transistor on a semiconductor substrate,
Measuring the thickness of the gate insulating film;
Calculating a film thickness of an insulating film serving as a sidewall of the gate electrode based on a difference in measured film thickness with respect to a design film thickness of the gate insulating film;
Forming a gate electrode on the gate insulating film;
Forming an insulating film having the calculated film thickness on and around the gate electrode;
Etching back the insulating film to form a sidewall on the side wall of the gate electrode;
Forming two impurity regions serving as a source and a drain in the semiconductor substrate by introducing impurities into the semiconductor substrate using the gate electrode and the sidewall as a mask.

  According to this method for manufacturing a semiconductor device, the width of the sidewall is adjusted by the film thickness of the gate insulating film. Therefore, variation in threshold voltage of transistors can be reduced and yield of semiconductor devices can be improved.

Another method of manufacturing a semiconductor device according to the present invention includes a step of forming a gate insulating film of a transistor on a semiconductor substrate,
Forming a gate electrode on the gate insulating film;
Measuring the width of the gate electrode;
Calculating a film thickness of an insulating film serving as a sidewall of the gate electrode based on a difference of a measurement width of the gate electrode with respect to a design width of the gate electrode;
Forming an insulating film having the calculated film thickness on and around the gate electrode;
Etching back the insulating film to form a sidewall on the side wall of the gate electrode;
Forming two impurity regions serving as a source and a drain in the semiconductor substrate by introducing impurities into the semiconductor substrate using the gate electrode and the sidewall as a mask.

  According to this method for manufacturing a semiconductor device, the width of the sidewall is adjusted by the width of the gate electrode. Therefore, variation in threshold voltage of transistors can be reduced and yield of semiconductor devices can be improved.

The method of manufacturing a semiconductor device according to the present invention includes a step of forming an element isolation film on each of the first and second semiconductor substrates,
Forming a semiconductor film on the element isolation film in each of the first and second semiconductor substrates;
Measuring the thickness of the semiconductor film formed on the first semiconductor substrate;
Calculating an amount of impurities to be introduced into the semiconductor film based on a difference in measured film thickness with respect to a design film thickness of the semiconductor film;
Introducing impurities into the semiconductor film formed on the second semiconductor substrate according to the calculated amount of impurities;
Forming a resistance element on the second semiconductor substrate by selectively removing the semiconductor film.

Another method of manufacturing a semiconductor device according to the present invention includes a step of forming an element isolation film on each of the first and second semiconductor substrates,
Forming a semiconductor film on the element isolation film in each of the first and second semiconductor substrates;
Measuring the thickness of the semiconductor film formed on the first semiconductor substrate;
Forming a resistance element by selectively removing the semiconductor film formed on the second semiconductor substrate;
A step of calculating an impurity amount to be introduced into the resistance element based on a difference in measured film thickness with respect to a design film thickness of the semiconductor film;
Introducing an impurity into the resistance element according to the calculated impurity amount.

  According to these semiconductor device manufacturing methods, the amount of impurities introduced into the resistance element is adjusted by the thickness of the resistance element. Therefore, variation in the resistance value of the resistance element is reduced, and the yield of the semiconductor device is improved.

Another method of manufacturing a semiconductor device according to the present invention includes a step of forming an element isolation film on each of the first and second semiconductor substrates,
Forming a semiconductor film on the element isolation film in each of the first and second semiconductor substrates;
Measuring the thickness of the semiconductor film formed on the first semiconductor substrate;
Forming a photoresist film on the semiconductor film formed on the second semiconductor substrate;
Calculating an exposure amount of the photoresist film based on a difference in measured film thickness with respect to a design film thickness of the semiconductor film;
Forming a resist pattern located on the semiconductor film by exposing the photoresist film in accordance with the calculated exposure amount and then developing the photoresist film; and
Forming a resistance element on the second semiconductor substrate by etching the semiconductor film using the resist pattern as a mask.

  According to this method for manufacturing a semiconductor device, the width of the resistance element is adjusted by the thickness of the resistance element. Therefore, variation in the resistance value of the resistance element is reduced, and the yield of the semiconductor device is improved. Note that the step of calculating the exposure amount may be performed at any timing after the film thickness of the semiconductor film is measured and before the resist pattern is formed.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. Each drawing in FIG. 1 is a cross-sectional view for explaining the method for manufacturing a semiconductor device according to the first embodiment of the present invention. In this embodiment, when forming the element isolation film by the LOCOS oxidation method, the dimension of the mask film covering the element region is measured, and the oxidization time is adjusted based on the measurement result, whereby the variation in the dimension of the element region is achieved. It is a method of suppressing the above.

  First, as shown in FIG. 1A, a silicon oxide film 21 is formed on a silicon substrate 1 by a CVD method, and a silicon nitride film 22 is further formed on the silicon oxide film 21 by a CVD method. Next, a resist pattern (not shown) is formed on the silicon nitride film 22, and the silicon nitride film 22 and the silicon oxide film 21 are etched using the resist pattern as a mask. Thereby, the silicon nitride film 22 and the silicon oxide film 21 are removed except for the element region where the transistor is formed. Thereafter, the resist pattern is removed.

Then, measure the width _{L 1} of the silicon nitride film 22. Then, based on the difference between the measurement results for the design value of the width L _1, to calculate the thermal oxidation time of the silicon substrate 1. Specifically, larger than the design value width L _1, the thermal oxidation time longer than the standard time, when the width L ₁ is smaller than the design value, is shorter than the standard time thermal oxidation time.

Next, as shown in FIG. 1B, the silicon substrate 1 is thermally oxidized. Thereby, the element isolation film 2 is formed on the silicon substrate 1, and the element region covered with the silicon nitride film 22 and the silicon oxide film 21 is isolated from other areas. As described above, larger than the design value width L ₁ of the silicon nitride film 22, the thermal oxidation time is longer than the standard time, bird's beak 2a grow than standard. Further, when the width L ₁ is smaller than the design value, since the thermal oxidation time is shorter than the standard time, bird's beak 2a is smaller than the standard. Accordingly, variation in the dimensions of the element region can be reduced.

  Thereafter, as shown in FIG. 1C, the silicon nitride film 22 and the silicon oxide film 21 are removed. Next, the silicon substrate 1 is thermally oxidized. Thereby, a gate oxide film 3 is formed on the silicon substrate 1. Next, a polysilicon film is formed on the gate oxide film 3 by the CVD method, and this polysilicon film is selectively removed. Thereby, a gate electrode 4 is formed on the gate oxide film 3. Next, a first conductivity type (for example, n-type) impurity is introduced into the silicon substrate 1 using the gate electrode 4 and the element isolation film 2 as a mask. As a result, a low concentration impurity region (LDD region) 6 is formed in the silicon substrate 1. Next, a second conductivity type (for example, p-type) impurity is introduced into the silicon substrate 1 using the gate electrode 4 and the element isolation film 2 as a mask. As a result, pocket regions 6 a are formed in the silicon substrate 1.

Next, an insulating film (for example, a silicon nitride film) is formed on the entire surface including the gate electrode 4, and this insulating film is etched back. Thereby, the side wall of the gate electrode 4 is covered with the side wall 5. Next, a first conductivity type impurity is introduced into the silicon substrate 1 using the sidewall 5, the gate electrode 4, and the element isolation film 2 as a mask. As a result, two impurity regions 7 functioning as a source and a drain are formed in the silicon substrate 1.
In this way, a transistor is formed on the silicon substrate 1.

Above, first according to one embodiment, when the width L ₁ of the silicon nitride film 22 is larger than the design value is a mask layer for forming the device isolation film 2, a standard time thermal oxidation time of the present invention and longer, when the width L ₁ is smaller than the design value, it is shorter than the standard time thermal oxidation time. For this reason, the dispersion | variation in the dimension of an element area | region can be made small. Accordingly, variation in transistor characteristics is suppressed, and the yield of the semiconductor device is improved.

  When a TEG for measuring the dimensions of the silicon nitride film 22 and the silicon oxide film 21 is formed on the silicon substrate 1, the thermal oxidation time of the silicon substrate 1 is calculated based on the TEG measurement result. good.

  Each drawing in FIG. 2 is a cross-sectional view for explaining the method for manufacturing a semiconductor device according to the second embodiment. In this embodiment, after the element isolation film 2 is formed, the dimension of the element region is measured, and the etching time for etching the sacrificial oxide film is calculated based on the measurement result. It is a method of suppressing. Hereinafter, the same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

First, as shown in FIG. 2A, an element isolation film 2 is formed, and an element region is isolated from other regions. The method for forming the element isolation film 2 is the same as in the first embodiment. Then, measure the width L ₂ of the element region. Then, based on the difference between the measured value for the design value of the width L _2, calculates the etch time of the sacrificial oxide film formed on the silicon substrate 1. Specifically, larger than the design value width L _2, the etching time was shorter than the standard time, when the width L ₂ is smaller than the design value, is longer than the standard time and the etching time.

  Next, as shown in FIG. 2B, the silicon substrate 1 is thermally oxidized. Thereby, a sacrificial oxide film 23 is formed on the silicon substrate 1 located in the element region.

Next, as shown in FIG. 2C, the sacrificial oxide film 23 is removed by etching. At this time, the surface layer of the element isolation film 2 is also removed. As described above, larger than the design value width L ₂ of the element region, the etching time is shorter than the standard time, etched than the surface layer of the isolation layer 2 standard, erosion of the bird's beak i.e. The amount of expansion of the element region is reduced. Further, when the width L ₂ is smaller than the design value, is longer than the standard time and the etching time, it is etched than the surface layer of the isolation layer 2 standard, expansion amount of the element region is increased. Accordingly, variation in the dimensions of the element region can be reduced.

  Next, as shown in FIG. 2D, a gate oxide film 3, a gate electrode 4, a low concentration impurity region 6, a pocket region 6a, a sidewall 5, and an impurity region 7 are formed. These forming methods are the same as those in the first embodiment.

  As described above, also in this embodiment, the same effect as that of the first embodiment can be obtained. When a TEG for measuring the dimension of the element region is formed on the silicon substrate 1, the etching time of the sacrificial oxide film 23 may be calculated based on the TEG measurement result.

  FIG. 3 is a cross-sectional view for explaining the method for manufacturing a semiconductor device according to the third embodiment. In the present embodiment, after the element isolation film 2 is formed, the dimension of the element region is measured, and the exposure amount of the photoresist film when the gate electrode 4 is etched based on the measurement result is calculated. It is a method of suppressing the variation of the. Hereinafter, the same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

First, as shown in FIG. 3A, an element isolation film 2 is formed, and an element region is isolated from other regions. The method for forming the element isolation film 2 is the same as in the first embodiment. Then, measure the width L ₂ of the element region.

  Next, as shown in FIG. 3B, a gate oxide film 3 is formed. The method for forming the gate oxide film 3 is the same as in the first embodiment. Next, a polysilicon film 40 is formed on the gate oxide film 3, and a photoresist film is applied on the polysilicon film 40.

Then, based on the difference between the measured value for the design value of the width L ₂ of the element region, to calculate the exposure amount of the photoresist film. Specifically, if the width L ₂ is smaller than the design value, the resist pattern to be formed is shifted from the standard value exposure amount narrowing direction than the design value. The width L ₂ is the larger than the design value, the resist pattern to be formed is shifted from the standard value exposure amount thicker consisting direction than the designed value. Next, the photoresist film is exposed and developed. Thereby, a resist pattern 50 is formed on the polysilicon film 40. Width L ₃ of the resist pattern 50 is narrower than the design value when the width L ₂ is smaller than the design value, thicker than the design value larger than the design value width L _2.

Next, as shown in FIG. 3C, the polysilicon film 40 is etched using the resist pattern 50 as a mask. Thereby, a gate electrode 4 is formed on the gate oxide film 3. As described above, the width L ₃ of the resist pattern 50 is narrower than the design value when the width L _{2 of the} element region is smaller than the design value, and thicker than the design value when the width L ₂ is larger than the design value. Therefore, the width of the gate electrode 4 is thinner than the design value when the width L ₂ is smaller than the design value, thicker than the design value larger than the design value width L _2. When the width L ₂ of the element area becomes smaller, the threshold voltage V _th of the transistor becomes high, the width of the gate electrode 4 is increased, the threshold voltage V _th of the transistor becomes small. Therefore, by adjusting the width of the gate electrode 4 on the basis of the width L _2, it is possible to reduce variations in the threshold voltage V _th of the transistor.

  Thereafter, as shown in FIG. 3D, the resist pattern 50 is removed. Next, the low concentration impurity region 6, the pocket region 6a, the sidewall 5, and the impurity region 7 are formed. These forming methods are the same as those in the first embodiment.

As described above, according to this embodiment, since the adjusting the width of the gate electrode 4 on the basis of the width L ₂ of the device region, it is possible to reduce variations in the threshold voltage V _th of the transistor. Accordingly, the yield of the semiconductor device is improved.

  Each drawing in FIG. 4 is a cross-sectional view for explaining the method for manufacturing a semiconductor device according to the fourth embodiment. This embodiment is a method for suppressing variations in transistor characteristics by adjusting the amount of impurities in the pocket region 6a based on the thickness of the gate oxide film. Hereinafter, the same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

  First, as shown in FIG. 4A, element isolation films 2 and 32 and gate oxide films 3 and 33 are formed on the silicon substrate 1 and the monitor substrate 30 in the same process. These forming methods are the same as the method of forming the element isolation film 2 and the gate oxide film 3 on the silicon substrate 1 in the first embodiment.

Next, the monitor substrate 30 is cut, and the thickness t ₁ of the gate oxide film 33 is measured. Since the gate oxide films 3 and 33 are simultaneously formed in the same process, the thickness t ₁ of the gate oxide film 33 can be considered to be substantially the same as the thickness t ₂ of the gate oxide film 3. Then, based on the difference between the measured value for the design value of the thickness t ₁ of the gate oxide film 33, and calculates the amount of impurities in the pocket region 6a.

Specifically, when the thickness of the gate oxide film 33 is thinner than the design value, the amount of impurities in the pocket region 6a is made larger than the design value, and when the thickness of the gate oxide film 33 is thicker than the design value, The impurity amount of 6a is made smaller than the design value. When the gate oxide film 33 is reduced threshold voltage V _th of the transistor is lowered, but by increasing the amount of impurities in the pocket area 6a, it is because it is possible to raise the threshold voltage V _th.

  Next, as shown in FIG. 4B, the gate electrode 4, the low concentration impurity region 6, the pocket region 6a, the sidewall 5, and the impurity region 7 are formed. These forming methods are the same as those in the first embodiment. However, the amount of impurities introduced into the pocket region 6a follows the calculated value.

As described above, according to the present embodiment, based on the thickness t ₁ of the gate oxide film 33, for calculating the amount of impurities in the pocket regions 6a, it is possible to reduce variations in the threshold voltage V _th of the transistor. Therefore, the yield of the semiconductor device can be improved.

In the present embodiment, the impurity amount of the low concentration impurity region 6 may be adjusted based on the thickness t ₁ of the gate oxide film 33 instead of the impurity amount of the pocket region 6a. Specifically, when the thickness of the gate oxide film 33 is thinner than the design value, the impurity amount of the low concentration impurity region 6 is made smaller than the design value, and when the thickness of the gate oxide film 33 is thicker than the design value, The amount of impurities in the low concentration impurity region 6 is made larger than the design value. Even in this case, the variation in the threshold voltage _Vth of the transistor can be reduced and the yield of the semiconductor device can be improved.

Further, for example, when the film thickness t ₂ of the gate oxide film 3 can be measured nondestructively by an optical technique, the above-described implementation is performed based on the difference in the measured value with respect to the design value of the film thickness t ₂ of the gate oxide film 3. Similarly to the example, the impurity amount of the pocket region 6a or the impurity amount of the low-concentration impurity region 6 may be calculated.

  Each drawing in FIG. 5 is a cross-sectional view for explaining the method for manufacturing a semiconductor device according to the fifth embodiment. The present embodiment is a method of suppressing variations in transistor characteristics by calculating the exposure amount of a photoresist film when the gate electrode 4 is etched by the thickness of the gate oxide film. Hereinafter, the same components as those in the fourth embodiment are denoted by the same reference numerals, and description thereof is omitted.

First, as shown in FIG. 5A, the element isolation films 2 and 32 and the gate oxide films 3 and 33 are formed on the silicon substrate 1 and the monitor substrate 30, and the thickness t ₁ of the gate oxide film 33 is measured. . These steps are the same as those in the fourth embodiment.

Next, as shown in FIG. 5B, a polysilicon film 40 is formed on the gate oxide film 3, and a photoresist film is applied on the polysilicon film 40. Next, the exposure amount of the photoresist film is calculated based on the difference of the measured value with respect to the design value of the thickness t ₁ of the gate oxide film 33. Specifically, when the thickness t ₁ is thinner than the design value, the resist pattern to be formed is shifted from the standard value exposure amount thicker consisting direction than the designed value. Further, if the thickness t ₁ is larger than the design value, the resist pattern to be formed is shifted from the standard value exposure amount narrowing direction than the design value.

Next, the photoresist film is exposed and developed. Thereby, a resist pattern 50 is formed on the polysilicon film 40. Width L ₃ of the resist pattern 50, when the thickness t ₁ is smaller than the design value thicker than the designed value, when the thickness t ₁ is greater than the design value thinner than the design value.

Next, as shown in FIG. 5C, the polysilicon film 40 is etched using the resist pattern 50 as a mask. Thereby, a gate electrode 4 is formed on the gate oxide film 3. The width of the gate electrode 4, when the thickness t ₁ is smaller than the design value thicker than the designed value, when the thickness t ₁ is greater than the design value thinner than the design value. If the thickness t ₂ of the gate oxide film 3 becomes thin, the threshold voltage V _th of the transistor is low, but when the width of the gate electrode 4 is reduced, the threshold voltage V _th of the transistor increases. Therefore, by adjusting the width of the gate electrode 4 based on the thickness t ₁ of the gate electrode 33, the variation in the threshold voltage _Vth of the transistor can be reduced.

  Thereafter, as shown in FIG. 5D, the resist pattern 50 is removed. Next, the low concentration impurity region 6, the pocket region 6a, the sidewall 5, and the impurity region 7 are formed. These forming methods are the same as those in the fourth embodiment.

As described above, according to this embodiment, since the width of the gate electrode 4 is adjusted based on the thickness t ₁ of the gate oxide film 33 formed on the monitor substrate 30, the variation in the threshold voltage V _th of the transistor is reduced. can do. Accordingly, the yield of the semiconductor device is improved.

In the present embodiment, when the film thickness t ₂ of the gate oxide film 3 can be measured non-destructively by, for example, an optical technique, based on the difference between the measured values with respect to the design value of the film thickness t ₂ of the gate oxide film 3. Thus, the exposure amount when forming the resist pattern 50 may be calculated.

  Each drawing in FIG. 6 is a cross-sectional view for explaining the method for manufacturing a semiconductor device according to the sixth embodiment. The present embodiment is a method of suppressing variations in transistor characteristics by adjusting the thickness of the insulating film to be the sidewall 5 according to the thickness of the gate oxide film. Hereinafter, the same components as those in the fourth embodiment are denoted by the same reference numerals, and description thereof is omitted.

First, as shown in FIG. 6A, the element isolation films 2 and 32 and the gate oxide films 3 and 33 are formed on the silicon substrate 1 and the monitor substrate 30, and the thickness t ₁ of the gate oxide film 33 is measured. . Next, the deposition time of the insulating film to be the sidewall 5 is calculated based on the difference between the measured value with respect to the design value of the thickness t ₁ of the gate oxide film 33. Specifically, when the thickness t ₁ is thinner than the design value is greater than the reference value the deposition time, if the thickness t ₁ is larger than the design value is shorter than the reference value the deposition time.

Next, as shown in FIG. 6B, the gate electrode 4, the low concentration impurity region 6, and the pocket region 6a are formed. These forming methods are the same as those in the fourth embodiment. Next, an insulating film 5a (for example, a silicon nitride film) is formed on the entire surface including the gate electrode 4 by a CVD method. Since the deposition time at this time is determined based on the thickness t ₁ of the gate oxide film 33 as described above, the insulating film 5a is thicker than the reference value when the thickness t ₁ is smaller than the design value. It is thinner than the reference value when the difference between t ₁ is thicker than the design value.

Next, as shown in FIG. 6C, the insulating film 5a is etched back. Thereby, the sidewall 5 is formed. If the thickness t ₂ of the gate oxide film 3 becomes thin, the threshold voltage V _th of the transistor is lowered, if the thickness t ₂ of the gate oxide film 3 becomes thicker, the threshold voltage V _th of the transistor Becomes higher. In the present embodiment, when the thickness t ₁ of the gate oxide film 33 is thinner than the design value, since the insulating film 5a is thicker than the reference value, the width of the side wall 5 is made wider, the threshold voltage V _th of the transistor is high. Further, when the thickness t ₁ of the gate oxide film 33 is thicker than the design value, since the insulating film 5a is thinner than the reference value, the width of the side wall 5 is made wider, the threshold voltage V _th of the transistor is high. Accordingly, the variation in the threshold voltage _Vth of the transistor is reduced.

  Next, as shown in FIG. 6D, the impurity region 7 is formed by the same method as in the fourth embodiment.

As described above, according to the present embodiment, since the width of the sidewall 5 is adjusted based on the thickness t ₁ of the gate oxide film 33 formed on the monitor substrate 30, the variation in the threshold voltage V _th of the transistor is reduced. be able to. Accordingly, the yield of the semiconductor device is improved.

In the present embodiment, for example, by optical method when the thickness t ₂ of the gate oxide film 3 can be measured by non-destructive, the deposition time of the insulating film 5a on the basis of the thickness t ₂ of the gate oxide film 3 It may be calculated.

  Each drawing in FIG. 7 is a cross-sectional view for explaining the method for manufacturing a semiconductor device according to the seventh embodiment. The present embodiment is a method for suppressing variations in transistor characteristics by adjusting the thickness of the insulating film to be the sidewall 5 according to the width of the gate electrode 4. Hereinafter, the same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

First, as shown in FIG. 7A, an element isolation film 2, a gate oxide film 3, and a gate electrode 4 are formed on a silicon substrate 1. These forming methods are the same as those in the first embodiment. Next, the width L ₄ of the gate electrode 4 is measured. Then, based on the difference between the measured value for the design value of the width L _4, and calculates the deposition time of the insulating film serving as the side walls 5. Specifically, longer than the reference value the deposition time when the width L ₄ is narrower than the design value, if the width L ₄ is wider than the designed value shorter than the reference value the deposition time.

Next, as shown in FIG. 7B, a gate electrode 4, a low concentration impurity region 6, and a pocket region 6a are formed. These forming methods are the same as those in the fourth embodiment. Next, an insulating film 5a (for example, a silicon nitride film) is formed on the entire surface including the gate electrode 4 by a CVD method. Deposition time of this time, since that is determined based on the width L ₄ of the gate electrode 4 as described above, the insulating film 5a is made larger than the reference value when the width L ₄ is narrower than the design value, the width L ₄ When it is thicker than the design value, it becomes wider than the reference value.

  Next, as shown in FIG. 7C, the insulating film 5a is etched back. Thereby, the sidewall 5 is formed.

When the width L ₄ of the gate electrode 4 is narrowed, the threshold voltage V _th of the transistor is lowered, if the width L ₄ of the gate electrode 4 is wider, the threshold voltage V _th of the transistor is high. In contrast, as described above, when the width L ₄ of the gate electrode 4 is narrower than the design value, since the insulating film 5a is thicker than the reference value, the width of the side wall 5 is made wider, the threshold voltage V _th of the transistor Get higher. Also, if the width L ₄ of the gate electrode 4 is wider than the designed value, since the insulating film 5a is thinner than the reference value, the width of the side wall 5 is made wider, the threshold voltage V _th of the transistor is high. Accordingly, the variation in the threshold voltage _Vth of the transistor is reduced.

  Next, as shown in FIG. 7D, the low-concentration impurity region 6, the pocket region 6a, the sidewall 5, and the impurity region 7 are formed by the same method as in the first embodiment.

As described above, according to the present embodiment, since the width of the sidewall 5 is adjusted based on the width L ₄ of the gate electrode 4, the variation in the threshold voltage _Vth of the transistor can be reduced. Accordingly, the yield of the semiconductor device is improved.

FIG. 8 is a cross-sectional view for explaining the method for manufacturing a semiconductor device according to the eighth embodiment. In the present embodiment, the amount of impurities introduced into the polysilicon resistor is adjusted based on the thickness t ₃ of the polysilicon film formed on the monitor substrate 30 to reduce the resistance value variation.

First, as shown in FIG. 8A, the element isolation films 2 and 32 are formed on the silicon substrate 1 and the monitor substrate 30, and the polysilicon films 12 and 34 are further formed on the element isolation films 2 and 32 in the same process. Form. Next, the monitor substrate 30 is cut and the thickness of the polysilicon film 34 is measured. Since the polysilicon film 12, 34 is simultaneously formed in the same process, the thickness t ₃ of the polysilicon film 34 can be considered a thickness substantially the same as the polysilicon film 12.

Next, the amount of impurities introduced into the polysilicon resistor is calculated based on the difference between the measured value with respect to the design value of the thickness t ₃ of the polysilicon film 34. Specifically, when the thickness t ₃ is greater than the design value, less than the reference value amount of impurities to be introduced, if the thickness t ₃ is less than the design value, is greater than the reference value amount of impurities to be introduced .

  Next, as shown in FIG. 8B, impurities are introduced into the polysilicon film 12 according to the calculated values. The amount of impurities introduced is adjusted by, for example, the time for performing ion implantation.

  Next, as shown in FIG. 8C, a resist pattern (not shown) is formed on the polysilicon film 12, and the polysilicon film 12 is etched using this resist pattern as a mask. As a result, the polysilicon film 12 is selectively removed and a polysilicon resistor 12a is formed.

As described above, according to this embodiment, if the thickness t ₃ of the polysilicon film 34 is thicker than the design value, the amount of impurity introduced into the polysilicon resistor 12a is less than the reference value, the thickness t ₃ is above the design value If it is thin, the amount of impurities introduced into the polysilicon resistor 12a becomes larger than the reference value. For this reason, variation in the resistance value of the polysilicon resistor 12a is reduced, and the yield of the semiconductor device is improved.

In the present embodiment, the polysilicon film 12 is selectively removed after introducing impurities into the polysilicon film 12. However, after the polysilicon film 12 is selectively removed to form the polysilicon resistor 12a, Impurities may be introduced into the polysilicon resistor 12a.
Further, when the thickness of the polysilicon film 12 can be measured nondestructively by an optical method or the like, the thickness of the polysilicon film 12 may be used instead of the thickness of the polysilicon film 34.

FIG. 9 is a cross-sectional view for explaining the method for manufacturing a semiconductor device according to the ninth embodiment of the present invention. This embodiment is based on the thickness t ₃ of the polysilicon film formed on the monitor substrate 30, by adjusting the exposure amount of the photoresist film for forming the polysilicon resistor, the width of the polysilicon resistor This is a method of adjusting to reduce variation in resistance value. Hereinafter, the same components as those in the eighth embodiment are denoted by the same reference numerals, and description thereof is omitted.

  First, as shown in FIG. 9A, the element isolation films 2 and 32 are formed on the silicon substrate 1 and the monitor substrate 30, and the polysilicon films 12 and 34 are further formed on the element isolation films 2 and 32 in the same process. Form. Next, the monitor substrate 30 is cut and the thickness of the polysilicon film 34 is measured.

Next, the exposure amount of the photoresist film on the polysilicon film 12 is calculated based on the thickness t ₃ of the polysilicon film 34. Specifically, if greater than the thickness t ₃ is the design value, the resist pattern to be formed is shifted exposure amount narrowing direction than the design value from the standard value. Further, if the thickness t ₃ is less than the design value, the resist pattern to be formed is shifted from the standard value exposure amount thicker consisting direction than the designed value.

Next, as shown in FIG. 9B, impurities are introduced into the polysilicon film 12. Next, a photoresist film is formed on the polysilicon film 12, and this photoresist film is exposed and developed. Thereby, a resist pattern 52 is formed on the polysilicon film 12. The width L ₅ of the resist pattern 50 is thinner than the design value when the thickness t ₃ of the polysilicon film 34 is thicker than the design value, and wider than the design value when the thickness t ₃ is thinner than the design value.

Next, as shown in FIG. 9C, the polysilicon film 12 is etched using the resist pattern 52 as a mask. As a result, the polysilicon film 12 is selectively removed and a polysilicon resistor 12a is formed. If the thickness t ₃ of the polysilicon film 34 is thicker than the design value, the width of the polysilicon resistor 12a becomes narrower than the reference value, if the thickness t ₃ is less than the design value, the width of the polysilicon resistor 12a is higher than the reference value Become wider.

  For this reason, according to the present embodiment, the variation in the resistance value of the polysilicon resistor 12a is reduced, and the yield of the semiconductor device is improved.

In the present embodiment, the polysilicon film 12 is selectively removed after introducing impurities into the polysilicon film 12. However, after the polysilicon film 12 is selectively removed to form the polysilicon resistor 12a, Impurities may be introduced into the polysilicon resistor 12a.
Further, when the thickness of the polysilicon film 12 can be measured nondestructively by an optical method or the like, the thickness of the polysilicon film 12 may be used instead of the thickness of the polysilicon film 34.

  Note that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention.

FIGS. 4A to 4C are cross-sectional views for explaining a method for manufacturing a semiconductor device according to the first embodiment. FIGS. 9A to 9D are cross-sectional views for explaining a method for manufacturing a semiconductor device according to a second embodiment. 9A to 9D are cross-sectional views for explaining a method for manufacturing a semiconductor device according to a third embodiment. 9A and 9B are cross-sectional views for explaining a method for manufacturing a semiconductor device according to a fourth embodiment. 10A to 10D are cross-sectional views for explaining a method for manufacturing a semiconductor device according to a fifth embodiment. 10A to 10D are cross-sectional views for explaining a method for manufacturing a semiconductor device according to a sixth embodiment. 10A to 10D are cross-sectional views for explaining a method for manufacturing a semiconductor device according to a seventh embodiment. (A)-(C) are sectional drawings for demonstrating the manufacturing method of the semiconductor device which concerns on 8th Embodiment. (A)-(C) are sectional drawings for demonstrating the manufacturing method of the semiconductor device which concerns on 9th Embodiment. Sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on a 1st prior art example. Sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on a 2nd prior art example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,100 ... Silicon substrate, 2, 32, 102 ... Element isolation film, 2a ... Side wall, 3, 33, 103 ... Gate oxide film, 4,104 ... Gate electrode, 5,105 ... Side wall, 5a ... Insulating film 6, 106 ... low concentration impurity region, 6a, 106a ... pocket region, 7, 107 ... impurity region, 12 ... polysilicon film, 12a. 34, 40, 112 ... polysilicon resistance, 21 ... silicon oxide film, 22 ... silicon nitride film, 23 ... sacrificial oxide film, 30 ... monitor substrate, 50, 52 ... resist pattern

Claims (13)

Forming a mask film on a semiconductor substrate located in the element region in order to form an element isolation film;
Measuring the width of the mask film;
Calculating a thermal oxidation amount for forming an element isolation film based on a difference in measurement width with respect to a design width of the mask film;
Forming an element isolation film on the semiconductor substrate by thermally oxidizing the semiconductor substrate using the mask film as a mask according to the calculated thermal oxidation amount;
A method for manufacturing a semiconductor device comprising: Forming an element isolation film on a semiconductor substrate;
Measuring a width of an element region of the semiconductor substrate separated by the element isolation film;
Forming a sacrificial thermal oxide film on a semiconductor substrate located in the element region;
Calculating an etching amount when removing the sacrificial thermal oxide film based on a difference in measurement width with respect to a design width of the element region;
Etching according to the calculated etching amount to remove the sacrificial thermal oxide film and remove the surface layer of the element isolation film;
A method for manufacturing a semiconductor device comprising: Forming an element isolation film on a semiconductor substrate;
Measuring a width of an element region of the semiconductor substrate separated by the element isolation film;
Forming a gate insulating film on the semiconductor substrate located in the element region;
Forming a semiconductor film on the gate insulating film and the element isolation film;
Forming a photoresist film on the semiconductor film;
Calculating an exposure amount of the photoresist film based on a difference in measurement width with respect to a design width of the element region;
Forming a resist pattern located on the semiconductor film by exposing the photoresist film in accordance with the calculated exposure amount and then developing the photoresist film; and
Forming a gate electrode by etching the semiconductor film using the resist pattern as a mask;
A method for manufacturing a semiconductor device comprising: Forming a gate insulating film of a transistor on each of the first and second semiconductor substrates;
Measuring the thickness of the gate insulating film of the first semiconductor substrate;
The amount of impurities introduced into the pocket region or LDD region formed below the gate insulating film of the second semiconductor substrate based on the difference in the measured film thickness of the gate insulating film with respect to the design film thickness of the gate insulating film Calculating
Introducing impurities into the pocket region or the LDD region of the second semiconductor substrate according to the calculated amount of impurities;
A method for manufacturing a semiconductor device comprising: Forming a gate insulating film of a transistor on a semiconductor substrate;
Measuring the thickness of the gate insulating film;
Calculating an impurity amount to be introduced into a pocket region or an LDD region located below the gate insulating film based on a difference in measured film thickness with respect to a design film thickness of the gate insulating film;
Introducing impurities into the pocket region or LDD region according to the calculated amount of impurities;
A method for manufacturing a semiconductor device comprising: Forming a gate insulating film of a transistor on each of the first and second semiconductor substrates;
Measuring a thickness of the gate insulating film formed on the first semiconductor substrate;

Forming a semiconductor film on the gate insulating film of the second semiconductor substrate;
Forming a photoresist film on the semiconductor film;
Calculating an exposure amount of the photoresist film based on a difference in measured film thickness with respect to a design film thickness of the gate insulating film;
Forming a resist pattern located on the semiconductor film by exposing the photoresist film in accordance with the calculated exposure amount and then developing the photoresist film; and
Forming a gate electrode on the second semiconductor substrate by etching the semiconductor film using the resist pattern as a mask;
A method for manufacturing a semiconductor device comprising: Forming a gate insulating film of a transistor on a semiconductor substrate;
Measuring the thickness of the gate insulating film;
Forming a semiconductor film on the gate insulating film;
Forming a photoresist film on the semiconductor film;
Calculating an exposure amount of the photoresist film based on a difference in measured film thickness with respect to a design film thickness of the gate insulating film;
Forming a resist pattern located on the semiconductor film by exposing the photoresist film in accordance with the calculated exposure amount and then developing the photoresist film; and
Forming a gate electrode by etching the semiconductor film using the resist pattern as a mask;
A method for manufacturing a semiconductor device comprising: Forming a gate insulating film of a transistor on each of the first and second semiconductor substrates;
Measuring a thickness of the gate insulating film formed on the first semiconductor substrate;
Calculating a film thickness of an insulating film serving as a sidewall of a gate electrode formed on the second semiconductor substrate based on a difference in measured film thickness with respect to a design film thickness of the gate insulating film;
Forming a gate electrode on the gate insulating film of the second semiconductor substrate;
Forming an insulating film having the calculated film thickness on and around the gate electrode;
Etching back the insulating film to form a sidewall on the side wall of the gate electrode;
Forming two impurity regions serving as a source and a drain in the semiconductor substrate by introducing impurities into the semiconductor substrate using the gate electrode and the sidewall as a mask;
A method for manufacturing a semiconductor device comprising: Forming a gate insulating film of a transistor on a semiconductor substrate;
Measuring the thickness of the gate insulating film;
Calculating a film thickness of an insulating film serving as a sidewall of the gate electrode based on a difference in measured film thickness with respect to a design film thickness of the gate insulating film;
Forming a gate electrode on the gate insulating film;
Forming an insulating film having the calculated film thickness on and around the gate electrode;
Etching back the insulating film to form a sidewall on the side wall of the gate electrode;
Forming two impurity regions serving as a source and a drain in the semiconductor substrate by introducing impurities into the semiconductor substrate using the gate electrode and the sidewall as a mask;
A method for manufacturing a semiconductor device comprising: Forming a gate insulating film of a transistor on a semiconductor substrate;
Forming a gate electrode on the gate insulating film;
Measuring the width of the gate electrode;
Calculating a film thickness of an insulating film serving as a sidewall of the gate electrode based on a difference of a measurement width of the gate electrode with respect to a design width of the gate electrode;
Forming an insulating film having the calculated film thickness on and around the gate electrode;
Etching back the insulating film to form a sidewall on the side wall of the gate electrode;
Forming two impurity regions serving as a source and a drain in the semiconductor substrate by introducing impurities into the semiconductor substrate using the gate electrode and the sidewall as a mask;
A method for manufacturing a semiconductor device comprising: Forming an element isolation film on each of the first and second semiconductor substrates;
Forming a semiconductor film on the element isolation film in each of the first and second semiconductor substrates;
Measuring the thickness of the semiconductor film formed on the first semiconductor substrate;
Calculating an amount of impurities to be introduced into the semiconductor film based on a difference in measured film thickness with respect to a design film thickness of the semiconductor film;
Introducing impurities into the semiconductor film formed on the second semiconductor substrate according to the calculated amount of impurities;
Forming a resistance element on the second semiconductor substrate by selectively removing the semiconductor film;
A method for manufacturing a semiconductor device comprising: Forming an element isolation film on each of the first and second semiconductor substrates;
Forming a semiconductor film on the element isolation film in each of the first and second semiconductor substrates;
Measuring the thickness of the semiconductor film formed on the first semiconductor substrate;
Forming a resistance element by selectively removing the semiconductor film formed on the second semiconductor substrate;
A step of calculating an impurity amount to be introduced into the resistance element based on a difference in measured film thickness with respect to a design film thickness of the semiconductor film;
Introducing impurities into the resistance element according to the calculated amount of impurities;
A method for manufacturing a semiconductor device comprising: Forming an element isolation film on each of the first and second semiconductor substrates;
Forming a semiconductor film on the element isolation film in each of the first and second semiconductor substrates;
Measuring the thickness of the semiconductor film formed on the first semiconductor substrate;
Forming a photoresist film on the semiconductor film formed on the second semiconductor substrate;
A step of calculating an exposure amount of the photoresist film based on a difference in measured film thickness with respect to a design film thickness of the semiconductor film;
Forming a resist pattern located on the semiconductor film by exposing the photoresist film in accordance with the calculated exposure amount and then developing the photoresist film; and
Forming a resistive element on the second semiconductor substrate by etching the semiconductor film using the resist pattern as a mask;
A method for manufacturing a semiconductor device comprising:

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