JP2009267111A - Manufacturing method for semiconductor device, manufacturing apparatus, computer program, and computer-readable memory medium - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method for a semiconductor device that enables adjustment of the size of a portion to be adjusted in size, and to provide a semiconductor device manufacturing apparatus which is suitable for the method. <P>SOLUTION: The manufacturing method for the semiconductor device includes a size measuring step S8 of measuring the size of a portion to be adjusted in size, determining steps S9 and S11 of determining whether a measurement obtained at the size measuring step S8 is larger than a reference value, and a size-adjusting step of carrying out either a first step of reducing the portion, when the measurement is determined to be larger than the reference value at the determining steps S9 and S11 or a second step of enlarging the portion, when the measurement is determined as being smaller than the reference value in the determining steps. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to a semiconductor device manufacturing method and a manufacturing apparatus suitable for performing the manufacturing method, and more particularly, to a manufacturing method and a manufacturing apparatus that enable dimension adjustment of a part whose dimensions are to be controlled.

  In recent years, miniaturization of device elements has progressed due to a demand for higher integration of LSIs, and accordingly, wiring having a line width of, for example, 45 nm or 32 nm is required. However, an etching mask for realizing such a line width cannot be realized by a conventional photolithography technique. For example, development of EUV exposure technology using extreme ultraviolet (EUV) having a wavelength of 13.5 nm has been developed, but so far it has not been put into practical use.

Under such circumstances, so-called double patterning technology has attracted attention (for example, Patent Document 1). One of the techniques is sidewall transfer (SWT) (for example, Patent Document 2).
JP 2007-27742 A US Pat. No. 5,013,680 (columns 9 to 10)

  In SWT, a silicon oxide film or the like is deposited on a sacrificial film pattern formed of resist or the like, the silicon oxide film or the like is etched back, and the sacrificial film pattern is further removed. For this reason, the critical dimension (CD) may vary depending on the film thickness, conformality, etch back amount, and the like of the deposited silicon oxide film.

  The present invention has been made in view of such circumstances, and an object of the present invention is to provide a semiconductor device manufacturing method capable of adjusting the size of a portion whose size should be controlled, and a semiconductor device manufacturing apparatus suitable for this method. For the purpose.

  In order to achieve the above object, according to the first aspect of the present invention, a dimension measuring step for measuring a dimension of a part whose dimension is to be controlled; is the measured value obtained in the dimension measuring process larger than a reference value? A determination step for determining whether or not; and a first step for reducing a part when the measurement value is determined to be larger than the reference value in the determination step; and a determination step that determines that the measurement value is smaller than the reference value A method for adjusting the size of the semiconductor device is provided. The method includes the step of adjusting the size of the second step of increasing the number of sites in the case of the semiconductor device.

  According to the second aspect of the present invention, there is provided a manufacturing method according to the first aspect, wherein the portion is in an etching mask formed of a silicon oxide film, and the first step is performed by forming the etching mask. A loading step of loading the substrate into the processing vessel, an adsorption step of supplying ammonia and hydrofluoric acid into the processing vessel to adsorb ammonia and hydrofluoric acid to the substrate, and heating to heat the substrate on which ammonia and hydrofluoric acid have been adsorbed And a manufacturing method including the steps.

  According to the third aspect of the present invention, in the manufacturing method according to the first aspect, the portion is in the etching mask, and the second step includes placing the substrate on which the etching mask is formed in the processing container. There is provided a manufacturing method including a carrying-in process for carrying in and a deposition process for alternately supplying a silicon-containing source gas and an oxygen-containing gas into a processing container to deposit a silicon oxide film on a substrate.

  According to a fourth aspect of the present invention, there is provided the manufacturing method according to any one of the first to third aspects, wherein the portion is in an etching mask formed of a silicon oxide film, and the photoresist film is formed on the substrate. A photoresist forming step, a silicon oxide forming step for forming a silicon oxide film so as to cover the photoresist film on the substrate, and an etching step for etching the silicon oxide film so that the silicon oxide film remains on the sidewall of the photoresist film. And a manufacturing method further comprising:

  According to the fifth aspect of the present invention, in the manufacturing method according to the first aspect, the part is formed of silicon, and the first step is an oxidation in which the part is oxidized to form a silicon oxide film. The manufacturing method including the step and the removing step of removing the silicon oxide film is resisted.

  According to the sixth aspect of the present invention, a plurality of process chambers in which a predetermined process is performed on the substrate, a plurality of process chambers and a transfer chamber are coupled to each other, and the substrate is disposed in at least one of the plurality of process chambers. The measurement unit that measures the size of the part whose size is to be controlled formed above, the determination unit that determines whether the measurement value obtained in the measurement unit is larger than the reference value, and the measurement by the determination unit A first step of reducing the portion when the value is determined to be larger than the reference value, and a second step of increasing the portion when the determination unit determines that the measured value is smaller than the reference value. And a process determining unit that determines to perform any one of the above.

  According to a seventh aspect of the present invention, there is provided the manufacturing apparatus according to the sixth aspect, wherein ammonia and hydrofluoric acid are supplied to the plurality of process chambers to adsorb the ammonia and hydrofluoric acid to the substrate. And a heating chamber for heating the substrate on which ammonia and hydrofluoric acid are adsorbed, and when the site is in an etching mask formed of a silicon oxide film, the vacuum chamber and the heating chamber are the first step. A manufacturing apparatus used for the above is provided.

  According to an eighth aspect of the present invention, there is provided the manufacturing apparatus according to the sixth aspect, wherein a silicon-containing source gas and an oxygen-containing gas are alternately supplied to a plurality of process chambers to form a silicon oxide film on the substrate. A manufacturing apparatus is provided in which a first deposition chamber is configured to deposit the first deposition chamber when the site is in the etching mask and the first deposition chamber is used for the second step.

  According to a ninth aspect of the present invention, in the manufacturing apparatus according to the sixth aspect, a silicon oxide film is formed on the substrate so as to cover the photoresist film formed on the substrate in the plurality of process chambers. When the second deposition chamber, the first etching chamber for etching the silicon oxide film so that the silicon oxide film remains on the sidewall of the photoresist film, and the portion of the etching mask formed of the silicon oxide film, A manufacturing apparatus is provided in which two deposition chambers and a first etching chamber are utilized to form the etching mask.

  According to a tenth aspect of the present invention, in the manufacturing apparatus according to the sixth aspect, the plurality of process chambers include an oxidation chamber configured to form a silicon oxide film on the substrate; A second etching chamber configured to be able to remove the silicon oxide film, wherein the portion is formed of silicon, and the first step is performed in the oxidation chamber and the second etching chamber. An apparatus is provided.

  According to an eleventh aspect of the present invention, in the manufacturing apparatus according to the ninth aspect, plasma oxidation in which the oxidation chamber forms a silicon oxide film by oxidizing a portion formed of silicon using plasma. A manufacturing apparatus that is a chamber is provided.

  According to a twelfth aspect of the present invention, there is provided the supply apparatus according to the ninth aspect, wherein the first etching chamber supplies the silicon-containing source gas into the processing container of the first etching chamber. A manufacturing apparatus is provided.

  According to a thirteenth aspect of the present invention, there is provided the manufacturing apparatus according to the tenth aspect, wherein the second etching chamber supplies the silicon-containing source gas into the processing container of the first etching chamber. A manufacturing apparatus is provided.

  According to a fourteenth aspect of the present invention, there is provided a computer program that runs on a computer and causes the manufacturing apparatus according to any one of the sixth to thirteenth aspects to implement the manufacturing method according to any one of the first to fifth aspects. Provided.

  According to a fifteenth aspect of the present invention, there is provided a computer-readable storage medium storing the computer program according to the fourteenth aspect.

  According to the embodiment of the present invention, there is provided a semiconductor device manufacturing method capable of adjusting the size of a portion whose size is to be controlled, and a semiconductor device manufacturing apparatus suitable for this method.

  Hereinafter, a semiconductor device manufacturing method according to a preferred embodiment of the present invention will be described with reference to the accompanying drawings. In all the accompanying drawings, the same or corresponding members or parts are denoted by the same or corresponding reference numerals, and redundant description is omitted. Also, the drawings are not intended to show relative ratios between members or parts or between the thicknesses of the various layers, and therefore specific thicknesses and dimensions are in light of the following non-limiting embodiments. Should be determined by those skilled in the art.

<First Embodiment>
A method for manufacturing a semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS. 1 and 2A to 3C. This manufacturing method is applied to, for example, a process of forming a gate electrode and a gate insulating film by etching a polysilicon film and a silicon oxide film among all manufacturing processes of a semiconductor device including a transistor.

  In step S1 (FIG. 1), a silicon oxide film 10, a polysilicon film 12, a lower anti-reflection film (BARC) 14, and a resist film 16 are laminated in this order on the silicon wafer w, and the multilayer shown in FIG. A film is formed. Of these films, the silicon oxide film 10 and the polysilicon film 12 are objects to be etched. For example, the silicon oxide film 10 may be formed by thermally oxidizing the wafer w in a diffusion furnace, or may be formed by oxidizing the surface of the wafer w using oxygen plasma. The polysilicon film 12 is deposited on the silicon oxide film 10 by chemical vapor deposition (CVD). The lower prevention reflection film (BARC) 14 is applied on the polysilicon film 12 by spin coating. The resist film 16 is applied on the BARC 14 by spin coating.

  Next, in step S2, a resist pattern 16a is formed by exposing, developing, and peeling the resist film 16 by a normal photolithography technique using a predetermined photomask. Subsequently, in step S3, the resist pattern 16a is trimmed to form a reduced resist pattern 16b (FIG. 2C). Specifically, this trimming is performed by carrying the wafer w on which the resist pattern 16a is formed into a predetermined plasma etching apparatus and exposing the wafer w to oxygen plasma. Due to the oxygen plasma, the resist pattern 16a is uniformly ashed and reduced to obtain a resist pattern 16b.

  Thereafter, in step S4, the BARC 14 is etched by oxygen plasma using the resist pattern 16b to form a sacrificial film 17 composed of the resist pattern 16b and the etched BARC 14b (FIG. 1D).

  Thereafter, in step S5, a silicon oxide film 18 is deposited on the polysilicon film 12 so as to cover the sacrificial film 17 (FIG. 2E). Since the silicon oxide film 18 is deposited on the resist pattern 16b, plasma CVD capable of depositing the silicon oxide film 18 at a low temperature is used. Specifically, it is preferable to use a silicon oxide film deposition apparatus that uses Vistaly butylaminosilane (BTBAS) and oxygen plasmatized by a predetermined plasma source. Furthermore, using a molecular layer deposition (MLD) apparatus that can deposit at the atomic layer or molecular layer level by alternately supplying BTBAS and plasma oxygen, the film thickness is strictly controlled at the molecular layer level. It is further preferable in that it can be performed.

Next, in step S6, etching (etchback) is performed to remove the sacrificial film 17 and the silicon oxide film 18 on the polysilicon film 12. This etching is performed using a mixed gas of a fluorocarbon gas such as CF ₄ , C ₄ F ₈ , CHF ₃ , CH ₃ F, or CH ₂ F ₂ and Ar gas. By such etching, the sacrificial film 17 and the polysilicon film 12 are exposed, and silicon oxide portions 18a are formed on both side walls of the sacrificial film 17 (FIG. 2F). The silicon oxide portion 18a serves as a hard mask used for etching the polysilicon film 12 and the silicon oxide film 10, as will be described later. Hereinafter, this is referred to as a hard mask 18a.

  Next, in step S7, ashing is performed to remove the sacrificial film 17 (resist mask 16b and BARC 14b) used for forming the hard mask 18a (FIG. 2E). As a result, only the hard mask 18a remains on the polysilicon film 12 to be etched.

  Thereafter, in step S8, the dimensions (width, sidewall angle (SWA), interval, etc.) of the hard mask 18a are measured. This measurement can be performed by, for example, a scatterometry technique using a spectroscopic ellipsometer or a spectroscopic spectrophotometer. Specifically, as will be described later, it is preferable to use an integrated metrology (IM) system that is coupled via an etching chamber and a transfer chamber. In particular, it is more preferable that the IM system and the etching chamber are coupled via a transfer chamber capable of maintaining the inside at a reduced pressure, and transfer and dimension measurement of the wafer w are performed under reduced pressure. This is because according to the conveyance and measurement under reduced pressure, it is possible to prevent the generation of particles due to the raising and lowering pressure of the conveyance chamber and the measurement chamber.

  After the dimension measurement, in step S9, the measurement result is compared with the desired dimension, and it is determined whether or not the width of the hard mask 18a is within the tolerance of the desired dimension (step S9). If it is determined that the width of the hard mask 18a is within the allowable error (step S9: YES), the polysilicon film 12 and the silicon oxide film 10 are etched using the hard mask 18a (step S10). The polysilicon film 12 can be etched by, for example, plasma etching using HBr as an etching gas. The etching of the silicon oxide film 10 can be performed by dry etching using HF. Thereby, the gate insulating layer GOX and the gate electrode G are formed.

  If it is determined that the width of the hard mask 18a is not within the tolerance of the desired dimension (step S9: NO), it is determined whether the width is larger than the desired dimension (step S11). ). When the width of the hard mask 18a is larger than the desired dimension (step S11: YES), a trimming process for reducing the hard mask 18a is performed. On the other hand, when the width of the hard mask 18a is smaller than a desired dimension (step S11: NO), a thickening process for increasing the width of the hard mask 18a is performed.

(Trim process)
Hereinafter, the trimming process and the etching process performed thereafter will be described with reference to FIGS. 3 and 4A to 4D.
FIG. 4A shows the hard mask 18a on the polysilicon film 12, where the width W of the formed hard mask 18a is larger than the upper limit of the allowable range of the desired dimension W ₀ (for example, 30 nm). First, in step S31 (FIG. 3), the wafer w on which such a hard mask 18a is formed is transferred into the vacuum chamber and placed on the wafer stage in the vacuum chamber. The temperature of the wafer stage may be about 20 ° C., and the pressure in the vacuum chamber may be about 13.3 to 1,333 Pa (100 mTorr to 10 Torr).

Next, in step S32, ammonia (NH ₃ ) gas and hydrofluoric acid (HF) gas are respectively supplied from the separate supply lines into the vacuum chamber by predetermined amounts. As a result, NH ₄ F ₆ is formed from NH ₃ and HF in the vacuum chamber or on the wafer w, and particularly on the hard mask 18a formed of silicon oxide, NH ₄ F ₆ is further combined with silicon oxide, As shown in FIG. 4B, the (NH ₄ ) ₂ SiF ₆ layer 22 is formed. Note that when supplying NH ₃ and HF to the vacuum chamber, nitrogen (N ₂ ) gas may be supplied as necessary.

Next, in step S33, the wafer w is transferred into another vacuum chamber. The vacuum chamber includes a heater stage that holds the wafer w and can heat the wafer w to, for example, about 200 ° C. When the wafer w is heated to 200 ° C. by the heater stage in step S34, the (NH ₄ ) ₂ SiF ₆ layer 22 is sublimated, and as a result, as shown in FIG. The hard mask 18b thus formed is formed.

  In step S35, the wafer w is transferred into a predetermined etching apparatus, and when the polysilicon film 12 and the silicon oxide film 10 are etched using the hard mask 18b, as shown in FIG. The gate insulating layer GOX and the gate electrode G are provided.

As described above, only the (NH ₄ ) ₂ SiF ₆ layer 22 is sublimated by the heat treatment, and therefore the width to be reduced is determined by the thickness of the (NH ₄ ) ₂ SiF ₆ layer 22. On the other hand, the formation of the (NH ₄ ) ₂ SiF ₆ layer 22 is based on a self-stop process, and its thickness is determined by the amount of NH ₃ and NF supplied. That is, NH ₃ and HF adhering to the hard mask 18a combine with silicon oxide to generate the (NH ₄ ) ₂ SiF ₆ layer 22, and when NH ₃ and HF are depleted, the (NH ₄ ) ₂ SiF ₆ layer 22 The thickness does not increase further. Therefore, if the relationship between the supply amount of NH ₃ and HF and the thickness of the (NH ₄ ) ₂ SiF ₆ layer 22 is obtained from a preliminary experiment, for example, the width to be reduced is determined from the measurement result of step S9. Based on this, the supply amount can be determined. As a result, as shown in FIG. 4C, the width of the hard mask 18b can be easily adjusted to a desired dimension W ₀ (30 nm). This allows CD controlled etching.

(Thickening process)
Next, the thickening process will be described with reference to FIGS. 5 and 6A to 6C.
6 (a) shows a hard mask 18a on the polysilicon film 12, the width W of the formed hard mask 18a is smaller than the lower limit of the allowable range of the desired size W _0. First, in step S51 (FIG. 5), the wafer w on which such a hard mask 18a is formed is transferred into a chamber of the MLD apparatus and placed on a susceptor in the chamber. The susceptor temperature may be about 20 ° C. and the pressure in the chamber may be about 13.3 Pa (100 mTorr).

Next, in step S52, for example, BTBAS and oxygen plasma are alternately supplied into the MLD chamber. When BTBAS is supplied, BTBAS molecules are adsorbed on the wafer w (polysilicon film 12 and hard mask 18a). After purging the BTBAS in the chamber and supplying oxygen plasma, the BTBAS adsorbed on the wafer w is oxidized to form one molecular layer of silicon oxide. Next, the oxygen plasma in the chamber is purged. If such alternate supply is performed once, silicon oxide of one molecular layer is formed. Therefore, by performing alternate supply a predetermined number of times, a silicon oxide film 23 whose film thickness is controlled at the molecular layer level is deposited. be able to. Therefore, as shown in FIG. 6B, the width of the hard mask 18b can be easily adjusted to a desired dimension W ₀ (30 nm). This allows CD controlled etching. That is, when the wafer w is transferred into a predetermined etching apparatus in step S55 and the polysilicon film 12 and the silicon oxide film 10 are etched, a gate insulating layer having a CD of 30 nm is obtained as shown in FIG. GOX and the gate electrode G are realized.

  As a result of the deposition of the silicon oxide film 23 in the MLD chamber, the silicon oxide film 23 is also deposited on the polysilicon film 12, but since the thickness of the silicon oxide film 23 is several nm to several tens of nm, It is easily removed when the polysilicon film 12 and the silicon oxide film 10 are etched.

  As described above, according to the semiconductor device manufacturing method of the first embodiment of the present invention, the dimensions of the hard mask 18a formed through resist pattern trimming and SWT are measured by the IM system, and the measurement results are as follows. Accordingly, the dimension of the hard mask 18a can be adjusted by performing a trimming process or a thickening process. Therefore, a hard mask 18b capable of realizing CD can be formed, and a CD-controlled etching process can be provided.

  In addition, although the size of the hard mask can be measured even in the conventional double patterning, if the result of the measurement is not within the allowable range of the predetermined size, it is necessary to remove the hard mask and perform rework. However, according to the semiconductor device manufacturing method of the present embodiment, it is not necessary to perform rework. Therefore, the manufacturing cost can be reduced.

In the trim step, the width of the hard mask 18a to be trimmed is determined by the thickness of the (NH ₄ ) ₂ SiF ₆ layer 22 formed on the side wall of the hard mask 18a from NH ₃ and HF. Since the length is determined by the supply amounts of NH ₃ and HF, it can be strictly controlled by controlling the supply amounts. Furthermore, in the thickening step, an MLD apparatus capable of controlling the thickness of the silicon oxide film in units of one molecular layer is used, so that the width to be added can be controlled at the molecular layer level. Therefore, a CD-controlled etching process can be easily realized.

<Second Embodiment>
A method for manufacturing a semiconductor device according to the second embodiment of the present invention will be described with reference to FIGS. 7 and 8A to 8H. This manufacturing method is applied to a step of etching a silicon wafer to form a convex portion of silicon among all manufacturing steps of a semiconductor device including a transistor, for example. This convex portion can function as a channel of, for example, a finFET.

  First, in step S71 (FIG. 7), the silicon oxide film 80, the BARC 82, and the resist film 84 are laminated in this order on the silicon wafer w to form the multilayer film shown in FIG. The object of etching is the wafer w. The silicon oxide film 80 may be formed by, for example, thermally oxidizing the wafer w in a diffusion furnace, or may be formed by oxidizing the surface of the wafer w with, for example, oxygen plasma. You may form by depositing a silicon oxide film by plasma CVD using source gas and oxygen gas. The BARC 82 is applied on the silicon oxide film 80 by a spin coating method, and the resist film 84 is applied on the BARC 82 by a spin coating method.

  Next, in step S72, a resist pattern 84a is formed by exposing, developing, and peeling the resist film 84 by a normal photolithography technique using a predetermined photomask (FIG. 8B). Subsequently, in step S73, the resist pattern 16a is trimmed to form a reduced resist pattern 84b (FIG. 8C). Specifically, the trimming is performed by loading the wafer w on which the resist pattern 84a is formed into a predetermined plasma etching apparatus and exposing the wafer w to oxygen plasma. By the oxygen plasma, the resist pattern 84a is uniformly ashed and reduced to form a resist pattern 84b having a desired dimension.

  Thereafter, in step S74, the BARC 82 is etched using the resist pattern 84b to form the BARC portion 82a, and then the silicon oxide film 80 is etched to form the silicon oxide portion 80a (FIG. 8D). ). The etching of the silicon oxide film 80 is performed with a mixed gas of fluorocarbon gas and Ar gas.

  Next, in step S75, ashing using oxygen plasma is performed to remove the resist pattern 84b and the BARC portion 82a. As shown in FIG. 8E, only the silicon oxide portion 80a remains on the wafer w. This silicon oxide portion 80a is used for etching the wafer w as a hard mask. Hereinafter, this is referred to as a hard mask 80a.

  After that, as described in the first embodiment, the dimension of the hard mask 80a is measured using the IM system, the measurement result is compared with the desired dimension, and the trimming process or the thickening process is performed. It is more preferable to adjust the dimensions of the hard mask 80a.

  In step S76, the wafer w is etched using the hard mask 80a to form a convex portion wf as shown in FIG. For this etching, HBr or HCl is used as an etching gas. The height of the convex portion wf is adjusted by the etching time.

  Thereafter, in step S77, when the wafer w is transferred to the plasma processing apparatus and oxidized by oxygen plasma, a silicon oxide film is formed on the surface of the wafer w and the side surface of the convex portion wf as shown in FIG. 86 is formed. Next, the wafer w is transferred again to the etching apparatus, and the hard mask 80a and the silicon oxide film 86 are removed by etching. As a result, the width of the convex portion wf is narrowed by a width corresponding to twice the thickness of the silicon oxide film 86.

  Next, in step S79, the wafer w is transferred to the IM system, and the dimension of the convex portion wf is measured. This measurement can be performed by a scatterometry technique using a spectroscopic ellipsometer or a spectrophotometer. Specifically, it is preferable to use an IM system coupled through an etching chamber and a transfer chamber as described later. In particular, it is more preferable that the IM system is coupled to the etching chamber via a transfer chamber capable of maintaining the inside at a reduced pressure, and the wafer w is transferred and dimensioned under reduced pressure. When the wafer w is exposed to the atmosphere after the removal of the sacrificial oxide film 86 (step S78), the surface of the wafer w and the side wall of the convex portion Wf are oxidized to form a silicon oxide film. This can be prevented. Moreover, according to the conveyance and measurement under reduced pressure, it is possible to prevent the generation of particles due to the raising and lowering pressure of the conveyance chamber and the measurement chamber.

  After the dimension measurement, the measurement result is compared with the desired dimension, and it is determined whether or not the width of the convex portion wf is within the tolerance of the desired dimension (step S80). If within the allowable error (step S80: YES), the wafer w is transferred to the thermal oxidation furnace under reduced pressure to form a silicon oxide film as a protective film (step S81). Thereafter, the wafer w is sent to the subsequent manufacturing process.

  On the other hand, as a result of the measurement, when the width of the convex portion wf is larger than the upper limit of the allowable range of the desired dimension (step S80: NO), the process returns to step S77. That is, the wafer w is returned to the plasma processing apparatus under reduced pressure, and by exposing the wafer w to oxygen plasma, a silicon oxide film as a sacrificial oxide film is formed on the surface of the wafer w and the side wall of the convex portion wf. Thereafter, the wafer w is transferred to an etching apparatus, and the sacrificial oxide film is removed. Thus, the convex portion wf is narrowed by a thickness corresponding to twice the thickness of the sacrificial oxide film (step S78). Thereafter, the width of the convex portion wf is measured again in step S79. If the measurement result is within the tolerance of the desired dimension (step S80: YES), the process proceeds to step S81. If the measurement result is not within the tolerance of the desired dimension, step S77 to step S80 are repeated until it falls within the tolerance. As a result, a convex portion wf having a desired dimension is obtained. Then, a silicon oxide film as a protective film is formed by plasma oxidation or MLD (step S81), and then the wafer w is sent to the subsequent manufacturing process.

  According to the semiconductor device manufacturing method of the second embodiment of the present invention, the width of the convex portion wf is measured, and when the width is larger than the error range of the predetermined dimension as a result of the measurement, the sacrificial oxide film And the etching thereof are repeated to obtain a silicon convex portion wf having a predetermined dimension.

  The sacrificial oxide film may be formed by thermal oxidation instead of plasma oxidation. According to thermal oxidation, the thickness of the sacrificial oxide film can be strictly controlled, and as a result, the dimension of the convex portion wf can be more strictly controlled.

<Third Embodiment>
Next, a process apparatus suitable for carrying out the semiconductor device manufacturing method according to the first embodiment (particularly after step S3) will be described with reference to FIGS. FIG. 9 is a schematic view of this process apparatus. As shown in the figure, the process apparatus 90 is coupled to and placed on cassette stages 91A to 91C on which cassettes or FOUPs (Front Opening Unified Pods) for storing wafers w are placed, and cassette stages 91A to 91C. A loader module 92 that functions as an interface between the cassette or hoop and a transfer chamber 93 described later, and the wafer w is unloaded from the cassette (hoop), or the wafer w is loaded into the cassette (hoop). A transfer mechanism 92a for carrying in and a loader module 92 are coupled to each other, and a transfer chamber 93 for loading / unloading a wafer w between a processing chamber or the like, which will be described later, and the loader module 92; Are coupled to a transfer mechanism 94 and a transfer chamber 93 to execute predetermined processes. With processing chambers 95A-95E and IM system 96 configured to dispense. The loader module 92 is coupled with an orienter 97 that detects and adjusts the position of the wafer w by the orientation flat or notch of the wafer w. As shown by arrows in FIG. 9, the transport mechanism 94 can move in two horizontal directions, can rotate in the horizontal direction, and can move up and down. A gate valve (not shown) is provided between each of the cassette stages 91A to 91C and the loader module 92, between the loader module 92 and the transfer chamber 93, and between the transfer chamber 93 and the processing chambers 95A to 95E. It is opened and closed when the wafer w is loaded / unloaded.

  The processing chamber 95A may be, for example, a plasma etching apparatus, and the resist pattern trimming process (step S3) and the etching processes (steps S4, S6, S7, and S10) in the first embodiment are performed in the processing chamber 95A. Can do.

  The processing chamber 95C may be, for example, a processing apparatus that performs the first half (steps S31 and S32) of the trim process of the first embodiment. FIG. 10 is a schematic view showing a processing apparatus suitable for the trimming process. As illustrated, the processing apparatus 100 includes a processing container 101 and a wafer stage 102 that is disposed in the processing container 101 and on which a wafer w is placed.

Further, in order to supply HF to the processing container 101, the processing apparatus 100 supplies an HF gas supply source 103a, a supply line 103b connecting the HF gas supply source 103a and the processing container 101, and an opening / closing provided in the middle of the supply line 103b. And a valve 103c. Furthermore, since the processing apparatus 100 supplies NH ₃ to the processing container 101, the NH ₃ gas supply source 104a, the supply line 104b connecting the NH ₃ gas supply source 104a and the processing container 101, and the supply line 104b are provided in the middle. And an open / close valve 104c provided. In this way, HF and NH ₃ are supplied into the processing vessel 101 from separate supply lines without being mixed with each other.

In addition, a low vacuum evacuation device is connected to the processing vessel 101 at the bottom. The low vacuum exhaust device includes an exhaust pipe 30b having one end connected to the bottom of the processing vessel 101, a dry pump 35 connected to the other end of the exhaust pipe 30b, and a pressure regulator 31b provided in the middle of the exhaust pipe 30b. Have Further, a high vacuum evacuation device is connected to the processing container 101 at its side. The high vacuum exhaust system has an exhaust pipe 30a having one end connected to the side of the processing vessel 101 and the other end joined to the exhaust pipe 30b, a pressure regulator 31a provided in the middle of the exhaust pipe 30a, an isolation valve 32, a turbo A molecular pump 33 and an opening / closing valve 34 are provided. The high vacuum evacuation apparatus uses a turbo molecular pump 33 having the dry pump 35 as an auxiliary pump to a high vacuum of 1.33 × 10 ^{−10 to} 1.33 × 10 ⁻⁸ Pa (10 ⁻¹² to 10 ⁻¹⁰ Torr). The inside of the processing container 101 can be exhausted.

  A chiller 52 is connected to the wafer stage 102, and a flow path (not shown) through which the fluid 53 from the chiller 52 flows is provided inside the wafer stage 102. A thermocouple 51 is arranged inside the wafer stage 102, and the thermocouple 51 is connected to the temperature regulator 50. The temperature adjuster 50 transmits a signal for controlling the temperature of the fluid 53 to the chiller 52 based on the measurement result of the thermocouple 51. The chiller 52 adjusts the temperature of the fluid 53 based on the received signal, thereby maintaining the wafer stage 102 at about 20 ° C., for example.

In the processing apparatus 100, the trimming process (first half) is performed as follows. For example, when it is determined in step S11 of the first embodiment that the trimming process should be performed (step S11: YES), the wafer w is transferred by the transfer mechanism 94 through an opening (not shown) provided in the processing container 101. It is carried in and placed on the wafer stage 102. Next, the processing vessel 101 is maintained at a predetermined pressure by the low vacuum evacuation device and / or the high vacuum evacuation device, and HF and NH ₃ are supplied into the processing vessel 101 at a predetermined flow rate. Close valve 103c when a predetermined amount of supply of HF and NH ₃ is supplied, by closing 104c, to stop the supply of HF and NH _3. HF and NH ₃ are combined in the processing chamber 101 or on the wafer w, and further combined with silicon oxide on silicon oxide to generate (NH ₄ ) ₂ SiF ₆ . These operations are performed by controlling the pressure regulators 31a and 31b, the gas supply sources 103a and 104a, the temperature regulator 50, and the like by the control device 60. The control device 60 is controlled by a process controller 98a described later.

On the other hand, the processing chamber 95D (FIG. 9) of the process apparatus 90 may be a heat treatment apparatus for performing the latter half of the trim process (steps S33 and S34, that is, sublimation of (NH ₄ ) ₂ SiF ₆ ). FIG. 11 is a schematic view showing an example of this heat treatment apparatus. As illustrated, the heat treatment apparatus 110 includes a processing container 111 and a heater stage 112 that is disposed in the processing container 111 and on which a wafer w is placed.

In addition, the heat treatment apparatus 110 supplies nitrogen (N ₂ ), oxygen (O ₂ ), hydrogen (H ₂ ), and the like to the processing container 111, so that the gas supply source 113 a, the gas supply source 113 a, and the processing container 111 are supplied. And an open / close valve 113c provided in the middle of the supply line 113b.

  Furthermore, a low vacuum exhaust device and a high vacuum exhaust device are connected to the processing container 111. These configurations are almost the same as those of the high vacuum evacuation apparatus of the processing apparatus 100 of FIG. However, the high vacuum evacuation apparatus of the heat treatment apparatus 110 is not provided with a pressure regulator. This is because it is not necessary to perform the heat treatment under a high vacuum. A duplicate description of the same configuration as that of the processing apparatus 100 is omitted.

  The heater stage 112 includes a heater such as a heating wire, a lamp for heating a lamp, and the like. A power source 54 is connected to the heater (lamp) to supply power to them. A thermocouple 51 is disposed in the heater stage 112, and a temperature regulator 50 is connected to the thermocouple 51. The temperature regulator 50 transmits a predetermined signal to the power source 54 based on the measurement result of the thermocouple 51, and the power source 54 supplies power to the heater (lamp) based on the received signal. Accordingly, the wafer w placed on the heater stage 112 can be heated to, for example, about 200 ° C.

In the heat treatment apparatus 110, the trim process (second half) is performed as follows. The wafer w is transferred from the processing apparatus 100 in FIG. 10 into the processing container 111 of the heat treatment apparatus 110 by the transfer mechanism 94 and placed on the heater stage 112. Thereafter, N ₂ gas is supplied from the gas supply source 113a, and the pressure in the processing container 111 is maintained at a predetermined pressure by the pressure regulator 31b. Next, the heater stage 112 is heated to about 200 ° C., the wafer w is heated for a predetermined time, and (NH ₄ ) ₂ SiF ₆ is sublimated. These operations are performed by controlling the pressure regulator 31b, the gas supply source 113a, the temperature regulator 50, and the like by the control device 60. The control device 60 is controlled by a process controller 98a described later.

  Note that the heat treatment apparatus 110 may include a plasma source 114, which can generate plasma in the processing container 111. Therefore, in some cases, a plasma oxidation process or the like can be performed by the heat treatment apparatus 110 (processing chamber 95D).

  Further, the processing chamber 95B (FIG. 9) of the process apparatus 90 may be an MLD apparatus for performing a thickening process (steps S51 and S52), for example. FIG. 12 is a schematic view showing an MLD apparatus suitable for the thickening process. As illustrated, the MLD apparatus 120 includes a processing container 121 and a wafer stage 122 that is disposed in the processing container 121 and on which a wafer w is placed.

Further, the MLD apparatus 120 supplies BTBAS to the processing vessel 121, so that the BTBAS vaporizer 123a, the BTBAS gas supply source 123b connected to the BTBAS vaporizer 123a and controlling the flow rate of the BTBAS gas, the BTBAS gas supply source 123b, It has the supply line 123c which connects the process container 121, and the opening-and-closing valve 123d provided in the middle of the supply line 123c. Further, the MLD apparatus 120 includes a plasma source 114a that generates plasma in the processing container 121 at the top of the processing container 121, an O ₂ gas supply unit 114c that supplies oxygen to the plasma source 114a, and an O ₂ gas supply unit 114c. And a supply line 114d connecting the plasma source 114a.

  Further, a low vacuum evacuation device and a high vacuum evacuation device are connected to the processing vessel 121. Since these have the same configuration as the low vacuum evacuation apparatus and the high vacuum evacuation apparatus connected to the heat treatment apparatus 110 in FIG.

  The wafer stage 122 in the processing container 121 is configured to be temperature adjustable. The configuration for this temperature adjustment is the same as that of the processing apparatus 100 of FIG.

In the MLD apparatus 120, the thickening process is performed as follows. For example, if it is determined in step S11 of the first embodiment that the thickening process should be performed (step S11: YES), the wafer w is opened in the processing container 121 by the transfer mechanism 94 (not shown). ) And is placed on the wafer stage 122. Next, the processing vessel 121 is maintained at a predetermined pressure by the low vacuum evacuation device and / or the high vacuum evacuation device, and BTBAS is supplied into the processing vessel 121 at a predetermined flow rate. Thereby, BTBAS is adsorbed on the wafer w. After the supply of BTBAS is stopped and the inside of the processing container 121 is purged with N ₂ gas, O ₂ is supplied and the plasma source 114 a is activated to generate plasma in the processing container 121. The active species of oxygen generated in the plasma oxidizes BTBAS adsorbed on the surface of the wafer w to form a monomolecular silicon oxide. Thereafter, alternating supply of BTBAS and O ₂ is repeated a predetermined number of times, so that a silicon oxide film having a required thickness is formed on the wafer w. These operations are performed by the control device 60 controlling the pressure regulator 31b, the BTBAS vaporizer 123a, the gas supply source 123b, the O ₂ gas supply unit 114c, the plasma source 114a, the temperature regulator 50, and the like. The control device 60 is controlled by a process controller 98a described later.

  Referring again to FIG. 9, the process apparatus 90 includes a control unit 98, and the control unit 98 controls the processing chambers 95 </ b> A to 95 </ b> E, the IM system 96, the transfer mechanisms 92 a and 94, and the like. The control unit 98 includes, for example, a process controller 98a including a CPU, a user interface unit 98b, and a storage unit 98c.

  The user interface unit 98b is a display for displaying the operation status of the process apparatus 90, a keyboard or a touch panel for an operator of the process apparatus 90 to select a process recipe, or for a process manager to change process recipe parameters. Etc.

  The storage unit 98c stores a control program, a process recipe, parameters in various processes, and the like that cause the process controller 98a to perform various processes in the process chambers 95A to 95E. These control programs and process recipes are read and executed by the process controller 98a in accordance with instructions from the user interface unit 98b. Further, the control program and the process recipe are stored in the computer-readable recording medium 99, and may be stored in the storage unit 98c through an input / output device (not shown) corresponding thereto, or may be downloaded through a line. The computer-readable recording medium 99 may be a hard disk, CD, CD-R / RW, DVD-R / RW, flexible disk, semiconductor memory, or the like.

The storage unit 98c can include a data storage unit 98d. The data storage unit 98d may store, for example, a table indicating the correlation between the supply amounts of NH ₃ and HF described in the first embodiment and the thickness of the (NH ₄ ) ₂ SiF ₆ layer 22. The data storage unit 98d may store, for example, a table indicating the correlation between the number of times BTBAS and oxygen plasma are alternately supplied in the processing chamber 95B and the thickness of the silicon oxide film corresponding to the number of times. These tables may be created from the data obtained in the preliminary experiment, and can be corrected through the interface unit 98b based on the result obtained from the manufacturing run.

On the other hand, the process controller 98 a can include a process determining unit 98 e that determines a subsequent process based on the result in the IM system 96. That is, when the process controller 98a controls the transport mechanism 94 and the IM system 96 and causes them to perform dimension measurement (step S8), the process determining unit 98e compares the measurement result with a desired dimension (step S9, S11) is performed. As a result of this determination, when it is determined that the trim process is to be performed, the process determination unit 98e determines the trim amount based on the measurement result in the IM system 96, and refers to the predetermined table in the data storage unit 98d, thereby The supply amount of NH ₃ and HF corresponding to the trim amount can be determined. Then, the process controller 98a transmits supply amount information to the processing chamber 95C, and transmits an instruction signal to the transport mechanism 94, the IM system 96, the processing chamber 95C, the processing chamber 95D, and the like, and performs a trim process. Let it be implemented.

  If it is determined that the thickening process is to be performed as a result of the determination, the process determining unit 98e determines a width to be thickened based on the measurement result in the IM system 96, and refers to a predetermined table in the data storage unit 98d. Thus, it is possible to determine the number of alternate supplies corresponding to the width. Then, the process controller 98a transmits the number-of-times information to the processing chamber 95B, and transmits an instruction signal to the transport mechanism 94, the IM system 96, the processing chamber 95B, and the like to perform the thickening process.

According to the process apparatus 90 having the above-described configuration, the operator of the process apparatus 90 does not need to determine the supply amount of NH ₃ and HF or the number of alternate supply times of BTBAS and oxygen plasma from the result of the dimension measurement. An etching mask that realizes the above can be formed automatically. Moreover, the etching can be automatically performed after the etching mask is formed. Therefore, since a series of manufacturing steps are automatically performed, it is possible to reduce the time and cost required for manufacturing a semiconductor device.

  Although the present invention has been described with several embodiments, the present invention is not limited to the specifically disclosed embodiments, and various modifications and implementations are possible without departing from the scope of the claims. Examples are possible.

  For example, the semiconductor device manufacturing method according to the first embodiment may be changed so as to perform only one of the trimming process and the thickening process. For example, if the silicon oxide film 18 is deposited in step S5 so that the width of the silicon oxide portion 18a is surely larger than the desired dimension, the measurement result becomes larger than the desired dimension (step S11: YES), and trimming is performed. Only the process can be performed. If the silicon oxide film 18 is deposited so that the width of the silicon oxide portion 18a is surely smaller than the desired dimension, the measurement result is smaller than the desired dimension (step S11: NO), and only the thickening process is performed. Can be done. In this case, the hard mask 18a may be formed of silicon nitride or silicon oxynitride by depositing a silicon nitride film or a silicon oxynitride film instead of the silicon oxide film 18.

In the second embodiment, the hard mask 80a is formed of silicon oxide, but may be SiN. Since SiN can be etched at an etching rate 15 to 60 times higher than the etching rate of the silicon wafer w by using a mixed gas of CH ₃ F and N ₂ as an etching gas, a hard mask can be easily formed. can do.

  Further, the configuration of the processing chambers 95A to 95D is merely an example, and may have other various configurations. For example, in the third embodiment, the processing chamber 95A is configured as an etching apparatus, but may be used for forming a sacrificial oxide film in the second embodiment. That is, after forming the convex portion wf on the wafer w, the sacrificial oxide film may be formed by transferring the wafer w to the processing chamber 95A and exposing the wafer w to oxygen plasma. Further, a supply system for supplying a silicon-containing raw material such as BTBAS or TEOS may be provided in the processing chamber 95A serving as an etching apparatus, and the silicon oxide film may be deposited in the etching apparatus (step S5).

The processing chamber 95C may be configured so that the wafer stage 102 can be heated. That is, similarly to the heater stage 112 of the processing chamber 95D, a heater such as a heating wire or a lamp for lamp heating is arranged on the wafer stage 102, and a thermocouple, a temperature regulator, and a power supply source to the heater or the lamp are provided. May be deployed. Thereby, it is possible to sublimate (NH ₄ ) ₂ SiF ₆ by performing a heat treatment without transferring the wafer w to the processing chamber 95D.

Furthermore, in the third embodiment, the processing chamber 95B is configured as an MLD apparatus. The processing chamber 95B includes an HF gas supply source 103a, a supply line 103b, and an opening / closing valve 103c included in the processing apparatus 100 of FIG. An NH ₃ gas supply source 104a, a supply line 104b, and an opening / closing valve 104c may be included. Thereby, the first half (step S31, 32) of the above-mentioned trim process can be performed in the processing chamber 95B. Further, the processing chamber 95B as an MLD apparatus has a plasma source and is configured to generate oxygen plasma. However, instead of the oxygen plasma, the processing chamber 95B may have an ozone supply source to supply ozone.

  In the second embodiment, when it is determined as a result of step S80 (FIG. 7) that the dimension of the convex portion wf is narrower than a desired dimension, for example, the thickness is increased using an epitaxial deposition apparatus of silicon. You may perform a process.

It is a 1st flowchart which shows the manufacturing method of the semiconductor device by the 1st Embodiment of this invention. (A)-(f) is a figure which shows typically the cross section of the semiconductor device in each step of the manufacturing method of the semiconductor device by the 1st Embodiment of this invention. It is a 2nd flowchart which shows the manufacturing method of the semiconductor device by the 1st Embodiment of this invention. (A)-(d) is a figure which shows typically the cross section of the semiconductor device in each step of the manufacturing method of the semiconductor device by the 1st Embodiment of this invention. It is a 3rd flowchart which shows the manufacturing method of the semiconductor device by the 1st Embodiment of this invention. (A)-(c) is a figure which shows typically the cross section of the semiconductor device in each step of the manufacturing method of the semiconductor device by the 1st Embodiment of this invention. 5 is a flowchart illustrating a method for manufacturing a semiconductor device according to a second embodiment of the present invention. (A)-(f) is a figure which shows typically the cross section of the semiconductor device in each step of the manufacturing method of the semiconductor device by the 2nd Embodiment of this invention. It is a schematic diagram of the manufacturing apparatus of the semiconductor device by the 3rd Embodiment of this invention. It is a schematic diagram of the processing chamber of the manufacturing apparatus of FIG. It is a schematic diagram of the other process chamber of the manufacturing apparatus of FIG. It is a schematic diagram of the other process chamber of the manufacturing apparatus of FIG.

Explanation of symbols

10, 18, 23, 80 Silicon oxide film 12 Polysilicon film 14, 82 BARC
16, 84 Resist films 18a, 80a Hard mask 22 (NH ₄ ) ₂ SiF ₆ layers 90 Process equipment 95A to 95E Processing chamber 96 IM system 100 Processing equipment 110 Heat treatment equipment 120 MLD equipment

Claims (15)

A dimension measuring step for measuring the dimension of the part whose dimension is to be controlled;
A determination step of determining whether or not a measurement value obtained in the dimension measurement step is larger than a reference value; and reducing the portion when the measurement value is determined to be larger than the reference value in the determination step A dimension adjustment step of performing either one of a first step of performing and a second step of increasing the portion when the measurement value is determined to be smaller than the reference value in the determination step;
A method for manufacturing a semiconductor device, comprising: The portion is in an etching mask formed of a silicon oxide film,
The first step includes
A loading step of loading the substrate on which the etching mask is formed into a processing container;
An adsorption step of supplying ammonia and hydrofluoric acid into the processing vessel to adsorb the ammonia and hydrofluoric acid to the substrate;
A heating step of heating the substrate on which the ammonia and the hydrofluoric acid are adsorbed;
The manufacturing method of Claim 1 containing this. The part is in the etching mask;
The second step includes
A loading step of loading the substrate on which the etching mask is formed into a processing container;
A deposition step of alternately depositing a silicon-containing source gas and an oxygen-containing gas in the processing container to deposit a silicon oxide film on the substrate;
The manufacturing method of Claim 1 containing this. The portion is in an etching mask formed of a silicon oxide film,
A photoresist forming step of forming a photoresist film on the substrate;
Forming a silicon oxide film on the substrate so as to cover the photoresist film;
An etching step of etching the silicon oxide film so that the silicon oxide film remains on a sidewall of the photoresist film;
The manufacturing method according to claim 1, further comprising: The part is formed of silicon;
The first step includes
An oxidation step of oxidizing the part to form a silicon oxide film;
A removal step of removing the silicon oxide film;
The manufacturing method of Claim 1 containing this. A plurality of process chambers in which a predetermined process is performed on the substrate;
A measuring unit that is coupled to the plurality of process chambers via a transfer chamber, and that measures a dimension of a part whose dimension is to be controlled, which is formed on the substrate in at least one of the plurality of process chambers;
A determination unit for determining whether or not a measurement value obtained in the measurement unit is larger than a reference value;
A first step of reducing the portion when the determination unit determines that the measurement value is larger than the reference value; and the determination unit determines that the measurement value is smaller than the reference value. A process determining unit that determines to perform any of the second process of increasing the portion in the case of
An apparatus for manufacturing a semiconductor device. The plurality of process chambers include
A vacuum chamber configured to supply ammonia and hydrofluoric acid therein to adsorb the ammonia and hydrofluoric acid to the substrate;
A heating chamber for heating the substrate on which the ammonia and the hydrofluoric acid are adsorbed;
Contains
The manufacturing apparatus according to claim 6, wherein the vacuum chamber and the heating chamber are used for the first step when the part is in an etching mask formed of a silicon oxide film. The plurality of process chambers include
A first deposition chamber configured to alternately supply a silicon-containing source gas and an oxygen-containing gas to deposit a silicon oxide film on the substrate;
The manufacturing apparatus according to claim 6, wherein the first deposition chamber is used for the second step when the portion is in an etching mask. The plurality of process chambers include
A second deposition chamber for forming a silicon oxide film on the substrate so as to cover the photoresist film formed on the substrate;
A first etching chamber for etching the silicon oxide film so that the silicon oxide film remains on a sidewall of the photoresist film;
The manufacturing apparatus according to claim 6, wherein when the part is in an etching mask formed of a silicon oxide film, the second deposition chamber and the first etching chamber are used for forming the etching mask. The plurality of process chambers include
An oxidation chamber configured to form a silicon oxide film on the substrate;
A second etching chamber configured to be able to remove the silicon oxide film;
Contains
The manufacturing apparatus according to claim 6, wherein the part is formed of silicon, and the first step is performed in the oxidation chamber and the second etching chamber.   The manufacturing apparatus according to claim 9, wherein the oxidation chamber is a plasma oxidation chamber that forms the silicon oxide film by oxidizing the portion formed of silicon using plasma.   The manufacturing apparatus according to claim 9, wherein the first etching chamber includes a supply system that supplies a silicon-containing source gas into a processing container of the first etching chamber.   The manufacturing apparatus according to claim 10, wherein the second etching chamber includes a supply system that supplies a silicon-containing source gas into a processing container of the first etching chamber.   A computer program that runs on a computer and causes the semiconductor device manufacturing apparatus according to any one of claims 6 to 13 to implement the semiconductor device manufacturing method according to any one of claims 1 to 5.   A computer readable storage medium storing the computer program according to claim 14.

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