JP2003031557A - Method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a trimming process capable of reducing line width and suppressing the extent of spatial width. SOLUTION: A method for manufacturing a semiconductor device comprises the steps of forming silicon films 12 on surface of side faces of insides and outsides of two line patterns in the longitudinal direction, by including the two line patterns isolated at a predetermined distance, in such a manner that the thickness of the film 12 is larger at the side face of the outside than at the side face of the inside, and forming a mask pattern made of a polycrystalire silicon film 6. The method thereafter comprises the steps of removing the film 12, and trimming the mask pattern constituting the film 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device, which improves a trimming process which is one of the techniques for forming a fine mask pattern.

[0002]

2. Description of the Related Art In pattern transfer technology for semiconductor devices, light exposure technology using photoresist is generally used. As miniaturization of elements constituting an LSI progresses, it becomes difficult to transfer a fine pattern by a normal pattern transfer technique.

On the other hand, the trimming process is given as one solution. FIG. 4 is a sectional view for explaining the conventional trimming process.

First, as shown in FIG. 4A, a resist pattern 60 of lines and spaces is formed by using a normal light exposure technique. Line width L of resist pattern 60
Both the space width S and the space width S are the minimum dimension F determined by the exposure limit.

Next, as shown in FIG. 4B, the surface portion of the resist pattern 60 is carbonized and removed by plasma treatment. As a result, a resist pattern 60 having a line width L smaller than the minimum dimension F is obtained.

However, this type of trimming process has the following problems. That is, since the resist pattern 60 is isotropically carbonized, there is a problem that the space width S becomes larger than the minimum dimension F. Such a widening of the space width S hinders high integration.

[0007]

As described above, in the conventional trimming process, the line width can be made smaller than the minimum size determined by the exposure limit, but there is a problem that the space width is widened.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a method of manufacturing a semiconductor device including a trimming process capable of reducing the line width and suppressing the expansion of the space width. To do.

[0009]

Among the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows. That is, in order to achieve the above object, a method for manufacturing a semiconductor device according to the present invention includes a plurality of line patterns separated by a certain distance, and each of the plurality of line patterns has a longitudinal direction. A step of forming a mask pattern in which the two side surfaces are altered and the outer side surfaces of the two line patterns at both ends of the two side surfaces have the largest amount of variation, and the altered portion of the line pattern is etched. And a step of trimming the mask pattern.

The pattern as the mask may include a plurality of other line patterns separated from the plurality of line patterns by a certain distance.

With this structure, it is possible to suppress an increase in the amount of etching on the side surfaces where the line patterns face each other, which causes an increase in the space width.
It is possible to realize a method of manufacturing a semiconductor device including a trimming process that can reduce the line width and suppress the expansion of the space width.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention (hereinafter referred to as embodiments) will be described below with reference to the drawings.

1 and 2 are cross-sectional views showing a manufacturing process of a semiconductor device according to one embodiment of the present invention.

First, as shown in FIG. 1A, a gate oxide film 2 is formed on the surface of a silicon substrate 1 by thermal oxidation, and then a thickness 20 to be a gate electrode is formed on the gate oxide film 2.
A 0 nm polycrystalline silicon film 3 is deposited. When the gate electrode is for a MOS transistor of a memory cell, polycrystalline silicon film 3 contains impurities. On the other hand, when the gate electrode is a MOS transistor of a logic circuit, the polycrystalline silicon film 3 is undoped.

Next, as shown in FIG. 3A, a silicon oxide film 4, a silicon nitride film 5, and an undoped polycrystalline silicon film 6 which serve as a mask are sequentially formed on the polycrystalline silicon film 3.

The silicon oxide film 4 has a film thickness of 50 nm, the silicon nitride film 5 has a film thickness of 50 nm, and the polycrystalline silicon film 6 has a film thickness of 150 nm. These membranes 4-6 are LP-C
It is formed using the VD method. Instead of the polycrystalline silicon film 6, an undoped amorphous silicon film may be used.

Next, as shown in FIG. 1B, a photoresist is applied on the polycrystalline silicon film 6 and a resist pattern 7 is formed by using a known light exposure technique. The resist pattern 7 has a line & space pattern corresponding to two gate electrodes (word lines). When the gate electrode is a MOS transistor of a memory cell, both the line width L and the space width S of the resist pattern 7 are the minimum dimension F determined by the exposure limit.

Next, as shown in FIG. 1C, boron (B) ions 8 are implanted into the polycrystalline silicon film 6 by oblique ion implantation using the resist pattern 7 as a mask. The implantation conditions are, for example, an acceleration voltage of 20 keV, a dose amount of 1 × 10 ¹⁴ atoms / cm ⁻² , and an implantation angle of 15 °.

In the figure, 9 indicates the polycrystalline silicon film 6 into which the B ions 8 have been implanted. Since the region 10 sandwiched by the line patterns is narrow and has a high aspect ratio, the B ions 8 are hardly implanted into the polycrystalline silicon film 6 through the region 10. Therefore,
Of the portion of the polycrystalline silicon film 6 covered with the resist pattern 7, the portion where the B ions 8 are substantially implanted is
Only the portion 11 below the peripheral portion of the resist pattern 7 is formed.

The accelerating voltage and the dose amount are not limited to the above values, and may be any value as long as the B ions 8 are implanted to the bottom of the polycrystalline silicon film 6. Since the B ion has a small mass,
It can be easily implanted to the bottom of the polycrystalline silicon film 6.

Next, as shown in FIG. 1D, the polycrystalline silicon film 6 is formed on the HB with the resist pattern 7 as a mask.
Etching is performed by the RIE (Reactive Ion Etching) method using an r-based gas, and the pattern of the resist pattern 7 is transferred to the polycrystalline silicon film 6. In this way, a mask pattern made of the polycrystalline silicon film 6 is obtained. Then, the resist pattern 7 is peeled off using sulfuric acid.

Next, as shown in FIG. 1 (e), the temperature 90
The surface of the polycrystalline silicon film 6 is oxidized by thermal oxidation in an oxygen (O ₂ ) atmosphere at 0 ° C., and a silicon oxide film 12 (altered layer) is formed on the surface of the polycrystalline silicon film 6.

At this time, the polycrystalline silicon film 6 is oxidized only by 10 nm where B ions are not implanted, but is oxidized by 20 nm where B ions are implanted. As a result, as shown in FIG. 1E, the silicon oxide film 12 having a film thickness distribution that is thicker on the outside of the line pattern than on the inside is formed on the surface of the polycrystalline silicon film 6.

Next, as shown in FIG. 2F, the silicon oxide film 12 is selectively removed using dilute HF. As a result, with respect to the pattern transferred from the resist pattern 7, the outside of the line pattern is 20 nm and the inside is 10 nm.
And the total line width becomes 30 nm, but the space width is 2
Only 0 nm spreads. Therefore, according to the present embodiment, it is possible to realize the trimming process that can reduce the line width while suppressing the expansion of the space width.

Further, there is little variation in oxidation, and the two line patterns are similarly oxidized. Oxidation has less variation than ashing. Therefore, when the oxidation is applied to a line-and-space pattern having sparse and dense areas, the difference in the amount of oxidization between the sparse area and the dense area can be reduced and the variation can be reduced.

Next, as shown in FIG. 2G, the silicon nitride film 5 is etched by the RIE method using, for example, a CF ₄ gas by using the polycrystalline silicon film 6 as a mask,
The pattern of the polycrystalline silicon film 6 is transferred to the silicon nitride film 5. Thus, the mask pattern made of the silicon nitride film 5 is obtained.

Next, as shown in FIG. 2 (h), for example, S
The polycrystalline silicon film 6 is selectively removed from the silicon nitride film 5 and the silicon oxide film 4 by etching by the RIE method using an F ₆ gas. At this time, since the polycrystalline silicon film 3 is covered with the silicon oxide film 4, it is not etched.

Here, RI is used as a dry etching method.
Although the E method was used, the downflow type etching (C
DE: Also called Chemical Dry Etching. ) Method may be used. Also in this case, for example, SF ₆ type gas is used.

Next, as shown in FIG. 2I, the silicon oxide film 4 is, for example, C, with the silicon nitride film 5 as a mask.
Etching by RIE method using HF ₃ gas,
The pattern of the silicon nitride film 5 is transferred to the silicon oxide film 4. In this way, a mask pattern made of the silicon oxide film 4 is obtained.

Next, as shown in FIG. 2 (j), heat H ₃ P
The silicon nitride film 5 is selectively removed by wet etching using O ₄ .

Finally, as shown in FIG. 2K, the polycrystalline silicon film 3 is etched by the RIE method using, for example, an HBr-based gas, using the silicon oxide film 4 as a mask to remove the silicon oxide film 4 by etching. Pattern the polycrystalline silicon film 3
Then, two gate electrodes made of the polycrystalline silicon film 3 are obtained. This is followed by a process of removing the silicon oxide film 4, a well-known MOS transistor process.

In this embodiment, the case where the number of line patterns is two has been described, but the number of line patterns may be three or more. For example, in the case of three lines,
As shown in FIG. 3A, the widths L1 and L3 of the two left and right line patterns before trimming are made wider than the width L2 of the central line pattern by a predetermined amount, and as shown in FIG. By setting the widths L1 ′ to L3 ′ after trimming to be the same, the same effect as this embodiment can be obtained. The space widths are all the same.

Silicon oxide film 12 outside the line pattern
Where T1 is the film thickness (trimming amount) of the line pattern and T2 is the film thickness (trimming amount) of the silicon oxide film 12 inside the line pattern, L1-L1 '= L3-L3' = T1-T2 (predetermined amount). Setting L1 '= L2' = L
3'can be realized.

Similarly, in the case of four or more lines, the widths of the two outermost line patterns before trimming are made wider than the widths of the remaining line patterns by a predetermined amount, and the widths of all line patterns after trimming are increased. By making them equal, the same effect as this embodiment can be obtained.

The present invention is not limited to the above embodiment. For example, the line & space pattern is not limited to the gate electrode (word line), the implanted ions are not limited to the B ions, and the polycrystalline silicon may be altered by a method other than oxidation.

Furthermore, the above embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some constituent features are deleted from all the constituent features shown in the embodiment, if the problem described in the column of the problem to be solved by the invention can be solved, the constituent feature is deleted. Can be extracted as an invention.

In addition, various modifications can be made without departing from the scope of the present invention.

[0039]

As described above in detail, according to the present invention, it is possible to realize a method of manufacturing a semiconductor device including a trimming process capable of reducing the line width and suppressing the expansion of the space width.

[Brief description of drawings]

FIG. 1 is a sectional view showing a manufacturing process of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG.

FIG. 3 is a sectional view showing a manufacturing process of a semiconductor device according to another embodiment of the present invention.

FIG. 4 is a sectional view showing a conventional trimming process.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Silicon substrate 2 ... Gate oxide film 3 ... Polycrystalline silicon film (gate electrode) 4 ... Silicon oxide film 5 ... Silicon nitride film 6 ... Polycrystalline silicon film (mask pattern) 7 ... Resist pattern 8 ... B ion 9 ... Ion Injected polycrystalline silicon film 10 ... Region 11 sandwiched by line patterns ... Polycrystalline silicon film 12 ... Ion-implanted resist pattern peripheral edge portion ... Silicon oxide film

Claims (5)

[Claims] 1. A plurality of line patterns separated by a certain distance, each of the plurality of line patterns having two longitudinal side surfaces altered, and one of the two side surfaces at both ends. The method further comprises a step of forming a mask pattern having the largest amount of change in the outer side surfaces of the two line patterns, and a step of removing the changed portion of the line patterns by etching and trimming the mask patterns. And a method for manufacturing a semiconductor device. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the alteration is alteration caused by oxidation. 3. A step of forming a resist pattern including a plurality of line patterns separated by a constant distance on a silicon film, and using the resist pattern as a mask, oblique ion implantation is used to form the silicon film. A step of implanting ions into the substrate, a step of etching the silicon film using the resist pattern as a mask to form a mask pattern made of the silicon film, and a step of removing the resist pattern and then making the mask pattern made of the silicon film. And oxidizing the surface of the mask pattern to form a silicon oxide film on the surface of the mask pattern, and etching the silicon oxide film to trim the mask pattern made of the silicon film. Manufacturing method of semiconductor device. 4. The method of manufacturing a semiconductor device according to claim 3, wherein the silicon film is an undoped polycrystalline silicon film or an amorphous silicon film. 5. The method of manufacturing a semiconductor device according to claim 3, wherein the ions are boron ions.