JP5417998B2 - Wafer manufacturing history tracking method - Google Patents

Description

  The present invention relates to a wafer manufacturing history tracking method, and more particularly to a wafer manufacturing history tracking method capable of tracking the history of each manufacturing process for each semiconductor wafer.

  A silicon wafer which is a formation substrate of an ultra-high integrated device such as ULSI is manufactured by performing wafer processing on a single crystal silicon ingot pulled up by the Czochralski (CZ) method. Specifically, the single crystal silicon ingot is cut into blocks, and then the silicon block is subjected to peripheral grinding with a grinding wheel and slicing with a wire saw in order to obtain a large number of silicon wafers. Next, chamfering, lapping, etching, and polishing are sequentially performed on each silicon wafer to manufacture a product wafer for device formation.

  Conventionally, a silicon wafer management method in each wafer processing using a single crystal silicon ingot as a starting material has been generally performed in batch units of several tens to several hundreds of silicon wafers (for example, patents). Reference 1).

JP 2001-358199 A

However, the silicon wafer management method based on Patent Document 1 is a technique for managing wafers in lot units as described above. Therefore, the wafer that the specific silicon wafer was sliced from which position of the single crystal silicon ingot, and after that, which wafer processing equipment (heat treatment equipment, etc.) was used and under what conditions (heat treatment conditions, etc.) Unit information could not be acquired.
For this reason, for example, when quality improvement of silicon wafers or tracking of the cause of defects is performed, since only the information in units of lots is relied on, it has not been possible to perform optimum quality improvement with high accuracy.
Therefore, as a result of diligent research, the inventor managed a single wafer by ID, and what ingot of which ingot the specific wafer was sliced, and what kind of processing was performed after that. The present invention has been completed.

  The present invention provides a wafer manufacturing history tracking method capable of acquiring various manufacturing information of a semiconductor wafer for each piece and easily tracking the manufacturing history of each semiconductor wafer. It is an object.

According to the first aspect of the present invention, crystal processing including block cutting for obtaining a crystal block from a semiconductor crystal and wafer processing including a slice for obtaining a plurality of semiconductor wafers from the crystal block are sequentially performed on the semiconductor crystal. In a wafer manufacturing history tracking method for tracking a manufacturing history of a semiconductor wafer manufactured by the method, a crystal number assigned to the semiconductor crystal is stored in a storage medium, assigned to the crystal block, and becomes a base of the crystal block Information on the semiconductor crystal acquired from the crystal number assigned to the semiconductor crystal, and each time after the semiconductor crystal is manufactured until the crystal block is obtained by performing crystal processing including the block cutting on the semiconductor crystal. a crystal processing information, the semiconductor formation of the crystal block before being cut into crystal block from said semiconductor crystal And position information, a block ID which is included is stored in the storage medium in the granted to the semiconductor wafer, and given to the crystalline block to be the base with respect to respective semiconductor wafers one by one and information of the crystal block obtained from the block ID, a respective wafer processing information after production of the crystal block to said each semiconductor wafer is subjected to wafer processing including the slice to the crystal block is obtained, wherein The wafer ID including the position information of the semiconductor wafer in the crystal block before being sliced from the crystal block into the semiconductor wafer is stored in the storage medium, the crystal number stored in the storage medium, A wafer that tracks the manufacturing history of each semiconductor wafer based on the block ID and the wafer ID. A manufacturing history tracking method.

According to the first aspect of the present invention, the crystal number assigned to the semiconductor crystal, the block ID assigned to the crystal block, and the wafer ID assigned to each semiconductor wafer are previously stored in the storage medium. Remember.
The block ID includes information on the semiconductor crystal obtained from the crystal number assigned to the semiconductor crystal that is the basis of the crystal block, and crystal processing including block cutting on the semiconductor crystal after fabrication of the semiconductor crystal. Each crystal processing information until it is obtained is included.
In addition, the wafer ID includes information on the crystal block obtained from the block ID assigned to the base crystal block for each semiconductor wafer, and wafer processing including a slice in the crystal block after the crystal block is produced. Each wafer processing information until each semiconductor wafer is obtained after being applied is included.
After that, based on the crystal number, block ID, and wafer ID stored in the storage medium, the path through which each specific semiconductor wafer passes through each processing step and how each processing step is processed for each wafer. To track. Thereby, various kinds of unique manufacturing information of each semiconductor wafer can be acquired, and the manufacturing history of each semiconductor wafer can be easily traced.
In other words, the present invention cuts a semiconductor crystal (such as a CZ silicon single crystal) into a plurality of crystal blocks, slices each crystal block to obtain a large number of semiconductor wafers, and processes various types of semiconductor wafers. In a semiconductor wafer manufacturing process for obtaining a semiconductor wafer for shipping (single-sided mirror wafer, etc.) by performing processing (all processing such as chamfering, grinding, polishing, heat treatment, cleaning, cassette storage, conveyance, etc.) The crystal ID (crystal number) assigned to each crystal is stored in a storage medium (electronic or electromagnetic storage medium), and the block ID assigned to each crystal block is stored in the storage medium in association with the crystal ID. (For example, the crystal ID is included in the block ID) and all the above semiconductor wafers are assigned to each semiconductor wafer. The wafer ID associated with the block ID is stored in the storage medium (eg, the block ID is included in the wafer ID), and the processing information given to each of the plurality of types of processing / processing of each semiconductor wafer. Is stored in the storage medium in association with the wafer ID (store processing for all wafers, for example, store processing information for wafers that have not been transferred to the next process as defective products in inspection, for example) Then, the wafer manufacturing history tracking method enables the manufacturing history of the shipping semiconductor wafer to be tracked by searching based on the wafer ID. Therefore, by searching the storage medium based on the wafer ID, the processing information of the semiconductor wafer and the position information in the semiconductor crystal (position information such as the position of the wafer of the CZ silicon single crystal rod) are acquired. Can do.

As the semiconductor crystal, for example, a single crystal silicon ingot grown by the Czochralski method (CZ method) or the floating zone dissolution (FZ) method can be employed. In addition, a polycrystalline silicon ingot manufactured by a casting method or the like may be used.
In crystal processing, in addition to block cutting for cutting a semiconductor crystal into a crystal block of a predetermined length, for example, outer periphery grinding is performed to press the grinding against the outer peripheral surface of the crystal block to make the outer diameter of the crystal block uniform. . The number of crystal blocks cut from the semiconductor crystal may be one or two or more.

In wafer processing, in addition to slicing, chamfering of the outer periphery of the semiconductor wafer, lapping to increase the parallelism of the front and back surfaces of the semiconductor wafer, etching to remove the processing damage of the semiconductor wafer, polishing to mirror the surface of the semiconductor wafer, etc. Is done.
Examples of the crystal block slicing method include a wire saw method in which a slurry block in which free abrasive grains are mixed with wrapping oil is applied to the crystal block while the crystal block is pressed against a wire train that runs at high speed and is cut by a grinding action. Can be adopted.
“Tracking the manufacturing history of a semiconductor wafer” refers to tracing a path from a specific semiconductor crystal to a product wafer that is sequentially manufactured through crystal processing and wafer processing.

  Examples of what is stored as the manufacturing history here include raw material information, processing history of crystal blocks and semiconductor wafers, quality information, and material information required for processing. Specifically, in each processing device, such as product types (semiconductor wafers) including intermediate products (semiconductor crystals, crystal blocks, etc.) and manufacturing order, product handling container types and container numbers, processing device types, device numbers, etc. And the like.

Examples of the identification mark (identifier) used as the ID include numbers, characters, symbols, and combinations thereof. The ID may be printed or laser marked on a semiconductor crystal, a crystal block, or a semiconductor wafer. As a notation method of ID, for example, in the case of a wafer ID, the wafer ID may be indicated in a column in succession to the block ID of the crystal block that is the basis of the semiconductor wafer to which the wafer ID is assigned. In addition, the information of the crystal block that can be acquired from the corresponding block ID and the information of each wafer processing from when the crystal block is manufactured until each semiconductor wafer is obtained by performing wafer processing including slices on the crystal block are reflected. A new identifier may be written.
As the storage medium, for example, a computer (memory), a computer network, a CD, a DVD, a magnetic tape, paper, or the like can be employed.
As the semiconductor wafer, for example, a silicon wafer (single crystal silicon wafer, polycrystalline silicon wafer, etc.) can be employed.
The diameter of the semiconductor wafer is arbitrary, such as 300 mm or 450 mm.

  A second aspect of the present invention is the wafer manufacturing history tracking method according to the first aspect, wherein the unique wafer ID is laser-marked on each semiconductor wafer.

According to the second aspect of the present invention, each semiconductor wafer is laser-marked with a unique wafer ID, so that various device wafer manufacturing information can be obtained from the wafer ID stamped on the semiconductor wafer in the device manufacturing process. Can be obtained.
As the position of the laser marking on the semiconductor wafer, for example, the outer peripheral portion of the wafer surface can be adopted. The timing of laser marking is arbitrary.

  According to the first aspect of the present invention, based on the crystal number, the block ID, and the wafer ID stored in the storage medium, the specific semiconductor wafer passes through each processing step and how in each processing step. It can be easily traced for each wafer. Thereby, various unique manufacturing information can be acquired about each semiconductor wafer.

  According to the second aspect of the present invention, each semiconductor wafer is laser-marked with a unique wafer ID, so that various device wafer manufacturing information can be obtained from the wafer ID stamped on the semiconductor wafer in the device manufacturing process. Can be obtained.

It is a flow sheet which shows the manufacturing process of the semiconductor wafer to which the wafer manufacturing history tracking method concerning Example 1 of this invention is applied. It is a flow sheet which shows the example of ID provision in each manufacturing process of the semiconductor wafer in the wafer manufacturing log | history tracking method which concerns on Example 1 of this invention.

  Examples of the present invention will be specifically described below. Here, a case where a silicon wafer having a diameter of 300 mm is manufactured from a single crystal silicon ingot pulled up by the Czochralski method is taken as an example.

  As shown in the flow sheet of FIG. 1, a semiconductor wafer manufacturing process to which the wafer manufacturing history tracking method according to the first embodiment of the present invention is applied includes a crystal pulling process, a crystal processing process, a slicing process, a crystal evaluation process, and a chamfering. Process, lapping process, grinding process, hard laser marking (HLM) process, post-grinding cleaning process, crack inspection process, finish chamfering process, double-side polishing process, final polishing process, epitaxial growth process, appearance inspection process, final cleaning process, surface inspection It includes a process, a warehouse approval process (determination for each rod), a shipping approval process (inspection report issuance), and a product shipping process.

  In addition, each process from the crystal pulling process to the product shipping process manages raw material information, crystal block (silicon block) and silicon wafer processing history, quality information, material information required for processing, transport route, etc. Computers reporting to other processes are in place.

  Specifically, a crystal pulling process management computer, a crystal processing process management computer, a slicing process management computer, a crystal evaluation process management computer, a chamfering process management computer, a lapping process management computer, a grinding process management computer, Computer for hard laser marking process management, computer for cleaning process after grinding, computer for crack inspection process management, computer for finishing chamfering process management, computer for double-side polishing process management, computer for finishing polishing process management, computer for epitaxial growth process management, Computer for visual inspection process management, final cleaning process management computer, surface inspection process management computer, warehouse entry approval process management computer, shipping approval process management computer These through a computer network system (LAN), connected to the host computer. The host computer creates a database by associating the various information reported on a wafer basis with each silicon wafer.

Hereafter, each said process is demonstrated concretely.
In the crystal pulling step, a single crystal silicon ingot (semiconductor crystal having a diameter of 306 mm, a length of the straight body of 2500 mm, a specific resistance of 10 mΩ · cm, and an initial oxygen concentration of 1.0 × 10 ¹⁸ atoms / cm ³ by the Czochralski method. ) Is raised. Here, a unique crystal number (S02805010000) is assigned to the single crystal silicon ingot. The crystal number is input to the crystal pulling process management computer, which is also input to the host computer via the computer network.

  Next, in the crystal processing step, one single crystal silicon ingot is cut into eight crystal blocks having a certain resistivity range. Thereafter, each crystal block is ground peripherally. Specifically, the outer peripheral portion of the crystal block is subjected to outer peripheral grinding by 5 mm by an outer peripheral grinding apparatus having a resinoid grinding wheel containing # 200 abrasive grains (SiC). Thereby, each crystal block is formed in a cylindrical shape. Here, a unique block ID (S02805010100 to S02805010800) is assigned to each crystal block. Each crystal block is individually placed on eight trays to which a tray ID is assigned, and is transported to the subsequent slicing step. Each block ID and each tray ID are input to the crystal processing process management computer, and then input to the host computer via the computer network. Each block ID also indicates where in the single crystal silicon ingot the corresponding crystal block is located.

  In the slicing step, each crystal block is sliced into a large number of silicon wafers having a thickness of 775 μm by a wire saw. Here, a mold ID (MSA004) indicating a jig for setting a crystal block in the slicing apparatus is input to the slicing process management computer, and then the mold ID is also transmitted to the host computer via the computer network. Is entered. Each sliced silicon wafer is transferred to the crystal evaluation process.

  In the crystal evaluation step, crystal evaluation is performed on each sliced silicon wafer. Specifically, the crystal characteristics of each silicon wafer are evaluated. At that time, a unique SXLID (S028050101060 to S028050108J60) is assigned to the silicon wafer group sliced from one crystal block. Among them, a unique wafer lot ID (93B085AA00, etc.) is also given to one lot of silicon wafers. One lot of silicon wafers are individually placed on each carrier to which a carrier ID (BB3506) is assigned, and are transferred to the next chamfering step. Each carrier is formed with a large number of grooves into which one silicon wafer is loaded. Each SXLID and each carrier ID (including the groove number) are input to the crystal processing process management computer, and then input to the host computer via the computer network. Thereby, the identification of each silicon wafer can be expressed by the groove position of the carrier.

  In the chamfering step, a metal bond chamfering grindstone is pressed against the outer peripheral portion of each silicon wafer, and the wafer outer peripheral portion is chamfered into a cross-sectional shell shape. The chamfered silicon wafer is placed on a tray to which a unique tray ID (LP0001) is assigned in units of lots, and is transferred to a lapping process. At that time, gathering in the tray is performed in order from the carrier ID of the top portion of the silicon wafer. Here, “gathering on a tray” means that a large number of silicon wafers are stacked and arranged so that the silicon wafer can be easily loaded into the next processing apparatus (lapping apparatus). The tray ID is input to the chamfering process management computer and then input to the host computer via the computer network.

  In the lapping step, the silicon wafer is held in five wafer holding holes formed in the template to which the template ID (0039-32B-P-1206, etc.) is assigned by a pair of upper and lower lapping surface plates. Thereafter, both the front and back surfaces of each silicon wafer are lapped by the upper and lower lapping surface plates while supplying the lapping solution. The loading position and collection order of each silicon wafer into the wafer holding hole are in accordance with instructions from the host computer. The lapped silicon wafer is placed on a grooved carrier to which a carrier ID (BB3506) is assigned and is transferred to a grinding process. The template ID and the carrier ID (including the groove number) are input to the lapping process management computer and then input to the host computer via the computer network.

  In the grinding process, surface grinding is performed on each lapped silicon wafer. Specifically, the surface of each silicon wafer is ground by several tens of μm by a leaf-type surface grinding apparatus having a resinoid grinding wheel. Each silicon wafer immediately after being ground is directly transferred to the hard laser marking process one by one. The fact that each silicon wafer has been ground is input to a grinding process management computer, and then input to a host computer via a computer network.

  In the hard laser marking process, hard laser marking is performed on each silicon wafer immediately after grinding. Specifically, a silicon wafer is sequentially drawn out from the groove of each carrier, and a laser mark ID (BDIGR002SJE5) serving as a wafer ID is imprinted at a depth of several 10 μm on the outer peripheral portion of the wafer surface. Each silicon wafer subjected to hard laser marking is directly transferred to a cleaning process after grinding. Each laser mark ID is input to a hard laser marking process management computer, and then input to a host computer via a computer network.

  In the post-grinding cleaning process, post-grinding cleaning is performed on each silicon wafer immediately after the hard laser marking. Specifically, cleaning with an alkaline solution is performed. Each silicon wafer after grinding and cleaning is stored one by one in each groove of a grooved transfer container provided with FOUPID, and transferred to the next crack inspection step. Each FOUPID and each groove number are input to a post-grinding cleaning process management computer, and then input to a host computer via a computer network.

  In the crack inspection process, a crack inspection is performed on each silicon wafer cleaned after grinding. Specifically, an inspection device is used to inspect the outer periphery for cracks and chipping using a CCD camera. Each silicon wafer immediately after the crack inspection is transported to a finishing chamfering process. The result of the crack inspection of each silicon wafer is input to the crack inspection process management computer, and then input to the host computer via the computer network.

  In the finishing chamfering process, finishing chamfering is performed on each silicon wafer immediately after being determined to be non-defective by the crack inspection. Specifically, the chamfered portion of each silicon wafer is finished (mirrored) by a mechanochemical finishing chamfering device. Each silicon wafer immediately after the finishing chamfering is transferred to the double-side polishing step. The fact that each silicon wafer has been chamfered is input to the computer for finishing chamfering process management, and then input to the host computer via a computer network.

  In the double-side polishing step, surface polishing is performed on each silicon wafer immediately after the finish chamfering. Specifically, a planetary gear type double-side polishing apparatus is used to hold silicon wafers in a predetermined order in one wafer holding hole (with a hole number) of a template assigned with a template ID (wafer management ID, etc.). The front and back surfaces of the silicon wafers are simultaneously polished while supplying the polishing liquid by the polishing cloth adhered to the upper surface of the lower surface plate and the polishing cloth adhered to the lower surface of the upper surface plate. The loading position and collection order of each silicon wafer into the wafer holding hole are in accordance with instructions from the host computer. Loading and unloading of each silicon wafer is performed automatically.

  Each silicon wafer after double-side polishing is sequentially stored in each groove of a grooved carrier to which a carrier ID (BZ0538, etc.) is given, and then a grooved transport container to which a FOUPID (FA2140, etc.) is given. Are sequentially stored in the respective grooves and conveyed to the next finish polishing step. A carrier is a container that is stored in an open state. Further, the template ID, the carrier ID (including the groove number), and the FOUPID (including the groove number) are input to the double-side polishing process management computer, and then input to the host computer via the computer network.

  In the double-side polishing step, double-side polishing is performed on each finished chamfered silicon wafer. Specifically, using a planetary gear type double-side polishing apparatus, a silicon wafer is held in five wafer holding holes of a template to which a template ID is assigned, and a polishing cloth and an upper surface fixed on the upper surface of a lower surface plate are used. The front and back surfaces of each silicon wafer are simultaneously polished with a polishing cloth adhered to the lower surface of the board.

  In the final polishing step, the surface of each silicon wafer subjected to double-side polishing is subjected to finish (mirror surface) polishing one by one. Here, a polishing surface plate having a polishing cloth for finishing attached on the upper surface, and a polishing head disposed on the lower surface facing the polishing surface plate and holding a silicon wafer on a lower surface by a predetermined holding structure. A leaf-type finish polishing apparatus is used. At the time of polishing, the surface of the silicon wafer that is rotating integrally with the polishing head is brought into sliding contact with the surface of the polishing cloth (polishing working surface) while supplying an abrasive (slurry) containing polishing abrasive grains to the polishing cloth. Finish polishing. Each finish-polished silicon wafer is sequentially accommodated in each groove of a grooved carrier to which a carrier ID (BZ0551, etc.) is assigned, and is transferred to the next epitaxial growth step. The carrier ID is input to the finish polishing process management computer, and then also input to the host computer via the computer network.

  In the epitaxial growth process, an epitaxial silicon film is grown on the surface of each silicon wafer. Specifically, a silicon wafer is placed on a susceptor provided in a reaction furnace of a leaf-type epitaxial growth apparatus, and heated at a predetermined temperature while flowing a reaction gas containing silicon in the reaction furnace, whereby the wafer surface A single crystal silicon film is epitaxially grown. Each silicon wafer after the epitaxial growth is sequentially stored in each groove of a grooved transfer container provided with FOUPID (FD3516), and is transferred to the next appearance inspection process. FOUPID (FD3561, etc .; including groove number) is input to the double-side polishing process management computer, and then input to the host computer via the computer network.

  In the appearance inspection process, accuracy measurement and appearance inspection are performed on each silicon wafer. In the accuracy measurement, specifically, the thickness and variation regarding the flatness of the silicon wafer are measured. Each silicon wafer immediately after the appearance inspection is transported to the next final cleaning step. The accuracy measurement result and the appearance inspection result of each silicon wafer are input to the crack inspection process management computer, and then input to the host computer via the computer network.

  In the final cleaning step, each silicon wafer immediately after the appearance inspection is finally cleaned. Specifically, each silicon wafer is cleaned using an alkaline solution and an acid solution. Each silicon wafer immediately after the final cleaning is transported to the next surface inspection process. The fact that the final cleaning has been performed is input to the final cleaning process management computer, and then input to the host computer via the computer network.

  In the surface inspection step, surface inspection is performed on each finally cleaned silicon wafer. Specifically, defects such as foreign matter, scratches, slips, and pits are inspected. Each silicon wafer immediately after the surface inspection is then transferred to a warehouse approval process. The result of the surface inspection of each silicon wafer is input to the surface inspection process management computer, and then input to the host computer via the computer network.

  In the storehouse approval process, storehouse is approved for each silicon wafer, and a determination is made for each lot. “Kura insertion” means a state where all the processing steps of the silicon wafer are completed and packed in a shipping container. In the determination, a manufacturing specification and a specification are determined for each silicon wafer. Here, as for the silicon wafer determined to be non-defective, 25 wafers are collected as one lot, and a shipping lot ID (T93B0851 (M) to T93B0857, etc.) is given. Each silicon wafer is sequentially stored in each groove of a shipping container with a groove to which FOSBID (shipping lot ID, track number, etc.) is assigned for each lot, and is transferred to the next shipping approval process. The FOSBID (including the groove number) is input to the storage approval process management computer, and then input to the host computer via the computer network.

  In the shipping approval process, the shipping container is approved for shipping, then several are packed into one, a packing number (413573-415493) is given, and a shipment ID (00EA9408000000101) which is the ID of the assembly of shipping containers. , Etc.) are given and shipped. The package number and shipment ID are input to the shipping approval process management computer, and then input to the host computer via the computer network. Manufacturing information (including quality information) for each wafer is collectively managed by a host computer using a computer network, so that information can be maintained and information can be efficiently reused.

  With this configuration, how a specific silicon wafer is processed in each process and then transferred to the next process is determined based on the crystal number, block ID and hardware stored in the host computer. By tracking the laser mark ID (wafer ID) or the like, it is possible to easily search for each wafer. Thereby, various unique manufacturing information can be easily acquired about each silicon wafer. As a result, when a defective product is detected, it is possible to review and adjust the conditions in the previous processes accurately and quickly, and to prevent frequent defective products.

That is, since various pieces of information can be acquired in units of one wafer, high analysis accuracy of the silicon wafer, shortening of analysis time, and high work accuracy can be obtained. In addition, the history tracking of the single wafer information associates the position information of the single crystal silicon ingot in mm units, so that the quality information of the single crystal silicon ingot can be searched and analyzed in addition to the quality information of the wafer processing process. . Furthermore, by linking each processing and measurement device with system control, not only the device that has processed a given silicon wafer, but also the positional information within that device (for example, multiple chucks are mounted on each device). It is also possible to track the chuck information of the grinding and polishing equipment, the chamber information of the epitaxial equipment equipped with multiple chambers, etc. In addition, the system control allows selection of evaluation wafers, shipping lot configuration, and separation of nonconforming wafers. Manufacturing information here refers to raw material information, processing history of crystal blocks and silicon wafers, quality information, material information required for processing, and the like.
In addition, the management of silicon wafers for each wafer is performed rather than the management of silicon wafers in units of lots as in the past, so that defects in each process can be easily found, and detailed corrections can be made. It becomes easy and precise management can be performed.

Next, a wafer manufacturing history tracking method for tracking the manufacturing history of a silicon wafer obtained from another single crystal silicon ingot will be described with reference to the flow sheet of FIG.
Here, the crystal number of the single crystal silicon ingot is E01700710000. The single crystal silicon ingot is cut into five crystal blocks, and among these, the block ID of one crystal block is E01700710400. Further, the crystal block of E01700710400 is sliced into 256 silicon wafers, and an SXLID of E0170007104A20 is given to the wafer group in this state.

  The silicon wafer group to which SXLID of E017007104A20 is assigned is divided into a wafer lot consisting of 121 silicon wafers (wafer lot ID: 7Y501NAA00) and another wafer lot consisting of 125 silicon wafers (wafer lot ID; 7Y501PAA00). Divided into two.

  Among these, the silicon wafer group constituting the wafer lot (7Y501NAA00) is divided into six sublots (sublot ID; 7Y501NAA01 to 7Y501NAA06). The sub lot of 7Y501NAA01 is composed of 16 silicon wafers (wafer ID; 7Y501NAA00001 to 7Y501NAA00016). The sub lot of 7Y501NAA02 is composed of 24 silicon wafers (wafer ID; 7Y501NAA00017 to 7Y501NAA00040). The sub lot of 7Y501NAA03 is composed of 25 silicon wafers (wafer ID; 7Y501NAA00041 to 7Y501NAA00065). The sub lot of 7Y501NAA04 is composed of nine silicon wafers (wafer ID; 7Y501NAA00066 to 7Y501NAA00074). The sub lot of 7Y501NAA05 is composed of 23 silicon wafers (wafer ID; 7Y501NAA00075 to 7Y501NAA00097), and the sublot of 7Y501NAA06 is composed of 24 silicon wafers (wafer ID; 7Y501NAA00098 to 7Y501NAA00121).

  Further, the silicon wafer group constituting the wafer lot (7Y501PAA00) is divided into five sublots (sublot ID; 7Y501PAA01 to 7Y501PAA05). Each sublot is composed of 25 silicon wafers. Specifically, the sub lot of 7Y501PAA01 is composed of silicon wafers having wafer IDs: 7Y501PAA00001 to 7Y501PAA00025. The sub lot of 7Y501PAA02 is composed of silicon wafers with wafer IDs: 7Y501PAA02006 to 7Y501PAA000050. The sub lot of 7Y501PAA03 is composed of silicon wafers having wafer IDs: 7Y501PAA00041 to 7Y501PAA00065. The sub lot of 7Y501PAA04 is composed of silicon wafers with wafer IDs: 7Y501NAA00066 to 7Y501PAA00074. The sub lot of 7Y501PAA05 is composed of a silicon wafer having a wafer ID; 7Y501PAA00075 to 7Y501PAA00097.

The shipping lot is 11 lots (shipping lot ID; A8250CH1M, A7Y503D1 to A7Y503D4, A7Y503J5M, A7Y503J1 to A7Y503J4, A7Z500E1M), and one lot is composed of 25 silicon wafers. Assume that the previous crystal block (E01700710300) is sliced, and there are 20 remaining silicon wafers shipped through each step.
The remaining 20 silicon wafers from the previous crystal block and the 5 silicon wafers from the 7Y501NAA01 sub-lot (defective wafer; 0) are combined to constitute a shipping lot of A8250CH1M. Further, the remaining 11 silicon wafers in the 7Y501NAA01 sub-lot and the 14 silicon wafers from the 7Y501NAA02 sub-lot (defective wafer; 1) are combined to form a shipping lot of A7Y503D1.

The remaining 9 silicon wafers in the 7Y501NAA02 sub-lot and the 16 silicon wafers from the 7Y501NAA03 sub-lot (defective wafers: 2) are combined to form a shipping lot of A7Y503D2.
The remaining 7 silicon wafers in the 7Y501NAA03 sub-lot, 8 silicon wafers from the 7Y501NAA04 sub-lot (defective wafer; 1), and 10 silicon wafers from the 7Y501NAA05 sub-lot (defective wafer; 2) Together, a shipping lot of A7Y503D3 is configured.
The remaining 11 silicon wafers in the 7Y501NAA05 sub-lot and the 14 silicon wafers from the 7Y501NAA06 sub-lot (defective wafer; 1) are combined to form a shipping lot of A7Y503D4.

The remaining 9 silicon wafers in the 7Y501NAA06 sub-lot and 16 silicon wafers from the 7Y501PAA01 sub-lot (defective wafer; 0) are combined to form a shipping lot of A7Y503J5M.
The remaining 9 silicon wafers in the 7Y501PAA01 sub-lot and the 16 silicon wafers from the 7Y501PAA02 sub-lot (defective wafer; 1) are combined to form a shipping lot of A7Y503J1.
The remaining 8 silicon wafers in the 7Y501PAA02 sub-lot and the 17 silicon wafers from the 7Y501PAA03 sub-lot (defective wafer; 0) are combined to form a shipping lot of A7Y503J2.
The remaining 8 silicon wafers in the 7Y501PAA03 sub-lot and the 17 silicon wafers from the 7Y501PAA04 sub-lot (defective wafers: 2) are combined to form a shipping lot of A7Y503J3.

The remaining 6 silicon wafers of the 7Y501PAA04 sub-lot and the 19 silicon wafers from the 7Y501PAA05 sub-lot (defective wafer; 0) are combined to form a shipping lot of A7Y503J4.
The remaining 6 silicon wafers in the 7Y501PAA05 sub-lot and the next crystal block (E01700710500) are sliced and 19 silicon wafers shipped through each process are combined to form a shipping lot of A7Z500E1M.
The method of tracking the history of each silicon wafer is the same as that described in the flow sheet of FIG.

  The present invention is useful for tracking the history of manufacturing information of single crystals, polished wafers, epitaxial wafers, annealed wafers, and the like.

Claims (2)

Manufacturing history of a semiconductor wafer manufactured by sequentially performing crystal processing including block cutting for obtaining a crystal block from a semiconductor crystal and wafer processing including a slice for obtaining a plurality of semiconductor wafers from the crystal block on the semiconductor crystal. In the wafer manufacturing history tracking method for tracking
Storing a crystal number assigned to the semiconductor crystal in a storage medium;
Information on the semiconductor crystal obtained from the crystal number assigned to the crystal block and assigned to the semiconductor crystal that is the basis of the crystal block, and the block cutting of the semiconductor crystal after the semiconductor crystal is manufactured. Each crystal processing information until the crystal block is obtained by performing crystal processing including the position information of the crystal block in the semiconductor crystal before being cut into the crystal block from the semiconductor crystal was included Storing the block ID in the storage medium;
The information of the crystal block obtained from the block ID given to the semiconductor wafer and given to the crystal block that is the basis for each semiconductor wafer, and after the production of the crystal block Each wafer processing information until the semiconductor block is obtained by performing wafer processing including the slice on the crystal block, and the crystal block of the semiconductor wafer before being sliced from the crystal block to the semiconductor wafer. And storing the wafer ID including the position information in the storage medium,
A wafer manufacturing history tracking method for tracking a manufacturing history of each semiconductor wafer based on the crystal number, the block ID, and the wafer ID stored in the storage medium.   The wafer manufacturing history tracking method according to claim 1, wherein the unique wafer ID is laser-marked on each semiconductor wafer.

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