JP4244459B2 - Semiconductor wafer and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor wafer such as a silicon wafer sliced from an ingot such as single crystal silicon and a method for manufacturing the same.
[0002]
[Prior art]
A conventional process for manufacturing a semiconductor wafer will be described with respect to a silicon wafer. A slicing process for slicing a silicon wafer from an ingot of single crystal silicon, a chamfering process for forming a chamfered surface on the periphery of the sliced silicon wafer, and a chamfering process. A lapping process for rough polishing the silicon wafer by lapping, an etching process for etching the lapped silicon wafer with an etching solution, a polishing process for mirror polishing the etched silicon wafer, and a polished silicon wafer It is mainly composed of a cleaning process and the like for cleaning.
[0003]
Conventionally, a silicon wafer manufactured in this way is usually marked with a lot number or the like by laser marking on a part of its surface or the like.
[0004]
[Problems to be solved by the invention]
Semiconductor devices such as ICs manufactured from semiconductor wafers by multiple processes have different yields depending on crystallinity, and there is a desire to specify the position in the ingot from which the semiconductor wafer was cut out in order to investigate the relationship between yield and crystallinity. was there. However, conventionally, a plurality of silicon wafers sliced from an ingot are arranged in the order of slices immediately after the slicing step, but in the subsequent steps, the order is final because they are processed in units of cassettes. It was difficult to recognize the position in the original ingot.
[0005]
The present invention has been made in view of the above-described problems, and an object thereof is to provide a semiconductor wafer capable of specifying a position that has been cut out from an ingot and separated in order, and a method for manufacturing the same. And
[0006]
[Means for Solving the Problems]
The present invention employs the following configuration in order to solve the above problems.
That is, in the method for producing a silicon wafer of the present invention, a slicing step of slicing a plurality of silicon wafers from an ingot of single crystal silicon whose resistance value changes little by little in the axial direction;
A chamfering step of forming a chamfered surface by chamfering the peripheral edge of the sliced silicon wafer;
After the chamfering step, a lapping step of lapping the chamfered silicon wafer,
Etching process to remove the processing damage by etching the lapped silicon wafer,
A polishing step of mirroring the front and back surfaces of the silicon wafer after the chamfering step;
A heat treatment step for performing donor killer and gettering after the polishing step;
A resistance value measuring step for measuring the resistance value of each silicon wafer;
A marking step for forming an identification mark on at least one of the front surface or the back surface of the silicon wafer,
The marking process includes a symbol or a number indicating a rank when the plurality of silicon wafers are arranged in the order of the resistance value in the identification mark, and is clarified after the formation of the semiconductor element by the rank of the resistance value. said feedback slices order to facilitate to the single crystal pulling growth based on the relationship between device characteristics and yield and the ingot in the position of the silicon wafer that includes a feature that mark as the position information of said ingot To do.
Silicon wafer of the present invention may be more produced in the production method of the silicon wafer, characterized in that the identification mark is formed.
The semiconductor wafer of the present invention is a semiconductor wafer sliced from a semiconductor ingot, and an identification mark is provided on at least one of the front surface and the back surface, and the identification mark is information on a position sliced in the ingot. The technology including is adopted.
[0007]
Further, in the semiconductor wafer manufacturing method of the present invention , a slicing step of slicing a plurality of semiconductor wafers from a semiconductor ingot, and a marking step of forming an identification mark on at least one of the front surface or the back surface of the semiconductor wafer after the slicing step, The marking step employs a technique for including, in the identification mark, position information in the ingot where the semiconductor wafer is sliced in the slicing step.
[0008]
In these semiconductor wafers and semiconductor wafer manufacturing methods, the identification mark includes information on the position sliced in the ingot, so that the original position in the ingot is known by the identification mark, and the characteristics of the semiconductor wafer and the position in the ingot are determined. The relationship becomes clear.
[0009]
The semiconductor wafer manufacturing method of the present invention, the above-described method for fabricating a semiconductor wafer, comprising a resistance measuring step of measuring a resistance value of the plurality of semiconductor wafers, respectively after said slicing step, the marking process, the plurality of semiconductor A technique is adopted in which a symbol or number indicating the order when the wafers are arranged in the order of the resistance values is included in the identification mark.
[0010]
In this semiconductor wafer manufacturing method, in the marking process, the identification mark includes a symbol or a number indicating the order when a plurality of semiconductor wafers are arranged in the order of resistance value, so that the resistance value of the ingot is slightly in the axial direction. Even if the order is scattered after the slicing process, the position at the time of the ingot can be reproduced by arranging in the order of resistance value. The position in the ingot can be easily confirmed.
[0011]
In the semiconductor wafer manufacturing method of the present invention, in the semiconductor wafer manufacturing method described above, a technique is used in which the marking step is performed at least after a chamfering step of chamfering the periphery of the semiconductor wafer.
[0012]
In this method of manufacturing a semiconductor wafer, the marking process is performed at least after the chamfering process in which the peripheral edge of the semiconductor wafer is chamfered. The positional accuracy can be increased.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, an embodiment of a semiconductor wafer and a manufacturing method thereof according to the invention will be described with reference to FIGS.
[0014]
As shown in FIG. 1, the semiconductor wafer of this embodiment is a 12-inch silicon wafer W sliced from a single crystal silicon ingot I and finally mirror-polished, and is identified near the notch portion N. The mark MK is formed by laser marking.
The identification mark MK includes information on the position sliced in the ingot I, and numbers as shown in FIG. 2 are numbered with numbers sequentially from one end side of the ingot I. Note that the position and size of the identification mark M are set so as to prevent the formation of semiconductor elements as much as possible.
[0015]
In this method of manufacturing the silicon wafer W, first, as shown in FIG. 3, first, a plurality of silicon wafers W are sliced from the ingot I to a predetermined thickness by a slicing step S1. In addition, after this slicing step S1, each silicon wafer W is subjected to each step in a cassette unit.
Further, a chamfered surface M is formed by chamfering the periphery of the silicon wafer W sliced in the chamfering step S2. Note that, during the chamfering step S2, the silicon wafer W is processed to have an outer diameter smaller by about 1 mm than immediately after the slicing step S1.
[0016]
Next, in the lapping step S3, the chamfered silicon wafer W is lapped and rough polished. In this lapping step S3, for example, the silicon wafer W is held between the upper and lower lapping surface plates by a planetary carrier, and the silicon wafer W is pressurized and rotated by the upper and lower lapping surface plates while supplying lapping liquid containing abrasive grains. Then, a lapping apparatus that mechanically polishes both the front and back surfaces of the silicon wafer W is used.
[0017]
Next, in the etching step S4, the entire lapped silicon wafer W is immersed in an etching solution to perform an etching process, and processing damage due to mechanical polishing (lapping and chamfering) is removed.
[0018]
Next, mechanical and chemical polishing is performed on both the front and back surfaces of the silicon wafer W to form a mirror surface by the polishing step S6. In this polishing step S6, for example, an upper surface plate and a lower surface plate each having a polishing cloth affixed on the surface thereof are rotated from above and below to contact both front and back surfaces of the silicon wafer W, and mechanochemical while supplying an alkaline polishing liquid. A double-side polishing apparatus (polishing apparatus) that performs polishing is used.
[0019]
Further, after the polishing step S6, the wax and the like are removed from the silicon wafer W by the cleaning step S7.
Thereafter, the resistance value of each mirror-polished silicon wafer W is measured by a resistance value measuring step S7. Then, when the obtained resistance values are arranged in the order of their sizes, the order of the silicon wafers W is examined. At this time, if the silicon wafers W are arranged in the order of resistance values, the state of the ingot I immediately after slicing can be substantially reproduced as shown in FIG.
[0020]
Next, in the laser marking step S8, a number indicating the order is used as an identification mark MK at a predetermined position on the front surface or back surface of each silicon wafer W, and the silicon wafer W is numbered as shown in FIG. To do.
[0021]
Therefore, in this embodiment, since the identification mark MK includes information on the position sliced in the ingot I, even if each silicon wafer W flows through the process after the slicing step S1, the order is found from the resistance value. The original position in the ingot I can be known by the identification mark MK, and the relationship between the characteristics (the yield, etc.) of the silicon wafer W and the position in the ingot I becomes clear after the IC is formed.
Further, since the laser marking step S8 is performed after the chamfering step S2 in which the outer diameter of the silicon wafer W does not change, the positional accuracy of the identification mark MK is increased and the reading and recognition of the mark is ensured.
[0022]
The present invention includes the following embodiments.
In the above embodiment, the position information in the ingot based on the actually measured resistance value is marked on the silicon wafer W as the identification mark MK. However, information indicating the actual slice position is identified on each silicon wafer W immediately after the slicing step. You may mark directly as In this case, since it is before the chamfering process, as described above, the position accuracy of the identification mark is lowered. Therefore, it is preferable to perform marking after the chamfering process. Furthermore, it is desirable to perform a laser marking process after the polishing process in which mirror polishing is performed.
[0023]
In the above embodiment, the position information in the ingot I found from the resistance value is included in the identification mark MK, but other information may also be included. For example, an identification mark including a lot number or the like may be adopted.
[0024]
Further, the identification marks may be not only numbers but also alphabets, symbols, barcodes, etc., or a combination of these as long as they indicate the order when arranged in the order of resistance values. In the above embodiment, the order when arranged in the resistance value order is displayed as the identification mark, but a number or the like indicating the measured resistance value itself may be included in the identification mark. Even in this case, the identification mark functions as position information in the ingot, and the order can be confirmed from the resistance value of the identification mark.
[0025]
In the said embodiment, although applied to the process using a lapping process and an etching process, you may employ | adopt for an etching-less process etc. For example, the technique described in Japanese Patent Application Laid-Open No. 9-246216, that is, an etching-less process using a grinding process instead of a CCR (Chemical Corner Rounding) process in which only a chamfered surface is selectively etched with an etchant and a lapping process is used. You may apply to a process etc. Even in this case, the resistance value measuring step and the laser marking step are performed after the chamfering step, preferably after the polishing step.
[0026]
In the above-described embodiment, the present invention is applied to a silicon wafer as a semiconductor wafer. However, the present invention may be applied to other semiconductor wafers, for example, compound semiconductor wafers (gallium arsenide wafers, etc.) and manufacturing methods thereof.
Moreover, in the said embodiment, you may introduce | transduce a donor killer heat processing process, a gettering process, etc. after the PCR (Polishing corner rounding) process which performs a chemical-chemical polishing on a chamfering surface, and a polishing process.
[0027]
【The invention's effect】
The present invention has the following effects.
According to the semiconductor wafer of the present invention and the manufacturing method of the semiconductor wafer of the present invention , since the identification mark includes information on the position sliced in the ingot, the relationship between the characteristic of the semiconductor wafer and the position in the ingot is determined by the identification mark. It becomes clear, the feedback to the single crystal pulling growth is facilitated, and the device characteristics and the yield can be improved.
[0028]
According to the method for manufacturing a semiconductor wafer of the present invention , in the marking process, since the symbols or numbers indicating the order when a plurality of semiconductor wafers are arranged in the order of the resistance value are included in the identification mark, the order is dispersed after the slicing process. Even in this case, the position at the time of the ingot can be reproduced from the order, and the position information in the ingot can be easily added to the semiconductor wafer only by measuring the resistance value at any time after the slicing process.
[0029]
According to the semiconductor wafer manufacturing method of the present invention , the marking process is performed at least after the chamfering process in which the peripheral edge of the semiconductor wafer is chamfered. Therefore, the outer diameter of the semiconductor wafer does not change after marking, so that the positioning accuracy is high. A mark is obtained and the reading and recognition of the mark is ensured.
[Brief description of the drawings]
FIG. 1 is a plan view showing a silicon wafer in an embodiment of a semiconductor wafer and a manufacturing method thereof according to the present invention.
FIG. 2 is a side view showing a state in which silicon wafers in one embodiment of the semiconductor wafer and the manufacturing method thereof according to the present invention are arranged in order of resistance value and an ingot immediately after slicing is reproduced.
FIG. 3 is a flowchart showing a manufacturing process of a silicon wafer in an embodiment of a semiconductor wafer and a manufacturing method thereof according to the present invention.
[Explanation of symbols]
S1 Slicing step S2 Chamfering step S7 Resistance measurement step S8 Laser marking step I Ingot M Chamfering surface MK Identification mark W Silicon wafer (semiconductor wafer)

Claims (2)

A slicing step of slicing a plurality of silicon wafers from an ingot of single crystal silicon whose resistance value changes little by little in its axial direction;
A chamfering step of forming a chamfered surface by chamfering the peripheral edge of the sliced silicon wafer;
After the chamfering step, a lapping step of lapping the chamfered silicon wafer,
Etching process to remove the processing damage by etching the lapped silicon wafer,
A polishing step of mirroring the front and back surfaces of the silicon wafer after the chamfering step;
A heat treatment step for performing donor killer and gettering after the polishing step;
A resistance value measuring step for measuring the resistance value of each silicon wafer;
A marking step for forming an identification mark on at least one of the front surface or the back surface of the silicon wafer,
The marking process includes a symbol or a number indicating a rank when the plurality of silicon wafers are arranged in the order of the resistance value in the identification mark, and is clarified after the formation of the semiconductor element by the rank of the resistance value. said feedback slices order to facilitate to the single crystal pulling growth based on the relationship between device characteristics and yield and the ingot in the position of the silicon wafer that includes a feature that mark as the position information of said ingot A method for manufacturing a silicon wafer. Is more manufacturable method of manufacturing a silicon wafer according to claim 1, a silicon wafer, characterized in that the identification mark is formed.

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