CN108511417A - The manufacturing method of semiconductor wafer - Google Patents
The manufacturing method of semiconductor wafer Download PDFInfo
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- CN108511417A CN108511417A CN201710103704.5A CN201710103704A CN108511417A CN 108511417 A CN108511417 A CN 108511417A CN 201710103704 A CN201710103704 A CN 201710103704A CN 108511417 A CN108511417 A CN 108511417A
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- semiconductor wafer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54406—Marks applied to semiconductor devices or parts comprising alphanumeric information
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54413—Marks applied to semiconductor devices or parts comprising digital information, e.g. bar codes, data matrix
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/5442—Marks applied to semiconductor devices or parts comprising non digital, non alphanumeric information, e.g. symbols
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54433—Marks applied to semiconductor devices or parts containing identification or tracking information
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
The purpose of the present invention is to provide a kind of manufacturing methods of the semiconductor wafer with the identification label for simply obtaining various manufacture information.The manufacturing method of semiconductor wafer involved by the mode of the present invention has：Crystal pro cessing process obtains crystal block by semiconductor crystal；Slicing process cuts out the crystal block, obtains the chip group being made of more semiconductor wafers；Chip loads process, and the semiconductor wafer for constituting the chip group is placed in defined sequence in bracket, and position of the semiconductor wafer in the bracket is established with position of the semiconductor wafer in the chip group and is associated with；And mark process includes the machining information of the semiconductor single crystalline ingot, the crystal block and the semiconductor wafer to each imparting identification label of the semiconductor wafer, in the identification label according to the semiconductor wafer putting in order in the bracket.
Description
Technical field
The present invention relates to a kind of manufacturing methods of semiconductor wafer.
Background technology
Formation substrate, that is, silicon wafer of the superelevation integrated device such as ULSI to utilizing by cutting krousky（CZ）Method lifting
Monocrystal silicon is implemented chip processing and is made.Specifically, monocrystal silicon is cut blocking, then silico briquette is utilized successively
The periphery of abrasive grinding wheel is ground, using the slice of fret saw, to obtain more silicon wafers.Then, to each silicon wafer successively into
Row chamfered edge, polishing, etching, grinding carry out the product chip of making devices formation.
In the past, it is the management method of the silicon wafer in the processing of each chip of starting material generally with by number 10 using monocrystal silicon
The silicon wafer that piece~number is 100 is carried out as a bundle of lot-to-lot（Such as patent document 1）.
Patent document 1：Japanese Unexamined Patent Publication 2001-358199 bulletins
However, the management method of the silicon wafer based on patent document 1 is so to manage the technology of chip with lot-to-lot.Therefore,
It can not obtain when specific silicon wafer is sliced from which position of the monocrystal silicon of lifting, then, be processed using which chip
Device（Annealing device etc.）, when in which kind of condition（Heat treatment condition etc.）The information of the wafer units such as lower processing.
Therefore, the information that can only obtain lot-to-lot is unable to fully the defect cause etc. of tracking silicon wafer, can not be with high-precision
Exactness carries out best quality improving.
Invention content
Therefore, the present inventor furtherd investigate as a result, find by using ID to by semiconductor crystal（Crystal ingot）It obtains
The information of the crystal block obtained and the information of the semiconductor wafer obtained by crystal block carry out one chip management respectively, can track semiconductor
Crystal information that when chip obtains from which semiconductor crystal, the location information being sliced from which position of which crystal block, with
And machining information when crystal pro cessing process and slicing process, so as to complete the invention.
Invention described in claim 1 has：Crystal pro cessing process obtains crystal block by semiconductor single crystalline ingot；Slicing process,
The crystal block is cut out, the chip group being made of more semiconductor wafers is obtained；Chip loads process, will constitute the chip group's
The semiconductor wafer is placed in defined sequence in bracket, and by position of the semiconductor wafer in the bracket with
Association is established in position of the semiconductor wafer in the chip group；And mark process, according to the semiconductor wafer in institute
Putting in order in bracket is stated, to each imparting identification label of the semiconductor wafer.Include described half in identification label
The machining information of conductor single crystal rod, the crystal block and the semiconductor wafer.
In the manufacturing method of the semiconductor wafer, semiconductor wafer is placed according to the sequence of regulation in bracket.Therefore,
Semiconductor wafer, which will not lose in the stage being placed in bracket from where chip group and crystal block, to be obtained, is brilliant
Block the information such as obtains from which semiconductor crystal and is kept.Therefore, only pass through the row according to semiconductor wafer in bracket
For row sequence to each imparting identification label of semiconductor wafer, identification label will include various manufacture information.Thereby, it is possible to
It is easy that the manufacture resume of semiconductor wafer is made to retain in the semiconductor wafer, additionally it is possible to mark tracking manufacture resume according to identification.
In invention described in claim 2, according to putting in order after the chip group cut from crystal block just cutting, by institute
Semiconductor wafer is stated to be placed in the bracket.
According to the manufacturing method of the semiconductor wafer, from the sequence of crystal block cutting semiconductor chip, to be loaded in bracket
Semiconductor wafer.Therefore, it is possible to which location information of the semiconductor wafer in bracket is substituted for semiconductor wafer brilliant in the block
Location information.Therefore, it is possible to more simply obtain the correspondence of semiconductor wafer and crystal block.
In invention described in claim 3, has after the slicing process and crystal is carried out to the semiconductor wafer
The evaluation of crystal process of evaluation will with the resistance value sequence of the semiconductor wafer determined in the evaluation of crystal process
The semiconductor wafer is placed in the bracket.
The resistance value of crystal ingot little by little changes in its axial direction generally according to the segregation at liquid-solid interface.Therefore, exist
In the crystal block obtained by crystal ingot, resistance value is also little by little to change from one end towards the other end.If by semiconductor wafer to measure
The resistance value of the semiconductor wafer gone out is arranged sequentially in bracket, even if then in the case where the sequence of semiconductor wafer is at random,
Semiconductor wafer when can also reappear crystal ingot and crystal block puts in order.That is, can partly be led according to what is arranged according to resistance value
The sequence of body chip tracks the correspondence of semiconductor wafer and crystal block.
Invention effect
In accordance with the invention it is possible to the manufacture resume of semiconductor wafer are marked as identification easily and are retained, and being capable of basis
Identification label is easy to get crystal block the location information of semiconductor wafer and the machining information of semiconductor wafer.
Description of the drawings
Fig. 1 is half obtained by schematically showing the manufacturing method of the semiconductor wafer involved by the present embodiment
The figure of an example of conductor chip.
Fig. 2 is half obtained by schematically showing the manufacturing method of the semiconductor wafer involved by the present embodiment
Another figure of conductor chip.
Fig. 3 is the flow chart of an example of the manufacturing method of the semiconductor wafer involved by present embodiment.
Fig. 4 indicates that the ID in each manufacturing process of the manufacturing method of the semiconductor wafer involved by present embodiment is assigned
Example.
Specific implementation mode
Hereinafter, appropriate refer to the attached drawing, carries out specifically the manufacturing method of the semiconductor wafer involved by present embodiment
It is bright.
Fig. 1 is half obtained by schematically showing the manufacturing method of the semiconductor wafer involved by the present embodiment
The figure of an example of conductor chip.Hereinafter, in this specification, as an example of semiconductor wafer, illustrated according to silicon wafer.Figure
Silicon wafer W shown in 1 has identification label MK near recess N.The peripheral part of silicon wafer W shown in FIG. 1 is processed by chamfered edge
And there is chamfered edge face M.
Can be the bar codes such as GS1 data strips as long as identification label MK is able to record information（With reference to figure 1）, two dimension
Code（With reference to figure 2）And the arbitrary symbol for being formed by combining number, letter, mark.GS1 data strips are by by data pressure
It contracts and is encoded, so as to the identical data content of smaller spatial display.Also, GS1 data strips need not be in JAN
The white space of both sides needed for code etc.（Clear area）, easily save space.On the other hand, Quick Response Code is not easy falsification data,
It is excellent in terms of safety and the management of product.
Identification label MK is arranged with the position and size that will not cause obstacle to the formation of semiconductor element as possible.Identification mark
Note MK is preferably disposed on the outer edge for the silicon wafer W for becoming defined position relationship with recess N, in order to avoid pressing each silicon wafer W, knows
Not Biao Ji the position of MK change.Defined position relationship is arbitrarily set, such as is had on the left side of recess N, right side
Or top mark identification marks MK, situations such as the part opposed with recess N marks.Also, it is not limited to wafer surface,
Can be the back side.
Chip batches of the silicon wafer W sometimes as multi-disc binding carries out shipment.Here, " chip batch " refers to for example accommodating
In the aggregate of the chip in identical casings.For example, pack 25 wafers simultaneously in a shell, and as a wafer batch
Secondary shipment.The manufacturing condition for constituting each chip of chip batch can be different.Recess in each silicon wafer W of chip batch
The position relationship of N and identification label MK, which preferably presses each silicon wafer, has correspondence, more preferably consistent.
If pressing each silicon wafer, identification label is corresponding with the position relationship of recess, then only by the position of aligned recesses, just
It can be easy to differentiate the position of the identification label in each silicon wafer W.Therefore, when tracking the manufacture resume of semiconductor wafer,
It can more simply judge identification label.
Identification label is preferably by laser printing, due to can control working depth by laser power, such as also
It can print thin.By printing thin, additionally it is possible to which reply is the case where a part of information is left out in the midway of device process.
In addition, " position relationship has correspondence by each semiconductor wafer " refers in each semiconductor wafer
In, recess N and the position of identification label MK follow defined rule, and " position relationship is consistent by each semiconductor wafer " refers to
In each semiconductor wafer, the position consistency of recess N and identification label MK.In addition, the deviation of error degree is considered as unanimously
Range.
The information of manufacturing processes of the identification label MK with silicon wafer W.Hereinafter, to the silicon wafer involved by present embodiment
The manufacturing method of W illustrates, while illustrating the information how identification label MK keeps manufacturing process.
The manufacturing method of the silicon wafer at least has crystal pro cessing process, slicing process, chip mounting process and mark work
Sequence.Fig. 3 is the flow chart of an example of the manufacturing method of the semiconductor wafer involved by present embodiment.Also, Fig. 4 is to indicate this
ID given examples in each manufacturing process of the manufacturing method of semiconductor wafer involved by embodiment.Hereinafter, with reference to figure 3 and figure
4 pairs of each process are specifically described.
The manufacturing method of silicon wafer is preferably managed by computer.For example, from semiconductor crystal（Crystal ingot）Making
Raw material information, crystal block are managed to being equipped in each process of product turnout（Silico briquette）With the processing resume of silicon wafer, quality information plus
Material information, transport path needed for work etc. and the computer reported to other processes.By these computers via computer network
Network（LAN）It is connected to main control computer, the various information reported with wafer units are carried out with each silicon wafer corresponding, is carried out on one side
Data base system manufactures silicon wafer on one side.
First, semiconductor crystal is made（Crystal ingot）.Crystal ingot can be as shown in Figure 3 lifting process like that by cutting Crouse
Base method（CZ methods）To make.In addition it is also possible to molten using floating zone（FZ；Floating-Zone）The making such as method, the tape casting.Such as
Shown in Fig. 4, the semiconductor crystal obtained is endowed crystal number.
For example, in crystal pull process, a diameter of 306mm is lifted by Czochralski method, the length of straight metastomium is
2500mm, specific resistance are 10m Ω cm, initial oxygen concentration is 1.0 × 1018Atoms/cm3Monocrystal silicon（Semiconductor crystal）.
It is numbered here, assigning intrinsic crystal to monocrystal silicon（E01700710000）.Crystal number is input to crystal pull process
In supervisory computer, it is also input into main control computer via computer network.The information of input is the information of crystal,
The making resume for for example, lifting the time, lifting condition, the length of crystal, crystal ingot（For example, at the bottom that have passed through the straight metastomium of crystal
Portion midway, crystal such as cuts at the making resume）Deng.
Then, it cuts obtained semiconductor crystal in crystal pro cessing process and obtains the crystal block of specific length.Crystal block
Quantity can be 1, can also be 2 or more.In crystal pro cessing process, periphery grinding etc. can be carried out.In crystal block
Peripheral surface is ground in a manner of pressing and carries out periphery grinding, thus enables that the uniform external diameter of crystal block.As shown in figure 4, passing through
Block ID is marked to each crystal block, can identify that crystal block is cut out from which position of crystal ingot.
For example, cutting 8 crystal blocks of certain electrical resistivity range from 1 monocrystal silicon.Then, periphery is carried out to each crystal block
Grinding.Specifically, by with containing 200 abrasive grain（SiC）Resinoid bond abrasive grinding wheel apparatus for grinding outer circumference,
The peripheral part periphery of crystal block is ground 5mm.Each crystal block is formed as cylindric as a result,.
Each crystal block is endowed intrinsic block ID（E01700710400 etc.）.Each crystal block, which is independently placed in, has been assigned pallet
In 8 pallets of ID, and it is transported to next slicing process.Each piece of ID and each pallet ID are input to crystal pro cessing process
In supervisory computer, then, it is also input into main control computer via computer network.In addition, being also shown in each piece of ID
Corresponding crystal block is located at which position of crystal ingot.
Then, in slicing process, more silicon wafers are obtained by crystal block using fret saw etc..At this point it is possible to filleter
The input of sequence supervisory computer indicates to fix the metal die ID of the fixture of crystal block on slicing device（MSA004）.Metal die
ID is also input into via computer network into main control computer.By inputting metal die ID, which gold can be traced back through
Belong to mold to be handled.
The more silicon wafers obtained by a crystal block form chip group.Chip group is endowed intrinsic SXLID respectively
（E017007104A20）.As shown in figure 4, intrinsic SXLID is corresponding with intrinsic block ID.
Also, multiple chip batches are obtained by a chip group.Intrinsic chip batch is assigned to the silicon wafer of 1 batch quantity
ID（7Y501NAA00 etc.）.
At this point, as evaluation of crystal process, the respective evaluation of crystal of silicon wafer that can be sliced.In evaluation of crystal work
In sequence, such as measure resistance value, crystal orientation, diameter, oxygen concentration, surface roughness, the amounts of particles etc. of silicon wafer.It determines
These data and SXLID, the ID foundation of chip batch is associated with and is recorded.
Process is loaded as chip, the silicon wafer for having been assigned chip batch ID is independently placed on bracket, the support
Frame is formed with the multiple slots that can load each a piece of silicon wafer.Bracket imparting has bracket ID（BB3506）And slot number.
Silicon wafer is placed in defined sequence in bracket.Defined sequence refers to being arranged with defined systematicness, so as to
It can track and where defined chip batch is once located at the silicon wafer of defined slot number mounting.
If not loaded with defined sequence, there is the arrangement of the silicon wafer in the arrangement and bracket of the silicon wafer in chip group
Different situations can not track although can track which chip batch ID semiconductor wafers belongs to and once be located at chip batch
Which position.That is, it is the silicon wafer taken out from which position of chip group, crystal ingot that can not track.In other words, if can track
Once be located at chip batch which position, then can trace back to SXLID, block ID, can track once be located at crystal ingot which position,
Which kind of processing carried out.
As the method loaded with defined sequence, can enumerate according to after the chip group cut from crystal block just cutting
Put in order the method being placed in successively in the slot of bracket, according to the resistance value determined in evaluation of crystal process result into
The method etc. of row mounting.
Putting in order after the chip group cut from crystal block just cutting corresponds to from crystalline substance the 1st end in the block before cutting
Towards the sequence of the 2nd end.If sequentially silicon wafer is placed in the slot of bracket successively with this, row of the silicon wafer in bracket
Row sequence putting in order unanimously in chip group with silicon wafer.That is, being numbered according to the slot of bracket, it is from crystalline substance that can be easy tracking
Piece group（Chip batch）The silicon wafer that takes out of which position.
Also, since the segregation coefficient of the boron and phosphorus that are added as dopant is less than 1, the resistance value one of silicon wafer
As it is higher in the top side of crystal ingot, be lower with towards bottom side.That is, in crystal block, also in the part of the top side of crystal ingot
Resistance value is higher, and the resistance value for being located at the part of the bottom side of crystal ingot is relatively low.If, can that is, be ranked sequentially silicon wafer with resistance value
It is enough to reappear from putting in order after the chip group that crystal block is cut just cutting.Therefore, if with resistance value sequence by silicon wafer successively
It is placed in the slot of bracket, then putting in order according to resistance value, position of the silicon wafer in chip group can be tracked.
Also can when the sequence of the chip group after unexpectedly just cutting is at random in the tactic method of resistance value
Enough replies, in this regard preferably.On the other hand, how much the resistance value of silicon wafer generates partially because variation in diameter etc. influences sometimes
Difference will produce the position offset of several pieces units sometimes.
Each SXLID, each bracket ID（Including slot is numbered）It is input in crystal pro cessing process management computer, then,
It is also input into main control computer via computer network.The identification of each silicon wafer can be come with the groove location of bracket as a result,
Performance.
Then, the silicon wafer being placed on bracket is transported to chamfering process.In chamfering process, in the outer of each silicon wafer
Circumference presses metallic bond chamfered edge grinding wheel, and it is in shell shape that chip peripheral part, which is chamfered into section,.Silicon wafer shown in FIG. 1
Chamfered edge face M is processed by chamfered edge and is formed.
Silicon wafer after chamfered edge is placed in lot-to-lot has been assigned intrinsic pallet ID（LP0001）Pallet in, and
It is transported to polishing process.At this point, put in order progress of the collection with silicon wafer in bracket in pallet.That is, maintaining
Defined sequence carries out." collection in pallet " said here refers to by more silicon wafers overlapping arrangement, so that silicon wafer
It is easy to be loaded on next processing unit (plant)（Burnishing device）In.Pallet ID is input in chamfering process supervisory computer,
Then, it is also input into main control computer via computer network.
Then, in polishing process, tablet is polished by a pair of up and down, template ID is had been assigned being formed in（0039-
32B-P-1206 etc.）Template on 5 chip retaining holes in keep silicon wafer.Then, polishing fluid is supplied on one side, is passed through on one side
Upper and lower polishing tablet is polished the front and back sides of each silicon wafer.Each silicon wafer is to the input position of chip retaining hole and returns
Receipts sequence is according to the instruction from main control computer.Silicon wafer after polishing, which is placed in, has been assigned bracket ID（BB3506）Band
In the bracket of slot, and it is transported to grinding process.Template ID and bracket ID（Including slot is numbered）It is input to polishing process management
With in computer, then, it is also input into main control computer via computer network.
In grinding process, surface grinding is implemented to each silicon wafer after polishing.Specifically, by with resin-bonded
The surface of the one chip surface grinding attachment of agent abrasive grinding wheel, each silicon wafer is ground several 10 μm.Just each silicon wafer after grinding
Piece is directly transported to mark process by every 1.The case where each silicon wafer ground processing, is input to grinding process management use
In computer, then, it is also input into main control computer via computer network.
Then, in identifying process, according to silicon wafer putting in order to the silicon wafer after being just ground point in bracket
It Fu Yu not identify label.Specifically, lift silicon wafer successively from the slot of each bracket, and to the marking of the peripheral part on its surface at
For the laser labelling ID of chip ID（Bar code, Quick Response Code etc.）.If using bar code as laser labelling ID, can directly remember
Record forms the information of the process before laser labelling, therefore particularly preferably.Marking passes through the progress such as laser, such as in hard laser
In the case of mark, marked with several 10 μm or so of depth.Each laser labelling ID is input to mark process management and calculates
In machine, then, it is also input into main control computer via computer network.
Chip ID be according to silicon wafer putting in order in bracket and assign.Therefore, if assigning bracket to chip ID
ID（Including slot is numbered）Information, then can track be which position for being placed in bracket silicon wafer.Silicon wafer is with defined suitable
Sequence is placed in bracket, as long as therefore can track be which position being placed in bracket silicon wafer, then can track is
The silicon wafer taken out from which position of chip group and crystal block.
In addition, after this, during until shipment, washing procedure, crack detection process, essence after being ground sometimes
Chamfering process, twin grinding process, smooth grinding process, epitaxial growth procedure, visual examination process, final washing procedure, surface
Inspection operation, storage approval process（Judged by each batch）, shipment ratify process（Distribution checks achievement book）, product goes out
Goods process.If the data which kind of processing the silicon wafer with defined chip ID has been carried out to when by these processes are stored in
In main control computer, then the information in the subsequent handling for identifying process can also be tracked as resume according to chip ID.
Hereinafter, the subsequent handling after mark process is described in detail.
After grinding in washing procedure, washed after implementing grinding to each silicon wafer after firm matter laser-marking.Specifically
For, carry out the washing using alkaline solution.Each a piece of be contained in of each silicon wafer after being washed after grinding has been assigned
In each slot of the conveyance container of the trough of belt of FOUPID, and it is transported to next crack detection process.Each FOUPID and each slot
Number is input to after grinding in washing procedure supervisory computer, then, is also input into master control meter via computer network
In calculation machine.
In crack detection process, crack detection is carried out to each silicon wafer washed after grinding.Specifically, using inspection
Device is looked into, the inspection of the crackle and fragmentation of the peripheral part using CCD camera is implemented.Each silicon wafer after crack detection is just carried out
Piece is transported to smart chamfering process.The result of the crack detection of each silicon wafer is input to crack detection process management computer
In, then, it is also input into main control computer via computer network.
In smart chamfering process, implements essence to being just judged as each silicon wafer after certified products in crack detection and fall
Rib.Specifically, by the smart corner cutting off apparatus of mechanochemistry mode, essence is carried out to the chamfered edge portion of each silicon wafer（Minute surface）Chamfered edge.
Each silicon wafer after the smart chamfered edge of just progress is transported to twin grinding process.Each silicon wafer is input to through the fact that smart chamfered edge
In smart chamfering process supervisory computer, then, it is also input into main control computer via computer network.
In twin grinding process, twin grinding is carried out to just carrying out each silicon wafer after smart chamfered edge.Specifically, making
With the double-side polishing apparatus of planetary gear mode, template ID is being had been assigned（Chip management ID etc.）Template 1 chip protect
Hold hole（With holes number）In with regulation sequence keep silicon wafer, by be attached at lower tablet upper surface abrasive cloth and be attached at
The abrasive cloth of the lower surface of tablet supplies lapping liquid, is ground simultaneously to the table back side of each silicon wafer on one side on one side.Each silicon wafer
Piece is to the input position of chip retaining hole and recycling sequence according to the instruction from main control computer.It the taking-up of each silicon wafer and puts
Enter automatic progress.
Each silicon wafer after twin grinding is contained in successively has been assigned bracket ID（BZ0538 etc.）Trough of belt bracket
In each slot, then, it is contained in has been assigned FOUPID successively（FA2140 etc.）Trough of belt conveyance container each slot in, and removed
It send to next smooth grinding process.Bracket is the container being saved with opening state.Also, template ID, bracket ID（Including slot
Number）、FOUPID（Including slot is numbered）It is input in twin grinding process management computer, then, via computer network
Network is also input into main control computer.
In twin grinding process, twin grinding is implemented to each silicon wafer through smart chamfered edge.Specifically, using planet tooth
The double-side polishing apparatus of wheel mode keeps silicon wafer in having been assigned the 5 of template of template ID chip retaining holes, passes through patch
It invests the abrasive cloth of the upper surface of lower tablet and is attached at the abrasive cloth of the lower surface of upper flat plate, while the table of each silicon wafer is carried on the back
Face is ground.
In smooth grinding process, to the surface of each silicon wafer through twin grinding, implement essence by every 1（Minute surface）Grinding.
Here, using one chip lappingout mill apparatus, the one chip lappingout mill apparatus has：Grinding flat plate is pasted with essence in upper surface
The abrasive cloth of processing；And grinding head, it is arranged opposite in the top of grinding flat plate, it is protected by defined holding structure in lower surface
Hold silicon wafer.When being ground, on one side by the grinding agent containing grinding abrasive grain（Slurry）Supply makes and grinds to abrasive cloth on one side
Bistrique integrally rotate in silicon wafer surface and abrasive cloth surface（Abrasive action face）It slides against and carries out smooth grinding.
Each silicon wafer through smooth grinding is contained in successively has been assigned bracket ID（BZ0551 etc.）Trough of belt bracket each slot in, and by
It transports to next epitaxial growth procedure.Bracket ID is input in smooth grinding process management computer, then, via meter
Calculation machine network is also input into main control computer.
In epitaxial growth procedure, epitaxial silicon film is made to be grown on the surface of each silicon wafer.Specifically, being set to list
Pedestal in the reacting furnace of chip epitaxial growth device（susceptor）Upper mounting silicon wafer makes siliceous on one side in reacting furnace
Reactant gas flow, on one side heated at the specified temperature, thus make monocrystalline silicon membrane epitaxial growth on a surface of a wafer.Outside
Each silicon wafer after epitaxial growth is contained in successively has been assigned FOUPID（FD3516）Trough of belt conveyance container each slot in, and
It is transported to next visual examination process.FOUPID（FD3561 etc.；Including slot is numbered）It is input to twin grinding process
In supervisory computer, then, it is also input into main control computer via computer network.
In appearance inspection operation, accuracy measurement and visual examination are carried out to each silicon wafer.In accuracy measurement, tool
For body, the related thickness of flatness and deviation etc. of measurement and silicon wafer.Each silicon wafer quilt after visual examination is just carried out
It transports to next final washing procedure.The accuracy measurement result and visual examination result of each silicon wafer are input to crackle
In inspection operation supervisory computer, then, it is also input into main control computer via computer network.
In final washing procedure, finally washed to just carrying out each silicon wafer after visual examination.Specifically,
Washing using aqueous slkali and acid solution is carried out to each silicon wafer.Each silicon wafer after just progress is finally washed, which is transported to, to be connect
The surface inspection process got off.The fact that through finally washing, is input in final washing procedure supervisory computer, then, warp
It is also input into main control computer by computer network.
In surface inspection process, surface inspection is carried out to each silicon wafer through finally washing.Specifically, checking different
Object, scratch, sliding（slip）, pit（pit）The defects of.Just next each silicon wafer after progress surface inspection is transported to
Storage ratify process.The result of the surface inspection of each silicon wafer is input in surface inspection process management computer, so
Afterwards, it is also input into main control computer via computer network.
In storage ratifies process, ratifies each silicon wafer storage, judged by each batch." storage " refers to silicon wafer
Manufacturing procedure all terminate, and the state in the shipment container.Also, when judging, manufacture is detailed to be judged to each silicon wafer
Book and specification.Here, for the silicon wafer for being judged as certified products, chip 25 is bundled as 1 batch, and is endowed
Shipment batch ID（T93B0851（M）~T93B0857 etc.）.Each silicon wafer is contained in successively imparts FOSBID by each batch
（Shipment batch ID, truck No. etc.）Trough of belt shipment container each slot in, and be transported to next shipment approval work
Sequence.FOSBID（Including slot is numbered）It is input in storage approval process management computer, then, also via computer network
It is input in main control computer.
In process is ratified in shipment, the shipment approval of shipment container is carried out, then, by multiple bale packings at 1, and Fu Yu Bales
Packet number（413573~415493）, and the ID for assigning the aggregate of shipment container freights ID（A7Y503D1 etc.）After carry out
Product turnout（With reference to figure 4）.Bales packet numbers and loading ID are input in shipment approval process management computer, then, warp
It is also input into main control computer by computer network.The manufacture information that chip is every 1（Including quality information etc.）It is to utilize
Computer network is managed collectively by main control computer, therefore can be into the maintenance of row information and effective recycling etc. of information.
As described above, the manufacturing method of the semiconductor wafer involved by according to the present embodiment, can mark according to identification
（Chip ID）It is carried out until the location information and manufacture semiconductor wafer of tracking chip group and brilliant semiconductor wafer in the block
Machining information.
Also, by the way that by these information of computer management, retrieval manufacture resume can be easier.As a result, to each silicon wafer
It can be easy to obtain intrinsic various manufacture information.As a result, when detecting defective work, can accurately and in advance carry out to
The reset and adjustment of the condition in process until the present can prevent from frequently generating defective work.
That is, various information can be obtained with 1 wafer unit, high analyte accuracy, the analysis time of silicon wafer can get
Shortening, high work accuracy.Also, the resume of single sheet information, which are traced back through, builds the location information of monocrystal silicon with mm units
Vertical association, can not only carry out the retrieval and analysis of the quality information of wafer processing procedures, additionally it is possible to carry out the product of monocrystal silicon
The retrieval and analysis of matter information.In turn, it by making each device of processing and measurement link with system control, can not only determine pair
The device that defined silicon wafer is handled, additionally it is possible to location information of the tracking in the device（For example, respectively equipped with more
The chamber information of the grinding attachment of a chuck and the chuck information of grinding device and the epitaxial apparatus equipped with multiple chambers
Deng）.In addition, being controlled by system, additionally it is possible to carry out evaluation the selecting of chip, shipment batch is constituted, is not suitable for the separation of chip.
The material information in this manufactured needed for the processing resume, quality information, processing that information refers to raw material information, crystal block and silicon wafer
Deng.
Also, it is not the management of the silicon wafer with lot-to-lot as in the past, but each wafer is carried out
The management of silicon wafer, therefore can be easy to find bad etc. in each process, it is easy to make corrections to details, thus allow for
Strict management.
Symbol description
W- semiconductor wafers, M- chamfered edges face, N- recesses, MK- identification labels.
Claims (3)
1. a kind of manufacturing method of semiconductor wafer, has：
Crystal pro cessing process obtains crystal block by semiconductor single crystalline ingot；
Slicing process cuts out the crystal block, obtains the chip group being made of more semiconductor wafers；
Chip loads process, and the semiconductor wafer for constituting the chip group is placed in defined sequence in bracket, and
The position of position of the semiconductor wafer in the bracket and the semiconductor wafer in the chip group is established and is closed
Connection；And
Process is identified, according to the semiconductor wafer putting in order in the bracket, to each of the semiconductor wafer
A imparting identification label,
Machining information comprising the semiconductor single crystalline ingot, the crystal block and the semiconductor wafer in the identification label.
2. the manufacturing method of semiconductor wafer according to claim 1, wherein
According to putting in order after the chip group cut from crystal block just cutting, the semiconductor wafer is placed in the bracket
It is interior.
3. the manufacturing method of semiconductor wafer according to claim 1, wherein
There is the evaluation of crystal process for the evaluation of crystal for carrying out the semiconductor wafer after the slicing process,
With the resistance value sequence of the semiconductor wafer determined in the evaluation of crystal process, the semiconductor wafer is carried
It is placed in the bracket.
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| CN201710103704.5A CN108511417A (en) | 2017-02-24 | 2017-02-24 | The manufacturing method of semiconductor wafer |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114161596A (en) * | 2021-12-23 | 2022-03-11 | 西安奕斯伟材料科技有限公司 | System and method for producing silicon wafer and single crystal silicon rod |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001076981A (en) * | 1999-09-03 | 2001-03-23 | Mitsubishi Materials Silicon Corp | Semiconductor wafer and its manufacture |
| JP2010283227A (en) * | 2009-06-05 | 2010-12-16 | Sumco Corp | Wafer manufacturing history tracing method |
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2017
- 2017-02-24 CN CN201710103704.5A patent/CN108511417A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001076981A (en) * | 1999-09-03 | 2001-03-23 | Mitsubishi Materials Silicon Corp | Semiconductor wafer and its manufacture |
| JP2010283227A (en) * | 2009-06-05 | 2010-12-16 | Sumco Corp | Wafer manufacturing history tracing method |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114161596A (en) * | 2021-12-23 | 2022-03-11 | 西安奕斯伟材料科技有限公司 | System and method for producing silicon wafer and single crystal silicon rod |
| CN114161596B (en) * | 2021-12-23 | 2024-04-09 | 西安奕斯伟材料科技股份有限公司 | System and method for producing silicon wafer and monocrystalline silicon rod |
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Application publication date: 20180907 |