JP5413338B2 - Epitaxial wafer for transistor - Google Patents

Description

  The present invention relates to a method for manufacturing an epitaxial wafer made of a III-V compound semiconductor and an epitaxial wafer for a transistor.

  In recent years, communication terminal devices such as mobile phones are required to transmit and receive not only voice tests and text data but also a large amount of various moving image information at high speed. For this reason, transmission / reception power amplifiers used in these terminal devices are required to support high-speed and high-frequency operation and reduce power consumption. In such a transmission / reception power amplifier for terminal equipment, a hetero bipolar transistor (HBT) or a high electron mobility transistor (HEMT) formed using a compound semiconductor is used.

  This type of HEMT, for example, a high electron mobility transistor using a group III-V compound semiconductor centering on GaAs (see Patent Document 1) is a signal processing circuit of an optical communication system, etc. from the viewpoint of ultra-high frequency operation. It is used for switching transmission / reception signals and switching between built-in antennas and external antennas in high-speed digital circuits, mobile phones, or wireless communication devices such as wireless LANs. From the viewpoint of low noise, it is also expected to be used for a low noise amplifier used in the microwave or millimeter wave band.

  As shown in FIG. 1, the basic structure of this HEMT includes a buffer layer 2 for preventing current leakage and buffering strain on a semi-insulating substrate 1, and an electron transit layer (channel layer) in which electrons travel. ) 3, an electron supply layer 4 for supplying electrons, and a Schottky layer 5 in contact with the Schottky electrode and for taking a breakdown voltage are stacked in order, and the electrode is further formed on the Schottky layer 5. In order to reduce the contact resistance with the metal, a contact layer 6 doped with a high concentration of n-type carriers is laminated.

The buffer layer 2 is formed by alternately stacking non-doped GaAs and Al _x Ga _(1-x) As (where 0 <x <1) layers in the range of several nm to several tens of nm.

The channel layer 3 is a stack of In _x Ga _(1-x) As (where 0 <x <1) layers. However, since the InGaAs layer cannot be lattice-matched with GaAs, a composition and film thickness that do not cause lattice relaxation are used.

The electron supply layer 4 is formed by laminating high-concentration n-type Al _x Ga _(1-x) As (where 0 <x <1) is several tens of nm, or a Si planar doped layer.

The Schottky layer 5 is formed by laminating non-doped or low-concentration n-type Al _x Ga _(1-x) As (where 0 <x <1) to a few tens of nm.

The contact layer 6 is an n-type GaAs layer doped with Si at a high concentration. In order to reduce the contact resistance, an n-type In _x Ga _(1-x) As (provided that 0 <x <1) layer doped with Te or Se may be used.

  In this type of compound semiconductor epitaxial wafer manufacturing method, a solid or liquid organometallic raw material is gasified and supplied, pyrolyzed and chemically reacted on a heated substrate, and a thin film crystal is formed on the heated substrate. The chemical vapor deposition method for epitaxial growth (e.g., MOCVD method), or the constituent elements of the crystal are evaporated from separate crucibles in an ultra-vacuum and supplied in the form of molecular beams onto a heated substrate. Generally, it is manufactured by a molecular beam epitaxy method (MBE method) or the like in which a thin film crystal is epitaxially grown on a heated substrate.

JP 2005-32928 A

In the transistor element, an n-type In _x Ga _(1-x) As (provided 0 <x <1) layer doped with Te or Se is used to lower the contact resistance of the contact layer. At this time, since the doping uniformity in the wafer surface is poor, the contact resistance in the wafer surface varies. In addition, even if the concentration of Se or Te that is an n-type dopant in the contact layer is controlled, the contact resistance may not be kept low.

  The objective of this invention is providing the manufacturing method of the compound semiconductor epitaxial wafer which can solve the said subject, and the epitaxial wafer for transistors.

[1] In the first invention, a plurality of heaters are provided in a growth chamber in which a substrate is placed, a source gas is supplied into the growth chamber, and a compound semiconductor layer is formed on the substrate by chemical vapor deposition. Among the compound semiconductor layers, the n-type InGaAs contact layer doped with an n-type impurity containing Te or Se has a heater temperature of the first heater provided on the upstream side to which the source gas is supplied is set to 500. Growth is performed by setting the heater temperature of other heaters provided downstream from the first heater to be lower than the heater temperature of the first heater, and adjusting the substrate temperature to 350 ° C. or more and 500 ° C. or less. The present invention provides a method for producing a compound semiconductor epitaxial wafer.

[2] A second invention is the invention according to the above [1], wherein the n-type impurity concentration of the n-type InGaAs contact layer is 1.0E19 cm ⁻³ or more and 5.0E19 cm ⁻³ or less, and wherein the growing so that the carbon concentration of 1.0E16cm ^-3 or more 3.0E18cm ^-3 or less.

[3] A third invention is the invention according to the above [1] or [2], wherein the n-type InGaAs contact layer is formed on an InGaAs graded layer whose In composition ratio increases from 0 to x. An InGaAs layer having a constant composition ratio x (0.3 ≦ x ≦ 0.6) is formed, an n-type impurity concentration in the graded layer is 3.0E18 cm ⁻³ or more and 7.0E18 cm ⁻³ or less, and carbon concentration is equal to or less than 1.0E17cm ^-3 or more 1.0E18cm ^-3.

[4] A fourth invention is the invention according to any one of the above [1] to [3], wherein the other heater is provided above the substrate when the n-type InGaAs contact layer is grown. And a third heater provided on the downstream side of the first and second heaters. The third heater has a heater temperature higher than that of the second heater.

[5] A fifth invention is the invention described in the above [4], wherein the temperature difference between the first heater and the second heater during the growth of the n-type InGaAs contact layer is the same as that of the second heater. The temperature difference is larger than that of the third heater.

[6] A sixth invention includes a substrate, a compound semiconductor layer including a transistor functional layer provided on the substrate, and an n-type contact layer provided on the semiconductor layer, wherein the n-type contact layer is And Te or Se doped as an n-type impurity, and an InGaAs layer having a constant In composition ratio x (0.3 ≦ x ≦ 0.6), and the n-type impurity concentration in the InGaAs layer is 1.0E19 cm ⁻³ or more 5.0E19cm ^-3 or less, and the carbon concentration is at 1.0E16cm ^-3 or more 3.0E18cm ^-3 or less, the in-plane variation of the n-type impurity concentration of the InGaAs contact layer is 6.0% or less There, the InGaAs layer, mobility was Hall measurement by Van der Pauw method 500cm ² / V · s or more 1500cm ² / V · s or less An epitaxial wafer for a transistor is provided.

[7] A seventh invention is the invention described in the above [6], wherein the n-type contact layer is provided on an InGaAs graded layer having an In composition ratio increasing from 0 to x, and the graded layer The n-type impurity concentration is 3.0E18 cm ⁻³ or more and 7.0E18 cm ⁻³ or less, and the carbon concentration is 1.0E17 cm ⁻³ or more and 1.0E18 cm ⁻³ or less.

[8] The eighth invention is the invention according to the above [6] or [7], wherein the compound semiconductor layer has a buffer layer of 0.8 μm or more and 1.5 μm or less on the substrate side, Te concentration or Se concentration in the buffer layer is not 2.0E15cm ^-3 or less, and is characterized in that the carbon concentration is less 1.0E16cm ^-3 or more 5.0E17cm ^-3.

  By controlling the first heater at a high temperature of 500 ° C. or more which is the upper limit of the contact growth temperature, the carbon concentration which is a p-type impurity can be reduced, and the doping concentration of the n-type contact layer becomes uniform. The variation in contact resistance within the substrate surface can be suppressed to a small level.

It is a longitudinal cross-sectional view of HEMT which is typical embodiment of this invention. It is the structure figure which looked at the reaction furnace which is typical embodiment of this invention from the side. It is a figure which shows the relationship between the heater temperature and the variation in contact resistance. It is the structure figure which looked at the conventional reactor from the side.

(Configuration of HEMT epilayer)
Even in the basic structure of a compound semiconductor epitaxial wafer for a high electron mobility transistor (HEMT) according to this embodiment, a thin film crystal is epitaxially grown on a substrate 1 as shown in FIG. This epitaxial layer (hereinafter referred to as “epi layer”) is formed on a semi-insulating substrate 1, a buffer layer 2, an electron transit layer (channel layer) 3, an electron supply layer 4, and a Schottky layer 5. The n-type contact layer 6 is sequentially laminated.

According to the illustrated example, the buffer layer 2 is configured by alternately laminating non-doped GaAs and Al _x Ga _(1-x) As (where 0 <x <1) layers. The channel layer 3 is composed of an In _x Ga _(1-x) As (where 0 <x <1) layer. The electron supply layer 4 is configured by an n-type Al _x Ga _(1-x) As (where 0 <x <1) or Si planar doped layer of 5.0E17 cm ^{−3 to} 1.0E19 cm ⁻³ . . The Schottky layer 5 is made of non-doped or 1.0E17 cm ⁻³ or less n-type Al _x Ga _(1-x) As (where 0 <x <1). The n-type contact layer 6 is composed of an n-type In _x Ga _(1-x) As (where 0 <x <1) layer doped with Te or Se.

(Configuration of MOCVD equipment)
The main configuration according to this embodiment uses a plurality of heaters divided from the source gas supply side to the exhaust side, and when the n-type contact layer 6 grows, the upstream heater which is the source gas supply side By setting the temperature to be equal to or higher than a predetermined temperature that is the upper limit of the growth temperature of the n-type contact layer 6, the in-plane variation of resistance in the n-type contact layer 6 is to be suppressed to be small.

  Referring to FIG. 2, FIG. 2 schematically shows an example of an MOCVD apparatus 10 that introduces a source gas into a growth chamber in a furnace to grow a compound semiconductor crystal. In the illustrated example, the MOCVD apparatus 10 is configured to be a rotation and revolution type in which a plurality of substrates 1 are provided face-down inside an opening of a susceptor 11 via a soaking plate (not shown).

  A disc-shaped susceptor 11 is attached to the center upper portion of the inside of the growth chamber 12 via a rotating shaft 13 that is rotatably supported by an actuator (not shown). A gas pipe 14 for introducing a source gas from a gas supply source (not shown) into the growth chamber and a gas exhaust pipe 15 for exhausting the source gas inside the growth chamber 12 to the outside are installed at the lower center of the growth chamber 12. Has been.

  Above the susceptor 11, first to third heaters 16, 17, and 18 for heating the susceptor 11 at a predetermined interval are divided and arranged from the upstream side to the source gas supply side to the downstream side. According to the illustrated example, the first and third heaters 16 and 18 are installed in a portion that does not face the substrate 1, and the one second heater 17 is placed in a portion that faces the substrate 1.

  The source gas flows through the gas pipe 14 to the central lower portion of the rotating susceptor 11 and flows radially from the central lower portion of the susceptor 11 toward both sides in the radial direction, and the first to third heaters 16, 17, 18. The epitaxial layer grows on the substrate 1 by thermal decomposition. The source gas that flows radially from the center lower portion of the susceptor 11 toward both sides in the radial direction is exhausted to the outside through the gas exhaust pipe 15.

  If the heater temperature can be increased on the upstream side where the source gas is supplied, the heater arrangement position is not limited to the illustrated example. However, when the n-type contact layer 6 is grown, the third heater 18 is connected to the second heater 18. It is preferable to set the heater temperature higher than that of the heater 17, and the temperature difference between the first heater 16 and the second heater 17 may be set larger than the temperature difference between the second heater 17 and the third heater 18. Is preferred.

(Method for producing HEMT epilayer)
Using the MOCVD apparatus 10 configured as described above, an epi layer that achieves the intended purpose can be effectively obtained.

  In this embodiment, the heater temperature of the first heater 16 that heats the region from the lower center of the susceptor 11 to the substrate 1 under the above heater temperature condition is higher than 500 ° C., which is the upper limit of the growth temperature of the n-type contact layer 6. The temperature of the substrate 1 is controlled to 350 ° C. or more and 500 ° C. while controlling the temperature of the second and third heaters 17, 18 provided downstream of the first heater 16 to be lower than that of the first heater 16. It is important to control the temperature below ℃.

  During the growth of the n-type contact layer 6 among the epi layers, the heater temperature of the first heater 16 in the growth chamber 12 in the furnace is controlled to 500 ° C. or more, and the source gas is thermally decomposed to form the epi layer. Therefore, the heater temperatures of the other second and third heaters 17 and 18 are controlled so that the substrate temperature is 350 ° C. or more and 500 ° C. or less, and the carbon concentration is controlled together with the Te or Se impurity concentration.

The n-type contact layer 6 is made of InGaAs and doped with Te or Se as an n-type impurity. n-type impurity concentration in the n-type contact layer 6 is less 1.0E19cm ^-3 or more 5.0E19cm ^-3, grown so that the carbon concentration of 1.0E16cm ^-3 or more 3.0E18cm ^-3 or less.

The n-type contact layer 6 forms an InGaAs layer having a constant In composition ratio x (0.3 ≦ x ≦ 0.6) on an InGaAs graded layer (not shown) whose In composition ratio increases from 0 to x, It is also possible to grow so that the n-type impurity concentration in the graded layer is 3.0E18 cm ⁻³ or more and 7.0E18 cm ⁻³ or less and the carbon concentration is 1.0E17 cm ⁻³ or more and 1.0E18 cm ⁻³ or less. .

  By controlling the first heater 16 to a high temperature of 500 ° C. or more, which is the upper limit of the contact growth temperature, and controlling the substrate temperature to 350 ° C. or more and 500 ° C. or less, the carbon concentration which is a p-type impurity can be reduced. Thus, the doping concentration of the n-type contact layer 6 becomes uniform, and the variation in contact resistance within the substrate surface can be suppressed to a small level.

  Hereinafter, as a more specific embodiment of the present invention, a HEMT epilayer will be described with reference to examples and comparative examples.

  In the embodiment, by using the MOCVD apparatus 10 and independently controlling the heater temperatures of the first to third heaters 16, 17, and 18, an epitaxial layer was grown on the substrate 1 and its characteristics were examined. .

  The heater temperature for heating the growth chamber 12 of the reactor shown in FIG. 2 was controlled in the range of 300 to 1200 ° C. The growth conditions of the HEMT were 650 ° C. during the growth except for the buffer layer, contact layer, and graded layer. The pressure in the growth chamber 12 was 10132 Pa (76 Torr), and hydrogen was used as the dilution gas. The rotation speed of the susceptor 11 was 10 rotations / minute, and the substrate 1 was a GaAs substrate. “I-” indicates that the epi layer is semi-insulating.

For the growth of the i-GaAs layer of the buffer layer 2, Ga (CH ₃ ) ₃ and AsH ₃ were used as raw materials. The flow rate of Ga (CH ₃ ) ₃ was 10.5 cm ³ / min. On the other hand, the flow rate of AsH ₃ was 315 cm ³ / min.

Ga (CH ₃ ) ₃ , Al (CH ₃ ) ₃ and AsH ₃ were used as raw materials for the growth of the i-Al 0.25 GaAs layer of the buffer layer 2. Their flow rates were 5.3 cm ³ / min, 1.43 cm ³ / min, and 630 cm ³ / min, respectively.

Ga (CH ₃ ) ₃ , In (CH ₃ ) ₃ and AsH ₃ were used as raw materials for the growth of the i-In 0.20 GaAs layer of the channel layer 3. These flow rates are respectively 5.3 cm ³ / min, 2.09cm ³ / min, and was 500 cm ³ / min.

The growth of the n-Al0.25GaAs layer of the electron supply layer 4 and the Schottky layer 5, _Ga was used as a raw material for the growth of _{i-Al0.25GaAs (CH 3) 3} , Al (CH 3) 3 and AsH ₃ In addition, Si ₂ H ₆ was used. The flow rate of Si ₂ H ₆ was 7.78 × 10 ⁻³ cm ³ / min. On the other hand, the flow rate other than Si ₂ H ₆ is the same as that of the i-Al0.25GaAs layer.

For the growth of the n-InGaAs layer of the contact layer 6, H ₂ Se was used in addition to Ga (CH ₃ ) ₃ and AsH ₃ used as raw materials for the growth of i-GaAs. The flow rate of H ₂ Se was 1.47 × 10 ⁻⁴ cm ³ / min.

  The flow rate of the graded layer was appropriately controlled so as to achieve the designed composition ratio. The InGaAs layer which is the n-type contact layer 6 is the same as the i-InGaAs layer except for the dopant amount.

  The first to third heaters 16 to 18 were controlled so that the substrate temperature in the growth of the n-type contact layer 6 was 350 ° C. or higher and 500 ° C. or lower. The substrate temperature in the growth of the graded layer is the same as the substrate temperature in the growth of the n-type contact layer 6.

In the growth of the buffer layer 2, the first heater 16 was controlled so that the substrate temperature during the growth of the buffer layer was 600 ° C. or higher and 700 ° C. or lower. Group V / Group III was set to 30 to 150. Regarding the Al composition x <0.3 of Al _x Ga _(1-x) As used for the buffer layer 2, the oxygen concentration was set to 2.0E16 cm ⁻³ or less.

  The buffer layer 2 was set to a temperature higher than about 580 ° C., which is the normal optimum substrate temperature for the GaAs layer. This is to prevent the incorporation of Te or Se remaining in the growth chamber 12 and to control the amount of carbon that is a p-type dopant. In other words, since the impurity dopant is more easily taken in as the substrate temperature is lower, it is necessary to set the substrate temperature higher. Carbon can be controlled by the group V gas flow rate, but at a high temperature exceeding 700 ° C., it becomes difficult to control the amount of carbon impurities naturally mixed from the organometallic raw material.

  Although the oxygen concentration functions as increasing the resistance of the buffer layer 2, if the oxygen concentration changes from lot to lot, the device characteristics may be affected. Since it is taken in naturally from the organic metal raw material, the inside of the growth chamber 12 is difficult to control. Carbon can be controlled by the group V gas flow rate, but oxygen is difficult to control, so it is lowered to the detection lower limit level of SIMS analysis. This can be dealt with by increasing the substrate temperature. As described above, problems such as variation in characteristics when formed in an element or device are solved.

As the organometallic raw material, TEI, TMI, and TEG that can be thermally decomposed even at a substrate temperature of about 350 ° C. were used. In order to increase the doping efficiency of the n-type In _x Ga _(1-x) As (where 0 <x <1) layer, which is a contact layer doped with Te or Se, 580 which is a normal optimum GaAs layer growth substrate temperature If the substrate temperature is lower than 200 ° C. over 200 ° C. and the substrate temperature is 350 ° C. or lower, the V group material does not undergo thermal decomposition, and thus cannot be applied. In addition, since a large amount of carbon impurities are generated from the organometallic raw material and mixed into the In _x Ga _(1-x) As (where 0 <x <1) layer, it is difficult to apply. On the other hand, when the substrate temperature is raised to 500 ° C. or higher, the supply amount of Te or Se material increases due to a decrease in Te or Se doping efficiency, making it difficult to use.

  By controlling the first heater 16 that heats the region from the central lower part of the susceptor 11 to the substrate 1 at a temperature higher than 500 ° C. that is the upper limit of the contact growth temperature, the carbon concentration that is a p-type impurity is reduced. The n-type contact layer 6 has a uniform doping concentration, and an epi layer with a uniform contact resistance is formed.

  Se was used for the n-type dopant according to this example, and the substrate temperature was controlled while adjusting the heater temperatures of the first to third heaters 16 to 18 while paying attention to the following points.

Se concentration of the n-type contact layer 6 is at 1.0E19cm ^-3 or more 5.0E19cm ^-3 or less, the heater temperature and the substrate temperature so that the carbon concentration of 1.0E16cm ^-3 or more 3.0E18cm ^-3 or less Control was performed within a predetermined range.

  Specifically, the n-type contact layer 6 is a uniform layer with the graded layer. An InGaAs layer having a constant In composition ratio x (0.3 ≦ x ≦ 0.6) is formed on the InGaAs graded layer whose In composition ratio increases from 0 to x.

  The heater temperature and the substrate temperature were controlled so that the n-type impurity concentration in the graded layer was 3.0E18 or higher and 7.0E18 or lower, and the carbon concentration was 1.0E17 or higher and 1.0E18 or lower.

  From the above, in order to confirm the effect, the heater temperature of the first heater 16 was changed, and the contact resistance variation in the substrate surface was examined.

  In the growth of the n-type contact layer 6, the heater temperature of the first heater 16 was changed in four ways: 500 ° C., 550 ° C., 600 ° C., and 650 ° C. At this time, the heater temperature of the second heater 17 was controlled in the range of 400 to 450 ° C., the heater temperature of the third heater 18 was controlled in the range of 450 to 500 ° C., and the substrate temperature was controlled to be in the range of 350 to 500 ° C. . The substrate temperature was measured with a radiation thermometer. Note that the first heater 16 was provided at a position not facing the substrate 1 in order to set the first heater temperature to 500 ° C. or higher and the substrate temperature to 350 to 500 ° C.

(Evaluation results of examples)
The contact resistance variation in the substrate surface in the growth chamber 12 according to this example was examined. The result is shown in FIG.

  As is apparent from FIG. 3, when the heater temperature of the first heater 16 is 500 ° C., the in-plane variation of the contact resistance is 6.0%. It can be understood that when the heater temperature is 500 ° C. and the temperature condition is suitable, and the heater temperature of the first heater 16 is raised above 500 ° C., the in-plane variation of the contact resistance is reduced and the device characteristics are further improved. It can be seen that by controlling the heater temperature of the first heater 16 to 500 ° C. or more, the contact resistance variation in the substrate surface can be suppressed to be 6.0% or less. Furthermore, if the heater temperature was 550 ° C. or higher, the variation in contact resistance within the substrate surface could be suppressed to 5.0% or less (5.0%, 4.3%, 4.1%).

  According to this embodiment, the amount of carbon auto-doped in the n-type contact layer 6 is controlled by controlling the heater temperature setting of the first to third heaters 16 to 18 and controlling the substrate temperature within a predetermined range. It is suppressed. It is considered that the in-plane variation in resistance is reduced by reducing the carbon concentration that functions as the p-type.

  According to this example, the surface roughness Ra of the n-type contact layer 6 was suppressed to 15 nm or less. This is considered to be controllable by the substrate temperature and In composition during contact layer growth.

  If the surface irregularity of the n-type contact layer 6 is high, the surface becomes cloudy. If the surface irregularities are too high, the electrode film deposited on the n-type contact layer 6 may be cracked, or the epitaxial layer below the n-type contact layer 6 may be deteriorated. In some cases, it is necessary to set an upper limit. If the surface roughness Ra of the n-type contact layer 6 is 15 nm or less, there will be no problem even in the process step, and the yield will not be lowered.

  By controlling the amount of carbon incorporated into the n-type contact layer 6, the low contact resistance can be realized without the Te or Se doping amount (raw material supply amount) being in the late 19th to the 20th power range. . In addition, when the n-type contact layer 6 is grown, it is not necessary to supply an excessive Te or Se doping raw material, so that these memory effects can be reduced.

  According to this embodiment, since the amount of carbon concentration taken in can be reduced, it is not necessary to dope excessively Te or Se, and as a result, there is a memory effect that becomes a problem when Te or Se is used. Reduction was also achieved. This eliminates the need for maintenance for each growth (each lot), and controls the heater in the temperature range of 600 ° C. to 700 ° C. to form a film thickness of 0.8 μm to 1.5 μm. As a result, problems such as a leakage current generated in the buffer layer 2 due to the memory effect can be suppressed. At this time, variation in element characteristics can be reduced by eliminating variation in oxygen concentration mixed in the buffer layer 2.

[Comparative example]
In the comparative example, the epitaxial layer was grown on the substrate in the MOCVD apparatus according to the above embodiment and the conventional reactor shown in FIG. In FIG. 4, substantially the same members as those in the MOCVD apparatus are assigned the same member names and symbols.

[Comparative Example 1]
In Comparative Example 1, the heater temperature of the first heater 16 in the MOCVD apparatus 10 is set to four types of 300 ° C., 350 ° C., 400 ° C., and 450 ° C., and the heater temperatures of the second and third heaters 17 and 18 are set. By setting the temperature within the range of 450 to 550 ° C., the substrate temperature was controlled to be 350 ° C. or higher and 500 ° C. or lower. As a result, the variation in contact resistance in the substrate surface was 7.3% even when the first heater 16 was set to 450 ° C. which is the maximum heater temperature, which was higher than that in the above example.

[Comparative Example 2]
As Comparative Example 2, when the heater temperature was set to 400 to 500 ° C. and the epitaxial layer was grown on the substrate 1 in the conventional growth chamber 12 shown in FIG. Only over 9% was obtained.

(One structural example of the HEMT epilayer in an Example)
About the epilayer for HEMT obtained by manufacturing like the said Example, the impurity was measured by SIMS analysis. As a result, the following HEMT wafer was obtained.

In a HEMT wafer having a substrate 1, a compound semiconductor layer including a transistor functional layer provided on the substrate 1, and an n-type contact layer 6 provided on the semiconductor layer,
(1) The n-type contact layer 6 is an InGaAs layer having a constant In composition ratio x (0.3 ≦ x ≦ 0.6) on an InGaAs graded layer whose In composition ratio increases from 0 to x.
(2) The n-type impurity concentration in the graded layer is 3.0E18 cm ⁻³ or more and 7.0E18 cm ⁻³ or less, the carbon concentration is 1.0E17 or more and 1.0E18 or less, and the n-type impurity concentration in the InGaAs layer is 1 .0E19cm ^-3 or more 5.0E19cm ^-3 or less, the carbon concentration is less 1.0E16cm ^-3 or more 3.0E18cm ^-3. (3) The in-plane variation of the Te or Se n-type impurity concentration of the InGaAs contact layer 6 is 6.0% or less, and the mobility of the InGaAs layer measured by the van der Pauw method is 500 cm ² / V · s or more and 1500 cm ² / V · s or less.

  In this example, it is considered that the mobility can be achieved by defining the Te or Se concentration and the carbon concentration in the n-type contact layer 6 by the manufacturing method.

When the above configuration is used for a HEMT device, the compound semiconductor layer has a buffer layer 2 of 0.8 μm or more and 1.5 μm or less on the substrate side, and the Te concentration or Se concentration of the buffer layer 2 is 2.0E15 cm ⁻³ or less. , and the carbon concentration and 1.0E16cm ^-3 or more 5.0E17cm ^-3 or less.

  When the n-type contact layer 6 is used, the memory effect can be reduced, and the occurrence of leakage current can be suppressed by managing the buffer layer 2. The gate electrode, the source electrode, and the drain electrode were formed on the HEMT device epitaxial wafer obtained from the above example, and the electrical characteristics of the device were confirmed. Even in this case, it was confirmed that the leakage current, device withstand voltage, switching characteristics, and the like had electrical characteristics equivalent to or higher than those of conventional products.

[Modification]
As is clear from the above description, the compound semiconductor epitaxial wafer of the present invention has been described based on the above embodiment and examples, but the present invention is not limited to the above embodiment and examples. The present invention can be implemented in various modes without departing from the scope of the invention. In the present invention, for example, other modifications as shown below are possible.

  HBT described in Japanese Patent Application Laid-Open No. 2006-261364, BI-FET described in Japanese Patent Application Laid-Open No. 2006-228784, and Japanese Patent Application Laid-Open No. 2009-81284 described above. Also in the growth of the contact layer of each structure of the BI-HEMT, by using the MOCVD apparatus and controlling the temperature of the first heater to 500 ° C. or higher, the contact resistance variation in the substrate surface is suppressed to 6.0% or lower. Can do.

1 Substrate 2 Buffer layer 3 Electron travel layer (channel layer)
4 Electron supply layer 5 Schottky layer 6 Contact layer 10 MOCVD apparatus 11 Susceptor 12 Growth chamber 13 Rotating shaft 14 Gas pipe 15 Gas exhaust pipe 16 First heater 17 Second heater 18 Third heater

Claims (3)

A substrate, a compound semiconductor layer including a transistor functional layer provided on the substrate, and an n-type contact layer provided on the semiconductor layer,
The n-type contact layer is made of an InGaAs layer doped with Te or Se as an n-type impurity and having a constant In composition ratio x (0.3 ≦ x ≦ 0.6), and the n-type impurity concentration in the InGaAs layer is 1.0E19cm ^-3 or more 5.0E19cm ^-3 or less, and the carbon concentration is less 1.0E16cm ^-3 or more 3.0E18cm ^-3,
The in-plane variation of the n-type impurity concentration of the InGaAs contact layer is 6.0% or less, and the mobility of the InGaAs layer measured by the van der Pauw method is 500 cm ² / V · s or more and 1500 cm ^2. / V · s or less, an epitaxial wafer for transistors. The n-type contact layer is provided on an InGaAs graded layer whose In composition ratio increases from 0 to x,
The n-type impurity concentration in the graded layer is 3.0E18 cm ⁻³ or more and 7.0E18 cm ⁻³ or less, and the carbon concentration is 1.0E17 cm ⁻³ or more and 1.0E18 cm ⁻³ or less. Item 2. An epitaxial wafer for a transistor according to Item 1 . The compound semiconductor layer has a buffer layer of 0.8 μm or more and 1.5 μm or less on the substrate side,
Te concentration or Se concentration in the buffer layer has a 2.0E15cm ^-3 or less, and, according to claim 1 or 2, wherein the carbon concentration is less 1.0E16cm ^-3 or more 5.0E17cm ^-3 Epitaxial wafer for transistors.

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