JP5396169B2 - データアクセス制御装置 - Google Patents

データアクセス制御装置 Download PDF

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Publication number
JP5396169B2
JP5396169B2 JP2009148063A JP2009148063A JP5396169B2 JP 5396169 B2 JP5396169 B2 JP 5396169B2 JP 2009148063 A JP2009148063 A JP 2009148063A JP 2009148063 A JP2009148063 A JP 2009148063A JP 5396169 B2 JP5396169 B2 JP 5396169B2
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Japan
Prior art keywords
module
data access
data
access
memory
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JP2009148063A
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English (en)
Japanese (ja)
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JP2011003160A (ja
JP2011003160A5 (https=
Inventor
成康 小林
晃 上野
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Olympus Corp
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Olympus Corp
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Application filed by Olympus Corp filed Critical Olympus Corp
Priority to JP2009148063A priority Critical patent/JP5396169B2/ja
Priority to US12/818,571 priority patent/US20100325375A1/en
Priority to CN2010102117789A priority patent/CN101930414A/zh
Publication of JP2011003160A publication Critical patent/JP2011003160A/ja
Publication of JP2011003160A5 publication Critical patent/JP2011003160A5/ja
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1626—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
JP2009148063A 2009-06-22 2009-06-22 データアクセス制御装置 Active JP5396169B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2009148063A JP5396169B2 (ja) 2009-06-22 2009-06-22 データアクセス制御装置
US12/818,571 US20100325375A1 (en) 2009-06-22 2010-06-18 Data-access control device and data-access control method
CN2010102117789A CN101930414A (zh) 2009-06-22 2010-06-22 数据存取控制装置及数据存取控制方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009148063A JP5396169B2 (ja) 2009-06-22 2009-06-22 データアクセス制御装置

Publications (3)

Publication Number Publication Date
JP2011003160A JP2011003160A (ja) 2011-01-06
JP2011003160A5 JP2011003160A5 (https=) 2012-06-28
JP5396169B2 true JP5396169B2 (ja) 2014-01-22

Family

ID=43355296

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009148063A Active JP5396169B2 (ja) 2009-06-22 2009-06-22 データアクセス制御装置

Country Status (3)

Country Link
US (1) US20100325375A1 (https=)
JP (1) JP5396169B2 (https=)
CN (1) CN101930414A (https=)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5744650B2 (ja) 2011-07-06 2015-07-08 オリンパス株式会社 バスモニタ装置、バスモニタ方法、およびプログラム
US20130097433A1 (en) * 2011-10-18 2013-04-18 Stec, Inc. Systems and methods for dynamic resource management in solid state drive system
US9134919B2 (en) * 2012-03-29 2015-09-15 Samsung Electronics Co., Ltd. Memory device including priority information and method of operating the same
JP2014035549A (ja) * 2012-08-07 2014-02-24 Ricoh Co Ltd バス制御装置、画像処理装置及びバス制御方法
JP6210742B2 (ja) 2013-06-10 2017-10-11 オリンパス株式会社 データ処理装置およびデータ転送制御装置
JP6210743B2 (ja) 2013-06-10 2017-10-11 オリンパス株式会社 データ処理装置およびデータ転送制御装置
JP6883764B2 (ja) * 2018-09-28 2021-06-09 パナソニックＩｐマネジメント株式会社 コマンド制御システム、車両、コマンド制御方法及びプログラム
DE112021001279T5 (de) 2020-02-27 2022-12-15 Micron Technology, Inc. Geräte und Verfahren für adressenbasierte Speicherleistung
US11551746B2 (en) * 2020-11-19 2023-01-10 Micron Technology, Inc. Apparatuses including memory regions having different access speeds and methods for using the same
CN114020662B (zh) * 2021-11-02 2024-07-16 上海兆芯集成电路股份有限公司 桥接模块、数据传输系统和数据传输方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA1270338A (en) * 1985-09-11 1990-06-12 Akihiko Hoshino Data processing system for processing units having different throughputs
JPH01303543A (ja) * 1988-05-31 1989-12-07 Fujitsu Ltd メモリアクセス制御装置
JPH10334037A (ja) * 1997-05-30 1998-12-18 Sanyo Electric Co Ltd 通信ｄｍａ装置
JP4234829B2 (ja) * 1998-12-03 2009-03-04 パナソニック株式会社 メモリ制御装置
JP2000251470A (ja) * 1999-03-01 2000-09-14 Hitachi Ltd 半導体集積回路
JP2002328837A (ja) * 2001-04-27 2002-11-15 Fujitsu Ltd メモリ・コントローラ
JP4820566B2 (ja) * 2005-03-25 2011-11-24 パナソニック株式会社 メモリアクセス制御回路
EP2071468A4 (en) * 2006-12-25 2010-11-03 Panasonic Corp MEMORY CONTROL DEVICE, MEMORY DEVICE AND MEMORY CONTROL METHOD
JP2008269348A (ja) * 2007-04-20 2008-11-06 Toshiba Corp メモリ制御装置およびメモリ制御方法
JPWO2009125572A1 (ja) * 2008-04-08 2011-07-28 パナソニック株式会社 メモリ制御回路及びメモリ制御方法

Also Published As

Publication number Publication date
CN101930414A (zh) 2010-12-29
US20100325375A1 (en) 2010-12-23
JP2011003160A (ja) 2011-01-06

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