JP5394461B2 - Method for manufacturing optical semiconductor element - Google Patents

Description

The present invention relates to a method of manufacturing an optical semiconductor element with a connection electrode which is suitable for flip-chip mounting.

  Background of the Invention Light emitting diodes (LEDs) have come to be widely used against the background of technological developments such as the realization of whitening and a rapid increase in luminous efficiency. Examples include general household lighting and automobile headlights.

  From the viewpoints of light emission efficiency, manufacturing efficiency, manufacturing cost, and the like, the structures of LEDs that are currently mainstream are as follows. N-type and p-type gallium nitride compound semiconductors are stacked on an insulating transparent substrate (such as a sapphire substrate). Thereafter, a part of the p-type layer is etched, so that the surfaces of the n-type layer and the p-type layer are formed with steps. Electrodes are formed on the surfaces of the n-type layer and the p-type layer, and are flip-chip mounted. The light emitted from the LED is irradiated through the insulating transparent substrate.

  For an LED, it is important for the p-pole and n-pole conduction states to be uniform in order to reduce power consumption and improve durability. Therefore, in the LED to be flip-chip mounted, the connection electrode formation technique is an important technique. Patent Document 1 discloses a technique for forming an electrode on an LED chip having a step by a vacuum deposition method and lift-off. Patent Document 2 discloses a technique for forming an electrode on an optical semiconductor element having a step using electroless plating.

Japanese Patent Laid-Open No. 9-232632 (published on September 5, 1997) JP 2004-103975 A (released on April 2, 2004) Japanese Patent Laid-Open No. 10-64953 (published March 6, 1998)

  However, Patent Documents 1 and 2 cannot eliminate the steps of the LED and the optical semiconductor element because electrodes having the same film thickness are formed. Therefore, methods such as forming a thick electrode and crushing the electrode at the time of flip chip mounting, or absorbing a step using a large solder ball with respect to the step are performed. In these methods, it is possible to absorb the above steps and perform flip chip mounting, but it is not possible to make the conduction state uniform.

  On the other hand, Patent Document 3 discloses a technique that utilizes the fact that there is a correlation between the thickness of a plating layer to be formed and the opening diameter when performing electroplating. In semiconductor substrates having different surface heights, pillars having different heights are formed by changing the opening diameter of the pillar forming portion. As a result, the step on the surface of the semiconductor substrate is canceled and flip chip mounting is performed. However, although this technique can absorb the step on the surface of the semiconductor substrate, the conductive pillar (connection electrode) is limited to absorb the step on the surface of the semiconductor substrate.

The present invention has been made in view of the above problems, its object is a first connecting electrode and the second connection electrode no step together suitable for flip-chip mounting, constraints on the dimensions of the connection electrodes It is an object of the present invention to provide a method for manufacturing an optical semiconductor element that can be formed without being subjected to the above.

In order to solve the above problems, an optical semiconductor device according to an aspect of the present invention is provided.
A first semiconductor layer made of a first conductivity type semiconductor;
A second semiconductor layer made of a semiconductor of the second conductivity type and formed on a part of the upper surface of the first semiconductor layer;
A first electrode formed on another part of the upper surface of the first semiconductor layer;
A second electrode formed on the upper surface of the second semiconductor layer and having an upper surface at a position higher than the upper surface of the first electrode;
A first connection electrode formed on the upper surface of the first electrode;
A second connection electrode formed on the upper surface of the second electrode;
An insulating protective film covering the surface of the first semiconductor layer and the surface of the second semiconductor layer, the protective film having an opening exposing a part of the surface of the first semiconductor layer; It is characterized by having.

In order to solve the above problems, a method for manufacturing an optical semiconductor element according to an aspect of the present invention is provided.
A substrate, a first semiconductor layer made of a first conductivity type semiconductor formed on the upper surface of the substrate, and a semiconductor of a second conductivity type, formed on a part of the upper surface of the first semiconductor layer The formed second semiconductor layer, the first electrode formed on the other part of the upper surface of the first semiconductor layer, and the first electrode formed on the upper surface of the second semiconductor layer. An insulating protective film covering the second electrode having an upper surface higher than the upper surface of the first electrode, the surface of the first semiconductor layer, and the surface of the second semiconductor layer, Forming a conductive current film on the entire upper surface of the optical semiconductor substrate having a protective film having an opening that exposes part of the surface of the semiconductor layer;
After forming the current film, the optical semiconductor substrate is electroplated to form a first connection electrode on the upper surface of the first electrode, and a second connection is formed on the upper surface of the second electrode. A step of forming an electrode ,
The first semiconductor layer and the current film are electrically connected through the opening, thereby forming a parallel circuit between the first electrode and the opening.
In the step of forming the first connection electrode and the second connection electrode, since the parallel circuit is formed, the plating current flowing through the first electrode is greater than the plating current flowing through the second electrode. large.

  According to the above configuration, in the optical semiconductor element according to one embodiment of the present invention, the protective film covers the surface of the first semiconductor layer and the surface of the second semiconductor layer. The protective film has an opening that exposes a part of the surface of the first semiconductor layer.

  When manufacturing the optical semiconductor element having such a configuration, the first connection electrode and the second connection electrode are formed by using electroplating. Specifically, a current film is formed on the entire upper surface of the optical semiconductor substrate, then a photoresist pattern having openings on the first and second electrodes is formed, and then a plating current is applied to the optical semiconductor element.

  Here, the first electrode and the current film are in direct conduction. Further, the first semiconductor layer that is electrically connected to the first electrode is electrically connected to the current film through the opening of the protective film. Therefore, a plating current flows from the first electrode to both the current film and the first semiconductor layer.

  On the other hand, the second electrode is in direct conduction with the current film, but the second semiconductor layer in conduction with the second electrode is not in conduction with the current film. From this, the plating current only flows to the current film from the second electrode.

  As described above, when electroplating the optical semiconductor substrate, the flowing plating current is such that the first electrode side> the second electrode side. As a result, by controlling the parameter of the plating current flowing in the optical semiconductor element, the first connection electrode and the second connection electrode having no step are absorbed by absorbing the step between the first electrode and the second electrode. Can be formed. At this time, since it is only necessary to control the parameter of the plating current, there are no restrictions on the dimensions of the first connection electrode and the second connection electrode.

  Therefore, according to the method for manufacturing an optical semiconductor element according to one aspect of the present invention, the first connection electrode and the second connection electrode, which are suitable for flip chip mounting and have no step, are restricted in the dimensions of the connection electrodes. Can be formed without receiving. In addition, according to the optical semiconductor element of one embodiment of the present invention, an optical semiconductor element including the first connection electrode and the second connection electrode that are suitable for flip chip mounting and has no step difference can be realized.

In the optical semiconductor device according to one embodiment of the present invention,
The surface area of the opening is preferably a surface area that can form the first connection electrode and the second connection electrode without any step by electroplating.

  According to said structure, when manufacturing the optical semiconductor element which concerns on 1 aspect of this invention, the 1st connection electrode and 2nd connection electrode without a level | step difference can be formed reliably.

In the optical semiconductor device according to one embodiment of the present invention,
It is preferable that a groove is formed at a position corresponding to the opening in the first semiconductor layer.

  According to the above configuration, by dividing the optical semiconductor element at the groove, the optical semiconductor element can be divided into a predetermined size without causing a defect in the first semiconductor layer.

In the optical semiconductor device according to one embodiment of the present invention,
The surface area of the groove is preferably a surface area that can form the first connection electrode and the second connection electrode without any step by electroplating.

  According to said structure, when manufacturing the optical semiconductor element which concerns on 1 aspect of this invention, the 1st connection electrode and 2nd connection electrode without a level | step difference can be formed reliably.

In the method for manufacturing an optical semiconductor element according to one aspect of the present invention,
The optical semiconductor element is preferably electroplated by passing a pulsed plating current.

  According to said structure, the ratio of the plating rate in a 1st electrode and the plating rate in a 2nd electrode can be controlled efficiently by controlling the various parameters of a plating current.

In the method for manufacturing an optical semiconductor element according to one aspect of the present invention,
The period of the pulse waveform is preferably in the range of 0.1 to 100 seconds.

  According to said structure, the ratio of the plating rate in a 1st electrode and the plating rate in a 2nd electrode can be controlled efficiently. The reason is as follows. When a plating current is applied to the optical semiconductor substrate, the transient change in plating solution resistance converges within 30 seconds. Therefore, if the pulse waveform is in the range of 0.1 to 100 seconds, the effect of varying the pulse waveform can be obtained.

In the method for manufacturing an optical semiconductor element according to one aspect of the present invention,
It is preferable that the DUTY ratio of the pulse waveform is 80% or more.

  According to said structure, the ratio of the plating rate in a 1st electrode and the plating rate in a 2nd electrode can be controlled efficiently.

In the method for manufacturing an optical semiconductor element according to one aspect of the present invention,
It is preferable that the current stop time for each cycle of the pulse waveform is 2 seconds or less.

  According to said structure, the ratio of the plating rate in a 1st electrode and the plating rate in a 2nd electrode can be controlled efficiently.

In the method for manufacturing an optical semiconductor element according to one aspect of the present invention,
The sheet resistance of the current film is preferably in the range of 10 to 1000 mΩ / □.

  According to said structure, the sheet resistance of a current film exists in the range of 10-1000 mohm / square. Here, the sheet resistance of the first semiconductor layer in the optical semiconductor substrate is in the range of 1 to 20Ω / □. Therefore, the difference between the combined resistance of the path through which the plating current flows on the first electrode side and the combined resistance of the path through which the plating current flows on the second electrode side is 10% of the combined resistance on the first electrode side. can do. As a result, the ratio between the plating rate of the first electrode and the plating rate of the second electrode can be controlled efficiently.

In the method for manufacturing an optical semiconductor element according to one aspect of the present invention,
It is preferable that the plating rate ratio between the first electrode and the second electrode in the step of forming the connection electrode is determined according to the film thickness of the current film formed in the step of forming the current film. .

  According to the above configuration, the plating rate ratio can be changed by changing the film thickness of the current film. Therefore, by setting the film thickness of the current film to an appropriate value, it is possible to form the first connection electrode and the second connection electrode having no step.

In the method for manufacturing an optical semiconductor element according to one aspect of the present invention,
It is preferable that the current density of the plating current on the surface to be plated by the plating current having the pulse waveform satisfies the range from the lower limit value to the upper limit value of the critical current density.

  According to said structure, the 1st connection electrode and 2nd connection electrode of a normal shape can be formed. Also, the plating rate ratio can be changed by changing the current density in this range. Therefore, by setting the current density to an appropriate value, it is possible to form the first connection electrode and the second connection electrode having no step.

In the method for manufacturing an optical semiconductor element according to one aspect of the present invention,
When electroplating the optical semiconductor element, it is preferable to use a metal arbitrarily selected from gold, silver, platinum, copper, palladium, nickel, solder, and alloys thereof.

  According to said structure, the optical semiconductor element provided with the 1st connection electrode with a more favorable ohmic characteristic and suitable for flip chip mounting and the 2nd connection electrode can be manufactured.

The present invention relates to a method of manufacturing an optical semiconductor element capable of forming a first connection electrode and a second connection electrode, which are suitable for flip chip mounting, without any step difference, without being restricted by the dimensions of each connection electrode. To provide .

It is sectional drawing which shows the outline of the optical semiconductor element which concerns on one Embodiment of this invention. It is sectional drawing which shows the outline of the manufacturing method of the optical semiconductor element which concerns on one Embodiment of this invention. It is a figure which shows the equivalent circuit of the plating current circuit at the time of forming bump by electroplating in the manufacturing method of the optical semiconductor element which concerns on one Embodiment of this invention. R _cf is the resistance value of the current film, R ₁ is the resistance value of the first conductive type semiconductor layer, R _op is the connection resistance between the current film and the first conductive type semiconductor layer in the opening, and R _bath is the plating solution Each resistance value is shown. It is a figure which shows the pulse period dependence of the ratio of the plating rate in n pole, and the plating rate in p pole. Open circles indicate actual measurement values. A wavy line is a curve obtained as a result of fitting an actual measurement value. A solid line indicates a plating rate ratio obtained when a direct current plating current is used. It is sectional drawing which shows the shape of the bump formed by direct current | flow electroplating. It is a figure which shows the area ratio dependence of the opening part of the plating rate ratio which concerns on one Embodiment of this invention. It is a figure which shows the current density dependence of the plating rate ratio which concerns on one Embodiment of this invention. It is a figure which shows the experimental result which measured the relationship between the sheet resistance and plating rate ratio of the current film 33 which concerns on one Embodiment of this invention. It is sectional drawing which shows the outline of the optical semiconductor element which concerns on one Embodiment of this invention. It is sectional drawing which shows the outline of the manufacturing method of the optical semiconductor element which concerns on another one Embodiment of this invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS.

Embodiment 1
(Configuration of optical semiconductor element 10)
An optical semiconductor element 10 according to an embodiment of the present invention will be described with reference to FIG.

  FIG. 1 is a schematic diagram showing a configuration of an optical semiconductor element 10 according to an embodiment of the present invention. In the optical semiconductor element 10, a first conductivity type semiconductor layer 12 is formed on the upper surface of an insulating transparent substrate 11. Further, a second conductivity type semiconductor layer 13 is formed on a part of the upper surface of the first conductivity type semiconductor layer 12. In this embodiment, a sapphire substrate 11 is used as the insulating transparent substrate 11. In the present embodiment, the first conductive semiconductor layer 12 and the second conductive semiconductor layer 13 will be described as being made of n-type and p-type gallium nitride compound semiconductors. Therefore, the first conductive semiconductor layer 12 is the n-type layer 12, and the second conductive semiconductor layer 13 is the p-type layer 13. In this embodiment, an optical semiconductor substrate in which an n-type layer and a p-type layer made of a gallium nitride compound semiconductor are formed on a sapphire substrate 11 is called a pn junction wafer.

  An insulating protective film 15 having an opening 21 in a part of the upper surface of the n-type layer 12 is provided on a part of the upper surface of the n-type layer 12 and the p-type layer 13. Further, a groove 22 is formed in a region corresponding to the opening 21 in the n-type layer 12 (see FIG. 1).

  An n-pole electrode (first electrode) 14 a and a p-pole electrode (second electrode) 14 b are provided on part of the upper surface of the n-type layer 12 and part of the upper surface of the p-type layer 13. The n-pole electrode 14a and the p-pole electrode 14b are made of the same metal and have the same thickness. Since the p-type layer 13 is formed on the upper surface of the n-type layer 12, the upper surfaces of the n-type layer 12 and the p-type layer 13 have a step. Therefore, the upper surfaces of the n-pole electrode 14a and the p-pole electrode 14b also have a step.

  A current film 33 composed of two layers is provided on the entire surface of the pn junction wafer including the upper surfaces of the n-electrode 14a and the p-electrode 14b. The current film 33 has conductivity, and functions as a conductive layer for passing a plating current when bumps are formed by electroplating. The current film 33 includes a lower layer current film 31 and an upper layer current film 32.

  Via the current film 33, an n-pole bump 52 (first connection electrode) and a p-pole bump 51 (second connection electrode) are formed on the n-pole electrode 14a and the p-pole electrode 14b by electroplating. The The n-pole bump 52 and the p-pole bump 51 are formed to have different thicknesses. The n-pole bump 52 is formed to have a thickness greater than that of the p-pole bump 51, and eliminates the level difference between the upper surfaces of the n-type layer 12 and the p-type layer 13. Therefore, the upper surfaces of the n-pole bump 52 and the p-pole bump 51 are formed at the same height.

  Since the top surfaces of the n-pole bump 52 and the p-pole bump 51 are formed at the same height, the optical semiconductor element 10 according to one embodiment of the present invention can be suitably flip-chip mounted. As will be described in detail later, the thicknesses of the n-pole bump 52 and the p-pole bump 51 can be controlled without depending on the areas of the n-pole electrode 14a and the p-pole electrode 14b. Therefore, in the optical semiconductor element 10, the step on the surface of the semiconductor substrate is absorbed without restricting the dimensions of the n-pole bump 52 and the p-pole bump 51 formed on the n-pole electrode 14a and the p-pole electrode 14b. be able to.

  In the present embodiment, an n-type layer is used as the first conductive type semiconductor layer and a p-type layer is used as the second conductive type semiconductor layer. That is, a p-type layer may be used as the first conductive semiconductor layer, and an n-type layer may be used as the second conductive semiconductor layer.

(Method for Manufacturing Optical Semiconductor Element 10)
(1) Formation of Current Film A method for producing the optical semiconductor element 10 will be described with reference to FIG. The optical semiconductor element 10 is manufactured using the pn junction wafer in which an n-type layer and a p-type layer made of a gallium nitride compound semiconductor are formed on a sapphire substrate 11. The p-type layer 13 of the pn junction wafer is selectively etched to expose the n-type layer 12. In this step, a known technique similar to the conventional technique may be used. In addition, although the some optical semiconductor element 10 is formed on the said pn junction wafer, in FIG. 2, one of the some optical semiconductor elements 10 is shown in figure.

  On the exposed upper surface of the n-type layer 12 and the upper surface of the p-type layer 13 left unetched, an n-electrode 14a and a p-electrode 14b having a laminated structure made of nickel and gold are formed. By using a laminated structure made of nickel and gold as the n-pole electrode 14a and the p-pole electrode 14b, the contact interface between the n-type layer 12 and the n-pole electrode 14a, and the p-type layer 13 and the p-pole electrode 14b Good ohmic characteristics can be obtained at the contact interface. Techniques such as a sputtering method and a vacuum deposition method can be used to form a laminated structure composed of Ni (nickel) and Au (gold). For the patterning in the process such as electrode formation, for example, a photolithography method can be used.

After the n-electrode 14a and the p-electrode 14b are formed, SiO ₂ (silicon oxide) to be the insulating protective film 15 is formed on the upper surfaces of the n-type layer 12 and the p-type layer 13. After forming the protective film 15, the protective film 15 is removed from a part of the n-pole electrode 14 a and the p-pole electrode 14 b and the opening 21. Further, only the n-type layer 12 is selectively etched to form a groove 22 in a region corresponding to the opening 21. This state is shown in FIG.

  The shape of the opening 21 and the groove 22 is such that, when the optical semiconductor element 10 is viewed from above, the opening 21 surrounds the optical semiconductor element 10 and separates the individual optical semiconductor elements 10. Is more preferable.

  After the protective film 15 having the opening 21 and the groove 22 are formed, a current film 33 for flowing a plating current is formed. As shown in FIG. 2B, the current film 33 includes a lower layer current film 31 and an upper layer current film 32. For example, TiW is suitable as the material constituting the lower layer current film 31. By providing TiW as the lower layer current film 31, diffusion of atoms between the n-type layer 12 and the upper layer current film 32 can be suppressed. Similarly, diffusion of atoms between the n-pole electrode 14a and the p-pole electrode 14b and the upper layer current film 32 can be suppressed. TiW can be deposited by sputtering, for example.

  As the material constituting the upper layer current film 32, the same metal as the plating metal for forming the bump is used. By using the same metal as the plating metal for forming the bumps on the upper layer current film 32, the adhesion between the n-electrode 14a and the p-electrode 14b and the bumps through the current film is increased, and the durability of the optical semiconductor element 10 is increased. The nature is also increased. In the present embodiment, since Au is used as a material constituting the bump, Au is also used as a material constituting the upper layer current film 32. The upper layer current film 32 can be deposited by, for example, a sputtering method.

  When the current film 33 is formed, the current film 33 and the n-type layer 12 are not in direct contact with each other in the region where the protective film 15, the n-electrode 14a and the p-electrode 14b are formed (see FIG. 2B). ). On the other hand, by providing the opening 21, the current film 33 is also formed inside the opening 21 and the groove 22. By forming the current film 33 up to the inside of the opening 21 and the groove 22, the current film 33 and the n-type layer 12 are in direct contact with each other and become electrically conductive. As will be described in detail later, bumps having different thicknesses are formed on the n-electrode 14a and the p-electrode 14b by electroplating because the current film 33 and the n-type layer 12 are electrically connected in the opening 21. It becomes possible.

  On the element on which the current film 33 is formed, a photoresist 41 is applied by, eg, spin coating (see FIG. 2C). Thereafter, bump formation patterns 42 that are openings of the photoresist 41 are formed at positions corresponding to the n-pole electrode 14a and the p-pole electrode 14b by using a photolithography method (see FIG. 2D).

(2) Bump formation by electroplating After forming the bump formation pattern 42, the n-pole bump 52 and the p-pole bump 51 are formed by electroplating. In manufacturing the optical semiconductor element 10, a pn junction wafer is used. The current film 33 formed on the upper surface of the pn junction wafer is formed not only in the region where the optical semiconductor element 10 is manufactured, but also on the outer peripheral portion of the pn junction wafer. By connecting the cathode 30 of the external power source to the current film 33 on the outer periphery of the pn junction wafer, the current film 33 serves as one electrode in electroplating.

  By connecting an anode 80 of an external power source to an anode plate 81 made of the same material as the metal to be plated or an appropriate material, the other electrode in electroplating is obtained. In the present embodiment, a Pt (platinum) plate is used as the anode plate 81.

  The pn junction wafer to which the cathode 30 is connected and the anode plate 81 to which the anode 80 is connected are immersed in a plating solution, and a plating current is supplied from an external power source. In this embodiment, a gold plating solution is used to form bumps made of gold. Physical conditions such as the temperature of the plating solution and the concentration of metal ions contained in the plating solution are controlled so as not to fluctuate during electroplating.

  The plating rate of the film formed by electroplating depends on the current value (more precisely, current density) of the plating current flowing in the area to be plated. Here, the magnitude relationship between the current values flowing through the n-pole electrode 14a and the p-pole electrode 14b will be described.

  The current path from the cathode 30 to the opening 21 is common to the n-pole electrode 14a and the p-pole electrode 14b. Therefore, the value of the current flowing through the n-pole electrode 14a and the p-pole electrode 14b depends on the current path from the opening 21 to the n-pole electrode 14a and the current path from the opening 21 to the p-pole electrode 14b.

  When considering a current path formed between the opening 21 and the n-pole electrode 14 a, the current film 33 and the n-type layer 12 are electrically connected via the opening 21 and the groove 22. In addition, the upper surface of the n-type layer 12 and the n-electrode 14a are electrically connected. Therefore, the current circuit between the cathode 30 and the n-electrode 14a is a parallel circuit composed of the current film 33 and the n-type layer 12 (see FIG. 3).

  On the other hand, the p-type layer 13 exists between the p-electrode 14b and the n-type layer 12 (see FIG. 1). A pn junction layer is formed at the contact interface between the n-type layer 12 and the p-type layer 13. The potential difference generated between the n-electrode 14a and the p-electrode 14b during electroplating is sufficiently small as compared with the barrier height of the pn junction layer. Therefore, the n-type layer 12 and the p-electrode 14b are not electrically connected via the p-type layer 13. Therefore, the current path formed between the opening 21 and the p-electrode 14b is a series circuit including only the current film 33 (see FIG. 3).

  When comparing the magnitude relationship between the resistance value of the series circuit composed only of the current film 33 and the resistance value of the parallel circuit composed of the current film 33 and the n-type layer 12, the parallel circuit composed of the current film 33 and the n-type layer 12 is compared. The resistance value of becomes smaller. Therefore, the resistance value from the opening 21 to the n-pole electrode 14a is smaller than the resistance value from the opening 21 to the p-pole electrode 14b. Therefore, the resistance value between the cathode 30 and the n-electrode 14a is smaller than the resistance value between the cathode 30 and the p-electrode 14b.

  Since the resistance value and the current value are in an inversely proportional relationship, a larger plating current flows between the n-electrode 14a and the plating solution than between the p-electrode 14b and the plating solution. As a result, an n-pole bump 52 thicker than the p-pole bump 51 is formed on the n-pole electrode 14a (see FIG. 2E).

  The thicknesses of the p-pole bump 51 and the n-pole bump 52 are formed so as to eliminate a step caused by the p-type layer 13 being formed on the upper surface of the n-type layer 12. As a result, the upper surfaces of the p-pole bump 51 and the n-pole bump 52 are formed at the same height. A method for controlling the thicknesses of the n-pole bump 51 and the p-pole bump 52 will be described later.

  In the present embodiment, Au is used as the material for the n-pole bump 52 and the p-pole bump 51. However, as materials other than Au, Ag (silver), Pt (platinum), Cu (copper), Pd (palladium), Ni (nickel), solder, and alloys made of these are used for the n-pole bump 52 and the p-pole bump 51. Any material can be used. More preferably, the material constituting the n-pole bump 52 and the p-pole bump 51 and the material constituting the upper layer current film 32 are the same. Therefore, Ag, Pt, Cu, Pd, Ni, solder, and an alloy made thereof can be used as the material of the upper layer current film 32.

  By using Au, Ag, Pt, Cu, Pd, Ni, solder, and an alloy made of these as materials of the n-pole bump 52 and the p-pole bump 51, it is good when the optical semiconductor element 10 is flip-chip mounted. Can be obtained.

  After forming the n-pole bump 52 and the p-pole bump 51, the photoresist 41 is removed using an organic solvent (see FIG. 2F). As a result, a p-pole bump 51 is formed on the p-pole electrode 14b via the current film 33, and an n-pole bump 52 is formed on the n-pole electrode 14a via the current film 33.

  Thereafter, the current film 33 is removed from the element in the state of FIG. 2F, whereby the optical semiconductor element 10 is completed as shown in FIG. In order to remove the current film 33, the element in the state of FIG. 2 (f) may be immersed in an etchant capable of etching the metal constituting the lower layer current film 31 and the upper layer current film 32.

  Finally, the optical semiconductor element 10 is cut out from the pn junction wafer by dividing the pn junction wafer. Since the optical semiconductor element 10 includes the groove 22, the n-type layer 12 can be divided without generating defects when the pn junction wafer is divided into a predetermined size.

  By the above manufacturing method, the optical semiconductor element 10 suitable for flip chip mounting in which the upper surfaces of the p-pole bump 51 and the n-pole bump 52 are formed at the same height can be provided. The thicknesses of the p-pole bump 51 and the n-pole bump 52 are controlled by the current value of the plating current flowing through the p-pole electrode 14b and the n-pole electrode 14a. Therefore, in the method for manufacturing an optical semiconductor device according to the embodiment of the present invention, the dimensions of the p-pole bump 51 and the n-pole bump 52 are not limited.

(Bump thickness control method)
A method for controlling the thicknesses of the p-pole bump 51 and the n-pole bump 52 will be described with reference to FIGS.

(1) Plating current circuit In the production of the optical semiconductor element 10, a pn junction wafer is used. The pn junction wafer to which the cathode 30 is connected and the anode plate 81 to which the anode 80 is connected are immersed in a plating solution, and electroplating is performed by flowing a plating current from an external power source. An equivalent circuit of the plating current circuit at this time is shown in FIG.

  The current film 33 and the cathode 30 provided on the pn junction wafer are actually connected at one place. However, since the current film 33 is provided in the entire region of the pn junction wafer, when focusing on one set of the n-pole electrode 14a and the p-pole electrode 14b, the n-pole electrode 14a, the p-pole electrode 14b, and the cathode There are an infinite number of current paths to 30. In the present embodiment, FIG. 3 is shown in a form corresponding to the cross-sectional view shown in FIG. In the element in the state of FIG. 2D, a plating current flows from the n-pole electrode 14a and the p-pole electrode 14b to the left and right ends of the current film 33. To show this, two cathodes 30 are drawn outside the opening 21 in FIG.

  The anode 80 and the anode plate 81 are also actually connected at one place. However, in order to make it correspond to the cathode 30, the anode 80 is also shown so as to exist at both ends of the anode plate 81 (see FIG. 3).

  The cathode 30 is connected to the current film 33 at the outer periphery of the pn junction wafer. A pattern is arranged on the pn junction wafer so that a plurality of optical semiconductor elements 10 can be produced. Therefore, a plurality of openings 21 and grooves 22 are provided in the pn junction wafer, and the current film 33 and the n-type layer 12 are electrically connected to each other in the openings 21 and the grooves 22. Therefore, the current path from the cathode 30 to the opening 21 is composed of the current film 33 and the n-type layer 12. However, in order to simplify the explanation, the current path from the cathode 30 to the opening 21 is omitted, and it is shown in FIG. 3 that there is no resistance component. Note that the groove 22 is not shown in FIG. 3 for the sake of simplicity.

The n-electrode 14a and the p-electrode 14b and the anode plate 81 are electrically connected via a plating solution. In FIG. 3, the resistance value of the plating solution is R _bath .

The two openings 21 shown in FIG. 3 correspond to the two openings 21 in FIG. In FIG. 2D, a current film 33 is provided between the two openings 21 and the groove 22, and an n-pole electrode 14 a and a p-pole electrode 14 b exist in the middle of the current film 33. That is, the two openings 21 and the groove 22, the n-pole electrode 14a and the p-pole electrode 14b are electrically connected through the current film 33, respectively. In FIG. 3, 14 a and 14 b indicate the n-pole electrode 14 a and the p-pole electrode 14 b, and R _cf represents the resistance value of the current film 33.

The plating current flows through the current film 33 and also flows into the n-type layer 12 through the opening 21 and the groove 22. A connection resistance R _op exists at the interface where the current film 33 and the n-type layer 12 are in contact with each other in the opening 21. As the surface area of the opening 21 and the groove 22 increases, the contact area between the current film 33 and the n-type layer 12 increases and R _op decreases. In FIG. 3, R ₁ is the resistance value of the n-type layer 12. When the plating current flows through the current film 33 and the n-type layer 12, a parallel circuit is formed between the n-pole electrode 14a and the opening 21 (see FIG. 3). On the other hand, the p-electrode 14b and the opening 21 are electrically connected only through the current film 33.

A parallel circuit composed of R _cf , R ₁ and R _op is formed between the n-pole electrode 14 a and the opening 21, and a series composed of only R _cf is formed between the p-pole electrode 14 b and the opening 21. A circuit is formed. Therefore, the resistance value between the n-pole electrode 14 a and the opening 21 is smaller than the resistance value between the p-pole electrode 14 b and the opening 21.

  A plating current larger than that of the p-electrode 14b flows through the n-electrode 14a. As a result, the plating rate of the n-electrode 14a is higher than the plating rate of the p-electrode 14b. As a result, the n-pole bump 52 is thicker than the p-pole bump 51. In the present embodiment, the ratio of the plating rate at the n-electrode 14a and the plating rate at the p-electrode 14b is referred to as the plating rate ratio.

(2) Control of the plating rate ratio By making a difference between the resistance value between the n-electrode 14a and the opening 21 and the resistance value between the p-electrode 14b and the opening 21, the n-electrode 14a The plating current flowing through the p-electrode 14b is differentiated. In this way, the n-pole electrode 14a and the p-pole electrode 14b are controlled by controlling the resistance value between the n-pole electrode 14a and the opening 21 and the resistance value between the p-pole electrode 14b and the opening 21. The plating rate can be controlled. The difference in resistance value between the n-pole electrode 14a and the opening 21 and the resistance value between the p-pole electrode 14b and the opening 21 is the resistance value between the n-pole electrode 14a and the opening 21. More preferably, it is about 10%. As a result, the ratio between the plating rate at the n-electrode 14a and the plating rate at the p-electrode 14b can be controlled efficiently.

  The sheet resistance of the n-type layer 12 in the pn junction wafer used for manufacturing the optical semiconductor element 10 is 1 to 20Ω / □. Therefore, the sheet resistance of the current film 33 is preferably in the range of 10 mΩ / □ to 1000 mΩ / □, and more preferably 50 mΩ / □ to 200 mΩ / □. The sheet resistance of the current film 33 depends on the film thickness of the current film 33. When the film thickness is increased, the sheet resistance is decreased, and when the film thickness is decreased, the sheet resistance is increased.

  Thus, the sheet resistance of the current film 33 can be controlled using the film thickness of the current film 33 as a parameter. By setting the sheet resistance of the current film 33 within the above range, the difference between the resistance value between the n-pole electrode 14a and the opening 21 and the resistance value between the p-pole electrode 14b and the opening 21 is determined. Can be set to about 10%.

  When the sheet resistance of the current film 33 is small, most of the plating current flows through the current film 33. Therefore, the difference between the plating currents flowing through the n-pole electrode 14a and the p-pole electrode 14b is reduced, and the plating rate ratio is close to 1. When the sheet resistance of the current film 33 is large, the plating current flowing through the n-type layer 12 increases, and the difference between the plating currents flowing through the n-electrode 14a and the p-electrode 14b increases. Therefore, the plating rate ratio is a value larger than 1. Thus, by changing the film thickness of the current film 33, the plating rate ratio can be changed. Therefore, by setting the film thickness of the current film 33 to an appropriate value, it is possible to form the p-pole bump 51 and the n-pole bump 52 having no step.

As another method of making a difference between the resistance value between the n-pole electrode 14a and the opening 21 and the resistance value between the p-pole electrode 14b and the opening 21, the connection of the current film 33 and the n-type layer 12 is performed. The resistance R _op may be changed. Even when R _cf and R ₁ are the same, if R _op is large, the resistance value between the n-pole electrode 14a and the opening 21 becomes large. Conversely, if R _op is small, the resistance value between the n-electrode 14a and the opening 21 is also small. On the other hand, even if R _op is changed, the resistance value between the p-electrode 14b and the opening 21 does not change. Since R _op depends on the surface area of the opening 21 and the groove 22, the resistance value between the n-pole electrode 14 a and the opening 21 and the p-pole electrode 14 b and the opening 21 are changed by changing the surface area. The ratio of the resistance values between the two can be changed. In other words, the plating rate ratio can be controlled by designing the pattern size of the opening 21 to an arbitrary size (see FIG. 6). The area ratio of the opening in FIG. 6 is a ratio of the surface area of the opening 21 to the area of the region where the n-type layer 12 is formed.

  As described above, the surface area of the opening 21 is preferably a surface area that can form the p-pole bump 51 and the n-pole bump 52 without any step by electroplating. According to this configuration, when the optical semiconductor element 1 is manufactured, the p-pole bump 51 and the n-pole bump 52 having no step can be reliably formed.

  Moreover, it is preferable that the surface area of the groove | channel 22 is a surface area which can form the p pole bump 51 and the n pole bump 52 without a level | step difference mutually by electroplating. According to this configuration, when the optical semiconductor element 1 is manufactured, the p-pole bump 51 and the n-pole bump 52 having no step can be reliably formed.

  As described above, the plating rate ratio in the n-pole bump 52 and the p-pole bump 51 can be changed by controlling the plating current flowing through the n-pole electrode 14a and the p-pole electrode 14b. However, in order to eliminate the level difference between the n-type layer 12 and the p-type layer 13 and make the upper surfaces of the n-pole bump 52 and the p-pole bump 51 have the same height, more precise control of the plating rate ratio is required. .

  In order to control the plating rate ratio more precisely, in the method of manufacturing an optical semiconductor element according to one embodiment of the present application, the driving waveform of the plating current is a pulse waveform. The plating rate ratio can be controlled by changing the pulse period of the pulse waveform.

A step on the upper surfaces of the n-electrode 14a and the p-electrode 14b is D, and a desired height of the p-electrode bump 51 is H. The ratio of the plating rate in the n-electrode 14a to the plating rate in the p-electrode 14b is R. At this time, the plating rate ratio R necessary for forming the upper surfaces of the p-pole bump 51 and the n-pole bump 52 at the same height is expressed by the following equation.
R = (H + D) / H
The dependence of the plating rate ratio on the pulse period may be measured in advance as shown in FIG. Using the pulse period dependency of the plating rate ratio measured in advance, the pulse period of the plating current corresponding to R required for bump formation of the optical semiconductor element 10 is selected. By performing bump formation using the selected pulse period, the optical semiconductor element 10 in which the upper surfaces of the p-pole bump 51 and the n-pole bump 52 are formed at the same height can be obtained.

  By making the driving waveform of the plating current into a pulse waveform, in addition to enabling precise control of the plating rate ratio, it is possible to prevent the formed bumps from being in an abnormal plating state called burn plating. FIG. 5 shows the p-pole bump 51 and the n-pole bump 152. The p-pole bump 51 is a normally formed bump, and the n-pole bump 152 is an example of a bump that is in a state called burn plating. Burn plating is an anomaly that is likely to occur in plating formed by passing a large plating current for a long time. In the method for manufacturing an optical semiconductor device according to this embodiment, a larger current flows through the n-pole electrode 14a than the p-pole electrode 14b. In the state where a large plating current flows through the n-electrode 14a, if the drive waveform is a DC waveform, the formed bumps may be burnt plated. This possibility can be eliminated by making the driving waveform of the plating current into a pulse waveform.

(3) Pulse Cycle In the method for manufacturing an optical semiconductor device according to one embodiment of the present invention, the plating current drive waveform is a pulse waveform, and the pulse cycle is more preferably in the range of 0.1 to 100 seconds. . As can be seen from the dependence of the plating rate ratio on the pulse period shown in FIG. 4, the plating rate ratio shows a great dependence on the pulse period when the pulse period is in the range of 0.1 to 100 seconds. Therefore, a desired plating rate ratio can be obtained by setting the plating current pulse period within the range of 0.1 to 100 seconds.

  Immediately after application of the plating current, an electric double layer is formed on the surfaces of the n-electrode 14a and the p-electrode 14b. Immediately after application of the plating current, the electric double layer is in a transient state in which the plating current (non-Faraday current) is charged, and after about 30 seconds, the current value of the plating current converges to a constant value. By utilizing the transient state of the plating state, the plating rate ratio is controlled in the method of manufacturing an optical semiconductor device according to the embodiment of the present invention. By making the plating current into a pulse waveform, the transient state of the plating current can be used repeatedly. Therefore, the plating rate ratio can be reliably controlled.

(4) DUTY ratio In the method for manufacturing an optical semiconductor device according to one embodiment of the present invention, the DUTY ratio in the pulse period is 80% or more, or the plating current stop time in the pulse period is 2 seconds or less preferable. In manufacturing an optical semiconductor element, it is preferable that the time required for bump formation by electroplating (referred to as plating time) is short from the viewpoint of throughput. From the viewpoint of shortening the plating time, electroplating using a DC waveform (DC plating) is preferable, but the plating rate ratio cannot be controlled. Furthermore, there is a possibility that burn plating occurs due to the constant flow of the plating current. In addition to being able to control the plating rate ratio by setting the DUTY ratio in the pulse waveform to 80% or more by using a plating current of a pulse waveform for electroplating, an increase in plating time is achieved in the case of DC plating. On the other hand, it can be suppressed within 20%. In order to increase the throughput, it is desirable to increase the DUTY ratio. However, by setting the value to a value close to 100%, there is a higher possibility that burn plating will occur. The upper limit value of the DUTY ratio is a value smaller than 100%, and is a value that can eliminate the possibility of burnt plating.

  In addition, by setting the plating current stop time in one cycle of the pulse waveform to 2 seconds or less, it is possible to control the plating rate ratio and minimize the decrease in throughput and prevent the formation of burnt plating. it can. The lower limit value of the plating current stop time is a value greater than 0 seconds, and is a value that can eliminate the possibility of burnt plating.

(5) Plating current density In the method for manufacturing an optical semiconductor device according to one embodiment of the present invention, the plating rate ratio is changed by varying the current density of the plating current having a pulse waveform. In other words, the current density of the plating current can be used as a parameter for controlling the plating rate ratio.

  The range of current density at which good plating can be generated varies depending on the type of plating solution used for electroplating and the plating bath conditions typified by the pH, temperature, and presence / absence of stirring of the plating solution. However, when the plating rate ratio is controlled by changing the current density, the current density may be in a range satisfying the range from the lower limit value to the upper limit value of the critical current density. In other words, the current density range may be within the range from the lower limit value to the upper limit value of the critical current density.

  The critical current density means an upper limit and a lower limit of a current density that generates a normal film when a film is generated by electroplating. When the current density at the time of electroplating is less than the critical current density, bright plating occurs. On the other hand, burn plating (discoloration of the surface, uneven color) occurs. Neither is desirable, and it is necessary to avoid them.

  When the current density at the time of electroplating is larger than the lower limit value of the critical electric density, plating can be normally generated on the n-electrode 14a and the p-electrode 14b that are the surfaces to be plated. Further, since the current density is smaller than the upper limit value of the critical current density, it is possible to prevent generation of an abnormal plating state called burn plating. As a result, the p-shaped bump 51 and the n-polar bump 52 having a normal shape can be formed. Further, by setting the current density to an appropriate value in the range from the lower limit value to the upper limit value of the critical current density, the p-pole bump 51 and the n-pole bump 52 having no step can be formed.

[Example 1]
FIG. 4 shows the measurement result of the pulse period dependency of the plating rate ratio in the method for manufacturing the optical semiconductor element 10 according to the embodiment of the present invention. The manufacturing method of the optical semiconductor element 10 is based on the manufacturing method shown in FIG. After the steps from FIGS. 2A to 2D, bump formation by electroplating was performed (see FIG. 2E). When forming the bump, the pulse frequency of the plating current, which is a pulse waveform, is changed in the range from 0.1 second to 1000 seconds, and the ratio of the thickness of the n-pole bump 52 to the thickness of the p-pole bump 51 is determined as the plating rate. The ratio is shown in FIG.

  In FIG. 4, the measured values are indicated by white circles. A wavy line is a curve obtained as a result of fitting an actual measurement value. The plating rate ratio obtained by direct current plating is shown by a solid line.

  As is apparent from the results of FIG. 4, the plating rate ratio varies greatly from about 1.00 to about 1.25 when the pulse period of the plating current is in the range of 0.1 to 100 seconds. Accordingly, an appropriate plating rate ratio can be obtained by selecting the pulse period of the plating current from the range of 0.1 to 100 seconds.

  In order to determine the pulse period of the plating current, first, the required plating rate ratio is determined from the step between the n-electrode 14a and the p-electrode 14b and the thickness of the p-electrode bump 51 to be formed. Thereafter, the pulse period corresponding to the required plating rate ratio may be read from FIG.

[Example 2]
FIG. 6 shows an experimental result of measuring the relationship between the area ratio of the opening 21 and the plating rate ratio in the method for manufacturing the semiconductor element 10 according to the embodiment of the present invention. The plating conditions in this example are as follows.
・ Plating solution: EEJA non-cyan type gold plating solution ・ Plating bath temperature: 52 ° C
・ Plating current density: DC 6 mA / cm ²
・ Plating object: Wafer for optical semiconductor device creation (6 inches)
Under the above conditions, electroplating was performed using a wafer without an opening 21 (opening ratio 0%) and a wafer with the opening 21 formed (opening ratio 6%). As a result, as shown in FIG. 6, when the area ratio of the opening 21 is 0% (opening ratio 0%), the plating rate ratio is about 1.00, and the area ratio of the opening 21 is 6% (opening). In the case of the ratio of 6%), the result that the plating rate ratio was about 1.30 was obtained. Thus, it became clear that the plating rate ratio can be controlled by changing the area ratio of the opening 21.

Example 3
FIG. 7 shows the results of measuring the current density dependence of the plating rate ratio in the method for manufacturing the optical semiconductor element 10 according to the embodiment of the present invention. The plating conditions in this example are as follows.
・ Plating solution: EEJA non-cyan type gold plating solution ・ Plating bath temperature: 52 ° C
・ Pulse period: 1 second ・ DUTY ratio: 80%
・ Plating object: Wafer for optical semiconductor device creation (6 inches)
Plating current: range of the critical current density of 3.5mA / cm ² in the range of 11 mA / cm ² in the variable the plating condition is 8 mA / cm ² from 2 mA / cm ^2. Electroplating was performed by changing the current density of the plating current in the range of 3.5 mA / cm ² to 11 mA / cm ² . The reason why electroplating was performed even under conditions exceeding the range of the critical current density is to confirm the influence of the current density on the formed bump. As a result of the experiment, the obtained plating rate ratio changed in the range of about 1.45 to 1.10, and there was a clear negative correlation between the plating rate ratio and the current density (FIG. 7). It has also been clarified that a desired plating rate ratio can be obtained by changing the current density of the plating current within the range of the critical current density.

Example 4
FIG. 8 shows the experimental results of measuring the relationship between the sheet resistance of the current film 33 and the plating rate ratio in the method for manufacturing the semiconductor element 10 according to the embodiment of the present invention. The plating conditions in this example are as follows.
・ Plating solution: EEJA non-cyanide type gold plating solution ・ Plating bath temperature: 50 ℃
・ Plating current density: DC 6 mA / cm ²
・ Plating object: Wafer for optical semiconductor device creation (6 inches)
Under the above conditions, the value of the sheet resistance of the current film 33 was changed variously, and the plating rate ratio was measured. When changing the value of the sheet resistance, the film thickness of the current film 33 was changed. As a result of the experiment, when the sheet resistance was 10 mΩ / □ or more, the higher the sheet resistance, the higher the plating rate ratio. That is, a positive correlation was found between the sheet resistance and the plating rate ratio. Thus, it has become clear that the plating rate ratio can be controlled by changing the sheet resistance of the current film 33. When the sheet resistance was 200 mΩ / □ or more, burnt plating occurred at the n pole.

[Embodiment 2]
An optical semiconductor device 60 according to an embodiment of the present invention will be described with reference to FIGS. In addition, the same member number is attached | subjected about the member similar to Embodiment 1, and the description is abbreviate | omitted.

(Optical semiconductor element 60)
The optical semiconductor element 60 is a modification of the optical semiconductor element 10 according to the first embodiment. The difference between the optical semiconductor element 10 and the optical semiconductor element 60 is the shape of the n-type layer 62 (first conductivity type semiconductor layer) included in the optical semiconductor element 60 and the n-type layer 12 included in the optical semiconductor element 10. (See FIG. 9). The n-type layer 62 included in the optical semiconductor element 60 does not have a special structure in a region corresponding to the opening 21 included in the protective film 15. That is, in the region corresponding to the opening 21, the upper surface of the n-type layer 62 is a plane.

  The configuration other than the shape of the n-type layer is common to the optical semiconductor element 10 and the optical semiconductor element 60.

  The n-pole bump 52 is formed to have a thickness greater than that of the p-pole bump 51, and eliminates the level difference between the upper surfaces of the n-type layer 12 and the p-type layer 13. Since the upper surfaces of the n-pole bump 52 and the p-pole bump 51 are formed at the same height, the optical semiconductor device 60 according to one embodiment of the present invention can be suitably flip-chip mounted.

(Method for Manufacturing Optical Semiconductor Element 60)
A method for manufacturing the optical semiconductor element 60 will be described with reference to FIGS. Regarding the manufacturing method, the optical semiconductor element 60 and the optical semiconductor element 10 are the same.

  From the pn junction wafer in which the n-type layer 62 and the p-type layer 13 are deposited on the sapphire substrate 11, the n-type layer 62 is selectively etched leaving a part of the p-type layer 13. An n-pole electrode 14a and a p-pole electrode 14b are formed on the upper surfaces of the n-type layer 62 and the p-type layer 13, and a protective film 15 having an opening 21 is formed on a part of the upper surface of the n-type layer 62 (FIG. 10 ( a)). At this time, the n-type layer 62 is not provided with a groove, and the upper surface of the n-type layer 62 is a flat surface.

  Next, a lower layer current film 31 and an upper layer current film 32 are sequentially formed to form a current film 33 (FIG. 10B).

  After forming the current film 33, the following steps are sequentially performed. Photoresist 41 is applied (see FIG. 10C). A bump formation pattern 42 is formed by photolithography (FIG. 10D). A p-pole bump 51 and an n-pole bump 52 are formed by electroplating using a drive current having a pulse waveform (see FIG. 10E). The photoresist 41 is removed using an organic solvent (see FIG. 10F). Unnecessary portions of the current film 33 are removed by etching (see FIG. 10G). The optical semiconductor element 60 is completed through the above steps.

  When the current film 33 is formed, the current film 33 and the n-type layer 62 are brought into contact with each other through the opening 21 even if the upper surface of the n-type layer 62 is flat. Therefore, the current path from the opening 21 to the n-pole electrode 14 a is a parallel circuit composed of the current film 33 and the n-type layer 62. On the other hand, the current path from the opening 21 to the p-electrode 14b is only the current film 33.

  Therefore, the resistance value from the opening 21 to the n-pole electrode 14a is smaller than the resistance value from the opening 21 to the p-pole electrode 14b. Since a plating current larger than that of the p-electrode 14b flows through the n-electrode 14a, the plating rate at the n-electrode 14a is higher than the plating rate at the p-electrode 14b.

  By using the pulse waveform as the driving waveform for electroplating and changing the pulse period, the plating rate ratio between the plating rate at the n-electrode 14a and the plating rate at the p-electrode 14b can be controlled. Therefore, the optical semiconductor element 60 can absorb the level difference on the surface of the semiconductor substrate without restricting the dimensions of the n-pole bump 52 and the p-pole bump 51, and is an optical semiconductor element suitable for flip-chip mounting.

  The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope shown in the claims, and embodiments obtained by appropriately combining technical means disclosed in different embodiments. Is also included in the technical scope of the present invention.

  The present invention can be widely used as an optical semiconductor element such as a light emitting diode (LED). Moreover, it can utilize also as a method of manufacturing such an optical semiconductor element.

10 Optical semiconductor element 11 Sapphire substrate (insulating transparent substrate)
12 n-type layer (first conductivity type semiconductor layer)
13 p-type layer (second conductivity type semiconductor layer)
14a n-pole electrode (first electrode)
14b p-electrode (second electrode)
15 Protective film 21 Opening 22 Groove 30 Cathode 31 Lower layer current film 32 Upper layer current film 33 Current film 41 Photo resist 42 Bump formation pattern 51 P pole bump (second connection electrode)
52 n-pole bump (first connection electrode)
60 optical semiconductor element 62 n-type layer (first conductivity type semiconductor layer)
80 Anode 81 Anode plate 152 n-pole bump

Claims (9)

A substrate, a first semiconductor layer made of a first conductivity type semiconductor formed on the upper surface of the substrate, and a semiconductor of a second conductivity type, formed on a part of the upper surface of the first semiconductor layer The formed second semiconductor layer, the first electrode formed on the other part of the upper surface of the first semiconductor layer, and the first electrode formed on the upper surface of the second semiconductor layer. An insulating protective film covering the second electrode having an upper surface higher than the upper surface of the first electrode, the surface of the first semiconductor layer, and the surface of the second semiconductor layer, Forming a conductive current film on the entire upper surface of the optical semiconductor substrate having a protective film having an opening that exposes part of the surface of the semiconductor layer;
After forming the current film, the optical semiconductor substrate is electroplated to form a first connection electrode on the upper surface of the first electrode, and a second connection is formed on the upper surface of the second electrode. A step of forming an electrode ,
The first semiconductor layer and the current film are electrically connected through the opening, thereby forming a parallel circuit between the first electrode and the opening.
In the step of forming the first connection electrode and the second connection electrode, since the parallel circuit is formed, the plating current flowing through the first electrode is greater than the plating current flowing through the second electrode. A manufacturing method of an optical semiconductor element characterized by being large . 2. The method of manufacturing an optical semiconductor element according to claim 1 , wherein the optical semiconductor element is electroplated by passing a plating current having a pulse waveform. 3. The method of manufacturing an optical semiconductor element according to claim 2 , wherein a period of the pulse waveform is in a range of 0.1 to 100 seconds. 3. The method of manufacturing an optical semiconductor element according to claim 2 , wherein a DUTY ratio of the pulse waveform is 80% or more. 3. The method of manufacturing an optical semiconductor element according to claim 2 , wherein a stop time of the current for each cycle of the pulse waveform is 2 seconds or less. The sheet resistance of the said current film exists in the range of 10-1000 mohm / square, The manufacturing method of the optical semiconductor element of Claim 2 characterized by the above-mentioned. 3. The optical semiconductor element according to claim 2 , wherein a current density of the plating current on the surface plated by the plating current having the pulse waveform is in a range satisfying a range from a lower limit value to an upper limit value of the critical current density. Manufacturing method. The plating rate ratio between the first electrode and the second electrode in the step of forming the connection electrode is determined according to the film thickness of the current film formed in the step of forming the current film. method for manufacturing an optical semiconductor device according to claim 1, wherein. When electroplating the optical semiconductor element, gold, silver, platinum, copper, palladium, nickel, solder, and light according to claim 1, characterized in that a metal that is arbitrarily selected from these alloys A method for manufacturing a semiconductor device.

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