KR20130007411A - Optical semiconductor device and manufacturing method of optical semiconductor device - Google Patents

Optical semiconductor device and manufacturing method of optical semiconductor device Download PDF

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KR20130007411A
KR20130007411A KR1020120031893A KR20120031893A KR20130007411A KR 20130007411 A KR20130007411 A KR 20130007411A KR 1020120031893 A KR1020120031893 A KR 1020120031893A KR 20120031893 A KR20120031893 A KR 20120031893A KR 20130007411 A KR20130007411 A KR 20130007411A
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electrode
current
optical semiconductor
pole
plating
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KR1020120031893A
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Korean (ko)
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KR101254460B1 (en
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게이이치 사와이
후지오 아고
유지 와타나베
가츠지 가와카미
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샤프 가부시키가이샤
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body

Abstract

PURPOSE: An optical semiconductor device and a manufacturing method thereof are provided to form first and second connection electrodes which do not have a step between the connection electrodes. CONSTITUTION: An optical semiconductor device(10) comprises first and second semiconductor layers(12,13), first and second electrodes(14a,14b), first and second connection electrodes(52,51), and a protective film. The second semiconductor layer is formed on a portion of the top surface of the first semiconductor layer. The first electrode is formed on the other portion of the top surface of the first semiconductor layer. The second electrode is formed on the top surface of the second semiconductor layer. The first connection electrode is formed on the top surface of the first electrode. The second connection electrode is formed on the top surface of the second electrode. The protective film covers the surfaces of the first and second semiconductor layers and has an opening(21) for exposing a portion of the surface of the first semiconductor layer. [Reference numerals] (10) Optical semiconductor device; (11) Sapphire substrate; (12) n-type layer; (13) p-type layer; (14a) n-electrode; (14b) p-electrode; (15) Protective film; (21) Opening; (22) Groove; (31) Lower layer current film; (32) Upper layer current film; (33) Current film; (51) p-bump; (52) n-bump

Description

Optical semiconductor device and manufacturing method of optical semiconductor device {OPTICAL SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF OPTICAL SEMICONDUCTOR DEVICE}

TECHNICAL FIELD This invention relates to the optical semiconductor element which has a connection electrode suitable for flip chip mounting, and the manufacturing method of the said optical semiconductor element.

BACKGROUND OF THE INVENTION Light emitting diodes (LEDs) have come to be widely used in the background of technical developments such as the realization of whitening and the rapid rise in luminous efficiency. Examples include general household lighting and automotive headlights.

The LED, which is currently mainstream in terms of luminous efficiency, manufacturing efficiency and manufacturing cost, has the following structure. N-type and p-type gallium nitride compound semiconductors are laminated on an insulating transparent substrate (such as a sapphire substrate). Thereafter, a portion of the p-type layer is etched to form the surfaces of the n-type layer and the p-type layer in a stepped state. Electrodes are formed on the surfaces of the n-type layer and the p-type layer and flip chip mounted. Light emitted from the LED is irradiated through the insulating transparent substrate.

In the LED, it is important for the p and n poles to have a uniform conduction state in order to reduce power consumption and to improve durability. Therefore, the technique of forming a connection electrode is an important technique in the LED which flip-chip mounts. Patent Literature 1 discloses a technique of forming an electrode on an LED chip having a step by vacuum deposition and liftoff. Patent Literature 2 discloses a technique of forming an electrode on an optical semiconductor element having a step using electroless plating.

Japanese Unexamined Patent Publication No. 9-232632 (published September 5, 1997) Japanese Unexamined Patent Publication "Japanese Patent Publication No. 2004-103975 (published April 2, 2004)" Japanese Unexamined Patent Publication No. 10-64953 (published March 6, 1998)

However, Patent Documents 1 and 2 cannot form a step that the LED and the optical semiconductor element have because the electrodes having the same film thickness are formed. Therefore, a method of forming an electrode having a thick film thickness and pressing the electrode during flip chip mounting, or absorbing the step using a large solder ball with respect to the step, has been performed. In these methods, it is possible to absorb the step and flip chip mount, but the conduction state cannot be made uniform.

On the other hand, Patent Literature 3 discloses a technique that uses a correlation between the thickness of the plating layer to be formed and the opening diameter when performing electroplating. In a semiconductor substrate having a different surface height, a filler having a different height is formed by changing the opening diameter of the pillar forming portion. This offsets the step on the semiconductor substrate surface and performs flip chip mounting. However, in this technique, although the step on the surface of the semiconductor substrate can be absorbed, the conductive filler (connection electrode) is constrained because the step is absorbed on the semiconductor substrate surface.

This invention is made | formed in view of the said subject, Comprising: It aims at providing the optical semiconductor element provided with the 1st connection electrode and the 2nd connection electrode which do not have a mutual difference suitable for flip chip mounting. In addition, another object of the present invention is to provide a method for manufacturing an optical semiconductor element capable of forming the first connection electrode and the second connection electrode without any step suitable for flip chip mounting without being limited by the dimensions of each connection electrode. It is to offer.

In order for the optical semiconductor element which concerns on one aspect of this invention to solve the said subject,

A first semiconductor layer comprising a first conductive semiconductor,

A second semiconductor layer made of a second conductivity type semiconductor and formed on a part of an upper surface of the first semiconductor layer,

A first electrode formed on the other part of the upper surface of the first semiconductor layer,

A second electrode formed on an upper surface of the second semiconductor layer and having an upper surface located at a position higher than an upper surface of the first electrode;

A first connection electrode formed on an upper surface of the first electrode,

A second connection electrode formed on an upper surface of the second electrode,

An insulating protective film covering the surface of the first semiconductor layer and the surface of the second semiconductor layer, the protective film having an opening for exposing a part of the surface of the first semiconductor layer.

MEANS TO SOLVE THE PROBLEM In the manufacturing method of the optical semiconductor element which concerns on one aspect of this invention, in order to solve the said subject,

A first semiconductor layer comprising a substrate, a first conductive semiconductor formed on an upper surface of the substrate, a second semiconductor layer formed of a second conductive semiconductor, and formed on a portion of an upper surface of the first semiconductor layer; A first electrode formed on another part of the upper surface of the first semiconductor layer, a second electrode formed on the upper surface of the second semiconductor layer and having an upper surface located at a position higher than the upper surface of the first electrode; An insulating protective film covering the surface of the first semiconductor layer and the surface of the second semiconductor layer, the entire surface of the upper surface of the optical semiconductor substrate having a protective film having an opening for exposing a part of the surface of the first semiconductor layer; In the step of forming a conductive current film,

After forming the current film, electroplating the optical semiconductor substrate, thereby forming a first connection electrode on the upper surface of the first electrode, and forming a second connection electrode on the upper surface of the second electrode. It is characterized by having.

According to the said structure, in the optical semiconductor element which concerns on one aspect of this invention, the protective film has covered the surface of a 1st semiconductor layer and the surface of a 2nd semiconductor layer. The protective film has an opening that exposes a part of the surface of the first semiconductor layer.

When manufacturing the optical semiconductor element of the said structure, a 1st connection electrode and a 2nd connection electrode are formed by using electroplating. Specifically, a current film is formed on the entire surface of the upper surface of the optical semiconductor substrate, and then a photoresist pattern opening on the first and second electrodes is formed, and then a plating current is applied to the optical semiconductor element.

Here, the first electrode and the current film are in direct conduction. Moreover, the 1st semiconductor layer which is connected with the 1st electrode is conducting with the current film through the opening part of a protective film. As a result, the plating current flows to both the current film and the first semiconductor layer from the first electrode.

On the other hand, although the second electrode is in direct conduction with the current film, the second semiconductor layer in conducting with the second electrode is not in conduction with the current film. As a result, the plating current only flows from the second electrode to the current film.

As described above, when electroplating the optical semiconductor substrate, the flowing plating current becomes the first electrode side> the second electrode side. As a result, by controlling the parameters of the plating current flowing through the optical semiconductor element, it is possible to form the first connection electrode and the second connection electrode which have no step difference, which absorb the step difference between the first electrode and the second electrode. In that case, since only the parameter of a plating current needs to be controlled, there is no restriction | limiting at all in the dimension of a 1st connection electrode and a 2nd connection electrode.

Therefore, according to the manufacturing method of the optical semiconductor element which concerns on one aspect of this invention, the 1st connection electrode and the 2nd connection electrode which do not have a mutual difference suitable for flip chip mounting can be formed without restrict | limiting in the dimension of each connection electrode. Can be. Moreover, according to the optical semiconductor element which concerns on one aspect of this invention, the optical semiconductor element provided with the 1st connection electrode and the 2nd connection electrode which have no step difference mutually suitable for flip chip mounting can be implement | achieved.

Other objects, features and advantages of the present invention will be fully understood by the description below. Further advantages of the present invention will become apparent from the following description with reference to the accompanying drawings.

This invention provides the manufacturing method of the optical semiconductor element which can form the 1st connection electrode and the 2nd connection electrode which have no step difference suitable for flip chip mounting, without being restrict | limited by the dimension of each connection electrode. Moreover, according to the optical semiconductor element which concerns on one aspect of this invention, the optical semiconductor element provided with the 1st connection electrode and the 2nd connection electrode which have no step difference mutually suitable for flip chip mounting can be implement | achieved.

BRIEF DESCRIPTION OF THE DRAWINGS It is sectional drawing which shows the outline of the optical semiconductor element which concerns on one Embodiment of this invention.
2 is a cross-sectional view showing an outline of a method for manufacturing an optical semiconductor element according to one embodiment of the present invention.
FIG. 3 is a diagram showing an equivalent circuit of a plating current circuit when forming a bump by electroplating in the method for manufacturing an optical semiconductor element according to one embodiment of the present invention. R cf is the resistance of the current film, R 1 is the resistance of the first conductivity-type semiconductor layer, R op is the connection resistance of the current film and the first conductivity-type semiconductor layer in the opening, and R bath is the resistance of the plating solution. .
4 is a diagram showing the pulse period dependency of the ratio of the plating rate in the n pole and the plating rate in the p pole. White circles show measured values. The broken line is a curve obtained as a result of fitting the measured value. The solid line represents the plating rate ratio obtained when a direct current plating current is used.
5 is a cross-sectional view showing the shape of a bump formed by direct current electroplating.
It is a figure which shows the area ratio dependency of the opening part of the plating rate ratio which concerns on one Embodiment of this invention.
It is a figure which shows the current density dependence of the plating rate ratio which concerns on one Embodiment of this invention.
FIG. 8 is a diagram showing experimental results obtained by measuring the relationship between the sheet resistance and the plating rate ratio of the current film 33 according to the embodiment of the present invention.
9 is a cross-sectional view illustrating an outline of an optical semiconductor element according to one embodiment of the present invention.
It is sectional drawing which shows the outline of the manufacturing method of the optical semiconductor element which concerns on another embodiment of this invention.

EMBODIMENT OF THE INVENTION Hereinafter, one Embodiment of this invention is described in detail with reference to FIGS.

[Embodiment 1]

(Configuration of Optical Semiconductor Element 10)

The optical semiconductor element 10 which concerns on one Embodiment of this invention is demonstrated, referring FIG.

1, the schematic which showed the structure of the optical semiconductor element 10 which concerns on one Embodiment of this invention is shown. In the optical semiconductor element 10, the first conductive semiconductor layer 12 is formed on the upper surface of the insulating transparent substrate 11. In addition, the second conductive semiconductor layer 13 is formed on a part of the upper surface of the first conductive semiconductor layer 12. In this embodiment, the sapphire substrate 11 is used as the insulating transparent substrate 11. In the present embodiment, the first conductive semiconductor layer 12 and the second conductive semiconductor layer 13 will be described as being composed of n-type and p-type gallium nitride compound semiconductors. Therefore, the first conductivity type semiconductor layer 12 is the n type layer 12, and the second conductivity type semiconductor layer 13 is the p type layer 13. In this embodiment, the optical semiconductor substrate which formed the n type layer and p type layer which consist of a gallium nitride system compound semiconductor on the sapphire substrate 11 is called a p-n junction wafer.

The insulating protective film 15 provided with the opening part 21 is formed in one part of the upper surface of the n type layer 12 and the p type layer 13 in the upper surface of the n type layer 12. Moreover, the groove | channel 22 is formed in the area | region corresponding to the opening part 21 in the n-type layer 12 (refer FIG. 1).

On the part of the upper surface of the n-type layer 12 and the part of the upper surface of the p-type layer 13, n-pole electrodes (first electrodes) 14a and p-pole electrodes (second electrodes) 14b are formed. . The n-pole electrode 14a and the p-pole electrode 14b are made of the same metal and have the same thickness. Since the p-type layer 13 is formed in the upper surface of the n-type layer 12, the upper surface of the n-type layer 12 and the p-type layer 13 has a level difference. Therefore, the upper surfaces of the n-pole electrode 14a and the p-pole electrode 14b also have steps.

In the process of manufacturing the optical semiconductor element 10, the current film 33 composed of two layers is formed on the entire surface of the pn bonded wafer including the upper surfaces of the n-pole electrode 14a and the p-pole electrode 14b. It is formed (refer to FIG. 2 (b)-(f)). The current film 33 has electroconductivity and acts as a conductive layer for flowing a plating current when forming bumps by electroplating. The current film 33 consists of the lower current film 31 and the upper current film 32.

Plating current flows through the current film 33 to the n-pole electrode 14a and the p-pole electrode 14b, and on the n-pole electrode 14a and the p-pole electrode 14b, the n-pole bump 52 (first Connection electrode) and p-pole bump 51 (second connection electrode) are formed by electroplating. The n-pole bumps 52 and the p-pole bumps 51 are formed with different thicknesses, respectively. The thickness of the n-pole bumps 52 is formed thicker than the thickness of the p-pole bumps 51, thereby eliminating the step that the upper surfaces of the n-type layer 12 and the p-type layer 13 have. Thus, the upper surfaces of the n-pole bumps 52 and the p-pole bumps 51 are formed at the same height.

Since the upper surfaces of the n-pole bumps 52 and the p-pole bumps 51 are formed at the same height, the optical semiconductor element 10 according to the embodiment of the present invention can be preferably flip chip mounted. Although mentioned later in detail, the thickness of the n-pole bump 52 and the p-pole bump 51 can be controlled, regardless of the area of the n-pole electrode 14a and the p-pole electrode 14b. Therefore, in the optical semiconductor element 10, the dimensions of the n-pole bump 52 and the p-pole bump 51 formed on the n-pole electrode 14a and the p-pole electrode 14b are not restricted, and the semiconductor substrate It can absorb the step on the surface.

In addition, in this embodiment, although an n type layer is used as a 1st conductivity type semiconductor layer, and a p type layer is used as a 2nd conductivity type semiconductor layer, you may make it the opposite structure. In other words, the p-type layer may be used as the first conductivity-type semiconductor layer, and the n-type layer may be used as the second conductivity-type semiconductor layer.

(Manufacturing method of the optical semiconductor element 10)

(1) Formation of Current Film

The manufacturing method of the optical semiconductor element 10 is demonstrated, referring FIG. The p-n bonded wafer in which the n-type layer and p-type layer which consist of a gallium nitride system compound semiconductor on the sapphire substrate 11 was formed on the manufacture of the optical semiconductor element 10 is used. The p-type layer 13 of the p-n bonded wafer is selectively etched to expose the n-type layer 12. In this step, the same known technique as in the prior art may be used. In addition, although the some optical semiconductor element 10 is formed on the said p-n junction wafer, one of these some optical semiconductor elements 10 is shown in FIG.

On the upper surface of the exposed n-type layer 12 and the upper surface of the p-type layer 13 left unetched, n-pole electrodes 14a and p-pole electrodes 14b having a laminated structure made of nickel and gold are formed. As the n-pole electrode 14a and the p-pole electrode 14b, by using a laminated structure made of nickel and gold, the contact interface between the n-type layer 12 and the n-pole electrode 14a and the p-type layer 13 and Good ohmic characteristics can be obtained at the contact interface of the p-pole electrode 14b. What is necessary is just to use techniques, such as a sputtering method and a vacuum evaporation method, in formation of the laminated structure which consists of Ni (nickel) and Au (gold). For example, a photolithography method may be used for patterning in a step such as electrode formation.

After the n-pole electrode 14a and the p-pole electrode 14b are formed, SiO 2 (silicon oxide) serving as the insulating protective film 15 is placed on the upper surfaces of the n-type layer 12 and the p-type layer 13. Form. After the protective film 15 is formed, the protective film 15 is removed from a part of the n-pole electrode 14a and the p-pole electrode 14b and the opening 21. Further, only the n-type layer 12 is selectively etched to form the grooves 22 in the regions corresponding to the openings 21. This state is shown to Fig.2 (a).

The shape of the openings 21 and the grooves 22 is such that when the optical semiconductor element 10 is viewed from above, the openings 21 and the grooves 22 surround the optical semiconductor element 10, and the individual optical semiconductors are separated. It is more preferable that it is formed in the shape which isolate | separates the element 10.

After forming the protective film 15 and the groove | channel 22 provided with the opening part 21, the current film 33 for flowing a plating current is formed. As shown in FIG. 2B, the current film 33 is composed of a lower current film 31 and an upper current film 32. As a material which comprises the lower layer current film 31, TiW is preferable, for example. By forming TiW as the lower current film 31, the diffusion of atoms between the n-type layer 12 and the upper current film 32 can be suppressed. Similarly, the diffusion of atoms between the n-pole electrode 14a and the p-pole electrode 14b and the upper current film 32 can be suppressed. TiW may be deposited by, for example, a sputtering method.

The material which comprises the upper current film 32 uses the same metal as the plating metal which forms bump. By using the same metal as the plating metal which forms bump in the upper current film 32, adhesiveness of bump with n-pole electrode 14a and p-pole electrode 14b through a current film becomes high, and the optical semiconductor element 10 The durability is also high. In this embodiment, since Au is used as a material which comprises a bump, Au is used also for the material which comprises the upper current film 32. FIG. The upper current film 32 may be deposited by, for example, a sputtering method.

When the current film 33 is formed, in the region where the protective film 15, the n-pole electrode 14a and the p-pole electrode 14b are formed, the current film 33 and the n-type layer 12 are directly No contact (see FIG. 2B). On the other hand, since the opening part 21 is formed, the current film 33 is also formed inside the opening part 21 and the groove | channel 22. As shown in FIG. Since the current film 33 is formed inside the opening 21 and the groove 22, the current film 33 and the n-type layer 12 are in direct contact with each other to be in electrical conduction. Although mentioned later in detail, since the current film 33 and the n-type layer 12 are conducting in the opening part 21, it is carried out on the n pole electrode 14a and the p pole electrode 14b by electroplating. It is possible to form bumps with different thicknesses.

On the element on which the current film 33 is formed, the photoresist 41 is applied by, for example, a spin coating method (see FIG. 2C). Then, the bump formation pattern 42 which is an opening part of the photoresist 41 is formed in the position corresponding to the n-pole electrode 14a and the p-pole electrode 14b using the photolithographic method (FIG. 2). (d)).

(2) bump formation by electroplating

After the bump formation pattern 42 is formed, the n-pole bumps 52 and the p-pole bumps 51 are formed by electroplating. In the manufacture of the optical semiconductor element 10, a p-n bonded wafer is used. The current film 33 formed on the upper surface of the p-n bonded wafer is formed not only in the region where the optical semiconductor element 10 is produced, but also on the outer peripheral portion of the p-n bonded wafer. By connecting the cathode 30 of the external power supply to the current film 33 of the outer peripheral portion of the p-n bonded wafer, the current film 33 is used as one electrode in electroplating.

The positive electrode 80 of the external power supply is connected to the positive electrode plate 81 made of the same material or a suitable material as the metal to be plated, so as to be the other electrode in electroplating. In this embodiment, the plate of Pt (platinum) is used as the positive electrode plate 81.

The p-n bonded wafer to which the negative electrode 30 is connected and the positive electrode plate 81 to which the positive electrode 80 are connected are immersed in a plating solution, and a plating current flows from an external power supply. In this embodiment, a gold plating solution is used to form bumps made of gold. Physical conditions such as the temperature of the plating liquid and the metal ion concentration contained in the plating liquid are managed so as not to vary during electroplating.

The plating rate of the film formed by electroplating depends on the current value (more precisely the current density) of the plating current flowing in the region to be plated. Here, the magnitude relationship between the current values flowing through the n-pole electrode 14a and the p-pole electrode 14b will be described.

The current path from the cathode 30 to the opening 21 is common to the n-pole electrode 14a and the p-pole electrode 14b. Therefore, the current value flowing through the n-pole electrode 14a and the p-pole electrode 14b includes a current path from the opening 21 to the n-pole electrode 14a and a current from the opening 21 to the p-pole electrode 14b. Depends on the path

In the current path formed between the opening 21 and the n-pole electrode 14a, the current film 33 and the n-type layer 12 are conductive through the opening 21 and the groove 22. Further, the upper surface of the n-type layer 12 and the n-pole electrode 14a are also conductive. Therefore, the current circuit between the cathode 30 and the n-pole electrode 14a is a parallel circuit composed of the current film 33 and the n-type layer 12 (see FIG. 3).

On the other hand, the p-type layer 13 exists between the p-pole electrode 14b and the n-type layer 12 (refer FIG. 1). The p-n junction layer is formed in the contact interface of the n-type layer 12 and the p-type layer 13. The potential difference generated between the n-pole electrode 14a and the p-pole electrode 14b at the time of electroplating is sufficiently small compared with the barrier height of the said p-n junction layer. Therefore, the n-type layer 12 and the p-pole electrode 14b do not conduct through the p-type layer 13. Therefore, the current path formed between the opening 21 and the p-pole electrode 14b becomes a series circuit by only the current film 33 (see FIG. 3).

When comparing the magnitude relationship between the resistance value of the series circuit by only the current film 33 and the resistance value of the parallel circuit composed of the current film 33 and the n-type layer 12, the current film 33 and the n-type layer ( The resistance value of the parallel circuit which consists of 12) becomes small. Therefore, the resistance value from the opening part 21 to the n pole electrode 14a becomes smaller than the resistance value from the opening part 21 to the p pole electrode 14b. Therefore, the resistance value between the cathode 30 and the n-pole electrode 14a becomes smaller than the resistance value between the cathode 30 and the p-pole electrode 14b.

Since the resistance value and the current value are inversely related, a plating current larger than the p-pole electrode 14b and the plating liquid flows between the n-pole electrode 14a and the plating liquid. As a result, on the n-pole electrode 14a, an n-pole bump 52 thicker than the p-pole bump 51 is formed (see FIG. 2E).

The thicknesses of the p-pole bumps 51 and the n-pole bumps 52 are formed so as to eliminate the step resulting from the formation of the p-type layer 13 on the upper surface of the n-type layer 12. As a result, the upper surfaces of the p-pole bumps 51 and the n-pole bumps 52 are formed at the same height. The control method of the thickness of the p-pole bump 51 and the n-pole bump 52 is mentioned later.

In the present embodiment, Au was used as a material for the n-pole bumps 52 and the p-pole bumps 51. However, as materials other than Au, Ag (silver), Pt (platinum), Cu (copper), Pd (palladium), Ni (nickel), solder and alloys thereof are made of n-pole bumps 52 and p-pole bumps ( It can also be used arbitrarily as a material of 51). As for the material which comprises the n-pole bump 52 and the p-pole bump 51, and the material which comprises the upper current film 32, it is more preferable that it is the same. Therefore, Ag, Pt, Cu, Pd, Ni, solder, and alloys thereof can be used as the material of the upper current film 32.

When the optical semiconductor element 10 is flip-chip mounted by using Au, Ag, Pt, Cu, Pd, Ni, solder, and alloys thereof, as the material of the n-pole bump 52 and the p-pole bump 51. , Good ohmic characteristics can be obtained.

After the n-pole bumps 52 and the p-pole bumps 51 are formed, the photoresist 41 is removed using an organic solvent (see FIG. 2 (f)). As a result, the p-pole bump 51 is formed on the p-pole electrode 14b through the current film 33, and the n-pole bump 52 is formed on the n-pole electrode 14a through the current film 33. .

Subsequently, the optical semiconductor element 10 shown in FIG. 2G is completed by removing the current film 33 from the element in the state of FIG. 2F. In order to remove the current film 33, the element which is in the state of FIG.2 (f) may be immersed in the etching liquid which can etch the metal which comprises the lower current film 31 and the upper current film 32. FIG.

Finally, by dividing the p-n bonded wafer, the individual optical semiconductor elements 10 are cut out from the p-n bonded wafer. Since the optical semiconductor element 10 is provided with the groove | channel 22, when dividing the said p-n junction wafer by predetermined size, it becomes possible to divide | segment without creating a defect in the n-type layer 12. FIG.

By the above manufacturing method, the optical semiconductor element 10 suitable for flip chip mounting can be provided in which the upper surfaces of the p-pole bumps 51 and the n-pole bumps 52 are formed at the same height. The thicknesses of the p-pole bumps 51 and the n-pole bumps 52 are controlled by the current values of the plating current flowing through the p-pole electrodes 14b and the n-pole electrodes 14a. Therefore, in the manufacturing method of the optical semiconductor element which concerns on one Embodiment of this invention, the dimension of p-pole bump 51 and n-pole bump 52 is not restrict | limited.

(Thickness control method of bump)

A method of controlling the thicknesses of the p-pole bumps 51 and the n-pole bumps 52 will be described with reference to FIGS. 1 to 7.

(1) plating current circuit

In the manufacture of the optical semiconductor element 10, a p-n bonded wafer is used. The p-n junction wafer to which the negative electrode 30 is connected and the positive electrode plate 81 to which the positive electrode 80 are connected are immersed in a plating solution, and electroplating by flowing a plating current from an external power supply. The equivalent circuit of the plating current circuit at this time is shown in FIG.

The current film 33 and the cathode 30 formed on the p-n bonded wafer are actually connected at one point. However, since the current film 33 is formed in the whole area | region of the said pn bonded wafer, when paying attention to one set of n-pole electrode 14a and p-pole electrode 14b, n-pole electrode 14a and p The current path between the pole electrode 14b and the cathode 30 exists innumerably. In this embodiment, in order to simplify description, FIG. 3 was shown by the form corresponding to sectional drawing shown in FIG. In the device in the state of FIG. 2D, the plating current flows from the n-pole electrode 14a and the p-pole electrode 14b to the left and right ends of the current film 33. In order to show this, in FIG. 3, two cathodes 30 are drawn outside the opening 21.

The anode 80 and the anode plate 81 are also actually connected at one point. However, in order to make it correspond with the cathode 30, the anode 80 is also shown to exist at both ends of the anode plate 81 (see FIG. 3).

The cathode 30 is connected to the current film 33 in the outer peripheral portion of the p-n bonded wafer. The pattern is arrange | positioned on the said p-n bonded wafer so that the some optical semiconductor element 10 can be manufactured. Therefore, a plurality of openings 21 and grooves 22 are formed in the pn bonded wafer, and the current film 33 and the n-type layer 12 are conductive in each of the openings 21 and the grooves 22. Doing. Thus, the current path from the cathode 30 to the opening 21 consists of the current film 33 and the n-type layer 12. However, in order to simplify description, the electric current path from the cathode 30 to the opening part 21 is abbreviate | omitted and is shown in FIG. 3 as there is no resistance component. In addition, the groove 22 is not shown in FIG. 3 for the sake of simplicity.

The n pole electrode 14a, the p pole electrode 14b, and the positive electrode plate 81 are electrically conductive through the plating liquid. In Fig. 3, the resistance of the plating liquid is R bath .

The two opening parts 21 shown in FIG. 3 correspond to the two opening parts 21 in FIG. In FIG. 2D, a current film 33 is formed between the two openings 21 and the grooves 22, and the n-pole electrode 14a and the p-pole electrode 14b in the middle of the current film 33. ) Exists. In other words, the two opening portions 21, the grooves 22, the n-pole electrodes 14a, and the p-pole electrodes 14b are electrically connected via the current film 33, respectively. 14a and 14b in FIG. 3 represent the n-pole electrode 14a and the p-pole electrode 14b, and R cf represents the resistance value of the current film 33.

The plating current flows through the current film 33 and also flows into the n-type layer 12 through the openings 21 and the grooves 22. Connection resistance Rop exists in the interface which the current film 33 and the n type layer 12 contact in the opening part 21. Since the contact area of the current film 33 and the n-type layer 12 increases as the surface area of the openings 21 and the grooves 22 increases, the R op decreases. In FIG. 3, R 1 is the resistance of the n-type layer 12. As the plating current flows through the current film 33 and the n-type layer 12, a parallel circuit is formed between the n-pole electrode 14a and the opening 21 (see FIG. 3). On the other hand, the p-pole electrode 14b and the opening part 21 are electrically conductive through only the current film 33.

A parallel circuit composed of R cf and R 1 and R op is formed between the n-pole electrode 14a and the opening 21, and a series circuit consisting of only R cf is formed between the p-pole electrode 14b and the opening 21. do. Therefore, the resistance between the n-pole electrode 14a and the opening 21 is smaller than the resistance between the p-pole electrode 14b and the opening 21.

Plating current larger than the p-pole electrode 14b flows to the n-pole electrode 14a, and as a result, the plating rate in the n-pole electrode 14a becomes higher than the plating rate in the p-pole electrode 14b. . As a result, the thickness of the n-pole bumps 52 becomes thicker than the thickness of the p-pole bumps 51. In this embodiment, the ratio of the plating rate in the n pole electrode 14a and the plating rate in the p pole electrode 14b is called a plating rate ratio.

(2) control of plating rate ratio

By varying the resistance between the n-pole electrode 14a and the opening 21 and the resistance between the p-pole electrode 14b and the opening 21, the n-pole electrode 14a and the p-pole electrode 14b are different. Make a difference in the plating current flowing. Thus, by controlling the resistance between the n-pole electrode 14a and the opening 21 and the resistance between the p-pole electrode 14b and the opening 21, the n-pole electrode 14a and the p-pole electrode 14b are controlled. The plating rate in can be controlled. The difference in the resistance value between the n pole electrode 14a and the opening 21 and the resistance value between the p pole electrode 14b and the opening 21 is different between the n pole electrode 14a and the opening 21. More preferably, it is about 10% of the resistance value. As a result, the ratio of the plating rate in the n-pole electrode 14a and the plating rate in the p-pole electrode 14b can be controlled efficiently.

The sheet resistance of the n type layer 12 in the p-n bonded wafer used for preparation of the optical semiconductor element 10 is 1-20 ohms / square. Therefore, the sheet resistance of the current film 33 is preferably in the range of 10 mΩ / □ to 1000 mΩ / □, and more preferably 50 mΩ / □ to 200 mΩ / □. The sheet resistance of the current film 33 depends on the film thickness of the current film 33. The thicker the film thickness, the smaller the sheet resistance, and the thinner the film thickness, the larger the sheet resistance.

In this manner, the sheet resistance of the current film 33 can be controlled by using the film thickness of the current film 33 as a parameter. By setting the sheet resistance of the current film 33 in the above range, the difference in the resistance value between the n-pole electrode 14a and the opening 21 and the resistance value between the p-pole electrode 14b and the opening 21. Can be set to about 10%.

When the sheet resistance of the current film 33 is small, most of the plating current flows through the current film 33. Therefore, the difference of each plating current which flows through the n pole electrode 14a and the p pole electrode 14b becomes small, and a plating rate ratio becomes a value close to one. When the sheet resistance of the current film 33 is large, the plating current flowing through the n-type layer 12 increases, and the difference between the plating currents flowing through the n-pole electrode 14a and the p-pole electrode 14b increases. Therefore, the plating rate ratio becomes a value larger than one. In this way, the plating rate ratio can be changed by converting the film thickness of the current film 33. Therefore, by setting the film thickness of the current film 33 to an appropriate value, the p-pole bump 51 and the n-pole bump 52 without a step | step with each other can be formed.

As another method of making a difference in the resistance between the n-pole electrode 14a and the opening 21 and the resistance between the p-pole electrode 14b and the opening 21, the current film 33 and the n-type layer 12 R op which is the connection resistance of may be changed. Even when R cf and R 1 are the same, when R op is large, the resistance between the n-pole electrode 14a and the opening 21 is large. On the contrary, when R op is small, the resistance value between n-pole electrode 14a and opening part 21 also becomes small. On the other hand, even if R op is changed, the resistance value between the p-pole electrode 14b and the opening portion 21 does not change. Since R op depends on the surface area of the opening part 21 and the groove | channel 22, by changing the said surface area, the resistance value between the n pole electrode 14a and the opening part 21, and the p pole electrode 14b and the opening part are changed. The ratio of the resistance values between 21 can be changed. In other words, the plating rate ratio can be controlled by designing the pattern dimension of the opening part 21 to arbitrary sizes (refer FIG. 6). The area ratio of the opening part of FIG. 6 is a ratio which the surface area of the opening part 21 occupies with respect to the area of the area | region in which the n type layer 12 is formed.

As mentioned above, it is preferable that the surface area of the opening part 21 is the surface area which can form the p-pole bump 51 and the n-pole bump 52 which do not have a step | step with each other by electroplating. According to this structure, when manufacturing the optical semiconductor element 10, the p-pole bump 51 and the n-pole bump 52 which have no step | step difference mutually can be formed reliably.

Moreover, it is preferable that the surface area of the groove | channel 22 is the surface area which can form the p-pole bump 51 and the n-pole bump 52 which do not have a step | step with each other by electroplating. According to this structure, when manufacturing the optical semiconductor element 10, the p-pole bump 51 and the n-pole bump 52 which have no step | step difference mutually can be formed reliably.

By controlling the plating current flowing through the n-pole electrode 14a and the p-pole electrode 14b, the plating rate ratio in the n-pole bump 52 and the p-pole bump 51 can be changed so far. . However, in order to eliminate the step difference between the n-type layer 12 and the p-type layer 13 and to make the upper surfaces of the n-pole bump 52 and the p-pole bump 51 the same height, more precise plating rate control is controlled. Is required.

In order to more precisely control the plating rate ratio, in the manufacturing method of the optical semiconductor element according to the embodiment of the present application, the driving waveform of the plating current is a pulse waveform. By changing the pulse period of the pulse waveform, it is possible to control the plating rate ratio.

The step in the upper surface of the n-pole electrode 14a and the p-pole electrode 14b is set to D, and the height of the desired p-pole bump 51 is set to H. The plating rate ratio is set to R as a ratio with respect to the plating rate in the p pole electrode 14b of the plating rate in the n pole electrode 14a. At this time, the plating rate ratio R necessary for forming the upper surfaces of the p-pole bumps 51 and the n-pole bumps 52 at the same height is represented by the following equation.

R = (H + D) / H

The pulse period dependency of the plating rate ratio may be measured in advance as shown in, for example, FIG. 4. The pulse period of the plating current corresponding to R required at the time of bump formation of the optical semiconductor element 10 is selected using the pulse period dependency of the plating rate ratio previously measured. By performing bump formation using the pulse period selected in this way, the optical semiconductor element 10 in which the upper surfaces of the p-pole bumps 51 and the n-pole bumps 52 have the same height can be obtained.

By using the pulse waveform as the driving waveform of the plating current, not only the precise control of the plating rate ratio is possible, but also the bumps formed can be prevented from becoming an abnormal plating state called burned plating. 5 shows the p-pole bumps 51 and the n-pole bumps 152. The p-pole bumps 51 represent bumps normally formed, and the n-pole bumps 152 represent examples of bumps that have been brought into a state called bund plating. Bund plating is more than likely to occur in the plating formed by flowing a large current plating current for a long time. In the manufacturing method of the optical semiconductor element which concerns on this embodiment, the electric current larger than the p-pole electrode 14b flows through the n-pole electrode 14a. In a state where a large plating current flows through the n-pole electrode 14a, when the drive waveform is a direct current waveform, there is a possibility that the bumps formed become bun plating. This possibility can be eliminated by making the drive waveform of the plating current into a pulse waveform.

(3) pulse period

In the manufacturing method of the optical semiconductor element which concerns on one Embodiment of this invention, it is more preferable that the drive waveform of a plating current is a pulse waveform, and a pulse period is the range of 0.1 second-100 second. As can be seen from the pulse period dependency of the plating rate ratio shown in Fig. 4, the plating rate ratio shows a large dependency on the pulse period in the range of 0.1 second to 100 seconds. Therefore, a desired plating rate ratio can be obtained by setting the pulse period of plating current in the range of 0.1 second-100 second.

Immediately after application of the plating current, an electric double layer is formed on the surfaces of the n-pole electrode 14a and the p-pole electrode 14b. Immediately after the plating current is applied, the electric double layer is in a transient state in which the plating current (non-Faraday current) is charged, and after about 30 seconds, the current value of the plating current is converged to a constant value. By using the transient state of this plating state, in the manufacturing method of the optical semiconductor element which concerns on one Embodiment of this invention, plating rate ratio is controlled. By making a plating current into a pulse waveform, the transient state of plating current can be used repeatedly. Therefore, the plating rate ratio can be reliably controlled.

(4) DUTY ratio

In the manufacturing method of the optical semiconductor element which concerns on one Embodiment of this invention, it is more preferable that the DUTY ratio in a pulse period is 80% or more, or the stop time of the plating current in a pulse period is 2 second or less. In manufacturing an optical semiconductor element, the shorter the time (called plating time) required for bump formation by electroplating from the viewpoint of throughput. From the viewpoint of shortening the plating time, electroplating using a direct current waveform (called direct current plating) is preferable, but the plating rate ratio cannot be controlled. Furthermore, there is a possibility of bund plating due to the normal flow of the plating current. By setting the DUTY ratio in the pulse waveform to 80% or more by using the plating current of the pulse waveform for electroplating, not only can control the plating rate ratio, but also increase the plating time by 20% compared with the case of DC plating. It can be suppressed within. In order to increase the throughput, it is desirable to increase the DUTY ratio, but setting it to a value close to 100% increases the possibility of the bunting plating. The upper limit of the DUTY ratio is a value less than 100%, and also a value that can exclude the possibility of bund plating.

Further, by setting the stopping time of the plating current in one cycle of the pulse waveform to 2 seconds or less, the plating rate ratio can be controlled to minimize the decrease in throughput, and then prevent the formation of the bunting. have. The lower limit of the stop time of the plating current is a value larger than 0 seconds, and is a value which can exclude the possibility of occurrence of bund plating.

(5) plating current density

In the manufacturing method of the optical semiconductor element which concerns on one Embodiment of this invention, plating rate ratio changes by changing the current density of the plating current which has a pulse waveform. In other words, it is possible to use the current density of the plating current as a parameter for controlling the plating rate ratio.

The range of the current density which can produce favorable plating changes depending on the kind of plating liquid used for electroplating, the plating bath conditions represented by pH, temperature, and presence or absence of stirring of a plating liquid. However, when controlling the plating rate ratio by changing the current density, the current density may be a range that satisfies the range from the lower limit to the upper limit of the critical current density described later. In other words, the range of the current density may be within the range from the lower limit to the upper limit of the critical current density.

The critical current density refers to the upper limit and the lower limit of the current density for generating a normal film when the film is formed by electroplating. Glossy plating occurs when the current density at the time of electroplating is lower than the lower limit of the critical current density. On the other hand, when the current limit is higher than the upper limit of the critical current density, bund plating (discoloration of the surface and color unevenness) occurs. Glossy plating and bund plating are both undesirable and should be avoided.

When the current density at the time of electroplating is larger than the lower limit of the critical current degree, plating can be normally produced in the n-pole electrode 14a and p-pole electrode 14b which are to-be-plated surfaces. In addition, when the current density is smaller than the upper limit of the critical current density, generation of an abnormal plating state called bun plating can be prevented. By these, the p-pole bump 51 and the n-pole bump 52 of a normal shape can be formed. In addition, by setting the current density at an appropriate value in the range from the lower limit value to the upper limit value of the critical current density, the p-pole bumps 51 and the n-pole bumps 52 having no step difference can be formed.

[Example 1]

The measurement result of the pulse period dependency of the plating rate ratio in the manufacturing method of the optical semiconductor element 10 which concerns on one Embodiment of this invention is shown in FIG. The manufacturing method of the optical semiconductor element 10 conforms to the manufacturing method shown in FIG. After passing through the process of FIGS. 2A to 2D, bump formation by electroplating was performed (see FIG. 2E). When the bump is formed, the pulse frequency of the plating current, which is a pulse waveform, is changed in the range of 0.1 second to 1000 seconds, and the ratio of the thickness of the n-pole bump 52 and the thickness of the p-pole bump 51 is used as the plating rate ratio. 4 is shown.

In FIG. 4, the measured value is shown by the white circle. The broken line is a curve obtained as a result of fitting the measured value. The plating rate ratio obtained by direct current plating is shown by the solid line.

As is apparent from the results of Fig. 4, the plating rate ratio varies greatly from about 1.00 to about 1.25 in the pulse period of the plating current in the range of 0.1 second to 100 seconds. Therefore, an appropriate plating rate ratio can be obtained by selecting the pulse period of plating current in the range of 0.1 second-100 second.

In order to determine the pulse period of the plating current, first, the plating rate ratio required is determined from the step difference between the n-pole electrode 14a and the p-pole electrode 14b and the thickness of the p-pole bump 51 to be formed. Thereafter, the pulse period corresponding to the plating rate ratio required may be read from FIG. 4.

EXAMPLE 2

In the manufacturing method of the optical semiconductor element 10 which concerns on one Embodiment of this invention, the experiment result which measured the relationship between the area ratio of the opening part 21, and plating rate ratio is shown in FIG. The plating conditions in this example are as follows.

ㆍ Plating Solution: EEJA Non-cyanide Type Gold Plating Solution

Plating bath temperature: 52 ℃

ㆍ Plating Current Density: DC 6 mA / ㎠

ㆍ Plated object: Wafer for manufacturing optical semiconductor device (6 inch)

Under the above conditions, electroplating was performed using a wafer without the opening 21 (opening ratio 0%) and a wafer on which the opening 21 was formed (opening ratio 6%). As a result, as shown in FIG. 6, when the area ratio of the opening part 21 is 0% (opening ratio 0%), a plating rate ratio will be about 1.00, and the area ratio of the opening part 21 will be 6% (opening ratio). 6%), the plating rate ratio was about 1.30. Thus, it became clear that plating rate ratio can be controlled by changing the area ratio of the opening part 21. As shown in FIG.

[Example 3]

In the manufacturing method of the optical semiconductor element 10 which concerns on one Embodiment of this invention, the result of having measured the current density dependence of plating rate ratio is shown in FIG. The plating conditions in this example are as follows.

ㆍ Plating Solution: EEJA Non-cyanide Type Gold Plating Solution

Plating bath temperature: 52 ℃

Pulse period: 1 second

ㆍ DUTY Ratio: 80%

ㆍ Plated object: Wafer for manufacturing optical semiconductor device (6 inch)

ㆍ Plating current: variable in the range of 3.5 mA / ㎠ to 11 mA / ㎠

The range of the critical current density in the said plating conditions is 2 mA / cm <2> -8 mA / cm <2>. Electroplating was performed by changing the current density of the plating current in the range of 3.5 mA / cm 2 to 11 mA / cm 2. The electroplating was carried out even under the condition exceeding the range of the critical current density in order to confirm the influence of the current density on the formed bumps. As a result of the experiment, the obtained plating rate ratio varied in the range of approximately 1.45 to 1.10, and there was a clear negative correlation between the plating rate ratio and the current density (FIG. 7). Moreover, it became clear that desired plating rate ratio can be obtained by changing the current density of plating current in the range of a critical current density.

EXAMPLE 4

In the manufacturing method of the optical semiconductor element 10 which concerns on one Embodiment of this invention, the experiment result which measured the relationship between the sheet resistance of the current film 33 and plating rate ratio is shown in FIG. The plating conditions in this example are as follows.

ㆍ Plating Solution: EEJA Non-cyanide Type Gold Plating Solution

Plating bath temperature: 50 ℃

ㆍ Plating Current Density: DC 6 mA / ㎠

ㆍ Plated object: Wafer for manufacturing optical semiconductor device (6 inch)

Under the above conditions, the plating rate ratio was measured by varying the value of the sheet resistance of the current film 33. When changing the value of the sheet resistance, the film thickness of the current film 33 was changed. As a result of the experiment, when the sheet resistance was 10 mΩ / square or more, the higher the sheet resistance, the higher the plating rate ratio was obtained. That is, a positive correlation was found between sheet resistance and plating rate. In this way, it became clear that the plating rate ratio could be controlled by changing the sheet resistance of the current film 33. Moreover, when sheet resistance was 200 m (ohm) / square or more, it became a result that a bund plating generate | occur | produced in n pole.

[Embodiment 2]

The optical semiconductor element 60 which concerns on one Embodiment of this invention is demonstrated with reference to FIGS. In addition, about the same member as Embodiment 1, the same member number is attached | subjected and the description is abbreviate | omitted.

(Optical Semiconductor Element (60))

The optical semiconductor element 60 is a modification of the optical semiconductor element 10 according to the first embodiment. The difference between the optical semiconductor element 10 and the optical semiconductor element 60 is that the n-type layer 62 (first conductive semiconductor layer) and the optical semiconductor element 10 included in the optical semiconductor element 60 are different. It is the shape of the n-type layer 12 with which it is equipped (refer FIG. 9). The n type layer 62 with which the optical semiconductor element 60 is equipped does not have a special structure in the area | region corresponding to the opening part 21 with which the protective film 15 is equipped. That is, in the area | region corresponding to the opening part 21, the upper surface of the n-type layer 62 is planar.

The configuration other than the shape of the n-type layer is common in the optical semiconductor element 10 and the optical semiconductor element 60.

The thickness of the n-pole bumps 52 is formed thicker than the thickness of the p-pole bumps 51, thereby eliminating the step that the upper surfaces of the n-type layer 12 and the p-type layer 13 have. Since the upper surfaces of the n-pole bumps 52 and the p-pole bumps 51 are formed at the same height, the optical semiconductor element 60 according to the embodiment of the present invention can be preferably flip chip mounted.

(Manufacturing method of the optical semiconductor element 60)

The manufacturing method of the optical semiconductor element 60 is demonstrated referring FIG. Also in the manufacturing method, the optical semiconductor element 60 and the optical semiconductor element 10 are the same.

In the pn bonded wafer on which the n-type layer 62 and the p-type layer 13 are deposited on the sapphire substrate 11, the n-type layer 62 is selectively etched, leaving a part of the p-type layer 13. . The n-pole electrode 14a and the p-pole electrode 14b are formed in the upper surface of the n-type layer 62 and the p-type layer 13, and the opening part 21 is provided in a part of the upper surface of the n-type layer 62. A protective film 15 is formed (see FIG. 10A). At this time, the n-type layer 62 is not provided with the groove | channel, and the upper surface of the n-type layer 62 is planar.

Next, the lower current film 31 and the upper current film 32 are sequentially formed to be the current film 33 (FIG. 10B).

After forming the current film 33, the following processes are performed sequentially. The photoresist 41 is applied (see FIG. 10C). The bump formation pattern 42 is formed by the photolithography method (FIG. 10 (d)). The p-pole bumps 51 and the n-pole bumps 52 are formed by electroplating using the driving current of the pulse waveform (see FIG. 10E). The photoresist 41 is removed using an organic solvent (see FIG. 10 (f)). Unnecessary portions of the current film 33 are etched and removed (see FIG. 10G). The optical semiconductor element 60 is completed by the above process.

When the current film 33 is formed, the current film 33 and the n-type layer 62 are in contact with each other through the opening 21 even though the top surface of the n-type layer 62 is flat. Therefore, the current path from the opening portion 21 to the n-pole electrode 14a becomes a parallel circuit composed of the current film 33 and the n-type layer 62. On the other hand, the current path from the opening portion 21 to the p-pole electrode 14b becomes the current film 33 only.

Therefore, the resistance value from the opening portion 21 to the n-pole electrode 14a becomes smaller than the resistance value from the opening portion 21 to the p-pole electrode 14b. Since the plating current larger than the p-pole electrode 14b flows through the n-pole electrode 14a, the plating rate in the n-pole electrode 14a becomes higher than the plating rate in the p-pole electrode 14b.

By changing the pulse period using the pulse waveform in the drive waveform of electroplating, the plating rate ratio of the plating rate in the n-pole electrode 14a and the plating rate in the p-pole electrode 14b can be controlled. Therefore, the optical semiconductor element 60 is not limited in the dimensions of the n-pole bump 52 and the p-pole bump 51, can absorb the step on the surface of the semiconductor substrate, and becomes an optical semiconductor element suitable for flip chip mounting. .

(theorem)

In order for the optical semiconductor element which concerns on one aspect of this invention to solve the said subject,

A first semiconductor layer comprising a first conductive semiconductor,

A second semiconductor layer made of a second conductivity type semiconductor and formed on a part of an upper surface of the first semiconductor layer,

A first electrode formed on the other part of the upper surface of the first semiconductor layer,

A second electrode formed on an upper surface of the second semiconductor layer and having an upper surface located at a position higher than an upper surface of the first electrode;

A first connection electrode formed on an upper surface of the first electrode,

A second connection electrode formed on an upper surface of the second electrode,

An insulating protective film covering the surface of the first semiconductor layer and the surface of the second semiconductor layer, the protective film having an opening for exposing a part of the surface of the first semiconductor layer.

MEANS TO SOLVE THE PROBLEM In the manufacturing method of the optical semiconductor element which concerns on one aspect of this invention, in order to solve the said subject,

A first semiconductor layer comprising a substrate, a first conductive semiconductor formed on an upper surface of the substrate, a second semiconductor layer formed of a second conductive semiconductor, and formed on a portion of an upper surface of the first semiconductor layer; A first electrode formed on another part of the upper surface of the first semiconductor layer, a second electrode formed on the upper surface of the second semiconductor layer and having an upper surface located at a position higher than the upper surface of the first electrode; An insulating protective film covering the surface of the first semiconductor layer and the surface of the second semiconductor layer, the entire surface of the upper surface of the optical semiconductor substrate having a protective film having an opening for exposing a part of the surface of the first semiconductor layer; In the step of forming a conductive current film,

After forming the current film, electroplating the optical semiconductor substrate, thereby forming a first connection electrode on the upper surface of the first electrode, and forming a second connection electrode on the upper surface of the second electrode. It is characterized by having.

According to the said structure, in the optical semiconductor element which concerns on one aspect of this invention, the protective film has covered the surface of a 1st semiconductor layer and the surface of a 2nd semiconductor layer. The protective film has an opening that exposes a part of the surface of the first semiconductor layer.

When manufacturing the optical semiconductor element of the said structure, a 1st connection electrode and a 2nd connection electrode are formed by using electroplating. Specifically, a current film is formed on the entire surface of the upper surface of the optical semiconductor substrate, and then a photoresist pattern opening on the first and second electrodes is formed, and then a plating current is applied to the optical semiconductor element.

Here, the first electrode and the current film are in direct conduction. Moreover, the 1st semiconductor layer which is electrically connected with the 1st electrode is electrically conductive with the current film through the opening part of a protective film. As a result, the plating current flows to both the current film and the first semiconductor layer from the first electrode.

On the other hand, although the second electrode is in direct conduction with the current film, the second semiconductor layer in conducting with the second electrode is not in conduction with the current film. As a result, the plating current only flows from the second electrode to the current film.

As described above, when electroplating the optical semiconductor substrate, the flowing plating current becomes the first electrode side> the second electrode side. As a result, by controlling the parameters of the plating current flowing through the optical semiconductor element, it is possible to form the first connection electrode and the second connection electrode which have no step difference, which absorb the step difference between the first electrode and the second electrode. In that case, since only the parameter of a plating current needs to be controlled, there is no restriction | limiting at all in the dimension of a 1st connection electrode and a 2nd connection electrode.

Therefore, according to the manufacturing method of the optical semiconductor element which concerns on one aspect of this invention, the 1st connection electrode and the 2nd connection electrode which do not have a mutual difference suitable for flip chip mounting can be formed without restrict | limiting in the dimension of each connection electrode. Can be. Moreover, according to the optical semiconductor element which concerns on one aspect of this invention, the optical semiconductor element provided with the 1st connection electrode and the 2nd connection electrode which have no step difference mutually suitable for flip chip mounting can be implement | achieved.

Moreover, in the optical semiconductor element which concerns on one aspect of this invention,

It is preferable that the surface area of the said opening part is the surface area which can form the said 1st connection electrode and the 2nd connection electrode which do not have a step | step with each other by electroplating.

According to the said structure, when manufacturing the optical semiconductor element which concerns on one aspect of this invention, the 1st connection electrode and the 2nd connection electrode which do not have a step | step with each other can be reliably formed.

Moreover, in the optical semiconductor element which concerns on one aspect of this invention,

It is preferable that a groove is formed in the position corresponding to the said opening part in a said 1st semiconductor layer.

According to the above structure, by dividing the optical semiconductor element at the grooved point, the optical semiconductor element can be divided into a predetermined size without causing a defect in the first semiconductor layer.

Moreover, in the optical semiconductor element which concerns on one aspect of this invention,

It is preferable that the surface area of the said groove | channel is the surface area which can form the said 1st connection electrode and the 2nd connection electrode which do not have a step | step with each other by electroplating.

According to the said structure, when manufacturing the optical semiconductor element which concerns on one aspect of this invention, the 1st connection electrode and the 2nd connection electrode which do not have a step | step with each other can be reliably formed.

Moreover, in the manufacturing method of the optical semiconductor element which concerns on one aspect of this invention,

It is preferable to electroplate an optical semiconductor element by flowing the plating current of a pulse waveform.

According to the said structure, by controlling the various parameters of a plating current, the ratio of the plating rate in a 1st electrode and the plating rate in a 2nd electrode can be controlled efficiently.

Moreover, in the manufacturing method of the optical semiconductor element which concerns on one aspect of this invention,

It is preferable that the period of the said pulse waveform exists in the range of 0.1-100 second.

According to the said structure, the ratio of the plating rate in a 1st electrode and the plating rate in a 2nd electrode can be controlled efficiently. The reason for this is as follows. When a plating current is applied to the optical semiconductor substrate, the transient change in the plating liquid resistance is converged within 30 seconds. Therefore, when the pulse waveform is in the range of 0.1 to 100 seconds, the effect of making the pulse waveform variable can be obtained.

Moreover, in the manufacturing method of the optical semiconductor element which concerns on one aspect of this invention,

It is preferable that the duty ratio of the pulse waveform is 80% or more.

According to the said structure, the ratio of the plating rate in a 1st electrode and the plating rate in a 2nd electrode can be controlled efficiently.

Moreover, in the manufacturing method of the optical semiconductor element which concerns on one aspect of this invention,

It is preferable that the stop time of the current for each period of the pulse waveform is 2 seconds or less.

According to the said structure, the ratio of the plating rate in a 1st electrode and the plating rate in a 2nd electrode can be controlled efficiently.

Moreover, in the manufacturing method of the optical semiconductor element which concerns on one aspect of this invention,

It is preferable that the sheet resistance of the said current film exists in the range of 10-1000 m (ohm) / square.

According to the said structure, the sheet resistance of a current film exists in the range of 10-1000 m (ohm) / square. Here, the sheet resistance of the 1st semiconductor layer in an optical semiconductor substrate exists in the range of 1-20 ohms / square. Therefore, the difference between the combined resistance of the path through which the plating current flows on the first electrode side and the combined resistance of the path through which the plating current flows on the second electrode side is 10% of the combined resistance on the first electrode side. Can be. As a result, the ratio of the plating rate in a 1st electrode and the plating rate in a 2nd electrode can be controlled efficiently.

Moreover, in the manufacturing method of the optical semiconductor element which concerns on one aspect of this invention,

It is preferable that the current density of the said plating current in the surface plated by the plating current of the said pulse waveform is a range which satisfy | fills the range of an upper limit from the lower limit of a critical current density.

According to the said structure, the 1st connection electrode and the 2nd connection electrode of a normal shape can be formed. Moreover, plating rate ratio can be changed by changing a current density in this range. Therefore, by setting the current density to an appropriate value, it is possible to form the first connection electrode and the second connection electrode without any step.

Moreover, in the manufacturing method of the optical semiconductor element which concerns on one aspect of this invention,

It is preferable that the plating rate ratio of the said 1st electrode and the said 2nd electrode in the process of forming the said connection electrode is determined according to the film thickness of the said current film formed in the process of forming the said current film.

According to the said structure, plating rate ratio can be changed by changing the film thickness of a current film. Therefore, by making the film thickness of a current film into a suitable value, the 1st connection electrode and the 2nd connection electrode without a step | step with each other can be formed.

Moreover, in the manufacturing method of the optical semiconductor element which concerns on one aspect of this invention,

When electroplating the optical semiconductor element, it is preferable to use a metal arbitrarily selected from gold, silver, platinum, copper, palladium, nickel, solder and these alloys.

According to the said structure, the optical semiconductor element provided with the 1st connection electrode and the 2nd connection electrode which have more favorable ohmic characteristic and is suitable for flip chip mounting can be manufactured.

This invention is not limited to each embodiment mentioned above, Various changes are possible in the range shown to the claim, and also regarding embodiment obtained by combining suitably the technical means disclosed in each embodiment in the technical scope of this invention also in the technical scope of this invention. Included.

Industrial availability

INDUSTRIAL APPLICABILITY The present invention can be widely used as an optical semiconductor element such as a light emitting diode (LED). Moreover, it can use also as a method of manufacturing such an optical semiconductor element.

10: optical semiconductor element
11: sapphire substrate (insulating transparent substrate)
12: n type layer (1st conductivity type semiconductor layer)
13: p-type layer (second conductive semiconductor layer)
14a: n-pole electrode (first electrode)
14b: p pole electrode (second electrode)
15: protective film
21: opening
22: Home
30: cathode
31: lower layer current film
32: upper layer current film
33: current film
41: photoresist
42: bump formation pattern
51: p pole bump (second connection electrode)
52: n pole bump (first connection electrode)
60: optical semiconductor element
62: n-type layer (first conductive semiconductor layer)
80: anode
81: positive electrode plate
152: n pole bump

Claims (13)

A first semiconductor layer comprising a first conductive semiconductor,
A second semiconductor layer made of a second conductivity type semiconductor and formed on a part of an upper surface of the first semiconductor layer,
A first electrode formed on the other part of the upper surface of the first semiconductor layer,
A second electrode formed on an upper surface of the second semiconductor layer and having an upper surface located at a position higher than an upper surface of the first electrode;
A first connection electrode formed on an upper surface of the first electrode,
A second connection electrode formed on an upper surface of the second electrode,
An insulating protective film covering the surface of the first semiconductor layer and the surface of the second semiconductor layer, the protective film having an opening for exposing a part of the surface of the first semiconductor layer. The method of claim 1,
The surface area of the said opening part is the surface area which can form the said 1st connection electrode and the 2nd connection electrode which have no step mutually by electroplating, The optical semiconductor element characterized by the above-mentioned. The method of claim 1,
A groove is formed in a position corresponding to the opening portion in the first semiconductor layer. The method of claim 3, wherein
The surface area of the groove is a surface semiconductor that can form the first connection electrode and the second connection electrode which are free from steps by electroplating. A first semiconductor layer comprising a substrate, a first conductive semiconductor formed on an upper surface of the substrate, a second semiconductor layer composed of a second conductive semiconductor, and formed on a portion of an upper surface of the first semiconductor layer; A first electrode formed on another part of the upper surface of the first semiconductor layer, a second electrode formed on the upper surface of the second semiconductor layer and having an upper surface located at a position higher than the upper surface of the first electrode; An insulating protective film covering the surface of the first semiconductor layer and the surface of the second semiconductor layer, the entire surface of the upper surface of the optical semiconductor substrate having a protective film having an opening for exposing a part of the surface of the first semiconductor layer; In the step of forming a conductive current film,
After forming the current film, electroplating the optical semiconductor substrate, thereby forming a first connection electrode on the upper surface of the first electrode, and forming a second connection electrode on the upper surface of the second electrode. It is provided, The manufacturing method of the optical semiconductor element characterized by the above-mentioned. The method of claim 5, wherein
A method for manufacturing an optical semiconductor element, wherein the optical semiconductor element is electroplated by flowing a plating current of a pulse waveform. The method according to claim 6,
The period of the said pulse waveform is in the range of 0.1-100 second, The manufacturing method of the optical semiconductor element characterized by the above-mentioned. The method according to claim 6,
The DUTY ratio of the pulse waveform is 80% or more, the manufacturing method of the optical semiconductor device. The method according to claim 6,
A method for manufacturing an optical semiconductor element, wherein the stop time of the current per one cycle of the pulse waveform is 2 seconds or less. The method according to claim 6,
The sheet resistance of the said current film exists in the range of 10-1000 m (ohm) / square, The manufacturing method of the optical semiconductor element characterized by the above-mentioned. The method according to claim 6,
The current density of the plating current on the surface plated by the plating current of the pulse waveform is a range satisfying the range of the upper limit from the lower limit of the critical current density. The method of claim 5, wherein
In accordance with the film thickness of the current film formed in the step of forming the current film, the plating rate ratio of the first electrode and the second electrode in the step of forming the connection electrode is determined. Method of manufacturing the device. The method of claim 5, wherein
When electroplating the optical semiconductor device, a method of manufacturing an optical semiconductor device, characterized in that a metal selected from gold, silver, platinum, copper, palladium, nickel, solder and alloys thereof is used.
KR1020120031893A 2011-06-28 2012-03-28 Optical semiconductor device and manufacturing method of optical semiconductor device KR101254460B1 (en)

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