TW201301563A - Optical semiconductor device and manufacturing method of optical semiconductor device - Google Patents

Abstract

An optical semiconductor device 10 comprises a first semiconductor layer 12 comprising a first conductive-type semiconductor; a second semiconductor layer 13 comprising a second conductive-type semiconductor and formed on a portion of an upper surface of the first semiconductor layer 12; a first electrode 14a formed on the other portion of the upper surface of the first semiconductor layer 12; a second electrode 14b formed on an upper surface of the second semiconductor layer 13 and having an upper surface arranged at a position higher than an upper surface of the first electrode 14a; a first connecting electrode 52 formed on the upper surface of the first electrode 14a; a second connecting electrode 51 formed on an upper surface of the second electrode; and a protective film 51 covering the surface of the first semiconductor layer 12 and that of the second semiconductor layer 13, and having an opening portion 21 for exposing a portion of the surface of the first semiconductor layer 12.

Description

Optical semiconductor element and method of manufacturing optical semiconductor element

The present invention relates to an optical semiconductor element having a connection electrode suitable for flip chip mounting, and a method of manufacturing the same.

Light-emitting diodes (LEDs) are widely used in the background of technical development such as whitening and a sharp increase in luminous efficiency. For example, lighting for general household use, headlights for automobiles, and the like can be cited.

From the viewpoints of luminous efficiency, manufacturing efficiency, manufacturing cost, and the like, the structure of the LED which is currently in the mainstream is the following structure. An n-type and p-type gallium nitride-based compound semiconductor is laminated on an insulating transparent substrate (such as a sapphire substrate). Thereafter, the surface of the n-type layer and the p-type layer is formed in a state having a step by etching one of the p-type layers. An electrode is formed on the surface of the n-type layer and the p-type layer, and flip-chip mounting is performed. The light emitted from the LED is irradiated through the insulating transparent substrate.

For the LED, the conduction state of the p-pole and the n-pole is uniform, which is important for reducing power consumption and improving durability. Therefore, in the LED mounted with the flip chip, the formation technique of the connection electrode is an important technique. Patent Document 1 discloses a technique for forming an electrode on an LED chip having a step by vacuum deposition and stripping. Patent Document 2 discloses a technique for forming an electrode on an optical semiconductor element having a step by electroless plating.

[Previous Technical Literature] [Patent Literature]

[Patent Document 1] Japanese Laid-Open Patent Publication No. 9-232632 Gazette (public on September 5, 1997)

[Patent Document 2] Japanese Laid-Open Patent Publication No. 2004-103975 (published on April 2, 2004)

[Patent Document 3] Japanese Laid-Open Patent Publication No. 10-64953 (published on March 6, 1998)

However, in Patent Documents 1 and 2, since the electrodes having the same film thickness are formed, the step difference between the LED and the optical semiconductor element cannot be eliminated. Therefore, a method of forming an electrode having a thick film thickness, crushing the electrode when the flip chip is mounted, or using a solder ball having a larger step than the above to absorb a step or the like is performed. In these methods, the flip chip is mounted while absorbing the above-described step, but the conduction state cannot be made uniform.

On the other hand, Patent Document 3 discloses a technique in which a relationship between a thickness of a plating layer formed and an opening diameter is used when plating is performed. On the semiconductor substrate having different surface heights, the pillars having different heights are formed by changing the opening diameter of the pillar forming portion. According to this, the flip chip is mounted by offsetting the step on the surface of the semiconductor substrate. However, this technique can absorb the step on the surface of the semiconductor substrate, but constrains the conductive pillar (connecting electrode) by absorbing the step on the surface of the semiconductor substrate.

The present invention has been made in view of the above problems, and an object thereof is to provide an optical semiconductor element having a first connection electrode and a second connection electrode which are suitable for flip chip mounting without stepping therebetween. Further, another object of the present invention is to provide a light for forming a first connection electrode and a second connection electrode which are suitable for flip chip mounting without stepping on each other without restricting the size of each connection electrode. A method of manufacturing a semiconductor element.

In order to solve the above problems, an optical semiconductor device according to an aspect of the present invention includes a first semiconductor layer including a semiconductor of a first conductivity type, and a second semiconductor layer including a semiconductor of a second conductivity type and formed. a portion of the upper surface of the first semiconductor layer; a first electrode formed on the upper surface of the first semiconductor layer; and a second electrode formed on the upper surface of the second semiconductor layer And having an upper surface located higher than the upper surface of the first electrode; a first connection electrode formed on the upper surface of the first electrode; and a second connection electrode formed on the second electrode And a protective film covering the surface of the first semiconductor layer and the insulating film of the surface of the second semiconductor layer, and having an opening that exposes a part of the surface of the first semiconductor layer.

In order to solve the above problems, a method of fabricating an optical semiconductor device according to an aspect of the present invention includes the steps of forming a conductive current film on an entire surface of an upper surface of an optical semiconductor substrate, the optical semiconductor substrate comprising: a substrate; a first semiconductor layer including a semiconductor of a first conductivity type formed on an upper surface of the substrate; and a second semiconductor including a semiconductor of a second conductivity type and formed on a surface of the upper surface of the first semiconductor layer a first electrode formed on the other surface of the upper surface of the first semiconductor layer; formed on the second semiconductor layer a second electrode having an upper surface located higher than the upper surface of the first electrode; and an insulating protective film covering the surface of the first semiconductor layer and the surface of the second semiconductor layer, and a protective film having an opening for exposing a portion of the surface of the first semiconductor layer; and after forming the current film, the first connection electrode is formed on the upper surface of the first electrode by plating the optical semiconductor substrate. And forming a second connection electrode on the upper surface of the second electrode.

According to the above configuration, in the optical semiconductor device according to the aspect of the invention, the protective film covers the surface of the first semiconductor layer and the surface of the second semiconductor layer. Further, the protective film has an opening that exposes a part of the surface of the first semiconductor layer.

When the optical semiconductor element of this configuration is manufactured, the first connection electrode and the second connection electrode are formed by using electroplating. Specifically, a current film is formed on the entire surface of the upper surface of the optical semiconductor substrate, and then a photoresist pattern opened on the first and second electrodes is formed, and then a plating current is applied to the optical semiconductor element.

At this point, the first electrode and the current film are directly turned on. Further, the first electrode and the conductive first semiconductor layer pass through the opening of the protective film to be electrically connected to the current film. As a result, a plating current flows from both the first electrode to the current film and the first semiconductor layer.

On the other hand, although the second electrode is directly electrically connected to the current film, the second semiconductor layer that is electrically connected to the second electrode is not electrically connected to the current film. Accordingly, a plating current flows only from the second electrode to the current film.

As described above, when the optical semiconductor substrate is plated, the plating current flowing therethrough is the first electrode side > the second electrode side. As a result, by controlling the optical semiconductor component The parameters of the plating current flowing therethrough form a first connection electrode and a second connection electrode which absorb the step difference between the first electrode and the second electrode and have no step difference therebetween. In this case, as long as the parameters of the plating current are controlled, the dimensions of the first connection electrode and the second connection electrode are not restricted.

Therefore, according to the method of manufacturing an optical semiconductor device according to an aspect of the present invention, the first connection electrode and the second connection electrode which are suitable for flip chip mounting without stepping therebetween can be formed without constraining the size of each connection electrode. . Further, according to the optical semiconductor device of one aspect of the present invention, it is possible to realize an optical semiconductor element having a first connection electrode and a second connection electrode which are suitable for flip chip mounting without stepping therebetween.

Other objects, features, and advantages of the present invention will be apparent from the description appended claims. Further, the advantages of the present invention can be understood by referring to the description of the additional drawings.

The present invention provides a method of manufacturing an optical semiconductor device, which is capable of forming a first connection electrode and a second connection electrode which are suitable for flip chip mounting without stepping, without restricting the size of each connection electrode. Further, according to the optical semiconductor device of one aspect of the present invention, it is possible to realize an optical semiconductor element having a first connection electrode and a second connection electrode which are suitable for flip chip mounting without stepping therebetween.

Hereinafter, an embodiment of the present invention will be described in detail with reference to Figs. 1 to 8 .

[Embodiment 1] (Configuration of Optical Semiconductor Element 10)

An optical semiconductor device 10 according to an embodiment of the present invention will be described with reference to Fig. 1 .

Fig. 1 is a schematic view showing the configuration of an optical semiconductor device 10 according to an embodiment of the present invention. The optical semiconductor element 10 is formed with a first conductive semiconductor layer 12 on the upper surface of the insulating transparent substrate 11. Further, a second conductive semiconductor layer 13 is formed on one surface of the upper surface of the first conductive semiconductor layer 12. In the present embodiment, the sapphire substrate 11 is used as the insulating transparent substrate 11. In the present embodiment, the first conductive semiconductor layer 12 and the second conductive semiconductor layer 13 are described as including a n-type and p-type gallium nitride-based compound semiconductor. Therefore, the first conductive semiconductor layer 12 is the n-type layer 12, and the second conductive semiconductor layer 13 is the p-type layer 13. In the present embodiment, an optical semiconductor substrate in which an n-type layer and a p-type layer including a gallium nitride-based compound semiconductor are formed on a sapphire substrate 11 is referred to as a p-n junction wafer.

A part of the upper surface of the n-type layer 12 and the p-type layer 13 is provided with an insulating protective film 15 having an opening portion 21 in a portion of the upper surface of the n-type layer 12. Further, a groove 22 is formed in a region of the n-type layer 12 corresponding to the opening portion 21 (see FIG. 1).

An n-electrode (first electrode) 14a and a p-electrode (second electrode) 14b are provided on a portion of the upper surface of the n-type layer 12 and a portion of the upper surface of the p-type layer 13. The n-electrode electrode 14a and the p-pole electrode 14b comprise the same metal and have the same thickness. Since the p-type layer 13 is formed on the upper surface of the n-type layer 12, the upper surface of the n-type layer 12 and the p-type layer 13 has a step. Therefore, the upper surfaces of the n-electrode electrode 14a and the p-pole electrode 14b also have a step.

In the process of fabricating the optical semiconductor device 10, the n-pole electrodes 14a and p are included A current film 33 including two layers is provided on the entire surface of the p-n junction wafer on the upper surface of the electrode electrode 14b (see FIGS. 2(b) to (f)). The current film 33 has electrical conductivity, and when a bump is formed by plating, it functions as a conductive layer for plating current. The current film 33 includes a lower current film 31 and an upper current film 32.

The plating current flows through the n-electrode 14a and the p-electrode 14b, the n-electrode 14a, and the p-electrode 14b via the current film 33, and the n-pole bump 52 (first connection electrode) and the p-pole convex are formed by plating. Block 51 (second connecting electrode). The n-pole bumps 52 and the p-pole bumps 51 are respectively formed with different thicknesses. The thickness of the n-pole bump 52 is formed thicker than the thickness of the p-pole bump 51, eliminating the step difference between the upper surface of the n-type layer 12 and the p-type layer 13. Therefore, the upper surfaces of the n-pole bump 52 and the p-pole bump 51 are formed at the same height.

Since the upper surfaces of the n-pole bumps 52 and the p-pole bumps 51 are formed at the same height, the optical semiconductor device 10 according to an embodiment of the present invention can be suitably mounted with a flip chip. Although the details will be described later, the thickness of the n-pole bump 52 and the p-pole bump 51 can be controlled independently of the area of the n-pole electrode 14a and the p-pole electrode 14b. Therefore, the optical semiconductor element 10 can absorb the step on the surface of the semiconductor substrate without restricting the size of the n-pole bump 52 and the p-pole bump 51 formed on the n-electrode electrode 14a and the p-pole electrode 14b.

In the present embodiment, an n-type layer is used as the first conductive type semiconductor layer, and a p-type layer is used as the second conductive type semiconductor layer. However, the configuration may be reversed. In other words, a p-type layer is used as the first conductive semiconductor layer, and an n-type layer may be used as the second conductive semiconductor layer.

(Method of Manufacturing Optical Semiconductor Element 10) (1) Formation of current film

A method of fabricating the optical semiconductor device 10 will be described with reference to FIG. In the fabrication of the optical semiconductor device 10, the p-n junction wafer including the n-type layer and the p-type layer of the gallium nitride-based compound semiconductor is formed on the sapphire substrate 11. The p-type layer 13 of the p-n junction wafer is selectively etched to expose the n-type layer 12. In this step, the same well-known technique as before can be used. Further, a plurality of optical semiconductor elements 10 are formed on the p-n junction wafer, and one of the plurality of optical semiconductor elements 10 is illustrated in FIG.

An n-electrode 14a and a p-electrode 14b including a laminated structure of nickel and gold are formed on the upper surface of the exposed n-type layer 12 and the upper surface of the p-type layer 13 which is not etched. As the n-electrode electrode 14a and the p-electrode electrode 14b, a contact interface between the n-type layer 12 and the n-pole electrode 14a and a contact interface between the p-type layer 13 and the p-electrode electrode 14b can be used by using a laminated structure including nickel and gold. Good ohmic properties are obtained. In the formation of a laminated structure including Ni (nickel) and Au (gold), a technique such as a sputtering method or a vacuum coating method may be used. In the patterning of steps such as electrode formation, for example, photolithography may be used.

After the n-electrode electrode 14a and the p-pole electrode 14b are formed, SiO ₂ (cerium oxide) as an insulating protective film 15 is formed on the upper surfaces of the n-type layer 12 and the p-type layer 13. After the protective film 15 is formed, the protective film 15 is removed from a portion of the n-electrode electrode 14a and the p-electrode electrode 14b and the opening portion 21. Further, only the n-type layer 12 is selectively etched, and the groove 22 is formed in a region corresponding to the opening portion 21. This state is shown in Fig. 2(a).

The shape of the opening portion 21 and the recess 22 is more preferably such that the optical semiconductor element 10 is surrounded by the opening portion 21 and the recess 22 when the optical semiconductor element 10 is viewed from above. Around the periphery of 10, the shape of each of the optical semiconductor elements 10 is separated.

After the protective film 15 having the opening portion 21 and the recess 22 are formed, a current film 33 for circulating a plating current is formed. As shown in FIG. 2(b), the current film 33 includes a lower current film 31 and an upper current film 32. As a material constituting the lower current film 31, for example, TiW is suitable. By making TiW the lower layer current film 31, diffusion of atoms between the n-type layer 12 and the upper layer current film 32 can be suppressed. Similarly, the diffusion of atoms between the n-electrode electrode 14a and the p-electrode electrode 14b and the upper layer current film 32 can be suppressed. TiW can be deposited by, for example, sputtering.

The material constituting the upper current film 32 is made of the same metal as the plating metal forming the bump. By using the same metal as the plating metal forming the bumps for the upper current film 32, the adhesion between the n-electrode electrode 14a and the p-electrode electrode 14b of the current-intercepting film and the bump can be improved, and the optical semiconductor element 10 can be improved. Durability. In the present embodiment, since Au is used as the material constituting the bump, Au is also used as the material constituting the upper layer current film 32. The upper current film 32 can be deposited by, for example, sputtering.

When the current film 33 is formed, the current film 33 and the n-type layer 12 are not in direct contact with each other in the region where the protective film 15, the n-electrode 14a, and the p-electrode 14b are formed (see FIG. 2(b)). On the other hand, the current film 33 is also formed inside the opening portion 21 and the recess 22 by providing the opening portion 21. By forming the current film 33 to the inside of the opening 21 and the recess 22, the current film 33 is brought into direct contact with the n-type layer 12, and is electrically connected. As will be described later, by forming the current film 33 and the n-type layer 12 in the opening portion 21, bumps having different thicknesses can be formed on the n-electrode electrode 14a and the p-pole electrode 14b by electroplating.

On the element forming the current film 33, the photoresist 41 is applied by, for example, spin coating (see (c) of Fig. 2). Thereafter, a bump forming pattern 42 as an opening portion of the photoresist 41 is formed at a position corresponding to the n-electrode electrode 14a and the p-pole electrode 14b by photolithography (see (d) of FIG. 2).

(2) Using electroplated bump formation

After the bump formation pattern 42 is formed, the n-pole bump 52 and the p-pole bump 51 are formed by plating. In the fabrication of the optical semiconductor device 10, a p-n junction wafer is used. The current film 33 formed on the upper surface of the p-n junction wafer is formed not only in the fabrication region of the optical semiconductor device 10 but also on the outer peripheral portion of the p-n junction wafer. The current film 33 is used as one of the electroplated electrodes by connecting the cathode 30 of the external power source to the current film 33 on the outer peripheral portion of the p-n junction wafer.

An anode 80 of an external power source is connected to the anode plate 81 containing the same material as the plated metal or a suitable material, thereby serving as the other electrode for electroplating. In the present embodiment, a plate of Pt (platinum) is used as the anode plate 81.

The p-n junction wafer to which the cathode 30 is connected and the anode plate 81 to which the anode 80 is connected are immersed in the plating solution, and a plating current flows from the external power source. In the present embodiment, a gold plating solution is used to form a bump including gold. Physical conditions such as the temperature of the plating solution and the concentration of metal ions contained in the plating solution are managed in such a manner that they do not change during the plating process.

The plating rate of the film formed by electroplating depends on the current value (more precisely, the current density) of the plating current flowing in the area of the plating. Here, the magnitude relationship between the current values flowing through the n-electrode electrode 14a and the p-pole electrode 14b will be described.

The current path from the cathode 30 to the opening 21 is common to the n-electrode 14a and the p-electrode 14b. Therefore, the current values flowing through the n-electrode electrode 14a and the p-electrode electrode 14b depend on the current path from the opening portion 21 to the n-pole electrode 14a and the current path from the opening portion 21 to the p-electrode electrode 14b.

In the current path formed between the opening 21 and the n-electrode 14a, the current film 33 and the n-type layer 12 are electrically connected via the opening 21 and the groove 22. Further, the upper surface of the n-type layer 12 and the n-electrode electrode 14a are also turned on. Therefore, the current circuit between the cathode 30 and the n-electrode 14a includes a parallel circuit of the current film 33 and the n-type layer 12 (refer to FIG. 3).

On the other hand, a p-type layer 13 exists between the p-electrode electrode 14b and the n-type layer 12 (see FIG. 1). A p-n junction layer is formed on the contact interface between the n-type layer 12 and the p-type layer 13. When electroplating, the potential difference generated between the n-electrode electrode 14a and the p-electrode electrode 14b is extremely small compared to the barrier height of the p-n junction layer. Therefore, the n-type layer 12 and the p-electrode electrode 14b are not electrically connected to each other through the p-type layer 13. Therefore, the current path formed between the opening portion 21 and the p-electrode electrode 14b is a series circuit based only on the current film 33 (refer to FIG. 3).

Comparing only the magnitude relationship between the resistance value of the series circuit of the current film 33 and the resistance value of the parallel circuit including the current film 33 and the n-type layer 12, the resistance value of the parallel circuit including the current film 33 and the n-type layer 12 is compared. small. Therefore, the resistance value from the opening portion 21 to the n-pole electrode 14a is smaller than the resistance value from the opening portion 21 to the p-pole electrode 14b. Therefore, the resistance value between the cathode 30 and the n-electrode 14a is smaller than the resistance between the cathode 30 and the p-electrode 14b.

Since the resistance value is inversely proportional to the current value, the n-pole electrode 14a and plating Between the liquids, a larger plating current flows between the p-electrode electrode 14b and the plating solution. As a result, an n-pole bump 52 having a thicker thickness than the p-pole bump 51 is formed on the n-electrode electrode 14a (see FIG. 2(e)).

The thickness of the p-pole bump 51 and the n-pole bump 52 is formed by eliminating the step caused by the p-type layer 13 formed on the upper surface of the n-type layer 12. As a result, the upper surfaces of the p-pole bumps 51 and the n-pole bumps 52 are formed to have the same height. The method of controlling the thickness of the p-pole bump 51 and the n-pole bump 52 will be described later.

In the present embodiment, Au is used as the material of the n-pole bump 52 and the p-pole bump 51. However, as a material other than Au, Ag (silver), Pt (platinum), Cu (copper), Pd (palladium), Ni (nickel), solder, and an alloy containing the same may be used as the n-pole bump 52. The material of the p-pole bump 51 is used arbitrarily. More preferably, the material constituting the n-pole bump 52 and the p-pole bump 51 is the same as the material constituting the upper layer current film 32. Therefore, Ag, Pt, Cu, Pd, Ni, solder, and an alloy containing the same may be used as the material of the upper layer current film 32.

When the optical semiconductor element 10 is flip-chip mounted by using Au, Ag, Pt, Cu, Pd, Ni, solder, and the alloy containing the same as the material of the n-pole bump 52 and the p-pole bump 51, Good ohmic properties are obtained.

After the n-pole bump 52 and the p-pole bump 51 are formed, the photoresist 41 is removed using an organic solvent (see (f) of FIG. 2). As a result, the p-electrode 33 is interposed on the p-electrode 14b to form the p-pole bump 51, and the current film 33 is interposed on the n-electrode 14a to form the n-pole bump 52.

Thereafter, the optical semiconductor element 10 shown in Fig. 2(g) is completed by removing the current film 33 from the element in the state of (f) of Fig. 2 . In order to remove the current film 33, the element in the state of (f) of FIG. 2 can be immersed in an etchable composition. The metal current etching solution of the lower current film 31 and the upper current film 32.

Finally, each of the optical semiconductor elements 10 is drawn from the p-n junction wafer by dividing the p-n junction wafer. By providing the optical semiconductor element 10 with the recess 22, when the p-n junction wafer is divided by a specific size, the division can be performed without causing defects on the n-type layer 12.

According to the above manufacturing method, the optical semiconductor element 10 suitable for flip chip mounting in which the upper surfaces of the p-pole bumps 51 and the n-pole bumps 52 are formed to have the same height can be provided. The thicknesses of the p-pole bumps 51 and the n-pole bumps 52 are controlled based on the current values of the plating currents flowing through the p-electrode electrodes 14b and the n-electrode electrodes 14a. Therefore, in the method of manufacturing an optical semiconductor device according to an embodiment of the present invention, the size of the p-pole bump 51 and the n-pole bump 52 is not restricted.

(Bump thickness control method)

A method of controlling the thickness of the p-pole bump 51 and the n-pole bump 52 will be described with reference to FIGS. 1-7.

(1) Electroplating current circuit

In the fabrication of the optical semiconductor device 10, a p-n junction wafer is used. The p-n junction wafer to which the cathode 30 is connected and the anode plate 81 to which the anode 80 is connected are immersed in a plating solution, and plating is performed by circulating a plating current from an external power source. The equivalent circuit of the plating current circuit at this time is shown in FIG.

The current film 33 and the cathode 30 provided on the p-n junction wafer are actually connected to the same portion. However, since the current film 33 is provided over the entire area of the pn junction wafer, the current path of the n-pole electrode 14a and the p-pole electrode 14b and the cathode 30 is focused on the case of one set of the n-electrode electrode 14a and the p-pole electrode 14b. There are countless places. In the present embodiment, for the sake of simplicity, Figure 3 is shown in the form of a cross-sectional view shown in Fig. 2. In the element of the state of (d) of FIG. 2, the plating current flows from the n-electrode electrode 14a and the p-electrode electrode 14b to the left and right ends of the current film 33. To show this, in FIG. 3, two cathodes 30 are drawn on the outer side of the opening 21.

The anode 80 and the anode plate 81 are actually connected to the same portion. However, in order to be in a form corresponding to the cathode 30, the anode 80 is also present on both ends of the anode plate 81 (see FIG. 3).

The cathode 30 is connected to the current film 33 at the outer periphery of the p-n junction wafer. A pattern is formed on the p-n junction wafer in which a plurality of optical semiconductor elements 10 can be formed. Therefore, a plurality of openings 21 and recesses 22 are provided on the p-n junction wafer, and the current film 33 and the n-type layer 12 are electrically connected to the respective openings 21 and 22. Therefore, the current path from the cathode 30 to the opening portion 21 includes the current film 33 and the n-type layer 12. However, for simplification of explanation, the current path from the cathode 30 to the opening portion 21 is omitted, and is shown in Fig. 3 as a non-resistance component. In addition, the recess 22 is also not illustrated in FIG. 3 for simplicity of explanation.

The n-electrode electrode 14a and the p-pole electrode 14b and the anode plate 81 are electrically connected via a plating solution. In Fig. 3, the resistance value of the plating solution is R _bath .

The two opening portions 21 shown in Fig. 3 correspond to the two opening portions 21 of Fig. 2(d). In (d) of FIG. 2, a current film 33 is provided between the two openings 21 and the grooves 22, and an n-pole electrode 14a and a p-pole electrode 14b are present in the middle of the current film 33. In other words, the two openings 21 and the recesses 22, the n-electrode electrode 14a, and the p-electrode 14b are electrically connected to each other via the current film 33. 14a and 14b in Fig. 3 show an n-electrode electrode 14a and a p-electrode electrode 14b, and _Rcf represents a resistance value of the current film 33.

The plating current flows through the current film 33, and also flows through the opening portion 21 and the groove 22 to the n-type layer 12. In the opening portion 21, at the interface where the current film 33 and the n-type layer 12 are in contact, there is a connection resistance R _op . The larger the surface area of the opening portion 21 and the recess 22, the larger the contact area between the current film 33 and the n-type layer 12 is, so the smaller the R _{op is} . In Fig. 3, R ₁ is the resistance value of the n-type layer 12. By causing a plating current to flow through the current film 33 and the n-type layer 12, a parallel circuit is formed between the n-electrode electrode 14a and the opening portion 21 (see FIG. 3). On the other hand, the p-electrode electrode 14b and the opening portion 21 are electrically connected only by the current film 33.

A parallel circuit including R _cf , R _{1 ,} and R _op is formed between the n-electrode 14 a and the opening 21 , and a series circuit including only R _cf is formed between the p-electrode 14 b and the opening 21 . Therefore, the resistance value between the n-electrode electrode 14a and the opening portion 21 is smaller than the resistance value between the p-electrode electrode 14b and the opening portion 21.

A plating current larger than that of the p-electrode 14b flows through the n-electrode electrode 14a, and as a result, the plating rate of the n-electrode electrode 14a is higher than that of the p-electrode electrode 14b. As a result, the thickness of the n-pole bumps 52 is also thicker than the thickness of the p-pole bumps 51. In the present embodiment, the ratio of the plating rate of the n-electrode electrode 14a to the plating rate of the p-electrode electrode 14b is referred to as a plating ratio.

(2) Electroplating rate ratio control

By applying a difference between the resistance value between the n-electrode electrode 14a and the opening portion 21 and the resistance value between the p-electrode electrode 14b and the opening portion 21, the plating current flowing through the n-electrode electrode 14a and the p-electrode electrode 14b is given. And poor. Thus, by controlling the resistance between the n-electrode 14a and the opening 21 and the resistance between the p-electrode 14b and the opening 21, the plating of the n-electrode 14a and the p-electrode 14b can be controlled. rate. The resistance value between the n-electrode electrode 14a and the opening portion 21 and the resistance value of the resistance value between the p-electrode electrode 14b and the opening portion 21 are preferably about 10% of the resistance value between the n-electrode electrode 14a and the opening portion 21. As a result, the ratio of the plating rate of the n-electrode electrode 14a to the plating rate of the p-electrode electrode 14b can be effectively controlled.

The sheet resistance of the n-type layer 12 of the p-n junction wafer used in the fabrication of the optical semiconductor device 10 is 1 to 20 Ω/□. Therefore, the sheet resistance of the current film 33 is preferably in the range of 10 mΩ/□ to 1000 mΩ/□, and more preferably 50 mΩ/□ to 200 mΩ/□. The sheet resistance of the current film 33 depends on the film thickness of the current film 33. When the film thickness is increased, the sheet resistance becomes small, and if the film thickness is decreased, the sheet resistance becomes large.

Thus, the sheet resistance of the current film 33 can be controlled by using the film thickness of the current film 33 as a parameter. By setting the sheet resistance of the current film 33 to the above range, the difference between the resistance value between the n-electrode electrode 14a and the opening portion 21 and the resistance value between the p-electrode electrode 14b and the opening portion 21 can be set to about 10%. .

When the sheet resistance of the current film 33 is small, the plating current mostly flows through the current film 33. Therefore, the difference between the plating currents flowing through the n-electrode electrode 14a and the p-electrode electrode 14b becomes small, and the plating ratio becomes a value close to 1. When the sheet resistance of the current film 33 is large, the plating current flowing through the n-type layer 12 increases, and the difference between the plating currents flowing through the n-electrode electrode 14a and the p-electrode electrode 14b becomes large. Therefore, the plating ratio becomes a value larger than 1. Thus, by changing the film thickness of the current film 33, the plating rate ratio can be changed. Therefore, by setting the film thickness of the current film 33 to an appropriate value, the p-pole bumps 51 and the n-pole bumps 52 having no step difference therebetween can be formed.

As another method of imparting a difference between the resistance value between the n-electrode electrode 14a and the opening portion 21 and the resistance value between the p-electrode electrode 14b and the opening portion 21, the connection resistance _{Rop of the} current film 33 and the n-type layer 12 may be changed. . Even when R _cf is the same as R ₁ , as long as R _op becomes large, the resistance value between the n-electrode electrode 14a and the opening portion 21 becomes large. On the contrary, when R _op becomes small, the resistance value between the n-electrode electrode 14a and the opening portion 21 also becomes small. On the other hand, even if R _op changes, the resistance value between the p-electrode electrode 14b and the opening portion 21 does not change. R _op depends on the surface area of the opening 21 and the recess 22, so that the resistance between the n-electrode 14a and the opening 21 and the resistance between the p-electrode 14b and the opening 21 can be changed by changing the surface area. The ratio of values. In other words, by designing the pattern size of the opening portion 21 to an arbitrary size, the plating ratio can be controlled (refer to FIG. 6). The area ratio of the opening portion of Fig. 6 is the ratio of the area of the area formed by the n-type layer 12 to the surface area of the opening portion 21.

As described above, the surface area of the opening portion 21 is preferably a surface area of the p-pole bump 51 and the n-pole bump 52 which can be formed by plating without stepping therebetween. According to this configuration, when the optical semiconductor element 10 is manufactured, the p-pole bumps 51 and the n-pole bumps 52 having no step difference therebetween can be surely formed.

also. The surface area of the recess 22 is preferably a surface area of the p-pole bump 51 and the n-pole bump 52 which can be formed by electroplating without stepping between them. According to this configuration, when the optical semiconductor element 10 is manufactured, the p-pole bumps 51 and the n-pole bumps 52 having no step difference therebetween can be surely formed.

As described above, by controlling the plating current flowing through the n-electrode electrode 14a and the p-electrode electrode 14b, the plating ratio of the n-pole bump 52 and the p-pole bump 51 can be changed. However, in order to eliminate the step difference between the n-type layer 12 and the p-type layer 13, the upper surfaces of the n-pole bump 52 and the p-pole bump 51 are set to the same height, which requires more precision. The plating rate is controlled.

In order to control the plating ratio more precisely, in the method of manufacturing an optical semiconductor device according to an embodiment of the present application, a driving waveform of a plating current is used as a pulse waveform. The plating ratio can be controlled by changing the pulse period of the pulse waveform.

The step of the upper surface of the n-electrode electrode 14a and the p-pole electrode 14b is D, and the height of the desired p-pole bump 51 is H. The ratio of the plating rate of the n-electrode electrode 14a to the plating rate of the p-electrode electrode 14b is set to be the plating ratio R. At this time, the plating ratio R is required to form the upper surfaces of the p-pole bumps 51 and the n-pole bumps 52 at the same height.

The R=(H+D)/H plating ratio is proportional to the pulse period dependency, and may be measured in advance, for example, as shown in FIG. The pulse period of the plating current corresponding to the desired R is selected at the time of bump formation of the optical semiconductor element 10 using the pre-measured plating ratio as compared with the pulse period dependency. By forming the bumps using the pulse period thus selected, the optical semiconductor element 10 in which the upper surfaces of the p-pole bumps 51 and the n-pole bumps 52 are formed at the same height can be obtained.

By making the driving waveform of the plating current into a pulse waveform, in addition to the precise control of the plating rate ratio, it is possible to prevent the formed bump from becoming an abnormal plating state of so-called burnt plating. FIG. 5 shows a p-pole bump 51 and an n-pole bump 152. It is shown that the p-pole bumps 51 represent the bumps formed normally, and the n-pole bumps 152 represent the examples of the bumps in the state of the so-called burnt plating. The scorch plating is an abnormality that is easily generated in electroplating due to a plating current of a large current flowing for a long period of time. In the method of manufacturing an optical semiconductor device according to the embodiment, the n-pole is electrically A larger current is flown through the pole 14a than the p-pole electrode 14b. In the state where a large plating current flows in the n-electrode electrode 14a, in the case where the driving waveform is a DC waveform, the bump formed may be burnt-plated. This possibility can be eliminated by making the driving waveform of the plating current a pulse waveform.

(3) Pulse period

In the method of manufacturing an optical semiconductor device according to an embodiment of the present invention, it is more preferable that the driving waveform of the plating current is a pulse waveform, and the pulse period is in the range of 0.1 second to 100 seconds. The plating rate shown in Fig. 4 is more dependent on the pulse period dependency, and the plating ratio is in the range of 0.1 second to 100 seconds, and the plating ratio is more dependent on the pulse period. Therefore, by setting the pulse period of the plating current to be in the range of 0.1 second to 100 seconds, the desired plating ratio can be obtained.

Immediately after the plating current is applied, an electric double layer is formed on the surfaces of the n-electrode electrode 14a and the p-pole electrode 14b. Immediately after the application of the plating current, it becomes a transition state for charging the electric double layer charging plating current (illegal pulling current), and the current value of the plating current converges to a specific value after about 30 seconds. The plating ratio is controlled in the method of manufacturing an optical semiconductor device according to an embodiment of the present invention by utilizing the transition state of the plating state. By making the plating current a pulse waveform, the transition state of the plating current can be repeatedly used. Therefore, the plating ratio can be surely controlled.

(4) Work cycle ratio

In the method of manufacturing an optical semiconductor device according to an embodiment of the present invention, it is more preferable that the duty cycle ratio of the pulse period is 80% or more, or the stop time of the plating current of the pulse period is 2 seconds or less. Manufacturing optical semiconductor components At the time of output efficiency, the time required for forming bumps by electroplating (as plating time) is as short as possible. From the viewpoint of shortening the plating time, it is preferred to use a DC waveform plating (as a DC plating), but it is not possible to control the plating ratio. Furthermore, there is a possibility that the plating current is stably circulated to cause burnt plating. The electroplating current of the pulse waveform is used for electroplating, and the duty cycle ratio of the pulse waveform is set to be 80% or more. Therefore, in addition to controlling the plating ratio, the increase of the plating time can be controlled within 20% with respect to the DC plating. In order to increase the output, although it is desirable to increase the duty cycle ratio, setting a value close to 100% will increase the possibility of causing burnt plating. The duty cycle is less than 100% of the upper limit value, and is a value that excludes the possibility of causing burnt plating.

Further, by setting the stop time of the plating current for one cycle of the pulse waveform to 2 seconds or less, the plating rate ratio can be controlled to minimize the decrease in output, and the formation of scorch plating can be prevented. The lower limit of the stop time of the plating current is a value greater than 0 seconds, and is a value excluding the possibility of causing burnt plating.

(5) Electroplating current density

In the method of manufacturing an optical semiconductor device according to an embodiment of the present invention, the plating ratio is changed by changing the current density of the plating current having a pulse waveform. In other words, as a parameter for controlling the plating rate ratio, the current density of the plating current can be used.

The range of current density at which good plating can be produced varies depending on the type of plating solution used for electroplating, and the plating solution conditions represented by the pH, temperature, and presence or absence of stirring of the plating solution. However, by making the current density change In the case of controlling the plating ratio, the current density may be in a range that satisfies the range from the lower limit value to the upper limit value of the critical current density described later. In other words, the range of the current density is within the range from the lower limit of the critical current density to the upper limit.

The critical current density refers to an upper limit and a lower limit of the current density at which a normal coating film is produced when a coating film is formed by electroplating. Gloss plating is produced when the current density at the time of electroplating is lower than the lower limit of the critical current density, and on the other hand, scorch plating (discoloration of the surface, stain) occurs when the upper limit of the critical current density is exceeded. Gloss plating and charring plating are not good, so avoid it.

By making the current density at the time of plating larger than the lower limit of the critical electric density, plating can be normally performed on the n-electrode electrode 14a and the p-electrode electrode 14b as the surface to be plated. Further, by making the current density smaller than the upper limit of the critical electric density, it is possible to prevent the occurrence of an abnormal plating state called scorch plating. Thereby, the p-pole bumps 51 and the n-pole bumps 52 of a normal shape can be formed. Further, by setting the current density to a suitable value in the range from the lower limit value of the critical current density to the upper limit value, the p-pole bump 51 and the n-pole bump 52 having no step difference therebetween can be formed.

[Example 1]

In the method of manufacturing the optical semiconductor device 10 according to the embodiment of the present invention, the measurement results of the plating rate ratio and the pulse period dependency are shown in Fig. 4 . The manufacturing method of the optical semiconductor element 10 is based on the manufacturing method shown in FIG. After the steps (a) to (d) of Fig. 2, bumps are formed by electroplating (refer to Fig. 2 (e)). When the bump is formed, the pulse frequency of the plating current as the pulse waveform is varied in the range of 0.1 second to 1000 seconds, and the ratio of the thickness of the n-pole bump 52 to the thickness of the p-pole bump 51 is used as the plating ratio. Shown in Figure 4.

The measured values are indicated by open circles in Fig. 4. The wavy line is obtained as a result of fitting the measured values. The plating ratio obtained by direct current plating is shown by a solid line.

As can be seen from the results of Fig. 4, the plating ratio is greatly changed from about 1.00 to 1.25 in the range of the pulse period of the plating current from 0.1 second to 100 seconds. Therefore, by selecting the pulse period of the plating current from the range of 0.1 second to 100 seconds, a suitable plating ratio can be obtained.

In order to determine the pulse period of the plating current, first, the necessary plating ratio is determined according to the step difference between the n-electrode electrode 14a and the p-electrode electrode 14b and the thickness of the p-pole bump 51 to be formed. Thereafter, the above-mentioned necessary plating ratio is read from the corresponding pulse period in FIG.

[Embodiment 2]

In the method of manufacturing the optical semiconductor device 10 according to the embodiment of the present invention, an experimental result of measuring the relationship between the area ratio of the opening portion 21 and the plating ratio is shown in Fig. 6 . The plating conditions of this embodiment are as follows.

. Plating solution: non-cyano type gold plating solution made of EEJA

. Electroplating bath temperature: 52 ° C

. Plating current density: DC 6 mA/cm ²

. Electroplated material: wafer for optical semiconductor device fabrication (6 inch)

Under the above conditions, the wafer was formed using the wafer having no opening 21 (opening ratio: 0%) and the wafer on which the opening 21 was formed (opening ratio: 6%). As a result, as shown in FIG. 6, when the area ratio of the opening portion 21 is 0% (opening ratio 0%), the plating ratio is about 1.00, and the area ratio of the opening portion 21 is 6% (opening ratio 6%). In the case of the case, the plating ratio is about 1.30. in this way It can be seen that the plating ratio can be controlled by changing the area ratio of the opening portion 21.

[Example 3]

In the method of manufacturing the optical semiconductor device 10 according to the embodiment of the present invention, the result of measuring the plating ratio to the current density dependency is shown in Fig. 7 . The plating conditions of this embodiment are as follows.

. Plating solution: non-cyano type gold plating solution made of EEJA

. Electroplating bath temperature: 52 ° C

. Pulse period: 1 second

. Work cycle ratio: 80%

. Electroplated material: wafer for optical semiconductor device fabrication (6 inch)

. Plating current: variable from 3.5 mA/cm ² to 11 mA/cm ²

The critical current density of the above plating conditions ranges from 2 mA/cm ² to 8 mA/cm ² . Electroplating was performed by changing the current density of the plating current in the range of 3.5 mA/cm ² to 11 mA/cm ² . Electroplating is still performed under conditions exceeding the critical current density to confirm the influence of current density on the formed bumps. As a result of the experiment, the resulting electroplating rate was varied from about 1.45 to 1.10, and there was a clear negative correlation between the electroplating ratio and the current density (Fig. 7). Further, it can be seen that a desired plating ratio can be obtained by varying the current density of the plating current within the range of the critical current density.

[Example 4]

In the method for producing an optical semiconductor device 10 according to an embodiment of the present invention, an experimental result of measuring the relationship between the sheet resistance of the current film 33 and the plating ratio is shown in FIG. The plating conditions of this embodiment are as follows.

. Plating solution: non-cyano type gold plating solution made of EEJA

. Electroplating bath temperature: 50 ° C

. Plating current density: DC 6 mA/cm ²

. Electroplated material: wafer for optical semiconductor device fabrication (6 inch)

Under the above conditions, the values of the sheet resistances of the various current films 33 were varied, and the plating ratio was measured. When the value of the sheet resistance is changed, the film thickness of the current film 33 is changed. As a result of the experiment, a sheet resistance of 10 mΩ/□ or more was obtained, and the higher the sheet resistance, the higher the plating ratio. That is, it was found that the sheet resistance and the plating ratio were positively correlated. Thus, it can be seen that the plating ratio can be controlled by varying the sheet resistance of the current film 33. In addition, the sheet resistance is 200 mΩ/□ or more, resulting in the result of burnt plating of the n-pole.

[Embodiment 2]

An optical semiconductor device 60 according to an embodiment of the present invention will be described with reference to Figs. 9 and 10 . The same components as those in the first embodiment are denoted by the same reference numerals, and their description will be omitted.

(Opto Semiconductor Element 60)

The optical semiconductor element 60 is a modification of the optical semiconductor element 10 of the first embodiment. The optical semiconductor element 10 is different from the optical semiconductor element 60 in that the optical semiconductor element 60 has an n-type layer 62 (first conductive type semiconductor layer) and an optical semiconductor element 10 having an n-type layer 12 shape (refer to FIG. 9). ). The n-type layer 62 of the optical semiconductor element 60 does not have a special structure in a region corresponding to the opening portion 21 of the protective film 15. That is, in the region corresponding to the opening portion 21, the upper surface of the n-type layer 62 is a flat surface.

The configuration other than the shape of the n-type layer is common to the optical semiconductor element 10 and the optical semiconductor element 60.

The thickness of the n-pole bump 52 is formed thicker than the thickness of the p-pole bump 51, and the step on the upper surface of the n-type layer 12 and the p-type layer 13 is eliminated. Since the upper surfaces of the n-pole bumps 52 and the p-pole bumps 51 are formed at the same height, the optical semiconductor element 60 of one embodiment of the present invention can be suitably mounted with a flip chip.

(Method of Manufacturing Optical Semiconductor Element 60)

A method of fabricating the optical semiconductor element 60 will be described with reference to FIG. Regarding the manufacturing method, the optical semiconductor element 60 is the same as the optical semiconductor element 10.

A p-n junction wafer in which an n-type layer 62 and a p-type layer 13 are deposited from the sapphire substrate 11 is left, and one portion of the p-type layer 13 is left to selectively etch the n-type layer 62. An n-electrode electrode 14a and a p-pole electrode 14b are formed on the upper surface of the n-type layer 62 and the p-type layer 13, and a protective film 15 having an opening portion 21 is formed on a portion of the upper surface of the n-type layer 62 (refer to the figure). 10(a)). At this time, the n-type layer 62 does not have a groove, and the upper surface of the n-type layer 62 is a flat surface.

Then, the lower current film 31 and the upper current film 32 are sequentially formed as the current film 33 ((b) of FIG. 10).

After the current film 33 is formed, the following steps are sequentially performed. The photoresist 41 is applied (refer to (c) of FIG. 10). The bump forming pattern 42 is formed by photolithography ((d) of FIG. 10). The p-pole bumps 51 and the n-pole bumps 52 are formed by plating using a driving current of a pulse waveform (refer to (e) of FIG. 10). The photoresist 41 is removed using an organic solvent (refer to (f) of FIG. 10). The unnecessary portion of the current film 33 is removed by etching (refer to (g) of FIG. 10). The optical semiconductor element 60 is completed by the above steps.

After the current film 33 is formed, even if the upper surface of the n-type layer 62 is flat, the current film 33 is brought into contact with the n-type layer 62 via the opening portion 21 to be electrically connected. because Thus, the current path from the opening portion 21 to the n-pole electrode 14a is a parallel circuit including the current film 33 and the n-type layer 62. On the other hand, the current path from the opening portion 21 to the p-pole electrode 14b is only the current film 33.

Therefore, the resistance value of the opening portion 21 to the n-pole electrode 14a is smaller than the resistance value of the opening portion 21 to the p-pole electrode 14b. Since a plating current larger than that of the p-electrode 14b flows through the n-electrode electrode 14a, the plating rate of the n-electrode electrode 14a is higher than that of the p-electrode electrode 14b.

The driving waveform of the plating uses a pulse waveform to change the pulse period, whereby the plating ratio of the plating rate of the n-electrode electrode 14a and the plating rate of the p-electrode electrode 14b can be controlled. Therefore, the optical semiconductor element 60 is a size that does not constrain the size of the n-pole bump 52 and the p-pole bump 51, absorbs the step on the surface of the semiconductor substrate, and is suitable for flip-chip mounted optical semiconductor elements.

(to sum up)

In order to solve the above problems, an optical semiconductor device according to an aspect of the present invention includes a first semiconductor layer including a semiconductor of a first conductivity type, and a second semiconductor layer including a semiconductor of a second conductivity type, and a portion formed on an upper surface of the first semiconductor layer; a first electrode formed on the upper surface of the first semiconductor layer; and a second electrode formed on the second semiconductor layer a surface having an upper surface located higher than a surface of the first electrode; a first connection electrode formed on an upper surface of the first electrode; and a second connection electrode formed on the second electrode Upper surface; and The protective film covers an insulating protective film covering the surface of the first semiconductor layer and the surface of the second semiconductor layer, and has an opening that exposes a part of the surface of the first semiconductor layer.

In order to solve the above problems, a method for manufacturing an optical semiconductor device according to an aspect of the present invention includes the step of forming a conductive current film on an entire surface of an upper surface of an optical semiconductor substrate, the optical semiconductor substrate including a substrate; a first semiconductor layer including a semiconductor of a first conductivity type formed on an upper surface of the substrate; and a second semiconductor layer including a semiconductor of a second conductivity type and formed on a surface of the upper surface of the first semiconductor layer a semiconductor layer; a first electrode formed on the other surface of the upper surface of the first semiconductor layer; formed on the upper surface of the second semiconductor layer and having a higher position than the upper surface of the first electrode a second electrode on the upper surface; and an insulating protective film covering the surface of the first semiconductor layer and the surface of the second semiconductor layer, and having an opening for exposing a part of the surface of the first semiconductor layer a protective film; and after forming the current film, forming a first connection electrode on the upper surface of the first electrode by plating the photo-semiconductor substrate, and forming a surface on the upper surface of the second electrode The second step of connecting the electrodes.

According to the above configuration, in the optical semiconductor device according to the aspect of the invention, the protective film covers the surface of the first semiconductor layer and the surface of the second semiconductor layer. Further, the protective film has an opening that exposes a part of the surface of the first semiconductor layer.

When the optical semiconductor element of this configuration is manufactured, the first connection electrode and the second connection electrode are formed by using electroplating. Specifically, in the optical semiconductor base A current film is formed on the entire surface of the upper surface of the board, and then a photoresist pattern opening the first and second electrodes is formed, and then a plating current is applied to the optical semiconductor element.

Here, the first electrode and the current film are directly electrically connected. Further, the first semiconductor layer that is electrically connected to the first electrode is electrically connected to the current film through the opening of the protective film. From this, it is understood that a plating current flows from both the first electrode to the current film and the first semiconductor layer.

On the other hand, the second electrode is directly electrically connected to the current film, but the second semiconductor layer that is electrically connected to the second electrode is not electrically connected to the current film. Therefore, only the plating current flows from the second electrode to the current film.

As described above, when the optical semiconductor substrate is plated, the plating current flowing through the first electrode side is the second electrode side. As a result, by controlling the parameters of the plating current flowing through the optical semiconductor element, the first connection electrode and the second connection electrode which absorb the step difference between the first electrode and the second electrode without forming a step can be formed. In this case, as long as the parameters of the plating current are controlled, the dimensions of the first connection electrode and the second connection electrode are not subject to any restriction.

Therefore, according to the method of manufacturing an optical semiconductor device according to an aspect of the present invention, the first connection electrode and the second connection electrode which are suitable for flip chip mounting without stepping therebetween can be formed without constraining the size of each connection electrode. . Further, according to the optical semiconductor device of one aspect of the present invention, it is possible to realize an optical semiconductor element having a first connection electrode and a second connection electrode which are suitable for flip chip mounting without stepping therebetween.

Further, in an optical semiconductor device according to an aspect of the present invention, it is preferable that a surface area of the opening portion is formed by plating. The surface area of the first connection electrode and the second connection electrode without step difference therebetween.

According to the above configuration, when the optical semiconductor element of one aspect of the present invention is manufactured, the first connection electrode and the second connection electrode which are free from each other can be reliably formed.

Further, in an optical semiconductor device according to an aspect of the invention, it is preferable that a groove is formed at a position corresponding to the opening of the first semiconductor layer.

According to the above configuration, since the optical semiconductor element is cut by the recess, the optical semiconductor element can be divided into a specific size without causing defects on the first semiconductor layer.

Further, in the optical semiconductor device according to an aspect of the invention, it is preferable that the surface area of the groove is such that the surface areas of the first connection electrode and the second connection electrode which are formed without any step difference by plating are formed.

According to the above configuration, when the optical semiconductor element of one aspect of the present invention is manufactured, the first connection electrode and the second connection electrode having no step difference therebetween can be reliably formed.

Further, in the method of manufacturing an optical semiconductor device according to an aspect of the present invention, it is preferable that the optical semiconductor element is plated by a plating current of a pulse waveform.

According to the above configuration, by controlling various parameters of the plating current, the ratio of the plating rate of the first electrode to the plating rate of the second electrode can be efficiently controlled.

Moreover, a method of manufacturing an optical semiconductor device according to an aspect of the present invention is further Preferably, the period of the pulse waveform is in the range of 0.1 to 100 seconds.

According to the above configuration, the ratio of the plating rate of the first electrode to the plating rate of the second electrode can be efficiently controlled. The reason is as follows. When a plating current is applied to the optical semiconductor substrate, the transitional change in the plating solution resistance converges within 30 seconds. Therefore, if the pulse waveform is in the range of 0.1 to 100 seconds, the effect of the pulse waveform being variable can be obtained.

Further, in the method of manufacturing an optical semiconductor device according to one aspect of the invention, it is preferable that the duty cycle ratio of the pulse waveform is 80% or more.

According to the above configuration, the ratio of the plating rate of the first electrode to the plating rate of the second electrode can be efficiently controlled.

Further, in the method of manufacturing an optical semiconductor device according to an aspect of the invention, it is preferable that a current stop time of each of the pulse waveforms is 2 seconds or shorter.

According to the above configuration, the ratio of the plating rate of the first electrode to the plating rate of the second electrode can be efficiently controlled.

Further, in the method of manufacturing an optical semiconductor device according to an aspect of the invention, it is preferable that the sheet resistance of the current film is in the range of 10 to 1000 mΩ/□.

According to the above configuration, the sheet resistance of the current film is in the range of 10 to 1000 mΩ/□. Here, the sheet of the first semiconductor layer of the optical semiconductor substrate The resistance is in the range of 1 to 20 mΩ/□. Therefore, the difference between the combined resistance of the path through which the plating current flows in the first electrode side and the path of the plating current flowing through the second electrode side can be made 10% of the combined resistance on the first electrode side. As a result, the ratio of the plating rate of the first electrode to the plating rate of the second electrode can be efficiently controlled.

Further, in the method of manufacturing an optical semiconductor device according to an aspect of the present invention, it is preferable that the current density of the plating current on the surface of the plating is performed by the plating current of the pulse waveform to satisfy the self-critical current density. The range from the lower limit to the upper limit.

According to the above configuration, the first connection electrode and the second connection electrode of the normal shape can be formed. Further, by changing the current density in this range, the plating ratio can be changed. Therefore, by setting the current density to an appropriate value, the first connection electrode and the second connection electrode having no step difference therebetween can be formed.

Further, in the method of manufacturing an optical semiconductor device according to an aspect of the present invention, it is preferable that the step of forming the continuous electrode is performed in accordance with a film thickness of the current film formed in the step of forming the current film. The ratio of the plating rate of the first electrode to the second electrode is higher.

According to the above configuration, the plating ratio can be changed by changing the film thickness of the current film. Therefore, by setting the film thickness of the current film to an appropriate value, the first connection electrode and the second connection electrode having no step difference therebetween can be formed.

Moreover, a method of manufacturing an optical semiconductor device according to an aspect of the present invention is further Preferably, when the optical semiconductor element is plated, a metal selected from gold, silver, platinum, copper, palladium, nickel, solder, and the like is used.

According to the above configuration, it is possible to manufacture an optical semiconductor element having the first connection electrode and the second connection electrode which are more excellent in ohmic characteristics and suitable for flip chip mounting.

The present invention is not limited to the embodiments described above, and various modifications can be made without departing from the scope of the invention. The embodiments obtained by appropriately combining the technical means disclosed in the different embodiments are also included in the technology of the present invention. range.

[Industrial availability]

The present invention can be widely used as an optical semiconductor element such as a light emitting diode (LED). Moreover, it can also be utilized as a method of manufacturing such an optical semiconductor element.

10‧‧‧Optical semiconductor components

11‧‧‧Sapphire substrate (insulating transparent substrate)

12‧‧‧n type layer (first conductivity type semiconductor layer)

13‧‧‧p-type layer (second conductivity type semiconductor layer)

14a‧‧‧n pole electrode (first electrode)

14b‧‧‧p pole electrode (2nd electrode)

15‧‧‧Protective film

21‧‧‧ openings

22‧‧‧ Groove

30‧‧‧ cathode

31‧‧‧Under current film

32‧‧‧Upper current film

33‧‧‧current film

41‧‧‧Light resistance

42‧‧‧Bump formation pattern

51‧‧‧p pole bump (2nd connecting electrode)

52‧‧‧n pole bump (first connecting electrode)

60‧‧‧Optical semiconductor components

62‧‧‧n type layer (first conductivity type semiconductor layer)

80‧‧‧Anode

81‧‧‧Anode plate

152‧‧‧n pole bump

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic cross-sectional view showing an optical semiconductor device according to an embodiment of the present invention.

2(a) to 2(g) are schematic cross-sectional views showing a method of manufacturing an optical semiconductor device according to an embodiment of the present invention.

Fig. 3 is a view showing an equivalent circuit of a plating current circuit when a bump is formed by plating in a method of manufacturing an optical semiconductor device according to an embodiment of the present invention. R _cf represents the resistance value of the current film, R ₁ represents the resistance value of the first conductivity type semiconductor layer, R _op represents the connection resistance of the current film of the opening portion and the first conductivity type semiconductor layer, and R _bath represents the resistance of the plating solution. value.

Figure 4 shows the pulse period of the ratio of the plating rate of the n-pole to the plating rate of the p-pole. A map of dependence. The open circle shows the measured value. The wavy line is a curve obtained as a result of fitting the measured values. The solid line shows the plating ratio obtained by using the plating current of DC.

Fig. 5 is a cross-sectional view showing the shape of a bump formed by direct current plating.

Fig. 6 is a graph showing the ratio of the plating ratio to the area ratio of the opening in an embodiment of the present invention.

Fig. 7 is a graph showing the dependence of the plating rate ratio on the current density in an embodiment of the present invention.

Fig. 8 is a graph showing the results of an experiment for measuring the relationship between the sheet resistance of the current film 33 and the plating ratio in an embodiment of the present invention.

Fig. 9 is a schematic cross-sectional view showing an optical semiconductor device according to an embodiment of the present invention.

Figs. 10(a) through 10(g) are schematic cross sectional views showing a method of fabricating an optical semiconductor device according to another embodiment of the present invention.

10‧‧‧Optical semiconductor components

11‧‧‧Sapphire substrate

12‧‧‧n-type layer

13‧‧‧p-type layer

14a‧‧‧ pole electrode

14b‧‧‧p pole electrode

15‧‧‧Protective film

21‧‧‧ openings

22‧‧‧ Groove

31‧‧‧Under current film

32‧‧‧Upper current film

33‧‧‧current film

51‧‧‧p pole bump

52‧‧‧n pole bump

Claims (13)

An optical semiconductor device comprising: a first semiconductor layer including a semiconductor of a first conductivity type; and a second semiconductor layer comprising a semiconductor of a second conductivity type formed on an upper surface of the first semiconductor layer a first electrode formed on the upper surface of the upper surface of the first semiconductor layer; and a second electrode formed on the upper surface of the second semiconductor layer and having a position higher than the first electrode An upper surface having a higher upper surface; a first connection electrode formed on the upper surface of the first electrode; a second connection electrode formed on an upper surface of the second electrode; and a protective film covering the surface The insulating protective film on the surface of the first semiconductor layer and the surface of the second semiconductor layer has an opening that exposes a part of the surface of the first semiconductor layer. The optical semiconductor device according to claim 1, wherein the surface area of the opening portion is a surface area of the first connection electrode and the second connection electrode which are formed by plating to form a step difference between the first connection electrode and the second connection electrode. An optical semiconductor device according to claim 1, wherein a groove is formed at a position corresponding to the opening of the first semiconductor layer. The optical semiconductor device according to claim 3, wherein the surface area of the recess is a surface area of the first connection electrode and the second connection electrode which are formed by electroplating to have no step difference therebetween. A method of fabricating an optical semiconductor device, comprising: forming a conductive electric current on an entire surface of an upper surface of an optical semiconductor substrate a step of flowing a thin film comprising: a substrate; a first semiconductor layer including a semiconductor of a first conductivity type formed on an upper surface of the substrate; and a semiconductor including a second conductivity type formed on the first semiconductor layer a second semiconductor layer on a portion of the upper surface; a first electrode formed on the other surface of the upper surface of the first semiconductor layer; formed on the upper surface of the second semiconductor layer; a second electrode on the upper surface of the upper surface of the electrode, and an insulating protective film covering the surface of the first semiconductor layer and the surface of the second semiconductor layer, and having the first semiconductor layer a protective film for the exposed portion of the surface; and after forming the current film, the first connection electrode is formed on the upper surface of the first electrode by plating the photo-semiconductor substrate, and above the second electrode The step of forming the second connection electrode on the surface. A method of manufacturing an optical semiconductor device according to claim 5, wherein the optical semiconductor element is plated by circulating a plating current of a pulse waveform. The method of manufacturing an optical semiconductor device according to claim 6, wherein the period of the pulse waveform is in a range of 0.1 to 100 seconds. A method of manufacturing an optical semiconductor device according to claim 6, wherein a duty cycle ratio of said pulse waveform is 80% or more. The method of manufacturing an optical semiconductor device according to claim 6, wherein the current of each of the pulse waveforms has a stop time of 2 seconds or less. The method of producing an optical semiconductor device according to claim 6, wherein the sheet resistance of the current film is in the range of 10 to 1000 mΩ/□. A method of manufacturing an optical semiconductor component according to claim 6, wherein the above The current density of the plating current on the surface of the electroplated current of the pulse waveform is a range satisfying the range from the lower limit value to the upper limit value of the self-critical current density. The method of manufacturing an optical semiconductor device according to claim 5, wherein the plating of the first electrode and the second electrode in the step of forming the connection electrode is determined according to a film thickness of the current film formed in the step of forming the current film Rate ratio. A method of producing an optical semiconductor device according to claim 5, wherein a metal selected from the group consisting of gold, silver, platinum, copper, palladium, nickel, solder, and the like is used for plating the above-mentioned optical semiconductor element.