CN116885084B - LED chip with package substrate and preparation method thereof - Google Patents
LED chip with package substrate and preparation method thereof Download PDFInfo
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- CN116885084B CN116885084B CN202311146970.8A CN202311146970A CN116885084B CN 116885084 B CN116885084 B CN 116885084B CN 202311146970 A CN202311146970 A CN 202311146970A CN 116885084 B CN116885084 B CN 116885084B
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 7
- 229910052802 copper Inorganic materials 0.000 claims description 7
- 238000004519 manufacturing process Methods 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
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- 239000010703 silicon Substances 0.000 claims description 5
- 238000009713 electroplating Methods 0.000 claims description 3
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
- H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
Abstract
The application discloses an LED chip with a package substrate and a preparation method thereof, and belongs to the technical field of semiconductors. Through the integrated preparation of LED chip and encapsulation base plate, solved the big problem of LED chip encapsulation size, in the preparation process, through setting up the through-hole at the encapsulation base plate, and then set up the positive and negative electrode of chip on different faces, set up corresponding extension electrode for positive and negative electrode respectively in encapsulation base plate bottom moreover, the size of welding electrode has been enlarged when not reducing the chip effective area to the LED chip such the more condition of corresponding encapsulation base plate pin has improved the follow-up precision of being connected with other devices.
Description
Technical Field
The application relates to an LED chip with a packaging substrate and a preparation method thereof, and belongs to the technical field of semiconductor packaging.
Background
The LED chip is also called an LED light emitting chip, and is a core component of a display screen, a lighting device, and the like, and currently, the packaging structure of the LED chip mainly includes the following three forms: a normal structure, a flip-chip structure and a vertical structure, wherein,
(1) The LED chip electrode of the forward-mounted structure is positioned at the top end of the forward-mounted structure, and when in packaging, welding spots on the LED chip are connected to pins of the packaging shell through wires, and the pins are connected with other devices through circuits on the substrate, so that the LED chip is connected with an external circuit.
(2) The LED chip electrode of the flip-chip structure is positioned at the bottom end of the flip-chip structure, after the chip preparation is finished, the chip is inverted, and then the electrode of the LED chip is directly connected with a bonding pad on the substrate through a solder ball and the like;
(3) The LED chip electrodes with the vertical structure are respectively positioned at the top end and the bottom end of the LED chip electrode, and when in packaging, the electrode at the bottom end is connected with the substrate through the solder balls, and the electrode at the top end is connected with the substrate through the bonding wires.
According to the description of the LED chip packaging technology, after the existing LED chip and packaging substrate are respectively prepared by adopting independent processes, connection between the LED chip and the packaging substrate is realized by means of external connectors such as bonding wires and/or solder balls, and the packaging structure needs a certain space to accommodate the connectors, so that the whole packaging volume is larger.
Disclosure of Invention
In view of the above problems, the present application provides an LED chip with a package substrate, which can further reduce the package size, and a method for manufacturing an LED chip with a package substrate, which can realize integrated manufacturing of an LED chip and a package substrate, and can simplify the manufacturing process.
In order to achieve the above purpose, the application adopts the following technical scheme:
the utility model provides a from LED chip of taking package substrate, LED chip includes first electrode and second electrode, first electrode, second electrode are located respectively LED chip top, bottom are provided with conductive area in the package substrate, conductive area including run through in package substrate's conductive hole, conductive hole includes first conductive hole and second conductive hole, first electrode is connected with external circuit electricity through corresponding first conductive hole, second electrode is connected with external circuit through corresponding second conductive hole.
Optionally, the LED chips are arranged in an array on the package substrate.
Optionally, the LED chip includes an N-GaN layer, a light emitting layer, a P-GaN layer 1010, an ITO conductive layer, and a first insulating layer sequentially distributed from bottom to top; the first electrode is an N-type electrode and is used for being connected with the N-GaN layer; the second electrode is a P-type electrode and is connected with the P-GaN layer through the ITO conductive layer.
Optionally, the first electrode is located at the bottom end of the N-GaN layer of the LED chip, the second electrode is located at the top end of the first insulating layer of the LED chip, a third conductive hole is provided in the first insulating layer, and the second electrode is electrically connected with the ITO conductive layer through the third conductive hole.
Optionally, the conductive area further includes a conductive area disposed on the top of the package substrate, the conductive area is located at the top end of the first conductive hole, and the first electrode is electrically connected with the first conductive hole through the conductive area.
Optionally, the conductive area further includes a first extension electrode and a second extension electrode disposed at the bottom of the package substrate, the first electrode is electrically connected to the first extension electrode through a corresponding first conductive hole, and the second electrode is electrically connected to the second extension electrode through a corresponding second conductive hole.
The application also provides a preparation method of the LED chip with the package substrate, which comprises the following steps:
step 1, providing a packaging substrate;
step 2, a first conductive hole and a second conductive hole are formed in the packaging substrate, and a conductive metal layer is arranged on the top of the packaging substrate;
step 3, providing a first substrate, and preparing an LED chip on the first substrate, wherein the LED chip comprises an N-GaN layer, a light-emitting layer, a P-GaN layer, an ITO conductive layer and a first insulating layer which are sequentially distributed from bottom to top;
step 4, preparing a second electrode at the top end of the LED chip, wherein in the preparation process, a metal coating is arranged on the first insulating layer, the metal coating comprises a first metal layer, the first metal layer and the conductive metal layer at the top of the packaging substrate are subjected to hot-press bonding to form a bonding metal layer, and the second electrode is prepared on the bonding metal layer; the second electrode is electrically connected with the second conductive hole;
and 5, preparing a first electrode at the bottom end of the LED chip, wherein the first electrode is electrically connected with the first conductive hole.
Optionally, the step 2 includes:
step 2.1, deep silicon etching and perforating are firstly carried out on the non-conductive packaging substrate, and the whole packaging substrate is penetrated; then filling the through holes with conductive copper through a process of sputtering a seed layer and electroplating copper to form conductive holes, wherein the conductive holes comprise first conductive holes and second conductive holes;
and 2.2, preparing a conductive metal layer on the front surface of the packaging substrate, and/or respectively setting at least one corresponding expansion electrode for the first electrode and the second electrode of the LED chip on the back surface of the packaging substrate, wherein the corresponding expansion electrodes are respectively marked as a first expansion electrode and a second expansion electrode.
Optionally, the step 4 includes:
step 4.1, performing metal coating above the first substrate to form a reflecting layer and/or a blocking layer and a first metal layer, wherein the metal coating covers the whole surface including the front surface of the LED chip;
step 4.2, performing para-position hot-press bonding on the conductive metal layer and the first metal layer to form a bonding metal layer;
step 4.3, removing the first substrate;
step 4.4, removing the local area on the back surface of the N-GaN layer, so that the back surface of the first insulating layer and the back surface of the residual N-GaN layer are exposed;
step 4.5, etching the local area of the first insulating layer to expose the bonding metal layer, wherein the exposed bonding metal layer comprises a region to be etched and a conductive region;
and 4.6, etching the region to be etched to expose the back surface of the packaging substrate below the region to be etched, and forming second electrodes distributed at intervals in the row direction.
Optionally, the step 5 includes:
step 5.1, forming a second insulating layer on the back surface of the packaging substrate, wherein the second insulating layer covers the whole surface including the surface of the residual first insulating layer, and carrying out graphical etching on a local area of the second insulating layer to expose the conductive area;
step 5.2, forming a second metal layer on the back surface of the packaging substrate, wherein the second metal layer covers the whole surface including the surface of the rest second insulating layer;
and 5.3, treating the second metal layer by adopting a stripping process to form first electrodes which are distributed at intervals in the column direction.
Optionally, the step 3 includes:
step 3.1, evaporating ITO on the surface of the P-GaN layer to form an ITO conductive layer;
step 3.2, etching the partial area of the ITO conductive layer by adopting a photoetching process to form ITO table tops distributed in an array;
step 3.3, etching the luminous layer, the P-GaN layer and the N-GaN layer local area by adopting a photoetching process, and forming bosses which are arranged in an array on the front surface of the N-GaN layer, wherein the bosses are the LED chips;
step 3.4, growing a reflecting layer and/or a blocking layer and a first insulating layer above the first substrate, wherein the reflecting layer and/or the blocking layer and the first insulating layer cover the whole surface including the front surface of the LED chip;
and 3.5, etching the first insulating layer at the position needing P contact by adopting a photoetching process, and exposing the position needing P contact.
The application has the beneficial effects that:
in the application, the LED chip and the packaging substrate are of an integrated structure, the conducting holes are arranged in the packaging substrate, the first electrode and the second electrode at the top end and the bottom end of the LED chip are respectively connected with an external circuit or a driving IC through the corresponding first conducting holes and the second conducting holes, and the LED chip is not required to be provided with bonding wires and the like, so that the connection operation is simpler and faster, and meanwhile, the packaging size is saved.
In addition, in the preparation process of the LED chip, the integrated preparation of the LED chip and the packaging substrate is realized through the steps 1-5, and in the whole preparation process, the connection of the LED chip and the packaging substrate can be realized through the hot-press bonding of the first metal layer on the LED chip and the conductive metal layer on the top of the packaging substrate, so that the preparation process is greatly simplified; after the LED chip is connected with the packaging substrate, the bonding metal layer is etched, so that a second electrode for being connected with an external circuit can be obtained, the connection of the LED chip with the positive electrode and the negative electrode (namely the first electrode and the second electrode) which are not on the same surface and the corresponding first conductive hole and the second conductive hole in the packaging substrate is realized, and external connecting pieces such as welding wires or welding balls are not required, so that the further reduction of the packaging size of the chip is facilitated, and the miniaturization requirement of an electronic product is met.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of a conductive hole on a package substrate.
Fig. 2 is a schematic view of the location of the bottom extension electrode on the package substrate.
Fig. 3 is a perspective view of the package substrate after the conductive vias are opened.
Fig. 4 is a schematic cross-sectional view of the package substrate after the conductive vias are opened.
Fig. 5 is a structural view of forming an N-GaN layer, a light emitting layer, and a P-GaN layer on a first substrate.
Fig. 6 is a structural diagram of the ITO conductive layer after evaporation.
Fig. 7 is a schematic diagram of etching a partial region of an ITO conductive layer to an N-GaN region.
Fig. 8 is a schematic diagram after etching away the insulating layer at the locations where P-contacts are required.
Fig. 9 is a schematic diagram after vapor deposition of bonding metal.
Fig. 10 is a schematic cross-sectional view of a thermal compression bonding of a conductive metal layer on a front surface of a package substrate and a first metal layer.
Fig. 11 is an overall cross-sectional view after removal of the first substrate.
FIG. 12 is a cross-sectional view of the entire N-GaN layer after ICP etching.
Fig. 13 is a perspective view of the second electrode after formation and reserving a conductive area for subsequent fabrication of the first electrode.
Fig. 14 is a top perspective view of the second insulating layer after it has been grown.
Fig. 15 is a perspective view from above after forming the first electrode.
Fig. 16 is a cross-sectional view corresponding to the direction A-A in fig. 15.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the embodiments of the present application will be described in further detail with reference to the accompanying drawings.
Embodiment one:
the embodiment provides an LED chip with a package substrate, where the LED chip includes a first electrode 103 and a second electrode 104, the first electrode 103 and the second electrode 104 are respectively located at the top and bottom of the LED chip, a conductive region is disposed in the package substrate 101, the conductive region includes a conductive hole penetrating through the package substrate, the conductive hole includes a first conductive hole and a second conductive hole, the first electrode 103 is electrically connected with an external circuit through the corresponding first conductive hole, and the second electrode 104 is connected with the external circuit through the corresponding second conductive hole.
The LED chip comprises an N-GaN layer 108, a light-emitting layer 109, a P-GaN layer 1010, an ITO conductive layer 1011 and a first insulating layer 1012 which are distributed from bottom to top in sequence; the first electrode 103 is an N-type electrode and is used for connecting with the N-GaN layer 108; the second electrode 104 is a P-type electrode and is connected to the P-GaN layer 1010 through the ITO conductive layer 1011.
The first electrode 103 of the LED chip of the package substrate 101 is located at the bottom end of the N-GaN layer 108 of the LED chip, and the second electrode 104 thereof is located at the top end of the first insulating layer 1012 of the LED chip.
The conductive region further includes a conductive region 1017 disposed on the top of the package substrate, the conductive region 1017 is located at the top end of the first conductive hole, and the first electrode 103 is electrically connected to the first conductive hole through the conductive region 1017.
The conductive region further includes a first extension electrode 105 and a second extension electrode 106 disposed at the bottom of the package substrate 101, the first electrode 103 is electrically connected to the first extension electrode 105 through a corresponding first conductive hole, and the second electrode 104 is electrically connected to the second extension electrode 106 through a corresponding second conductive hole.
The preparation method of the LED chip with the package substrate comprises the following steps:
step 1, providing a package substrate 101;
step 2, a first conductive hole and a second conductive hole are formed in the packaging substrate, and a conductive metal layer 102 is arranged on the top of the packaging substrate 101;
step 3, providing a first substrate 107, and preparing an LED chip on the first substrate 107, wherein the LED chip comprises an N-GaN layer 108, a light-emitting layer 109, a P-GaN layer 1010, an ITO conductive layer 1011 and a first insulating layer 1012 which are sequentially distributed from bottom to top;
step 4, preparing a second electrode 104 on the top of the LED chip, in the preparation process, sequentially preparing a reflective layer and/or a barrier layer, a first metal layer 1013 on the first insulating layer 1012, performing para-position thermocompression bonding on the first metal layer 1013 and the conductive metal layer 102 on the top of the package substrate 101 to form a bonding metal layer 1014, and preparing the second electrode 104 on the bonding metal layer 1014; the second electrode 104 is electrically connected to the second conductive via;
and 5, preparing a first electrode 103 at the bottom end of the LED chip, wherein the first electrode 103 is electrically connected with the first conductive hole.
Embodiment two:
the embodiment provides a method for manufacturing an LED chip with a package substrate, which comprises the following steps:
step 1, providing a package substrate 101;
step 2, a first conductive hole and a second conductive hole are formed in the packaging substrate, and a conductive metal layer 102 is arranged on the top of the packaging substrate;
specifically, step 2 includes:
step 2.1, deep silicon etching and perforating are firstly carried out on the non-conductive packaging substrate, and the whole packaging substrate is penetrated; then, through the process of sputtering a seed layer and electroplating copper, filling the through holes with conductive copper to form conductive holes, wherein the conductive holes comprise first conductive holes and second conductive holes;
the positions of the conductive holes are positions corresponding to the first electrode 103 (N-pole) and the second electrode 104 (P-pole) of the LED chip. As shown in fig. 1, the package substrate is provided with six second conductive holes with the numbers 1, 2, 3, 4, 5 and 6 corresponding to the positive electrode (i.e., the second electrode) of the LED chip, and six first conductive holes with the numbers N1, N2, N3, N4, N5 and N6 corresponding to the negative electrode (i.e., the first electrode) of the LED chip, for a total of 12 conductive holes; fig. 3 is a cross-sectional view of the package substrate after the conductive vias are opened, wherein the corresponding cross-sectional positions are marked, and fig. 4 is a cross-sectional view of the package substrate at the cross-sectional positions shown in fig. 3, wherein the conductive vias are through holes.
The specific number of the conductive holes is determined according to the number of the electrodes of the chip actually produced.
The package substrate is made of non-conductive material, and the specific material is not limited, in this embodiment, the thickness of the package substrate is preferably 0.1 mm-0.3 mm.
Step 2.2, preparing a conductive metal layer 102 on the front surface of the package substrate, and respectively providing at least one corresponding extension electrode on the back surface of the package substrate 101 for the first electrode 103 and the second electrode 104 of the LED chip, which are correspondingly denoted as a first extension electrode 105 and a second extension electrode 106.
As shown in fig. 4, a conductive metal layer 102 is disposed on the front surface of the package substrate 101, and all the conductive vias are electrically connected to the conductive metal layer 102.
As shown in fig. 2, a plurality of extension electrodes are arranged at the bottom of the package substrate 101, and the extension electrodes are reasonably arranged, and each extension electrode is electrically connected with a corresponding conductive hole; specifically, the copper-plated area may be exposed by photolithography, and then electroplated with copper, or an electron gun may be used to deposit a conductive metal layer, which is a conductive material, but the specific material is not limited thereto, and in this embodiment, cr/Ti/Cu is preferable. The size of the extension electrode is typically larger than the size of its corresponding conductive aperture to facilitate subsequent solder alignment with external circuitry. The first electrode 103 of the chip is electrically connected to the first extension electrode 105 through a corresponding first conductive via, and the second electrode 104 is electrically connected to the second extension electrode 106 through a corresponding second conductive via.
The arrangement of the extension electrode not only does not reduce the effective area of the chip, but also enlarges the size of the welding electrode, thereby improving the precision of subsequent connection with other devices or external circuits for the situation that the LED chip corresponds to more pins of the packaging substrate.
The positions of the conductive vias on the package substrate 101 need to correspond to the positions of the electrodes of the corresponding chip, and in order to increase the effective area of the chip as much as possible, the on-chip electrodes are typically disposed in the edge region of the chip, and the size thereof is typically as small as possible. Correspondingly, the positions of the conductive holes on the packaging substrate are also in the edge area, and the size is smaller.
The present application contemplates providing each conductive via with a corresponding extension electrode, as shown in fig. 2, disposed at a location intermediate the package substrate 101.
Step 3, providing a first substrate 107, and preparing an LED chip on the first substrate, wherein the LED chip comprises an N-GaN layer 108, a light-emitting layer 109, a P-GaN layer 1010, an ITO conductive layer 1011 and a first insulating layer 1012 which are sequentially distributed from bottom to top;
the material of the first substrate 107 includes sapphire, silicon carbide, or the like, and an N-GaN layer 108, a light-emitting layer 109, and a P-GaN layer 1010 are sequentially formed on the substrate, as shown in fig. 5.
Specifically, step 3 includes:
step 3.1, performing ITO evaporation on the surface of the P-GaN layer 1010 to form an ITO conductive layer 1011, as shown in FIG. 6;
step 3.2, etching the local area of the ITO conductive layer 1011 by using a photolithography etching process (for example, an ICP process) to form an ITO mesa distributed in an array, specifically including: covering the surface of the ITO conductive layer 1011 with a first photoresist; exposing and developing the first photoresist based on the first mask plate to expose the position to be corroded of the ITO conductive layer 1011; etching the ITO conductive layer 1011 by adopting a plasma dry etching or chemical liquid wet etching mode to form an array distributed boss; and cleaning to remove the first photoresist.
As shown in fig. 7, a partial region of the ITO conductive layer 1011 is etched to expose the front surface of the P-GaN layer 1010 and form ITO mesas distributed in an array over the P-GaN layer 1010.
Step 3.3, etching the P-GaN layer 1010, the light-emitting layer 109 and the N-GaN layer 108 by using a photoetching process, wherein the etching depth reaches the middle of the N-GaN layer 108, and the front of the remaining N-GaN layer 108 is provided with bosses which are arranged in an array, namely LED chips; the method specifically comprises the following steps: covering the surface of the P-GaN layer 1010 and the surface of the ITO boss with a second photoresist; exposing and developing the second photoresist based on the second mask plate to expose the position to be corroded of the P-GaN layer 1010; the plasma dry etching or chemical liquid wet etching mode is adopted to sequentially etch the local areas of the P-GaN layer 1010, the luminous layer 109 and the N-GaN layer 108 to form conical tables distributed in an array, namely LED chips; and cleaning to remove the second photoresist.
Step 3.4, growing a first insulating layer 1012 on the whole surface including the front surface of the LED chip;
growth of the first insulating layer 1012 may be performed by PECVD 2 Thin films or SiNx films, or SiO growth by chemical vapor deposition (i.e. CVD/ALD) 2 Or a thin film medium such as AlN.
Step 3.5, etching the first insulating layer 1012 at the P contact position by using a photolithography etching process to expose the P contact position (the P contact position is a local area of the ITO conductive layer 1011, corresponding to the third conductive hole 1019 on the first insulating layer 1012, and the third conductive hole 1019 is a etched area of the first insulating layer 1012), specifically including: covering the surface of the first insulating layer 1012 with a third photoresist; exposing and developing the third photoresist based on the third mask plate to expose the position to be corroded of the first insulating layer 1012; etching the position to be etched of the first insulating layer 1012 by adopting a plasma dry etching or chemical liquid wet etching mode to expose the P contact position of the ITO conductive layer 1011; and cleaning to remove the third photoresist. Fig. 8 is a schematic diagram after etching away the first insulating layer 1012 at the location where P-contact is desired.
Step 4, preparing second electrodes 104 distributed at intervals in the row direction at the top end of the LED chip, sequentially preparing a reflective layer, a barrier layer and a first metal layer 1013 on a first insulating layer 1012 in the preparation process, performing para-position thermocompression bonding on the first metal layer 1013 and a conductive metal layer 102 at the top of a package substrate 101 to form a bonding metal layer 1014, preparing the second electrodes 104 on the bonding metal layer 1014, and electrically connecting the second electrodes 104 with second conductive holes;
the material of the reflecting layer is preferably a Ni/Ag/Au metal reflecting layer or an ITO/Ag/Tiw mixed reflecting layer; the reflecting layer is used for reflecting light rays emitted by the light-emitting layer, so that the light-emitting efficiency of the LED chip is improved;
the material of the barrier layer is preferably Ti or Pt, but is not limited to Ti or Pt, and is used for preventing diffusion between the metal layers;
specifically, step 4 includes:
step 4.1, performing metal coating on the whole surface including the front surface of the LED chip, and sequentially forming a reflecting layer, a barrier layer and a first metal layer 1013, as shown in fig. 9;
specifically, the metal plating may be performed by electron gun evaporation, where the first metal layer 1013 is NiSn (i.e., nickel-tin alloy), au (i.e., gold), auSn (i.e., gold-tin alloy), inSn (i.e., indium-tin alloy), inAu (i.e., jin Yin alloy), or NiIn (i.e., nickel-indium alloy), and the specific material is the same as that of the conductive metal layer 102 on top of the package substrate 101, so that the bonding metal layer 1014 is formed after the subsequent para-thermal compression bonding.
Step 4.2, thermocompression bonding the conductive metal layer 102 on the front surface of the package substrate 101 and the first metal layer 1013 to form a bonding metal layer 1014, so as to realize electrical connection between the two layers.
Fig. 10 is a schematic cross-sectional view of a thermal compression bonding process performed by aligning and thermally compressing the conductive metal layer 102 on the front surface of the package substrate 101 with the first metal layer 1013, and the conductive metal layer 102 on the front surface of the package substrate 101 and the first metal layer on the sapphire epitaxial surface are made of the same material, so that a better conductive effect can be achieved, and after bonding, the conductive metal layer 102 and the first metal layer 1013 are fused into the bonding metal layer 1014.
Step 4.3, removing the first substrate;
if the first substrate 107 is a sapphire substrate, it is removed by laser lift-off; if the first substrate 107 is a silicon-based substrate, it is removed by chemical solution. Fig. 11 is an overall cross-sectional view after removing the first substrate 107.
Step 4.4, removing the local area on the back of the N-GaN layer to expose the back of the first insulating layer 1012 and the back of the remaining N-GaN layer 108;
the back surface local region of the N-GaN layer is patterned by ICP process, and after the patterned etching is performed to the first insulating layer 1012, the back surface of the first insulating layer 1012 is exposed, as shown in fig. 12.
Step 4.5, etching a local area of the first insulating layer 1012 to expose the bonding metal layer 1014, wherein the exposed bonding metal layer 1014 comprises a region to be etched and a conductive region 1017;
step 4.6, etching the region to be etched to expose the back of the package substrate below the region to be etched, and forming second electrodes 104 distributed at intervals in the row direction, as shown in fig. 13.
And 5, preparing first electrodes 103 which are distributed at intervals in the column direction at the bottom end of the LED chip, wherein the first electrodes 103 are electrically connected with the first conductive holes.
Specifically, step 5 includes:
step 5.1, covering the whole surface including the surface of the remaining first insulating layer 1012 with the second insulating layer 1015, and performing patterning etching on a local area of the second insulating layer 1015 by using a photolithography etching process to expose the conductive area 1017; the second insulating layer 1015 has a function of preventing conduction between the first electrode 103 and the second electrode 104. As shown in fig. 14, a perspective view in a top view after the second insulating layer 1015 is grown.
Step 5.2, preparing a second metal layer 1016 on the whole surface of the remaining second insulating layer 1015;
step 5.3, processing the second metal layer 1016 by a lift-off process to form first electrodes 103 distributed at intervals in a column direction, including: before step S5.2, photoresist is first spin-coated on the second insulating layer 1015, exposed and developed, then a second metal layer 1016 is deposited on the whole surface including the photoresist surface (i.e. step S5.2), stripping treatment is performed on the second metal layer 1016 based on the developed pattern, so as to form a plurality of first electrodes 103 distributed at intervals in a column direction, and the first electrodes 103 are connected with corresponding first conductive holes through conductive areas 1017 reserved in the above steps.
As shown in fig. 15, the first electrode 103 is formed in a perspective view from above. Fig. 16 is a corresponding cross-sectional view.
Thus, an LED chip with a package substrate was obtained, in which the first electrode 103 and the second electrode 104 were located on different surfaces.
In the above method, a plurality of LED chips 1018 are simultaneously prepared on a single sapphire or silicon substrate when the LED chips are prepared. When the LED chip emits light, an external driving circuit introduces current to the P-GaN layer 1010 through the second conductive hole, the second electrode 104 and the ITO conductive layer 1011, and introduces current to the N-GaN layer 108 through the first conductive hole, the conductive region 1017 and the first electrode 103, so that the light emitted by the light emitting layer 109 is reflected by the reflecting layer and is emitted out through the N-GaN layer 108.
Some steps in the embodiments of the present application may be implemented by using software, and the corresponding software program may be stored in a readable storage medium, such as an optical disc or a hard disk.
The foregoing description of the preferred embodiments of the application is not intended to limit the application to the precise form disclosed, and any such modifications, equivalents, and alternatives falling within the spirit and scope of the application are intended to be included within the scope of the application.
Claims (7)
1. The LED chip with the package substrate is arranged on the package substrate (101) in an array manner, a conductive area is arranged in the package substrate (101), and the package substrate is made of Si, glass or BT carrier plates;
the LED chip is characterized by comprising first electrodes (103) distributed at intervals in a column direction and second electrodes (104) distributed at intervals in a row direction, wherein the first electrodes (103) and the second electrodes (104) are respectively positioned at the top end and the bottom end of the LED chip, the same column of the LED chip is connected with the first electrodes (103) in the same column direction, and the same row of the LED chip is connected with the second electrodes (104) in the same row direction;
the conductive area comprises conductive holes penetrating through the packaging substrate, the conductive holes comprise first conductive holes and second conductive holes, the first conductive holes are distributed at the row-direction edge of the packaging substrate at intervals in a row-direction manner, and the second conductive holes are distributed at the column-direction edge of the packaging substrate at intervals in a row-direction manner;
the conductive region further comprises a first extension electrode (105) and a second extension electrode (106) which are arranged at the bottom of the packaging substrate;
one end of the first electrode (103) extends towards the row direction edge of the packaging substrate and is electrically connected with an external circuit through the corresponding first conductive hole and the first extension electrode, and one end of the second electrode (104) extends towards the column direction edge of the packaging substrate and is electrically connected with the external circuit through the corresponding second conductive hole and the second extension electrode;
the external circuit is used for supplying current to the LED chip through the second expansion electrode, the second conductive hole and the second electrode (104), and supplying current to the LED chip through the first expansion electrode, the first conductive hole and the first electrode (103) so that the LED chip emits light.
2. The LED chip with package substrate according to claim 1, wherein the LED chip comprises an N-GaN layer (108), a light emitting layer (109), a P-GaN layer (1010), an ITO conductive layer (1011), a first insulating layer (1012) distributed in this order from bottom to top; the first electrode (103) is an N-type electrode and is used for being connected with the N-GaN layer (108); the second electrode (104) is a P-type electrode and is connected with the P-GaN layer (1010) through the ITO conductive layer (1011).
3. The LED chip with package substrate according to claim 2, wherein said first electrode (103) is located at the bottom end of the N-GaN layer (108) of said LED chip, said second electrode (104) is located at the top end of the first insulating layer (1012) of said LED chip, a third conductive hole (1019) is provided in said first insulating layer (1012), and said second electrode (104) is electrically connected to said ITO conductive layer (1011) through said third conductive hole (1019).
4. A LED chip with a package substrate according to claim 3, characterized in that the conductive area further comprises a conductive area (1017) arranged on top of the package substrate, the conductive area (1017) being located at the top end of the first conductive hole, the first electrode (103) being electrically connected to the first conductive hole through the conductive area (1017).
5. A method for manufacturing an LED chip with a package substrate, the LED chip with a package substrate being the LED chip with a package substrate according to claim 1, the method comprising:
step 1, providing a package substrate (101);
step 2, respectively forming first conductive holes distributed at intervals in the row direction and second conductive holes distributed at intervals in the column direction on the row direction edge and the column direction edge of the packaging substrate, and arranging a conductive metal layer (102) on the top of the packaging substrate (101);
step 2.1, deep silicon etching is firstly carried out on the edge of the non-conductive packaging substrate (101) to open holes, and the holes penetrate through the whole packaging substrate (101); then filling the through holes with conductive copper through a process of sputtering a seed layer and electroplating copper to form conductive holes, wherein the conductive holes comprise first conductive holes and second conductive holes;
step 2.2, preparing a conductive metal layer (102) on the front surface of the packaging substrate (101), and/or respectively setting at least one corresponding expansion electrode for a first electrode (103) and a second electrode (104) of the LED chip on the back surface of the packaging substrate (101), wherein the corresponding expansion electrodes are respectively marked as a first expansion electrode (105) and a second expansion electrode (106);
step 3, providing a first substrate (107), and preparing an LED chip on the first substrate (107), wherein the LED chip comprises an N-GaN layer (108), a light-emitting layer (109), a P-GaN layer (1010), an ITO conductive layer (1011) and a first insulating layer (1012) which are sequentially distributed from bottom to top;
step 4, preparing a second electrode (104) at the top end of the LED chip, wherein in the preparation process, a metal coating is performed on the first insulating layer (1012), the metal coating comprises a first metal layer (1013), the first metal layer (1013) and the conductive metal layer (102) are subjected to thermocompression bonding, a bonding metal layer (1014) is formed, and the second electrodes (104) which are distributed at intervals in the row direction are prepared on the bonding metal layer (1014); the second electrode (104) is electrically connected with the second conductive hole;
and 5, preparing first electrodes (103) which are distributed at intervals in the column direction at the bottom end of the LED chip, wherein the first electrodes (103) are electrically connected with the first conductive holes.
6. The method according to claim 5, wherein the step 4 comprises:
step 4.1, performing metal coating on the first substrate (107), and sequentially forming a reflecting layer and/or a blocking layer and a first metal layer (1013), wherein the reflecting layer and/or the blocking layer and the first metal layer (1013) cover the whole surface including the front surface of the LED chip;
step 4.2, thermocompression bonding the conductive metal layer (102) and the first metal layer to form a bonding metal layer (1014);
step 4.3, removing the first substrate (107);
step 4.4, removing a local area on the back surface of the N-GaN layer (108) to expose the back surface of the first insulating layer (1012) and the back surface of the residual N-GaN layer (108);
step 4.5, etching a local area of the first insulating layer (1012) to expose the bonding metal layer (1014), wherein the exposed bonding metal layer (1014) comprises a region to be etched and a conductive region (1017);
and 4.6, etching the region to be etched to expose the back surface of the packaging substrate (101) below the region to be etched, and forming second electrodes (104) distributed at intervals in the row direction.
7. The method according to claim 6, wherein the step 5 comprises:
step 5.1, growing a second insulating layer (1015) on the back surface of the packaging substrate (101), wherein the second insulating layer (1015) covers the whole surface including the surface of the residual first insulating layer (1012), and carrying out pattern etching on a local area of the second insulating layer (1015) to expose the conductive area (1017);
step 5.2, forming a second metal layer (1016) on the back surface of the packaging substrate (101), wherein the second metal layer (1016) covers the whole surface including the surface of the second insulating layer (1015);
and 5.3, treating the second metal layer (1015) by adopting a stripping process to form first electrodes (103) which are distributed at intervals in the column direction.
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