JP5394164B2 - Power supply device and image forming apparatus - Google Patents

Description

  The present invention relates to a power supply device using a piezoelectric transformer, and an image forming apparatus such as electrophotography using the power supply device.

  Conventionally, as a power supply device used in an electrophotographic image forming apparatus, for example, as described in Patent Document 1 below, a high voltage is generated with a low voltage input using a resonance phenomenon of a piezoelectric vibrator. 2. Description of the Related Art There is known an apparatus configured to output a high voltage by controlling a piezoelectric transformer that can be controlled by an output signal of a voltage controlled oscillator (hereinafter referred to as “VCO”).

JP 2006-91757 A

However, the conventional power supply device has the following problems (a) to (c).
(A) Since it is configured by an analog circuit such as a VCO, the number of parts increases.

  (B) When a high output voltage in the vicinity of the resonance frequency in the piezoelectric transformer is to be used, if the output voltage is controlled to be lower than the resonance frequency, control becomes impossible. For this reason, a high high-voltage output substantially in the vicinity of the resonance frequency cannot be used.

  (C) When the output voltage changes due to load fluctuations, the output voltage may subsequently fluctuate for a relatively long period of time due to the control characteristics of the power supply device including frequency change responsiveness.

A power supply apparatus according to a first aspect of the present invention includes an oscillator that generates a clock, pulse output means that divides the clock and outputs a pulse based on a control signal, and a switching element that is driven by the pulse And a piezoelectric transformer that outputs an alternating current (hereinafter referred to as “AC”) high voltage from the secondary side when a voltage is intermittently applied to the primary side by the switching element, and a direct current ( (Hereinafter referred to as “DC”), a rectifying means for converting into a high voltage, an output current supplying means for supplying a secondary output current of the piezoelectric transformer, and converting the secondary output current into a voltage to convert the output voltage to Current-voltage conversion means for outputting, target current setting means for setting a target current and outputting a target voltage corresponding to the target current, and a voltage for comparing the output voltage with the target voltage and outputting a comparison result Possess a compare unit, and the output frequency of the pulse is changed by said comparison result, the comparison result by controlling the output frequency such that the square wave at the output period of the pulse, the DC This is a power supply device that performs constant current control with respect to a high voltage.

Then, the frequency division ratio of the clock is a combination of α division and β division which are integer values in N (where N is a positive number) pulse periods, and the α division An average period of the N pulses is controlled by changing a combination of a pulse and the pulse obtained by dividing the β .

An image forming apparatus according to a second aspect includes the power supply apparatus according to the first aspect, and is driven by a high DC voltage output from the power supply apparatus to form an image on a medium .

According to the power supply device and the image forming apparatus of the present invention, the output current supply means and the current-voltage conversion means are provided on the secondary side of the piezoelectric transformer to perform constant current control and control the average period in N pulses. Therefore, stable constant current control is possible without exceeding control of the resonance frequency peak in the piezoelectric transformer during frequency control. In addition, since stable constant current control is possible, stable output is possible regardless of the environment, and a stable image free from density steps and horizontal stripes can be obtained.

FIG. 1 is a block diagram showing an outline of a power supply device according to Embodiment 1 of the present invention. FIG. 2 is a circuit diagram showing a detailed configuration example of the power supply device 70 of FIG. FIG. 3 is a configuration diagram illustrating an image forming apparatus using the power supply device according to the first exemplary embodiment of the present invention. FIG. 4 is a block diagram showing the configuration of the control circuit in the image forming apparatus 1 of FIG. FIG. 5 is a characteristic diagram of output voltage / frequency in the piezoelectric transformer 75 in FIG. FIG. 6 is a block diagram showing the control unit 72 in FIG. FIG. 7A is a diagram showing input / output values in the table register 106-1 in FIG. FIG. 7-2 is a diagram showing input / output values in the table register 106-2 in FIG. FIG. 7C is a diagram showing input / output values in the counter upper limit value table 103 in FIG. FIG. 8 is an operation waveform diagram in the power supply device 70 of FIG. FIG. 9 is a flowchart showing data processing in the arithmetic unit 105-1 in FIG. FIG. 10 is a block diagram showing a schematic configuration of the power supply device according to the second embodiment of the present invention. FIG. 11 is a circuit diagram showing a detailed configuration example of the power supply device 70A of FIG. FIG. 12 is a block diagram showing the control unit 72A in FIG. FIG. 13A is a diagram showing input / output values in the table register 106A-1 in FIG. FIG. 13-2 is a diagram showing input / output values in the table register 106A-2 in FIG. FIG. 13C is a diagram showing input / output values in the counter upper limit value table 103A in FIG.

  Modes for carrying out the present invention will become apparent from the following description of the preferred embodiments when read in light of the accompanying drawings. However, the drawings are only for explanation and do not limit the scope of the present invention.

(Configuration of image forming apparatus)
FIG. 3 is a configuration diagram illustrating an image forming apparatus using the power supply device according to the first embodiment of the present invention.

  The image forming apparatus 1 is, for example, an electrophotographic color image forming apparatus, and a black developing device 2K, a yellow developing device 2Y, a magenta developing device 2M, and a cyan developing device 2C are detachably inserted. The developing units 2K, 2Y, 2M, and 2C are uniformly charged by the charging rollers 36K, 36Y, 36M, and 36C of the respective colors that are in contact with the photosensitive drums 32K, 32Y, 32M, and 32C of the respective colors. The charged photosensitive drums 32K, 32Y, 32M, and 32C are respectively latentized by light emission from the black light emitting element (hereinafter referred to as “LED”) head 3K, yellow LED head 3Y, magenta LED head 3M, and cyan LED head 3C. An image is formed.

  Each color supply roller 33K, 33Y, 33M, 33C in each developing device 2K, 2Y, 2M, 2C supplies toner to each developing roller 34K, 34Y, 34M, 34C, and each color developing blade 35K, 35Y, 35M. , 35C uniformly form a toner layer on the surface of each developing roller 34K, 34Y, 34M, 34C, and develop a toner image on each photosensitive drum 32K, 32Y, 32M, 32C. The cleaning blades 37K, 37Y, 37M, and 37C in the developing devices 2K, 2Y, 2M, and 2C for the respective colors clean the residual toner after the transfer.

  The black toner cartridge 4K, the yellow toner cartridge 4Y, the magenta toner cartridge 4M, and the cyan toner cartridge 4C are detachably attached to the developing devices 2K, 2Y, 2M, and 2C, and the internal toner is supplied to the developing devices 2K, 2Y, and 2C, respectively. It has a structure that can be supplied to 2M and 2C. The black transfer roller 5K, the yellow transfer roller 5Y, the magenta transfer roller 5M, and the cyan transfer roller 5C are arranged so that a bias can be applied from the back surface of the transfer belt 8 to the transfer nip. The transfer belt driving roller 6 and the transfer belt driven roller 7 have a structure in which the transfer belt 8 is stretched and the paper 15 can be conveyed by driving the roller.

The transfer belt cleaning blade 11 can scrape off the toner on the transfer belt 8, and the toner thus scraped off is accommodated in the transfer belt cleaner container 12. The paper cassette 13 is detachably attached to the image forming apparatus 1 and is loaded with paper 15 as a medium . The hopping roller 14 conveys the paper 15 from the paper cassette 13. The registration rollers 16 and 17 convey the paper 15 to the transfer belt 8 at a predetermined timing. The fixing device 18 fixes the toner image on the paper 15 by heat and pressure. The paper guide 19 discharges the paper 15 to the paper discharge tray 20 face down.

  A sheet detection sensor 40 is disposed between the registration rollers 16 and 17 and the transfer belt driven roller 7. The paper detection sensor 40 detects the passage of the paper 15 in contact or non-contact. The transfer bias application timing when the power supply device performs transfer is determined from the time obtained from the relationship between the distance from the sensor position of the sheet detection sensor 40 to the transfer nip and the sheet conveyance speed.

FIG. 4 is a block diagram showing the configuration of the control circuit in the image forming apparatus 1 of FIG.
The control circuit includes a host interface unit 50, and the host interface unit 50 transmits and receives data to and from the command / image processing unit 51. The command / image processing unit 51 outputs image data to the LED head interface unit 52. The LED head interface unit 52 controls the head drive pulse and the like by the printer engine control unit 53, and causes the LED heads 3K, 3Y, 3M, and 3C to emit light.

  The printer engine control unit 53 sends control values such as a charging bias, a developing bias, and a transfer bias to the high voltage control unit 60 based on the detection result of the paper detection sensor 40. The high voltage control unit 60 sends signals to the charging bias generation unit 91, the development bias generation unit 92, and the transfer bias generation unit 93. The charging bias generating unit 91 and the developing bias generating unit 92 include the charging rollers 36K, 36Y, 36M, and 36C and the developing rollers 34K of the black developing unit 2K, the yellow developing unit 2Y, the magenta developing unit 2M, and the cyan developing unit 2C. , 34Y, 34M, and 34C are biased. The paper detection sensor 40 is used to adjust the generation timing of the transfer bias.

  The printer engine control unit 53 drives the hopping motor 54, registration motor 55, belt motor 56, fixing device heater motor 57, and drum motors 58K, 58Y, 58M, and 58C for each color at predetermined timings. The temperature of the fixing device heater 59 is controlled by the printer engine control unit 53 in accordance with the detection value of the thermistor 65.

(Configuration of power supply)
FIG. 1 is a block diagram schematically illustrating a power supply device according to the first embodiment of the present invention.

  The printer engine control unit 53 includes an output port OUT1 that outputs a reset signal RESET, serial communication means (for example, a plurality of input / output ports) I / O1, and the like. These output ports OUT1 and a plurality of input / outputs The power supply device 70 according to the first embodiment is connected to the port I / O1.

  The power supply device 70 according to the first embodiment includes, for example, a control circuit in the high-voltage control unit 60 and the transfer bias generation unit 93 in FIG. 4, and each transfer roller 5 (= 5K, 5Y, 5M, 5C) for each color. Is provided. Since each color power supply device 70 has the same circuit configuration, only one circuit will be described below.

  The power supply device 70 receives a control signal supplied from the plurality of input / output ports I / O1 of the printer engine control unit 53 and a reset signal RESET that is a control signal supplied from the output port OUT1, and supplies the target current to the target current. This is a device that generates a high DC voltage based on the corresponding target voltage S72a and supplies it to a load ZL as the transfer roller 5.

  The power supply device 70 includes an oscillator 71 that generates a reference clock (hereinafter simply referred to as “clock”) CLK having a constant frequency (for example, 50 MHz), and a pulse output means (for example, a control unit) 72 is connected to the output side. Has been. The control unit 72 is provided in the high voltage control unit 60, for example, and divides the clock CLK supplied from the oscillator 71 on the basis of a control signal supplied from the printer engine control unit 53 to piezo-electric transformer drive pulses (hereinafter simply referred to as “piezoelectric transformer driving pulse”). This is a circuit that outputs S72.

  The control unit 72 includes a clock input port CLK_IN for inputting the clock CLK, an input port IN11 for inputting the comparison result S78, a reset input port IN12 for inputting a reset signal RESET output from the output port OUT1 of the printer engine control unit 53, and a printer. A plurality of input / output ports I / O11 connected to the plurality of input / output ports I / O1 of the engine control unit 53, target current setting means for setting a target current and outputting a target voltage S72a corresponding to the target current (For example, a digital / analog converter, hereinafter referred to as “DAC”) 72a, and an analog / digital converter (hereinafter referred to as “ADC”) 72b for converting the input analog output voltage S77 into a digital signal. Yes.

  Since the control unit 72 of the first embodiment is for one channel, the input ports IN11 and IN12, the output port OUT11, the DAC 72a, and the ADC 72b are each one input / output, but a plurality of channels are realized. Hold them for the number of channels.

  The control unit 72 includes, for example, an ASIC (Application Specific Integrated Circuit, hereinafter referred to as “ASIC”), which is an integrated circuit in which a plurality of functions are combined into one for a specific application, and a central processing unit (hereinafter, “CPU”). Or a field programmable gate array (hereinafter referred to as “FPGA”), which is a kind of gate array in which a user can write an original logic circuit. It is configured.

  A piezoelectric transformer drive circuit 74 is connected to the output port OUT11 of the controller 72 and the DC power source 73 that outputs DC 24V. The piezoelectric transformer drive circuit 74 is a circuit that outputs a drive voltage using a switching element, and a piezoelectric transformer 75 is connected to the output side. The piezoelectric transformer 75 is a transformer that boosts the driving voltage by using a resonance phenomenon of a piezoelectric vibrator such as ceramic and outputs an AC high voltage, and a rectifying means (for example, a rectifying circuit) 76 and an output are provided on the output side. A voltage supply means 77 is connected. The rectifier circuit 76 is a circuit that converts the AC high voltage output from the piezoelectric transformer 75 into a DC high voltage and supplies it to the load ZL.

  The output voltage supply unit 77 includes an output current supply unit 77-1 that supplies a secondary output current of the piezoelectric transformer 75, and a current-voltage conversion unit 77-2 that converts the output current into an output voltage S77 and outputs the output voltage S77. Have. A voltage comparison unit 78 is connected to the output side of the current-voltage conversion unit 77-2 and the output side of the DAC 72a in the control unit 72. The voltage comparison unit 78 compares the output voltage S77 of the current-voltage conversion unit 77-2 with the target voltage S72a output from the DAC 72a in the control unit 72, and the comparison result S78 is input to the input port IN11 of the control unit 72. It is a circuit to give.

  1 is arranged in parallel for each color transfer roller 5 (= 5K, 5Y, 5M, 5C), that is, for each channel, but a part is shared for the plurality of channels. It may be configured. For example, the piezoelectric transformer 75 and the rectifier circuit 76 are required for a plurality of channels, but the oscillator 71 and the control unit 72 can be shared by one set. In this case, the controller 72 includes as many input ports and output ports as the number of channels. The control unit 72 is provided in the power supply device 70, but may be provided in a large-scale integrated circuit (hereinafter referred to as “LSI”) in the printer engine control unit 53.

  FIG. 2 is a circuit diagram showing a detailed configuration example of the power supply device 70 of FIG. Further, FIG. 5 is a characteristic diagram of output voltage / frequency in the piezoelectric transformer 75 in FIG.

  As shown in FIG. 2, a plurality of input / output port I / O1 as serial communication means of the printer engine control unit 53 and a plurality of input / output port I / O11 of the control unit 72 include three signal lines. (For example, SCLK line, SDI line, and SDO line).

The SCLK line is a signal line of a serial clock SCLK that outputs a clock synchronized with transfer data, which will be described later, from the printer engine control unit 53 to the control unit 72. The SDI line is a serial data input signal SDI that inputs data to the control unit 72 and is a signal line that transmits data from the printer engine control unit 53 to the control unit 72 in synchronization with the serial clock SCLK. Further, the SDO line is a serial data output signal SDO output from the control unit 72 in synchronization with the serial clock SCLK, and is a signal line for transmitting data in synchronization with the serial clock SCLK.

  Since this three-wire serial communication is a known communication, details are omitted. Since the accuracy of ON / OFF (hereinafter referred to as “ON / OFF”) timing of the high-voltage output of the image forming apparatus 1 is on the order of msec, there is no problem even if the communication speed is on the order of μsec by serial communication.

  The oscillator 71 that supplies the clock CLK to the control unit 72 is a circuit that operates by DC 3.3V supplied from the power source 71a and generates the clock CLK having an oscillation frequency of 50 MHz. The power supply terminal VDD to which DC 3.3V is applied, It has an output enable terminal OE to which DC 3.3V is applied, a clock output terminal CLK_OUT that outputs a clock CLK, and a ground terminal GND. The clock output terminal CLK_OUT is connected to the clock input port CLK_IN of the control unit 72 via the resistor 71b.

In the control unit 72 that operates in synchronization with the clock CLK, the piezoelectric transformer drive circuit 74 is connected to the output port OUT11 that outputs the drive pulse S72 via the resistor 72c. The DC power supply 73 is connected to the piezoelectric transformer drive circuit 74. Is connected. The DC power source 73 is, for example, a DC 24V power source that is supplied by transforming and rectifying AC 100V, which is a commercial power source, from a low-voltage power source device (not shown).

  The piezoelectric transformer driving circuit 74 has a power transistor (for example, an N-channel power MOSFET (hereinafter referred to as “NMOS”) 74a as a switching element, and a resistor 74b for preventing a short circuit is connected between the gate and source of the NMOS 74a. The drain of the NMOS 74a is connected to a DC power source 73 of DC 24V via an inductor (coil) 74c, and a capacitor 74d is connected in parallel between the drain and source of the NMOS 74a, and the capacitor 74d and the inductor When the drive pulse S72 from the control unit 72 is input to the gate of the NMOS 74a, DC24V is switched by the NMOS 74a, which is resonated by the resonance circuit and has a peak of about 100V AC. Driving voltage of the wave is output.

  The primary side input terminal 75a of the piezoelectric transformer 75 is connected to the output side of the resonance circuit, and an AC high voltage of 0 to several kV is output from the secondary side output terminal 75b according to the switching frequency of the NMOS 74a. It is configured to be. As shown in FIG. 5, the output voltage characteristic of the output terminal 75b on the secondary side varies depending on the frequency, and the boost ratio is determined by the switching frequency of the NMOS 74a.

  That is, as shown in FIG. 5, the output voltage / frequency characteristics of the piezoelectric transformer 75 are such that the output voltage has a maximum value at the frequency fx at a certain small load ZL1, and the frequency fy at the load ZL2 larger than the load ZL1. The output voltage takes a maximum value. Thus, the piezoelectric transformer 75 has different frequency characteristics depending on the loads ZL1 and ZL2. In the first embodiment, the output voltage is controlled by driving the piezoelectric transformer 75 at a frequency having a high frequency in the right side of FIG. 5 and lowering the drive frequency, thereby increasing the output voltage. The control is performed to increase the current and obtain a target output current.

  A rectifier circuit 76 for AC / DC conversion is connected to the output terminal 75 b on the secondary side of the piezoelectric transformer 75. The rectifier circuit 76 is a circuit that converts an AC high voltage output from the secondary-side output terminal 75b of the piezoelectric transformer 75 into a DC high voltage and outputs the DC high voltage, and includes diodes 76a and 76b and a capacitor 76c. The transfer roller 5 serving as a load ZL is connected to the output side of the rectifier circuit 76 via a resistor 76d.

  The output voltage supply means 77 is composed of capacitors 77a and 77c, an operational amplifier (hereinafter referred to as “op-amp”) 77b to which a 24V power supply voltage from a DC power supply 73 is applied, and a resistor 77d. In the operational amplifier 77b, the “+” input terminal is grounded, and the “−” input terminal is connected to the anode of the diode 76a and the capacitor 76c in the rectifier circuit 76, and between the “+” input terminal and the “−” input terminal. In addition, an operational amplifier output smoothing capacitor 77a is connected. A resistor 77d is connected between the “−” input terminal and the output terminal of the operational amplifier 77b, and a capacitor 77c for smoothing the operational amplifier output is connected in parallel with the resistor 77d.

The current output from the output terminal of the operational amplifier 77b is supplied to the anode of the diode 76a in the rectifier circuit 76 via the resistor 77d. Since the “+” input terminal of the operational amplifier 77 b is grounded, the voltage level of the “−” input terminal becomes 0 V, and the output signal of the operational amplifier 77 b becomes a voltage corresponding to the current flowing through the rectifier circuit 76. For example, when the resistance value of the resistor 77d is 33 kΩ and the current supplied from the operational amplifier 77b to the rectifier circuit 76 is 10 μA, the output voltage S77 of the operational amplifier 77b is 0.33V. Therefore, the operational amplifier 77b outputs a voltage corresponding to the current output when the piezoelectric transformer 75 is driven by the piezoelectric transformer drive circuit 74. For example, when the resistance 77d is 33 kΩ, the operational amplifier 77b outputs an output voltage S77 of 0 to 3.3 V for a current of 0 to 100 μA supplied from the operational amplifier 77b to the rectifier circuit 76 .

  The voltage comparator 78 and the ADC 72b in the controller 72 are connected to the output terminal of the operational amplifier 77b. The voltage comparison means 78 includes a comparator 78a which is a voltage comparator to which a 24V power supply voltage from the DC power supply 73 is applied, and a pull-up resistor for pulling up the output terminal of the comparator 78a by the DC 3.3V power supply 71a. 78b. The comparator 78a has a “−” input terminal for inputting the output voltage S77 of the operational amplifier 77b, and a “+” input terminal for inputting the target voltage S72a output from the DAC 72a in the printer engine control unit 53. This is a circuit that compares the voltage at the “−” input terminal with the voltage at the “+” input terminal, outputs the comparison result S78 from the output terminal, and applies the result to the input port IN11 of the control unit 72.

For example, the control unit 72 outputs the target voltage S72a in the range of 3.3V from the DAC 72a having a 10-bit resolution, and supplies the target voltage S72a to the comparator 78a. The comparator 78a
(Target voltage S72a of DAC 72a)> (Output voltage S77 of operational amplifier 77b)
During this time, the output terminal of the comparator 78a is pulled up by the DC 3.3V power supply 71a and the resistor 78b, and outputs a 3.3V “H” comparison result S78 to be input to the input port IN11 of the controller 72. To do. vice versa,
(Target voltage S72a of DAC 72a) <(Output voltage S77 of operational amplifier 77b)
Then, the output terminal of the comparator 78 a becomes “L”, and this “L” comparison result S 78 is input to the input port IN 11 of the control unit 72.

(Configuration of control unit in power supply)
FIG. 6 is a block diagram showing the control unit 72 in FIG.

  The control unit 72 is configured by an ASIC, for example, and is described in an ASIC by being described in a hardware description language or the like. Of the clock CLK and the reset signal RESET input thereto, the clock CLK is supplied to each circuit block (to be described later) constituting the synchronization circuit, and the reset signal RESET is supplied to each circuit block for initialization.

  The control unit 72 includes a communication data processing unit 101 that inputs serial communication signals (for example, SCLK, SDI, SDO) input from a plurality of input / output port I / Os 11. An input logical product circuit (hereinafter referred to as “AND circuit”) 102 and a counter upper limit value table 103 are connected. Corresponding to the counter upper limit value table 103, a counter lower limit value register 104 is also provided.

  The computing unit 105-1 is connected to the ADC 72b that receives the output voltage S77 of the output voltage supply unit 77 and the communication data processing unit 101, and the table register 106-1 is connected to the output side. Corresponding to this table register 106-1, another table register 106-2 is also provided.

  An up counter 107 is connected to the input port IN11 to which the comparison result S78 from the voltage comparison means 78 is input. A data latch (hereinafter referred to as “D latch”) is connected between the output side of the up counter 107 and the output side of the AND circuit 102. 108) is connected. Comparators 109-1 and 109-2 and a negative circuit (hereinafter referred to as “NOT circuit”) 110 are connected to the D latch 108, and a 9-input AND circuit 111 is connected to the output side of the NOT circuit 110. ing. The 9-input AND circuit 111 and the comparator 109-2 are connected to a 2-input OR circuit (hereinafter referred to as “OR circuit”) 112, and a multiplier 113 is connected to the output side of the OR circuit 112. ing.

  An arithmetic unit 105-2 is connected to the multiplier 113 and the timer 114. To the arithmetic unit 105-2, a counter upper limit value table 103, a counter lower limit value register 104, a table register 106-2, a 19-bit register 115, and A 1 adder 117 is connected. An error holding register 116 is connected to the 19-bit register 115, and a frequency division selector 118 is connected to the error holding register 116, 19-bit register 115, and 1 adder 117. The 19-bit register 115, the error holding register 116, the 1 adder 117, and the frequency divider selector 118 constitute an integer value converting means having a binarizing means by an error diffusion method.

  A frequency divider 119 is connected to the frequency divider selector 118, and an output selector 120 is connected to the output side of the frequency divider 119. The output selector 120 is connected to the AND circuit 102, the up counter 107, the arithmetic unit 105-1, the error holding register 116, and the output port OUT11 that outputs the drive pulse S72.

Hereinafter, the function of each circuit in the controller 72 will be described.
The up counter 107 connected to the input port IN11 enables “H” of the comparison result S78 input from the input port IN11 (that is, operates by “H” of S78), and the rising pulse of the clock CLK The 9-bit counter is incremented by the counter, and is not counted up when the comparison result S78 is “L”, and is counted up only when the comparison result S78 is “H”, and the drive pulse S72 output from the output selector 120 It is reset to 0 at the rising input (reset). The 9-bit signal of the up counter 107 is output to the D latch 108 at the next stage.

  In the D latch 108, the ON / OFF signal S 101 output from the communication data processing unit 101 is “H” by the 2-input AND circuit 102, that is, the rising edge of the drive pulse S 72 output from the output selector 120 under the high voltage ON condition. The 9-bit output value of the up-counter 107 is held at the input, and the held value is output to the comparators 109-1 and 109-2 and the 9-bit NOT circuit 110.

The comparator 109-1 outputs the output value of the D latch 108 and the upper 8-bit output value of the 19-bit register 115 (that is, an 8-bit value that is a half value of the upper 9 bits, which is the integer part of the 19-bit register 115). Compare and
(Output value of D latch 108) <(bits 18 to 11 of 19-bit register 115)
At this time, the “L” level is output to the arithmetic unit 105-2, and “H” is output under conditions other than those described above. The comparison process of the comparator 109-1 is performed at every rising edge of the clock CLK.

  The NOT circuit 110 receives the 9-bit output of the D latch 108 and outputs the 9-bit inverted version to the 9-input AND circuit 111. The 9-input AND circuit 111 outputs 1-bit “H” to the 2-input OR circuit 112 when all 9 bits are “H” with respect to the 9-bit input, and otherwise outputs “L” to the 2-input OR circuit 112. Output to.

The comparator 109-2 compares the upper 9-bit value of the 19-bit register 115 with the 9-bit value of the D latch 108,
(9-bit value of D latch 108)>
(Bits 18 to 10 of the 19-bit register 115) -1
In this case, “H” is output to the 2-input OR circuit 112, and “L” is output to the 2-input OR circuit 112 otherwise. The 2-input OR circuit 112 outputs “H” to the multiplier 113 when either the output signal of the 9-input AND circuit 111 or the output signal of the comparator 190-2 is “H”.

  When the output signal of the 2-input OR circuit 112 is “H”, the multiplier 113 multiplies the 8-bit output value of the table register 106-1 and the 8-bit output value of the table register 106-2, and 16 bits of the multiplication result. The value is output to the arithmetic unit 105-2, and when the output signal of the 2-input OR circuit 112 is “L”, the 16-bit output value is output as 0001 hex (hexadecimal) to the arithmetic unit 105-2.

  The communication data processing unit 101 connected to the plurality of input / output port I / Os 11 responds to the target current output according to the serial communication signal (for example, SCLK, SDI, SDO) received from the printer engine control unit 53. The 8-bit value is set in the DAC 72a, and the output ON / OFF signal S101 is switched between H and L. In serial communication, a command value and a data value are transmitted through a known three-wire interface. Data is transmitted in pairs with DAC setting data for the DAC setting command, ON command and OFF command values are transmitted for high voltage output ON / OFF, and dummy data (for example, 00 hex) is transmitted in pairs. .

The DAC 72a is an 8-bit digital / analog converter, and {(8-bit value) × 3.3 / 255} according to the 8-bit value output from the communication data processing unit 101 (V)
Target voltage S72a is output.

  The ADC 72b is a 12-bit analog / digital converter, which converts the output voltage S77 of the output voltage supply means 77 into 12-bit digital data every predetermined CLK cycle and outputs it to the arithmetic unit 105-1. The arithmetic unit 105-1 divides the 12-bit data output from the ADC 72b by the 8-bit data that sets the DAC 72a, and outputs the integer value of the division result to the table register 106-1 in 5 bits. The division of the arithmetic unit 105-1 is performed using the rising edge of the drive pulse S72 output from the output selector 120 as a trigger, the value is updated every pulse period from the output selector 120, and the 5-bit value is held during other than the update. . The table register 106-1 outputs 8-bit data corresponding to the 5-bit data output from the arithmetic unit 105-1 to the multiplier 113. The data in the table register 106-1 is a set of a 5-bit address and 8-bit data stored in advance in the table register 106-1, and details will be described later. The table register 106-2 outputs an 8-bit value corresponding to the upper 5-bit value of the 19-bit register 115 to the multiplier 113.

  The timer 114 outputs a signal for performing the calculation of the calculator 105-2 as a pulse at regular intervals. The computing unit 105-2 performs computation for each rising edge of the pulse output from the timer 114. The calculation of the calculator 105-2 is performed by adding and subtracting the 16-bit output value of the multiplier 113 and the value of the 19-bit register 115 according to the comparison result of the comparator 109-1.

In the 19-bit register 115, the upper 9 bits indicate a division ratio integer value, and the lower 10 bits indicate a division ratio decimal part. The decimal part is (10 bit value) / 1024 value. The counter lower limit register 104 is a 9-bit register, and sets an initial value in the 19-bit register 115 when the reset signal RESET is input. Further, the 9-bit value of the counter lower limit register 104 is also output to the arithmetic unit 105-2, and the value of the 19-bit register 115 is compared with the upper 9 bits when updating the operation.
(Counter lower limit value register 104 value) <(Upper 9-bit value of 19-bit register 115)
In this case, the value of the counter lower limit register 104 is set in the upper 9 bits of the 19-bit register 115.

The upper 4 bits of the 8-bit data output from the communication data processing unit 101 to the DAC 72a is input to the counter upper limit table 103, and the counter upper limit value table 103 corresponds to the 4-bit value from the 4-bit (ie 16 types) 19-bit value table. The 19-bit value is output to the arithmetic unit 105-2. The computing unit 105-2 has a computation result of (calculation result 19bit value)> (counter upper limit value).
In such a case, the calculation result is replaced with a counter upper limit table value 19 bits. The 19-bit register 115 holds the value of the frequency division ratio. The upper 9 bits of the 19-bit register 115 is an integer value, which is a cycle value of 9 bits × 20 nsec (50 MHz). The lower 10 bits of the 19-bit register 115 means a decimal value and means a value of 10 bits / 1024. The handling of decimal values will be described later. The 19-bit register 115 inputs the upper 9 bits to the comparator 109-1, the frequency divider selector 118, and the 1 adder 117. Further, the lower 10 bits of the 19-bit register 115 are output to the error holding register 116. The comparator 109-1 compares the output 9 bit of the D latch 108 with the upper 8 bits of the 19 bit register 115,
If (the output 9-bit value of the D latch 108)> (the upper 8-bit value of the 19-bit register 115), “H” is output to the arithmetic unit 105-2, and “L” is output otherwise.

  The error holding register 116 includes a 10-bit register and a 1-bit flag, and has the following functions. When the reset signal RESET is input and when the ON / OFF signal S101 output from the communication data processing unit 101 is “L”, the 10-bit register value and the 1-bit flag value are all initialized to 0. At the rising edge input of the drive pulse S72 output from the output selector 120, the lower 10-bit value output from the 19-bit register 115 and the 10-bit register value in the error holding register 116 are added, and this addition result is used as the 10-bit register value. Hold. Further, when a carry occurs during the addition, the overflow flag is set to 1, and when there is no carry, the overflow flag is cleared to 0. When the overflow flag value is 1, the output signal outputs “H” as the selection signal select to the frequency divider selector 118, and when the overflow flag is 0, the output signal is “L” as the selection signal select to the frequency divider selector 118. Is output.

  The 1 adder 117 receives the upper 9-bit value indicating the division ratio integer value output from the 19-bit register 115, and outputs a 9-bit value obtained by adding 1 to the 9-bit value to the frequency division selector 118. The frequency divider selector 118 receives the upper 9 bits of the 19-bit register 115 and the output 9 bits of the 1 adder 117, and selects one of the two inputs in response to a selection signal select that is an overflow signal output from the error holding register 116. Is selected and output. That is, the frequency divider selector 118 selects the 9-bit value of the 1 adder 117 when the selection signal select that is an overflow signal is “H”, and 19 bits when the selection signal select that is the overflow signal is “L”. The upper 9 bit value of the register 115 is selected and output to the frequency divider 119.

  The frequency divider 119 has a 9-bit counter that counts up at the rising edge of the clock signal CLK. The 9-bit output value of the frequency divider selector 118 and a value obtained by reducing the 9-bit output value to about 30%, more precisely, the 9-bit output value. The sum of the 1/4 value, 1/32 value, and 1/64 value, that is, the 9-bit output value of the frequency divider selector 118 is compared with the value obtained by right shifting 2 bits, right shifting 5 bits, and right shifting 6 bits, respectively. This frequency divider output signal is set to “L” when equal to 30% of the output value of 118, and this frequency divider output signal is set to “H” when equal to the output value of the frequency divider selector 118. At the same time, the internal counter is cleared to zero.

  Through the above operation, the frequency divider 119 outputs a pulse having an ON duty of about 30% to the output selector 120 at a frequency obtained by dividing the clock signal CLK by the frequency divider selector output value. In the frequency divider 119 according to the first embodiment, the 50 MHz clock CLK is frequency-divided into about 108 to 130 kHz, which is the piezoelectric transformer driving frequency, and therefore the frequency division ratio is in the range of about 384 (180 hex) to 463 (1 CF hex). Therefore, to be exact, the duty is 29.3 to 30.0%. The duty fluctuation within this range hardly affects the output voltage fluctuation in the circuit of the first embodiment. In the first embodiment, the sum of the shift values is shown as an example that can be calculated in one cycle. However, the frequency of the divided pulse is sufficiently low with respect to the 100 kHz range and the operating frequency of 50 MHz. It is also possible to use arithmetic.

  The output selector 120 selects the output pulse of the frequency divider 119 when the ON / OFF signal S101 output from the communication data processing unit 101 is input as the selection signal select and the ON / OFF signal S101 is “H”. When the ON / OFF signal S101 is “L”, “L” is selected, and the drive pulse S72 is output to the output port OUT11. The frequency divider 119 always outputs a pulse at the frequency division ratio of the counter initial value after resetting. However, the output selector 120 operates while the ON / OFF signal S101 provided from the communication data processing unit 101 is “L” (off). Does not output the drive pulse S72.

  7A is a diagram showing input / output values in the table register 106-1 in FIG. 6, FIG. 7-2 is a diagram showing input / output values in the table register 106-2 in FIG. 6, and FIG. These are the figures which show the input / output value in the counter upper limit table 103 in FIG.

(Overall operation of image forming apparatus)
3 and 4, when image data described in PDL (Page Description Language) or the like is input from an external device (not shown) via the host interface unit 50, the image forming apparatus 1 performs this printing. The data is converted into bitmap data (image data) by the command / image processing unit 51 and sent to the LED head interface unit 52 and the printer engine control unit 53. The printer engine control unit 53 controls the heater 59 in the fixing unit 18 according to the detection value of the thermistor 65, the heat fixing roller in the fixing unit 18 reaches a predetermined temperature, and the printing operation is started.

  The paper 15 set in the paper feed cassette 13 is fed by the hopping roller 14. The sheet 15 is conveyed onto the transfer belt 8 by the registration rollers 16 and 17 at a timing synchronized with the image forming operation described below. In the developing devices 2K, 2Y, 2M, and 2C for the respective colors, toner images are formed on the photosensitive drums 32K, 32Y, 32M, and 32C by an electrophotographic process. At this time, the LED heads 3K, 3M, 3Y, and 3C are turned on according to the bitmap data. The toner images developed by the developing devices 2K, 2Y, 2M, and 2C of the respective colors are conveyed on the transfer belt 8 by a high-voltage DC bias applied from the power supply device 70 to the transfer rollers 5K, 5Y, 5M, and 5C. Is transferred to the sheet 15 to be transferred. After the four color toner images are transferred to the paper 15, they are fixed by the fixing device 18 and discharged.

(Power supply operation)
First, a schematic operation in the power supply device 70 of FIG. 1 will be described.

  In the color image forming apparatus, transfer is four outputs, but all four circuits have the same configuration. Therefore, in the first embodiment, the operation of the one-output power supply device 70 will be described.

  The printer engine control unit 53 transmits predetermined command data from a plurality of input / output port I / O1, which are serial communication means, to a plurality of input / output ports I / O11 in the control unit 72 in the power supply device 70. To do. The controller 72 sets, for example, an 8-bit value corresponding to the command / data received at the input / output port I / O 11 to the DAC 72 a, and outputs the target voltage S 72 a from the DAC 72 a to the voltage comparison unit 78.

  For example, when the target current is 10 μA, the target voltage S72a is 0.33V and an 8-bit DAC, so it is converted to a hexadecimal number and set to a value of 1AH, and the voltage comparison means is set as a target voltage S72a (target current equivalent value) from DAC 72a to 0.336V Output to 78. As will be described later, the DAC 72a is set first at the time of high voltage output, and then the drive pulse S72 is output from the output port OUT11 of the control unit 72. At this time, the output port OUT11 maintains the “L” level output. To do.

  When the control unit 72 receives a command to turn on the high voltage output from the plurality of input / output ports I / O1 of the printer engine control unit 53 at the plurality of input / output ports I / O11, the control unit 72 is supplied from the oscillator 71. A drive pulse S72 obtained by dividing the clock CLK is output from the output port OUT11 to the piezoelectric transformer drive circuit 74. The controller 72 changes the frequency division ratio according to the comparison result S78 given from the voltage comparison means 78 to the input port IN11.

  The piezoelectric transformer drive circuit 74 switches the DC voltage 24V supplied from the DC power source 73 by the drive pulse S72 from the control unit 72, drives the primary side of the piezoelectric transformer 75, and the secondary side of the piezoelectric transformer 75. To output an AC high voltage. The AC high voltage is rectified to DC by the rectifier circuit 76, and the DC high voltage is supplied to the load ZL. At this time, a predetermined output voltage S77 is output from the output voltage supply means 77.

In the output voltage supply means 77, the secondary current of the piezoelectric transformer 75 supplied from the output current supply means 77-1 is converted into a voltage by the current-voltage conversion means 77-2, and this output voltage S77 is converted into the voltage comparison means. 78 and the ADC 72b in the control unit 72. The voltage comparison unit 78 compares the target voltage S72a corresponding to the target current output from the DAC 72a with the output voltage S77 of the current-voltage conversion unit 77-2,
(Target voltage S72a corresponding to target current)> (Output voltage S77)
In this case, “H” is output to the input port IN11 of the control unit 72 as the comparison result S78,
(Target voltage S72a corresponding to target current) <(Output voltage S77)
In this case, “L” is output to the input port IN11 of the controller 72 as the comparison result S78.

  When the output voltage S77 becomes substantially equal to the target voltage S72a corresponding to the target current, a ripple as an AC component remains in the output voltage S77 of the output voltage supply means 77, and the target voltage S72a corresponding to the target current output from the DAC 72a. Is a substantially stable DC voltage, a rectangular wave substantially synchronized with the drive pulse S72 from the control unit 72 input to the piezoelectric transformer drive circuit 74 is output from the output voltage comparison means 78 as the comparison result S78.

FIG. 8 is an operation waveform diagram in the power supply device 70 of FIG.
The detailed operation of the power supply device 70 of FIG. 2 will be described with reference to FIG.

  The printer engine control unit 53 resets various settings of the control unit 72 by setting the reset signal RESET output from the output port OUT1 to the input port IN12 of the control unit 72 in the power supply device 70 to “L”. By this reset operation, the value such as the frequency division ratio of the output of the output port OUT11 in the control unit 72 becomes the initial value. The controller 72 divides the clock CLK input from the clock input port CLK_IN by the initial value by the initial value dividing ratio (for example, ON duty 30%). However, the control unit 72 does not output the divided drive pulse S72 from the output port OUT11 until the high voltage ON command is received from the printer engine control unit 53, and the output port OUT11 is held at the “L” level. Is done.

  The printer engine control unit 53 outputs a serial clock SCLK for synchronization from the input / output port I / O1, and also outputs a serial data input signal SDI in synchronization with the serial clock SCLK to set a high-voltage output target current. An arbitrary command and 8-bit data as a DAC set value are transmitted to the control unit 72. The controller 72 outputs a target voltage S72a, which is an instruction voltage for the target current value of the high voltage output, from the DAC 72a. For example, when the target current value is 10 μA, 0.33 V is output as the target voltage S72a. In this case, since it is a 3.3V 8-bit DAC 72a, 1AH is set in a predetermined register (not shown).

  An oscillator 71 is connected to the clock input port CLK_IN of the control unit 72 via a resistor 71b. The oscillator 71 is supplied with 3.3 V of the DC power supply 71a to the power supply terminal VDD and the output enable terminal OE. Immediately after the power supply is turned on, the oscillator 71 receives the clock CLK having a frequency of 50 MHz and a cycle of 20 nsec from the clock output terminal CLK_OUT. Output to the clock input port CLK_IN.

  While the output port OUT11 of the control unit 72 is held at “L”, the NMOS 74a in the piezoelectric transformer driving circuit 74 is off, so that the DC power source 73 is connected to the primary side input terminal 75a of the piezoelectric transformer 75. DC24V supplied from is applied as it is. In this state, the current value of the DC power source 73 is approximately 0 A, and the piezoelectric transformer 75 is not oscillating. Therefore, the output voltage at the secondary output terminal 75 b of the piezoelectric transformer 75 is 0 V, and the output current is 0 A. At this time, the output voltage S77 of the operational amplifier 77b in the output voltage supply means 77 is at the VOL level.

  In the comparator 78a in the voltage comparison unit 78, since 0.336V of the target voltage S72a is input to the “+” input terminal and the VOL level of the operational amplifier 77b is input to the “−” input terminal in the above state, the operational amplifier 78a. The output terminal is DC 3.3V pulled up by the power source 71a. Therefore, “H” of the comparison result S78 is output from the operational amplifier 78a and input to the input port IN11 of the control unit 72.

  Next, after the target voltage S72a corresponding to the target current value is output from the DAC 72a in the control unit 72, the sheet 15 is transferred to the transfer roller at a predetermined timing (that is, after the sheet detection sensor 40 detects the sheet 15). Printer engine control unit 53 transmits a command to turn on the high voltage from input / output port I / O1 to input / output port IN12 of control unit 72 at the timing of reaching the nip portion between 5K and photosensitive drum 32K). To do. After the received data processing, the control unit 72 immediately outputs the drive pulse S72 divided by the initial value from the output port OUT11. In the first embodiment, the initial value is 384 frequency division, 7.68 μsec per cycle, and 29% ON duty.

  The NMOS 74a in the piezoelectric transformer drive circuit 74 is switched by the drive pulse S72 output from the output port OUT11 of the controller 72, and the primary side input terminal 75a of the piezoelectric transformer 75 is switched by the inductor 74c, the capacitor 74d, and the piezoelectric transformer 75. In addition, a half-wave sine waveform of several tens of volts shown in FIG. 8 is applied. As a result, a boosted AC voltage is generated at the secondary output terminal 75b of the piezoelectric transformer 75. However, at a driving frequency of 384 frequency division and 130 kHz, the output voltage is about 100 VAC and the output current is very small.

  Therefore, there is almost no current flowing through the resistor 77d in the output voltage supply means 77, and the output voltage S77 of the operational amplifier 77b input to the “−” input terminal of the comparator 78a in the voltage comparison means 78 is the DAC 72a in the controller 72. The comparison result S78 output from the comparator 78a is lower than the target voltage S72a output from 0.336V, and is at the “H” level pulled up by the DC 3.3V power supply 71a.

  The control unit 72 samples “H” of the comparison result S78 input from the input port IN11 for each cycle of the drive pulse S72 output from the output port OUT11, and the “72” of the comparison result S78 input to the input port IN11. The frequency of the drive pulse S72 output from the output port OUT11 is controlled so that the “H” period and the “L” period are equal. When the “H” period of the input port IN11 is 50% or more, control is performed to decrease the frequency, and when the “H” period is less than 50%, control is performed to increase the frequency. Since the frequency control value has an integer part of 9 bits and a decimal part of 10 bits, the minimum resolution is 0.33 Hz, and the duty of the rectangular wave finally inputted to the input port IN11 is 50%, and the drive pulse S72 The driving frequency is stabilized and constant current control is performed. At this time, the effective value of the output voltage S77 of the operational amplifier 77b is 0.336V.

(Operation of control unit in power supply)
The operation of the control unit 72 shown in FIG. 6 in the power supply device 70 will be described.

  When the reset signal RESET output from the output port OUT1 of the printer engine control unit 53 is input to the input port IN12 of the control unit 72, each counter value in the control unit 72 is initialized. In the 19-bit register 115, the 9-bit value of the counter lower limit register 104 is input to the upper 9 bits, and 0 is set to the lower 10 bits. The initial 19-bit value is 60000 hex. The 1-adder 117 inputs the upper 9-bit value 180 hex of the 19-bit register 115 and the 181 hex of the 1-adder 117 to the divider selector 118. In the initial state (that is, after the reset signal RESET is input), the 19-bit register 115 The higher 9-bit value 180 hex is input to the frequency divider 119.

  The frequency divider 119 outputs a pulse every time the clock CLK is counted from 0 to 180 hex. As a result, a pulse with a frequency of 384 and a duty of 30% is output from the frequency divider 119. The output selector 120 outputs a drive pulse S72 when the ON / OFF signal S101 output from the communication data processing unit 101 is turned on to “H”, and holds the output “L” otherwise. To do.

  The lower 10 bits of the 19-bit register 115 is a counter indicating a division ratio after the decimal point. The division ratio starts from 180 hex (384) division, and until it reaches 181 hex (385) division, an error of the value indicating the decimal point is added, and when the error addition result becomes 1 or more, the pulse Add 1 to the division ratio.

  For example, when the value of the 19-bit register 115 is 60200 hex, the integer part 9-bit value is 180 hex and the decimal part 10 bit is 200 hex. In this state, when the value of the error holding register 116 is 000 hex (10 bits) and the overflow flag is 0, the upper 9 bits of the 19-bit register 115 are selected by the frequency divider selector 118 and input to the frequency divider 119, and 180 hex (384) A drive pulse S72 having a frequency division of 130.208 kHz is output from the output selector 120.

  The drive pulse S72 output from the output selector 120 is applied to the piezoelectric transformer drive circuit 74 and simultaneously input to the error holding register 116. The error holding register 116 adds the 000 hex (10 bits) value and the lower 10 bits 200 hex of the 19 bit register 115, holds the addition result 200 hex, and sets the overflow flag to “L”.

  Similarly, when the next drive pulse S72 is output, the error holding register 116 adds the decimal part 200 hex and the error holding register value 200 hex to 400 hex, and the holding range of the 10-bit register value in the error holding register 116 is 000 to 3FF, the value of the error holding register 116 is set to 000 hex, and the overflow flag is set to “H”. The frequency instruction value output from the 19-bit register 115 has an integer part of 180 hex (384), a decimal part of 200 hex (512), and a real value of 384.5. As described above, in this case, a pulse of 384 frequency division and a pulse of 385 frequency division are alternately output from the output selector 120, and the average frequency division ratio is 384.5.

  When the decimal part is 180 hex, the value of the error holding register 116 is 000 hex, 180 hex, 300 hex, and 080 hex. When the value is 300 hex to 080 hex, the overflow flag output from the error holding register 116 is “H”. . When the integer part of the error holding register 116 is N, the division ratio is changed to N division, N division, N division, N + 1 division, and the average division ratio is finally N + (384/1024). It becomes.

  The division ratio instruction value output from the 19-bit register 115 is updated by the arithmetic unit 105-2. This update process will be described below.

  While the communication data processing unit 101 sets the high voltage ON / OFF signal S101 to “L”, the output selector 120 outputs “L”, and the piezoelectric transformer drive circuit 74 is turned off.

  In order to start the printing operation and output the transfer bias from the transfer bias generator 93, the image forming apparatus 1 first sets the DAC set value corresponding to the transfer target current with predetermined command data and the printer engine controller 53. To the control unit 72 by serial communication signals (for example, SCLK, SDI, SDO). When receiving the command data, the communication data processing unit 101 in the control unit 72 outputs 8-bit data to the DAC 72a. Thereby, for example, it is assumed that each circuit constant is set so that the target voltage S72a output from the DAC 72a is 0 to 3.3 V and the output current range is 0 to 100 μA. In this case, the resistance 77d in FIG. 2 is 33 kΩ. When the transfer target current is 10 μA, the set value of the DAC 72a is 1 Ahex. The DAC 72a outputs 0.336V of the target voltage S72a.

  At this time, the high voltage has not been output yet, the output voltage S77 of the operational amplifier 77b in FIG. 2 is almost 0V, 0V is applied to the “−” input terminal of the comparator 78a, and the “+” input terminal The target voltage S72a of 0.336V is applied. Therefore, the output terminal of the comparator 78a becomes an open collector output, and 3.3 V pulled up by the resistor 78b is input to the input port IN11 of the control unit 72 as the comparison result S78.

  Although the comparison result S78 becomes “H”, the up counter 107 in the control unit 72 only overflows and repeatedly counts up because the output terminal of the output selector 120 holds “L”. The D latch 108 holds the initial value 000000000000b because the ON / OFF signal S101 output from the communication data processing unit 101 is “L” and the output signal of the AND circuit 102 is also “L”. .

  The 19-bit register 115 is set to an initial value of 60000 hex (that is, the upper 9-bit integer part is 180 hex and the lower 10-bit decimal part is 000 hex). Since the output 9 bit of the D latch 108 is 000 hex and the upper 8 bits of the 19 bit register is C0 hex, the comparator 109-1 compares both values, and since 000 hex <C 0 hex, "L" is sent to the arithmetic unit 105-2. Output.

  The output signal of the D latch 108 is input to the NOT circuit 110 and the comparator 109-2. The 9-bit value 000hex input to the NOT circuit 110 is inverted and output, 1FF hex is input to the 9-input AND circuit 111, and the output “H” of the 9-input AND circuit 111 is input to the OR circuit 112. The comparator 109-2 compares the 9-bit value (000 hex) with 17F hex obtained by subtracting 1 from the higher 9 bits (180 hex) of the 19-bit register 115, and (the output value of the D latch 108 <17F hex). "Is output to the OR circuit 112. The OR circuit 112 receives “H” from the 9-input AND circuit 111 and “L” from the comparator 100-2, and outputs “H” to the multiplier 113.

  The ADC 72b converts the analog output voltage S77 supplied from the output voltage supply unit 77 into 12-bit digital data. The ADC 72b converts the output voltage S77 into a digital value every predetermined cycle, updates the output 12-bit data every conversion cycle, and holds the digital value until the update. In a state where no high voltage is output, 000 hex is output. The arithmetic unit 105-1 performs data processing on the output value 12 bits of the ADC 72b and the set value 8 bits of the DAC 72a, and outputs 5-bit data to the table register 106-1.

FIG. 9 is a flowchart showing data processing in the arithmetic unit 105-1 in FIG.
The arithmetic unit 105-1 starts data processing in step ST1, determines in step ST2 whether or not the set value of the DAC 72a is greater than 01 hex, and if so (Y), proceeds to step ST3, otherwise. If (N), the process proceeds to step ST4. In step ST3, it is determined whether or not the detected value of the ADC 72b is equal to or greater than 020 hex. If it is larger (Y), the process proceeds to step ST5, and if not (N), the process proceeds to step ST6.

  In step ST4, it is determined whether or not the integer value (the remainder is rounded down) obtained by dividing the ADC detection value 12 bits by the DAC setting value 8 bits is 20 hex or more. If it is large (Y), the process proceeds to step ST7. If (N), the process proceeds to step ST8. In step ST5, the 5-bit output value of the arithmetic unit 105-1 is output as 1Fhex. In step ST6, the 5-bit output value of the arithmetic unit 105-1 is set to the lower 5 bits of the input ADC detection value 12 bits. In step ST7, the output value 5 bits of the arithmetic unit 105-1 is output as 1Fhex. In step ST8, the output value 5bit of the arithmetic unit 105-1 is set to (ADC detection value 12bit) / (DAC setting value 8bit).

  In the control unit 72 of FIG. 6, since the detection value of the ADC 72b is 000 hex, the output value of the computing unit 105-1 is 00 hex (5 bits). The detection cycle of the ADC 72b and the calculation cycle of the calculator 105-1 do not need to be synchronized, and may be shorter than the 1-bit signal cycle output from the timer 114 described later.

  The data processing of the arithmetic unit 105-1 has been described with reference to the flowchart of FIG. 9, but is constituted by a known division circuit that is processed in the clock CLK cycle which is a predetermined cycle. The table register 106-1 receives 5 bits of data from the arithmetic unit 105-1, and outputs 8 bits of data to the multiplier 113. The relationship between the input and output values of the table register 106-1 is shown in FIG. In this case, since the input value of the table register 106-1 is 00 hex (5 bits), C0 hex (8 bits) is output from the table register 106-1.

  The table register 106-2 receives the upper 5 bits of the data from the 19 bit register 115 and outputs the 8 bits to the multiplier 113. The input / output values are shown in FIG. Since the upper 5 bits of the 19-bit register 115 is 18 hex, the table register 106-2 outputs 80 hex (8 bits) to the multiplier 113.

  When the output signal of the OR circuit 112 is “H”, the multiplier 113 multiplies the output value 8 bits of the table register 106-1 and the output value 8 bits of the table register 106-2 to obtain a 16-bit value as the arithmetic unit 105−. Output to 2. When the output signal of the OR circuit 112 is “L”, the multiplier 113 outputs a fixed 16-bit value of 0001 hex to the arithmetic unit 105-2. In this case, the output value of the multiplier 113 is (C0 hex) × (80 hex) = 6000 hex.

  The timer 114 has a 12-bit counter, and inverts the 1-bit output value every time the counter overflows. As a result, the timer 114 outputs a pulse of 6.1 kHz and a pulse of 6.1 kHz to the calculator 105-2.

  The computing unit 105-2 performs computation every time the pulse input from the timer 114 rises. As described above, since the comparison result of the comparator 109-1 is “L”, the arithmetic unit 105-2 calculates 6000 hex which is the 16-bit output value of the multiplier 113 from the 19-bit value input from the 19-bit register 115. Subtraction is performed and the calculation result is 60000-6000 = 5A000 hex. The calculator 105-2 compares the calculation result with the value of the counter lower limit register 104 at the time of subtraction.

  The lower limit value of the counter lower limit register 104 is a 9-bit value of 180 hex. Compared with the higher 9 bits of 168 hex of 5A000 hex, since 180 hex> 168 hex, the upper 9 bits of the calculation result in the arithmetic unit 105-2 is set to 180 hex. As a result, the 19-bit register 115 is updated to a value of 60000 hex and holds substantially the same value. The value of the 19-bit register 115 is maintained at a value of 60000 hex until the high voltage output ON / OFF signal S101 becomes “H”. Since the upper 9 bits of the 19-bit register 115 is 180 hex and the lower 10 bits are 000 hex, 180 hex is output to the frequency divider 119.

The frequency divider 119 is 180 hex (that is, 384 CLK period), and turns on a pulse having a period of 7.69 μsec on time (“H”),
Dividing counter value / 4 + dividing counter value / 32 + dividing counter value / 64
= 96 + 12 + 6 = 114 CLK period, that is, a pulse having an ON duty of about 30% at 2.28 μsec is output to the output selector 120. Since the ON / OFF signal S101 is “L”, the output selector 120 outputs “L”.

  As described above, first, the DAC set value corresponding to the target current is transmitted from the printer engine control unit 53 to the control unit 72, and the control unit 72 internally generates the drive pulse S72 with the initial value.

  Next, the image forming apparatus 1 starts a paper feeding operation, and after a predetermined time after the printer engine control unit 53 detects the leading edge of the paper by the paper detection sensor 40, a serial communication signal (for example, SCLK, SDI, SDO). Command data for turning on the high-voltage output is transmitted to the communication data processing unit 101 in the control unit 72. The communication data processing unit 101 immediately sets the ON / OFF signal S101 to “H” after the command / data reception processing.

  When the ON / OFF signal S101 becomes “H”, the output selector 120 outputs a drive pulse S72 with a 130.2 kHz, 30% duty, and a current flows to the secondary output terminal 75b of the piezoelectric transformer 75. At this time, the current value is also low, and the comparison result S78 output from the comparator 78a maintains the “H” level.

  The up counter 107 counts the “H” period of the comparison result S78 for each drive pulse S72 output from the frequency divider 119. While the comparison result S78 is maintained at “H”, counting and resetting to the upper 9-bit value of the 19-bit register 115 or the value of (9-bit value + 1) are repeated. Simultaneously with the reset, the count value immediately before the reset is held in the D latch 108. The drive pulse S72 obtained by ANDing the “H” level of the ON / OFF signal S101 by the AND circuit 102 is input to the D latch 108 and latched at the rising edge of this input. As a result, the upper 9-bit value of the 19-bit register 115 or the value of (9-bit value + 1) is held in the D latch 108.

The held value 9 bits of the D latch 108 is input to the comparator 109-1 and compared with the upper 8 bits of the 19-bit register 115. In the comparator 109-1, C0 hex (8 bits), which is a half value of the initial 9 upper bits, is compared with 180 or 181 hex,
(D latch output 9-bit value)> (19-bit register upper 8-bit value)
Therefore, the comparison result of the comparator 109-1 becomes “H”, and this “H” is input to the arithmetic unit 105-2. Further, the output signal of the D latch 108 is also input to the comparator 109-2 and compared with the upper 9 bits of the 19-bit register 115.
(D latch output 9-bit value)> (19-bit register upper 9-bit value-1)
Therefore, the comparator 109-2 outputs “H”. Since the 9-input AND circuit 111 outputs “H” only when the output 9 bits of the D latch 108 are all 0, in this case, “L” is output to the OR circuit 112. The OR circuit 112 receives “H” and “L” and outputs “H” to the multiplier 113.

Since the detection value of the ADC 72b is 000 hex, the table register 106-1 outputs C0 hex and the table register 106-2 outputs 80 hex to the multiplier 113, respectively, as described above. Since the output signal of the OR circuit 112 is “H”, the multiplier 113 is
(C0) × (80) = 6000 hex
Are output to the arithmetic unit 105-2. Since the comparison result of the comparator 109-1 is “H”, the arithmetic unit 105-2 adds the 6000 hex to 60000 hex of the 19-bit register 115, and sets 19 bits of 66000 hex to the output 19-bit value of the counter upper limit table 103. Compare.

  The counter upper limit value table 103 is a table for inputting the upper 4 bits of the DAC set value and outputting 19 bits. The relationship between the input and output values is shown in FIG. Since the DAC setting value is 1Ahex, the upper 4 bits are 1hex in this case. The output value 19 bits of the counter upper limit value table 103 is 70664 hex. The arithmetic unit 105-2 compares with the 66000 hex and is less than or equal to the upper limit table value, and thus updates the 19-bit register 115 with the value of 66000 hex. Thereafter, the 9-bit value is output to the 1 adder 117 and the frequency divider selector 118 as the updated value, and the frequency divider 119 outputs a pulse to the output selector 120 at the updated lower frequency.

  Thereafter, in the same flow, the frequency of the drive pulse S72 output from the output selector 120 is lowered. As a result, the high voltage output voltage is increased, and the high voltage output current is increased accordingly. As the output current increases, the detected value 12 bits of the ADC 72b changes, and the output values of the arithmetic unit 105-1, the table register 106-1, and the table register 106-2 are also shown in FIGS. 7-1 and 7-2. It will change as shown.

  When the frequency of the drive pulse S72 is controlled to be low and the high voltage output current becomes around 10 μA of the target current value as the high voltage output voltage increases, the holding value of the D latch 108 that holds the value of the up counter 107 is The value of the upper 9 bits of the 19-bit register 115 becomes smaller, and the output signal of the OR circuit 112 becomes “L”. As a result, the output 16-bit value of the multiplier 113 becomes 0001 hex, and the arithmetic unit 105-2 updates the 19-bit register 115 one by one.

  By updating the decimal part 10 bits in the 19-bit register 115 one by one (ie, adding one by one), the change of the two input signals input to the frequency divider selector 118 is reduced, and the error is retained by the lower 10-bit i value of the 19-bit register 115. The value of the register 116 changes, and the ratio per unit time of the frequency division ratio N and the frequency division ratio N + 1 selected by the frequency division selector 118 changes.

  When the target current is reached, only the least significant bit of the 19-bit register 115 repeats increasing and decreasing, the average frequency of the output drive pulse S72 changes less than ± 1 Hz, and the output current is stabilized at 10 μA.

  Immediately before the sheet 15 in the image forming apparatus 1 passes through the transfer nip, that is, after a predetermined period of time after the trailing end of the sheet 15 passes through the sheet detection sensor 40, the printer engine control unit 53 receives command data for instructing high voltage off. The data is transmitted to the communication data processing unit 101 in the control unit 72 by serial communication. The communication data processing unit 101 sets the setting data of the DAC 72a to 00 hex, and then sets the ON / OFF signal S101 to “L”. By setting the DAC setting data to 00 hex, the comparison result S78 output from the comparator 78a becomes “L”, and the output 9 bits of the D latch 108 becomes 000 hex within two output cycles of the drive pulse S72.

  Subsequently, the communication data processing unit 101 sets the ON / OFF signal S101 to “L” and the output value of the drive pulse S72 to “L”. As a result, the driving of the piezoelectric transformer 75 is stopped and the high voltage output is turned off. When the output value of the D latch 108 becomes 000 hex, the value of the 19-bit register 115 is subtracted by the arithmetic unit 105-2 from the value 9 bits of the counter lower limit register 104 to 180 hex and 19 bits to 60000 hex. Return and wait until the next high voltage output instruction by printing.

(Modification of Example 1)
The first embodiment may be modified as in the following (a) to (d).

  (A) In the first embodiment, the piezoelectric transformer 75 having a resonance frequency of about 108 kHz and a driving frequency range of 108 to 130 kHz is used. However, a piezoelectric transformer having a smaller driving frequency and a higher driving frequency may be used. A piezoelectric transformer having a large driving frequency and a low driving frequency may be used.

  (B) In the first embodiment, the frequency of the clock CLK is 50 MHz, but it can be realized even at a low frequency such as 20 MHz.

  (C) In the first embodiment, processing is performed with the integer part 9 bits and the decimal part 10 bits of the 19-bit register 115, but the optimum value differs depending on the required frequency resolution, and the number of bits is not limited to this.

  (D) In the first embodiment, the case of one transfer channel has been described. However, it can also be realized by arranging a plurality of channels in parallel.

(Effect of Example 1)
According to the first embodiment, since the output voltage supply means 77 is provided at the secondary output terminal 75b of the piezoelectric transformer 75 to perform constant current control, the peak of the resonance frequency in the piezoelectric transformer 75 is exceeded during frequency control. Thus, it becomes possible to control with a predetermined transfer current value without becoming uncontrollable. Furthermore, by setting the frequency limit to a different value depending on the target current value, the piezoelectric transformer 75 can be controlled within the withstand voltage ranges of the rectifier diodes 76a and 76b and the capacitor 76c. In addition, since stable constant current control is possible, stable output is possible regardless of the environment, and a stable image without density step and horizontal stripes can be obtained.

  In the second embodiment of the present invention, the configuration is the same as the configuration of the image forming apparatus 1 in FIG. 3 and the control circuit in FIG. 4 in the first embodiment, and the configuration is different from the power supply apparatus 70 in FIG. 2 in the first embodiment. A power supply device according to the second embodiment will be described.

(Configuration of power supply)
FIG. 10 is a block diagram illustrating a schematic configuration of the power supply device according to the second embodiment of the present invention. Elements common to those in FIG. 1 illustrating the power supply device according to the first embodiment are denoted by common reference numerals. Yes.

  Similarly to the first embodiment, the power supply device 70A of the second embodiment shows only one circuit of each color, and is different from the control unit 72, the rectifier circuit 76, and the output voltage supply unit 77 of the first embodiment. The control unit 72A, the rectifier circuit 76A, and the output voltage supply means 77A are provided, and the output voltage detection means 79 is further added. Other configurations are the same as those of the first embodiment.

  The control unit 72A of the second embodiment is a circuit that operates in synchronization with the clock CLK supplied from the oscillator 71, and that is controlled by the printer engine control unit 53 to output the drive pulse S72A, as in the first embodiment. Yes, it is composed of an ASIC, a microprocessor with a built-in CPU, or an FPGA. The control unit 72A of the second embodiment includes a clock input port CLK_IN, input ports IN11 and IN12, a plurality of input / output ports I / O11, and an output port OUT1 that outputs a drive pulse S72A, as in the first embodiment. DAC 72a similar to Example 1, ADC 72b having the same 0-3.3V range and 12-bit resolution as Example 1, ADC 72d having a newly added 0-3.3V range and 8-bit resolution, etc. Have.

  The rectifier circuit 76A is a circuit that converts the AC output voltage of the piezoelectric transformer 75 into a DC voltage, similarly to the rectifier circuit 76 of the first embodiment. Unlike the rectifier circuit 76 of the first embodiment, the rectifier circuit 76A is configured to output a negative bias. It has become. The output voltage supply unit 77A has a polarity opposite to that of the output voltage supply unit 77 of the first embodiment, and the output current supply unit 77A-1 and the output of 0 to 255 μA with respect to 0 to 100 μA of the first embodiment. It comprises current-voltage conversion means 77A-2 that outputs an output voltage S77A having a range.

  The output voltage detection means 79 is connected to the output side of the rectifier circuit 76A, detects the high voltage of negative bias that is the output voltage of the rectifier circuit 76A, converts it to a voltage in the range of 0 to 3.3V, and this conversion is performed. The voltage is supplied to the ADC 72d in the control unit 72A.

  FIG. 11 is a circuit diagram illustrating a detailed configuration example of the power supply device 70A of FIG. 10. Elements common to those in FIG. 2 illustrating the power supply device 70 of Embodiment 1 are denoted by common reference numerals. .

  The rectifier circuit 76A includes diodes 76e and 76f and a capacitor 76c for converting the AC voltage output from the secondary output terminal 75b of the piezoelectric transformer 75 into a negative bias DC voltage. The output voltage supply unit 77A includes capacitors 77a and 77c and an operational amplifier 77b similar to the output voltage supply unit 77 of the first embodiment, and a resistor 77e having a resistance value (for example, 13 kΩ) different from the resistor 77d of the first embodiment. Has been. The “+” input terminal of the operational amplifier 77b is grounded in the first embodiment, but in the second embodiment, unlike the first embodiment, the “+” input terminal is connected to the DC 3.3V power source 71a.

  The output voltage detection means 79 includes an operational amplifier 79a having a voltage follower circuit configuration, two voltage dividing resistors 79b and 79c for dividing the DC output voltage of the rectifier circuit 76A, and a voltage between the voltage dividing resistors 79b and 79c. The input resistor 79d is input to the “+” input terminal of the operational amplifier 79a, and the output terminal of the operational amplifier 79a is connected to the ADC 72d in the control unit 72A.

(Configuration of control unit in power supply)
FIG. 12 is a configuration diagram illustrating the control unit 72A in FIG. 11. Elements common to the elements in FIG. 6 illustrating the control unit 72 of the first embodiment are denoted by common reference numerals.

  In the control unit 72A of the second embodiment, instead of the counter upper limit value table 103, the arithmetic unit 105-2, and the table registers 106-1 and 106-2 in the control unit 72 of the first embodiment, these are configured or function. Are provided with a counter upper limit value table 103A, an arithmetic unit 105A-2, and table registers 106A-1 and 106A-2, and an ADC 72d, a comparator 109-3, and NOT circuits 121-1 to 121-3 are added. Has been. Other configurations are the same as those of the first embodiment.

  The ADC 72b that receives the output voltage S77A of the output voltage supply unit 77A is an output circuit that converts the input analog output voltage S77A of 0 to 3.3 V into a digital signal and outputs a value of 12 bit value 000hex to FFFhex. The computing unit 105-1 is connected to the output side via a 12-input 12-output NOT circuit 121-1. The 12-input 12-output NOT circuit 121-1 is a circuit that inverts the output voltage of the ADC 72b and supplies the inverted voltage to the computing unit 105-1.

  On the output side of the communication data processing unit 101, a DAC 72a is connected via a NOT circuit 121-2 with 8 inputs and 8 outputs, and a counter upper limit value table 103A is connected. The 8-input 8-output NOT circuit 121-2 is a circuit that inverts the output 8 bits of the communication data processing unit 101 and supplies it to the DAC 72a. The counter upper limit table 103A has different input / output values from the counter upper limit value table 103 of the first embodiment, and the upper 4 bits of the DAC setting value for the DAC 72a output from the communication data processing unit 101 is input. 15-bit data corresponding to 15 is output to the comparator 109-3.

The ADC 72d is also connected to the input side of the comparator 109-3. The ADC 72d converts the output voltage 0 to 3.3 V of the output voltage detection means 79 into an 8-bit value of 00 hex to FF hex, and outputs the conversion result 8 bit to the comparator 109-3. The comparator 109-3 compares the output 8-bit value of the counter upper limit value table 103A with the output 8-bit value of the ADC 72d,
(Output 8-bit value of counter upper limit value table 103A)> (Output 8-bit value of ADC 72d)
In such a case, the comparison result “H” is output to the computing unit 105A-2, and if not, the comparison result “L” is output to the computing unit 105A-2.

  The comparison result S78 output from the voltage comparison means 78 is inverted by the 1-input 1-output NOT circuit 121-3 and input to the up counter 107.

  The table registers 106A-1 and 106A-2 connected to the input side of the multiplier 113 have different input / output values from the table registers 106-1 and 106-2 of the first embodiment. Further, the arithmetic unit 105A-2 connected to the output side of the multiplier 113 has a function compared with the counter upper limit value table 103 at the time of addition in the first example compared to the arithmetic unit 105-2 of the first example. When the comparison result of the comparator 109-3 is “H” and the comparison result of the comparator 109-1 is “H”, the value of the 19-bit register 115 is set to the same value without being updated. However, the arithmetic unit 105A-2 performs subtraction with respect to the 19-bit register 115 when the comparison result of the comparator 109-1 is “L”.

  13-1 is a diagram showing input / output values in the table register 106A-1 in FIG. 12, FIG. 13-2 is a diagram showing input / output values in the table register 106A-2 in FIG. 12, and FIG. FIG. 13 is a diagram showing input / output values in a counter upper limit value table 103A in FIG.

(Operation of Example 2)
In the second embodiment, the operations of the image forming apparatus 1 in FIG. 3 and the control circuit in FIG. 4 are the same as those in the first embodiment. Hereinafter, operations of parts different from the first embodiment will be described.

  In the first embodiment, the operation when the power supply device 70 of FIGS. 1 and 2 is used as a transfer bias has been described. In the second embodiment, the power supply device 70A of FIGS. 10 and 11 is used as a charging bias. The operation of will be described.

  The power supply device 70A according to the second embodiment includes, for example, a control unit in the high-voltage control unit 60 and the charging bias generator 91 in FIG. 2 (= 2K, 2Y, 2M, 2C) is applied to each charging roller 36 (= 36K, 36Y, 36M, 36C), and the photosensitive drum 32 (= 32K, 32Y, 32M, 32C) of each color is applied. Charges up. Charging is started simultaneously with the start of driving of each charging roller 36 and each photosensitive drum 32 by a motor, and the application is stopped simultaneously with stopping.

First, the operation of the power supply device 70A shown in FIG. 10 will be described.
Immediately before the start of the printing operation, the printer engine control unit 53 sends an 8-bit DAC set value corresponding to the target current value to the control unit 72A by using a plurality of input / output ports I / O1, which are serial communication means. And data pairs. The data is 8 bits, 0 to FF hex, and corresponds to 0 to -255 μA. Next, the printer engine control unit 53 drives a motor (not shown) and simultaneously transmits a charging bias ON command to the control unit 72A through the plurality of input / output port I / O1.

  The control unit 72A that has received the command outputs a drive pulse S72A from the output port OUT11, and drives the piezoelectric transformer drive circuit 74 as in the first embodiment. The high voltage current output to the secondary output terminal 75b of the piezoelectric transformer 75 is supplied with the reverse polarity to the first embodiment by the output current supply means 77A-1 in the output voltage supply means 77A, and the current-voltage conversion means. The output voltage S77A is output after being converted into a voltage at 77A-2.

  The drive supplied to the piezoelectric transformer drive circuit 74 when the high voltage output value reaches the target current or the voltage detected by the output voltage detection means 79 is converted to a digital value by the ADC 72d and exceeds a predetermined threshold value. The frequency of the pulse S72A is stabilized at the target current or the upper limit voltage.

This operation will be described in detail with reference to FIG.
Since serial communication is the same as that of the first embodiment, description thereof is omitted. In the output voltage supply unit 77A, the “+” input terminal of the operational amplifier 77b is connected to the DC 3.3V power source 71a. Therefore, the level of the “−” input terminal of the operational amplifier 77b is also approximately 3.3V. The resistance 77e connected between the “−” input terminal and the output terminal of the operational amplifier 79a has a resistance value of, for example, 13 kΩ. Sometimes it becomes 3.3V.

  In the output voltage detecting means 79, for example, the resistance value of the voltage dividing resistor 79b is 150 kΩ, and the resistance value of the voltage dividing resistor 79c is 100 MΩ. The voltage dividing resistors 79b and 79c allow the negative bias output voltage and the positive potential 3. Divide between 3V. Therefore, when the negative bias potential output from the rectifier circuit 76A is 0V, the output voltage of the operational amplifier 79a is 3.3V, and when the output potential is -2200V, the output voltage of the operational amplifier 79a is 0V.

Next, the operation of the control unit 72A shown in FIG. 12 will be described in detail.
The communication data processing unit 101 in the control unit 72A receives the charging bias setting value as a predetermined command data by a serial communication signal (for example, SCLK, SDI, SDO) immediately before starting printing. For example, in the case of a set current of −120 μA, the communication data processing unit 101 receives 78 hex as data and outputs 8 bits of output data as 78 hex. The data 78 hex is inverted by the NOT circuit 121-2, converted into 87 hex, and set in the DAC 72a. The DAC 72a
3.3 (V) × 135 (87 hex) /255=1.747V
The target voltage S72a is output to the comparator 78a in FIG. Thus, in the initial state, the comparator 78a receives 3.3V at the “−” input terminal and 1.747 V at the “+” input terminal.

  Next, the communication data processing unit 101 in FIG. 12 receives a charging bias-on command from the printer engine control unit 53 at the same time that the drive motors such as the respective photosensitive drums 32 of the image forming apparatus 1 are turned on. The ON / OFF signal S101 is immediately set to “H”. The control unit 72A operates with a clock CLK of 50 MHz, and the meaning of “immediately” is, for example, within about 1 msec, which is low in terms of the operation speed of the control unit 72A.

  The comparison result S78 output from the comparator 78a in FIG. 11 is “L” in the initial state. Since this “L” is inverted by the NOT circuit 121-3 and input to the up counter 107, the frequency of the drive pulse S72A is controlled as in the first embodiment. When the charging current becomes -119.5 μA, the output voltage S77A of the operational amplifier 77b becomes 1.747V, and the constant current control is completed.

  The output voltage S77A of the output voltage supply means 77A is converted into a 12-bit digital value of 000 to FFF hex by the ADC 72b. When the output current is 0 A, 3.3 V is converted and becomes FFF hex. This is inverted by the NOT circuit 121-1, becomes 000 hex, and is input to the arithmetic unit 105-1. Subsequent circuit operations are the same as those in the first embodiment by being logically inverted by the NOT circuit 121-1. The table registers 106A-1 and 106A-2 differ from the first embodiment only in the internal tables shown in FIGS. 13-1 and 13-2, and other operations are the same as those in the first embodiment.

  The upper 4 bits of the DAC set value before inversion is input to the counter upper limit value table 103A, and 8 bits are output to the comparator 109-3. That is, the counter upper limit value table 103A receives the upper 4 bits and 7 hex of 78 hex, and outputs 51 hex to the comparator 109-3 as shown in FIG. The output voltage of the output voltage detection means 79 obtained by dividing the output voltage of the rectifier circuit 76A in FIG. 11 by the voltage dividing resistors 79b and 79c is converted into 8-bit digital data by the ADC 72d and input to the comparator 109-3. . The comparator 109-3 compares the 51 hex data with the 8-bit data, and the comparison result is output to the computing unit 105A-2.

  The arithmetic unit 105A-2 adds the 19-bit register 115 (that is, controls the frequency of the drive pulse S72A to be decreased) according to the comparison result of the comparator 109-3 so that the converted value by the ADC 72d does not exceed 51 hex. ).

  The 51 hex value corresponds to 1.048V, and the output voltage is controlled not to be −1500V or less. As is clear from the counter upper limit value table 103A shown in FIG. 13C, the absolute value of the output current set value is a limit value smaller than −1500 V in the region where the absolute value is larger than −176 μA. In the region where the output current is large, the output voltage maximum value of the piezoelectric transformer 75 becomes low. Therefore, by setting the upper limit of the control voltage, the piezoelectric transformer 75 is set so as not to be controlled to a low frequency exceeding the resonance frequency. . In this case, when the upper 4 bits are Bhex (that is, the current set value is -176 to -191 μA), the limit value is 68 hex (that is, 1.346 V, and the output voltage upper limit (absolute value) is -1300 V).

(Effect of Example 2)
According to the second embodiment, since the control is performed by setting the upper limit of the output voltage at the time of constant current control, even when the piezoelectric transformer 75 is used for the charging bias having a large load fluctuation, the resonance of the piezoelectric transformer 75 is achieved. Stable constant current control can be performed without exceeding the frequency. Further, since the control frequency resolution is increased by binarization of the frequency instruction value by the error diffusion method using the error holding register 116, 19-bit register 115, 1 adder 117, and frequency divider selector 118, output fluctuation at the time of control Stable control is possible with almost no noise.

(Other variations)
The present invention is not limited to the first and second embodiments and the modifications described above, and the following other modifications can also be applied.

  In the embodiments, the color tandem type image forming apparatus 1 has been described. However, the present invention is not limited to color, and can also be applied to other image forming apparatuses such as monochrome and monochrome image forming apparatuses. The power supply devices 70 and 70A can also be applied to other high-voltage power supplies other than those for transfer and charging.

DESCRIPTION OF SYMBOLS 1 Image forming apparatus 53 Printer engine control part 60 High voltage control part 61 Charging bias generation part 62 Development bias generator 63 Transfer bias generation part 70, 70A Power supply apparatus 72, 72A Control part

Claims (9)

An oscillator for generating a clock;
Based on a control signal, pulse output means for dividing the clock and outputting a pulse;
A switching element driven by the pulse;
A piezoelectric transformer that outputs an alternating high voltage from the secondary side when a voltage is intermittently applied to the primary side by the switching element;
Rectifying means for converting the alternating high voltage into a direct high voltage;
Output current supply means for supplying a secondary output current of the piezoelectric transformer;
Current-voltage conversion means for converting the secondary output current into a voltage and outputting an output voltage;
Target current setting means for setting a target current and outputting a target voltage corresponding to the target current;
Anda voltage comparing means for outputting a comparison result by comparing the target voltage and the output voltage,
By changing the output frequency of the pulse according to the comparison result, and controlling the output frequency so that the comparison result becomes a rectangular wave at the output period of the pulse, constant current control is performed for the high DC voltage A power supply that
A division ratio of the clock is a combination of an α division and a β division, which are integer values in N (where N is a positive number) pulse period, and the pulse of the α division is The power supply apparatus according to claim 1, wherein the average period of the N pulses is controlled by changing a combination of the β-divided pulses and the pulses. An integer value conversion means for holding a frequency division ratio indicating value for the frequency division ratio as a real value and converting the real value to an integer value for each pulse output,
2. The power supply device according to claim 1, wherein the average period of the pulse output becomes a real value by outputting the pulse at a frequency division ratio of the converted integer value and controlling the real value. . 3. The power supply apparatus according to claim 2, wherein the integer value converting means is constituted by binarizing means using an error diffusion method. 3. The power supply apparatus according to claim 2, wherein the step of changing the real value, which is the division ratio instruction value, is varied according to the value of the output voltage output from the current-voltage conversion means. 3. The power supply device according to claim 2, wherein the step of changing the real value, which is the division ratio instruction value, is made variable according to the frequency characteristics of the piezoelectric transformer. 3. The power supply according to claim 2, wherein an upper limit value of the real value that is the division ratio instruction value is held, and control is performed so that the division ratio instruction value that is a control value does not exceed the upper limit value. apparatus. 7. The power supply apparatus according to claim 6, wherein the upper limit value of the division ratio instruction value is variable according to the value of the target current set by the target current setting means. Output voltage detection means for detecting the high DC voltage converted by the rectification means;
The power supply apparatus according to any one of claims 1 to 7, wherein a control result of the output voltage detection means is controlled so as not to exceed a predetermined value. The power supply device according to any one of claims 1 to 8, comprising:
An image forming apparatus that is driven by the DC high voltage to form an image on a medium.

Images