JP2006340413A - High voltage power supply - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high voltage power supply which can output a stabilized voltage by performing drive control of a piezoelectric transformer precisely. <P>SOLUTION: The high voltage power supply 1 is arranged such that a detection circuit 4 creates the detection signal RiS of a half wave voltage signal from a load current outputted from a piezoelectric transformer 6, and a control circuit 2 creates a gate signal RiG including information of phase difference between a load current and a drive signal DRi incident to variation in inherent resonance frequency of the piezoelectric transformer 6 from the detection signal RiS and the drive signal DRi of a switching element Q1. A new drive signal DRi is created based on a frequency division ratio correction amount consisting of the difference between the count of the drive signal DRi for a half time duration and the count of the gate signal RiG and on a preset frequency division ratio, and then it is inputted to the switching element Q1. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a high-voltage power supply device used for an image forming apparatus such as a printer or a copying machine, and more particularly to a driving technique for a piezoelectric transformer.

  Conventionally, in image formation of an image forming apparatus, a charger that charges the surface of the photosensitive drum to a uniform potential, a developer that forms a toner image from an electrostatic latent image on the surface of the photosensitive drum, and a toner on the surface of the photosensitive drum A high voltage is applied from a high-voltage power supply device to a transfer roller or the like that transfers the image to the paper, and a toner image is formed on the paper.

  Conventionally, a high-voltage power supply device used for image formation of an image forming apparatus has used a winding transformer. However, the winding transformer needs to be insulated by separating the primary and secondary in order to handle a high voltage. As a result, power conversion efficiency was poor. Moreover, since the winding transformer uses an organic substance in a bobbin that winds a copper wire, there is a risk of combustion, and therefore, a protective measure must be sufficiently taken. The protection measures complicate the circuit configuration and increase the manufacturing cost.

  However, in recent years, a high-voltage power supply device has been proposed in which a piezoelectric transformer that does not require an organic substance is used as a substitute for the winding transformer. This piezoelectric transformer operates efficiently at a natural resonance frequency determined by its length and thickness, but due to dimensional tolerances, deviations in the natural resonance frequency occur between individual piezoelectric transformers. In addition, the natural resonance frequency of the piezoelectric transformer fluctuates due to load fluctuations and temperature changes.

Therefore, in order to compensate for these drawbacks, for example, the zero cross of the drive current of the piezoelectric transformer is detected from the drive current flowing from the input side (primary side) of the piezoelectric transformer toward the ground, and the drive frequency is detected by the zero cross detection signal. A high-voltage power supply device that resets and sets the counter that generates the signal to synchronize the phases of the drive voltage and the drive current is disclosed and proposed (for example, see Patent Document 1).
Japanese Patent Laid-Open No. 10-337016

  Certainly, in the case of the high-voltage power supply device proposed in Patent Document 1, the zero-cross detection signal of the driving current of the piezoelectric transformer detected from the driving current flowing from the input side of the piezoelectric transformer toward the ground is used to drive the driving voltage. Since the phase of the drive current is synchronized with the piezoelectric transformer, the piezoelectric transformer can be driven at the natural resonance frequency of the piezoelectric transformer.

  However, since the high-voltage power supply device proposed in Patent Document 1 detects the amplitude of the drive current flowing on the input side (primary side) of the piezoelectric transformer with a comparator, when the drive voltage of the piezoelectric transformer rises, the piezoelectric transformer Since the drive current input to the output increases and the pulse width of the current detection signal widens, the drive signal of the piezoelectric transformer is set lower than the optimum natural resonance frequency, so the accuracy of the drive control of the piezoelectric transformer There was a problem.

  In view of the above problems, an object of the present invention is to provide a high-voltage power supply device that can output a stable voltage by accurately driving and controlling a piezoelectric transformer.

  In order to achieve the above object, a high voltage power supply device according to the present invention includes a switching element to which a power supply is connected and a driving signal having a first state and a second state logical state controlled by a control unit is input; Detecting means for detecting a sine wave load current passed through the load by the switching element, and the detecting means includes a half-wave rectifier for half-wave rectifying the load current, and the half-wave rectifier. Voltage conversion means for converting the load current subjected to half-wave rectification into a voltage signal, and comparison means for generating a detection signal having a logic state of a first state and a second state from the voltage signal and inputting the detection signal to the control means The control means includes a transmission circuit unit that generates a clock signal, a division ratio correction amount for correcting a phase difference between the drive signal and the load current, and a predetermined predetermined amount. Based on the ratio, before A frequency dividing circuit unit that generates the drive signal from a clock signal and inputs the drive signal to the switching element, and detects a transition of the detection signal to the first state and then detects a transition of the detection signal to the first state A waveform generation circuit unit for generating a signal waveform until and a frequency division ratio correction amount comprising a difference between the count number of the drive signal in the first state for a half hour and the count number of the signal waveform And a phase comparison circuit unit that inputs to the frequency divider circuit unit.

  With such a configuration, the drive signal of the switching element and the load current are controlled so as to always maintain a constant phase difference, so that a stable output voltage can be input to the load.

  A high-voltage power supply apparatus according to the present invention includes a switching element that is connected to a power source and an inductance and that drives a piezoelectric transformer by input of a drive signal having a first state and a second state controlled by a control unit, and the piezoelectric element Detecting means for detecting a sine wave load current output from the transformer, the detecting means is a half wave rectifier for half wave rectifying the load current, and half wave rectified by the half wave rectifier. Voltage conversion means for converting the load current into a voltage signal; and comparison means for generating a detection signal having a logic state of a first state and a second state from the voltage signal and inputting the detection signal to the control means. The control means is based on a transmission circuit unit that generates a clock signal, a division ratio correction amount for correcting a phase difference between the drive signal and the load current, and a predetermined division ratio set in advance. A frequency dividing circuit unit that generates the drive signal from the clock signal and inputs it to the switching element, and detects a transition of the drive signal to the first state and then detects a transition of the detection signal to the first state A waveform generation circuit unit for generating a signal waveform until the signal is obtained, and the division ratio correction amount comprising the difference between the count number of the drive signal in the first state for half an hour and the count number of the signal waveform is obtained. And a phase comparison circuit unit that inputs to the frequency divider circuit unit.

  By adopting such a configuration, even if the natural resonance frequency of the piezoelectric transformer fluctuates due to fluctuations in the load current, the drive signal of the switching element and the load current output from the piezoelectric transformer always maintain a constant phase difference. It is possible to control the piezoelectric transformer efficiently and accurately. Therefore, a stable output voltage can be input to the load.

  In addition, the frequency of the drive signal generated by the frequency dividing circuit in the high-voltage power supply device configured as described above is a natural resonance frequency that resonates with the piezoelectric transformer or a frequency in the vicinity of the natural resonance frequency.

  With such a configuration, it is possible to output a voltage that is efficiently boosted from the piezoelectric transformer.

  The high-voltage power supply device having the above configuration is configured to be used in an image forming apparatus.

  With such a configuration, a good toner image can be stably formed on the paper.

  As described above, the high-voltage power supply device according to the present invention enables efficient and accurate drive control of the piezoelectric transformer and allows a stable output voltage to be input to the load.

  Embodiments of a high-voltage power supply device according to the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing an example of the configuration of the high-voltage power supply device according to this embodiment.

  As shown in FIG. 1, the high-voltage power supply device 1 of the present embodiment, which will be described in detail later, is connected to a piezoelectric transformer 6 made of a material such as lead zirconate titanate, a power source and an inductance, and a control circuit unit 2 detects a load current output from the output side (secondary side) of the piezoelectric transformer 6 and the drive circuit unit 3 that drives the piezoelectric transformer 6 by the switching element to which the drive signal controlled by 2 is input. A detection circuit unit 4 that generates a new detection signal from the control circuit unit 2 and inputs the detection signal to a control circuit unit 2 described later, an output stabilization circuit unit 5 for stabilizing the output voltage of the piezoelectric transformer 6, a drive signal, and a clock signal Further, a division ratio correction amount for correcting the phase difference between the drive signal and the load current is generated from the detection signal input from the detection circuit unit 4, and the division ratio correction amount and the natural resonance frequency of the piezoelectric transformer are generated. Generate driving signal for switching element Q1 so that the phase difference between the driving signal of switching element Q1 and the load current is always kept constant based on a frequency division ratio set in advance to generate a nearby frequency. And a control circuit unit 2 for performing the above-described operation. The frequency dividing ratio may be for generating the natural resonance frequency of the piezoelectric transformer 6.

  The drive circuit unit 3 includes a power supply 3a that outputs a voltage Vcc, a buffer amplifier U1, a switching element Q1 including an N-type FET [Field Effect Transistor], an inductance L1, capacitors C1 and C5, resistors R10 and R11. And an N-type transistor Q2.

  The output voltage stabilization circuit unit 5 includes an operational amplification comparator U3, resistors R1, R2, R12, and R13, capacitors C2 to C4, and a diode D2 that is a rectifier.

  The detection circuit unit 4 includes power supplies 4a and 4b that output a voltage Vcc, a comparator U2 (corresponding to comparison means), resistors R3 to R9, and diodes D1 and D3 that are rectifiers.

  Next, connection of the circuit of the high-voltage power supply device 1 having the above configuration will be described below. As shown in FIG. 1, in the high-voltage power supply device 1 of the present embodiment, the reference voltage D / A is input from the output terminal 21 of the control circuit unit 2 to the (+) input terminal of the operational amplification comparator U3. The (−) input terminal of the operational amplification comparator U3 is connected to one end of the resistor R13 and one end of the capacitor C3, and the other end of the resistor R13 is connected to one end of the capacitor C4. The other end of the capacitor C4 is connected to the output terminal of the operational amplification comparator U3 and one end of the resistor R12. The other end of the resistor R12 is connected to one end of the resistor R11 and the base of the transistor Q2. The other end of the resistor R11 is connected to the collector of the transistor Q2 and the power source 3a, and the voltage Vcc is supplied from the power source 3a to the other end of the resistor R11 and the collector of the transistor Q2. The emitter of the transistor Q2 is connected to the other end of the capacitor C5 whose one end is grounded and one end of the inductance L1.

  Furthermore, the other end of the inductance L1 is connected to the drain of the switching element Q1, the other end of the capacitor C1 whose one end is grounded, and the primary side terminal 6a which is the input side of the piezoelectric transformer 6. The primary side terminal 6b of the piezoelectric transformer 6 is grounded.

  The gate of the switching element Q1 is connected to the output of the buffer amplifier U1, and a rectangular wave drive signal DRi having a duty ratio of 50% is input to the buffer amplifier U1 from the output terminal 22 of the control circuit unit 2. The source of the switching element Q1 is connected to one end of the resistor R10, and the other end of the resistor R10 is grounded.

  Further, the output terminal 6c on the secondary side of the piezoelectric transformer 6 is connected to the cathode of the diode D1 and the anode of the diode D2. The cathode of the diode D2 is connected to the other end of the capacitor C2 whose one end is grounded, one end of the resistor R1, and the grounded load 7. The other end of the resistor R1 is connected to the other end of the resistor R2 having one end grounded and the other end of the capacitor C3 having one end grounded.

  The anode of the diode D1 is connected to the anode of the diode D3 whose cathode is grounded, the other end of the resistor R3 whose one end is grounded, and one end of the resistor R4. The other end of the resistor R4 is connected to one end of the resistor R7 and the (−) input terminal of the comparator U2. A voltage Vcc is supplied from the power source 4a to the other end of the resistor R7 and one end of the resistor R5, and the other end of the resistor R7 is connected to one end of the resistor R5. The other end of the resistor R5 is connected to the resistor R6 having one end grounded, the (+) input terminal of the comparator U2, and one end of the resistor R8. As a result, the resistor R3 is pulled up by the power source 4a and the resistors R4 and R7.

  Further, the output terminal of the comparator U2 is connected to the other end of the resistor R8, the other end of the resistor R9 to which the voltage Vcc is supplied from the power source 4b, and the input terminal 23 of the control circuit unit 2. Note that the output of the comparator U2 is stabilized by the power supply 4b and the resistor R9.

  The frequency of the drive signal DRi described above is initially set to a frequency in the vicinity of the natural resonance frequency of the piezoelectric transformer 6 that is not affected by the load current, as will be described later. Further, as described above, the drive signal DRi is a rectangular wave with a duty ratio of 50%. The frequency of the drive signal DRi may be initially set to the natural resonance frequency of the piezoelectric transformer 6 that is not affected by the load current.

  Next, the configuration of the main part of the control circuit unit 2 will be described below. FIG. 2 is a block diagram illustrating an example of the control circuit unit.

  As shown in FIG. 2, the control circuit unit 2 is input from a reference voltage circuit unit 24 that generates a reference voltage D / A, an oscillation circuit unit 25 that generates a clock signal CLK, and a phase comparison circuit unit 27 described later. Based on a frequency division ratio correction amount CV for correcting the phase difference between the drive signal DRi and the load current, and a predetermined frequency division ratio set in advance to generate a frequency in the vicinity of the natural resonance frequency of the piezoelectric transformer 6. The frequency dividing circuit unit 26 that divides and generates the drive signal DRi from the clock signal CLK and the detection signal RiS input to the reset input terminal R from the rising edge of the drive signal DRi input to the set input terminal S. Until the rising edge, or the falling edge of the detection signal RiS input to the reset input terminal R from the falling edge of the drive signal DRi input to the set input terminal S A flip-flop 28 (abbreviated as F / F 28, corresponding to the waveform generation circuit unit) that outputs a signal waveform from the output terminal Q as a gate signal RiG from the output terminal Q, a clock signal, a drive signal DRi, and a gate signal RiG Counts the number of one cycle of the clock signal CLK when the drive signal DRi is at the high level and the gate signal RiG is at the high level, and divides the difference between the counts. And a phase comparison circuit unit 27 that is input to the frequency division circuit unit 26 as the ratio correction amount CV.

  The phase comparison circuit unit 27 uses the clock signal CLK input from the oscillation circuit unit 25, and the DRi signal input from the frequency division circuit unit 26 has a high level of half the time of one cycle of the clock signal CLK. The gate signal RiG input from the flip-flop 28 is counted using the counter 27a that counts the minutes and inputs the count number to the comparison unit 27c described later and the clock signal CLK input from the oscillation circuit unit 25. A counter 27b that counts the number of one period of the clock signal CLK at the time of the high level of the clock signal CLK, and inputs the count number to the comparator 27c described later, and the counts input from the counter 27a and the counter 27b, respectively And a comparator 27c that inputs the difference in the number to the frequency dividing circuit 26 as the frequency division ratio correction amount CV.

  Next, the operation of the high-voltage power supply device 1 of the present embodiment configured as described above will be described below with reference to the drawings. FIG. 3 is a diagram illustrating operation waveforms at different timings of the high-voltage power supply device 1 of the present embodiment. 3A is a clock signal CLK generated by the oscillation circuit unit 25, FIG. 3B is a drive signal DRi of the switching element Q1 output from the frequency divider unit 26 of the control circuit unit 2, and FIG. ) Is a voltage signal Ri input to the (−) input terminal of the comparator U2, FIG. 3D is a detection signal RiS output from the comparator U2, and FIG. 3E is a gate signal RiG output from the flip-flop 28. It is.

  Also, the three operation waveforms shown in FIG. 3B to FIG. 3E respectively show the timing A from the left side of the page, and the phase of the load current output from the drive signal DRi and the piezoelectric transformer 6 coincides with the timing A. The operation waveform when timing B is the natural resonance frequency of the piezoelectric transformer 6 increases, and the phase of the load current output from the piezoelectric transformer 6 is advanced from the drive signal DRi, timing C is the piezoelectric transformer 6. Is the operation waveform when the phase of the load current output from the piezoelectric transformer 6 is delayed from the drive signal DRi.

  FIG. 4 is a diagram illustrating operation waveforms for explaining the frequency division ratio correction amount and generation of a new drive signal DRi at different timings. 4A shows the detection signal RiS input to the counter 27b, FIG. 4B shows the drive signal DRi input to the counter 27a, and FIG. 4C shows the new drive generated by the frequency divider 26. This is the signal DRi (NeW).

  Also, the three operation waveforms shown in FIGS. 4A to 4C are the load currents output from the drive signal DRi and the piezoelectric transformer 6 at the timing A from the left side of FIG. , The operation waveform when the phase of the load current outputted from the piezoelectric transformer 6 is advanced from the drive signal DRi, Timing C is an operation waveform when the phase of the load current output from the piezoelectric transformer 6 is delayed from the drive signal DRi because the natural resonance frequency of the piezoelectric transformer 6 is low.

  As shown in FIGS. 1 and 2, first, the oscillation circuit unit 25 generates the clock signal CLK shown in FIG. 3A having a frequency sufficiently higher than the natural resonance frequency of the piezoelectric transformer 6, and the clock signal CLK is divided. The signal is input to the peripheral circuit unit 26. In the frequency dividing circuit unit 26, since the frequency division ratio correction amount CV input from the phase comparison circuit unit 27 is zero at first, a predetermined frequency dividing ratio set in advance to generate a frequency in the vicinity of the natural resonance frequency is set. Based on, a drive signal DRi shown in FIG. 3B is generated as a rectangular wave (duty ratio 50%) which is a frequency near the natural resonance frequency of the piezoelectric transformer 6. The drive signal DRi is output from the frequency dividing circuit unit 26 via the terminal 22, passes through the buffer amplifier U1, and is input to the gate of the switching element Q1.

  Further, the reference voltage D / A output from the reference voltage circuit unit 24 is input to the arithmetic circuit comparator U3. The transistor Q2 is turned ON by the output voltage from the operational amplification comparator U3, and the voltage of the power source 3a is applied to the inductance L1, capacitors C5 and C2, the terminal 6a of the piezoelectric transformer 6, the switching element, and the drain of Q1. Further, when the gate of the switching element Q1 is driven by the drive signal DRi, the drain and source of the switching element Q1 are repeatedly turned ON / OFF, and the primary side (input side) terminals 6a and 6b of the piezoelectric transformer 6 are connected to each other. A rectangular wave accompanying resonance with the inductance L1 and the capacitors C5 and C2 is applied, and the piezoelectric transformer 6 mechanically vibrates. Then, an induced voltage boosted by the piezoelectric effect caused by the vibration of the piezoelectric transformer 6 is output as an output voltage to the output terminal 6 c of the piezoelectric transformer 6.

  The output voltage output from the output terminal 6c of the piezoelectric transformer 6 is rectified by the diodes D1 and D2, smoothed by the capacitor C2, and converted into a DC voltage. A DC voltage smoothed by the capacitor C <b> 2 is applied to the load 7.

  The resistors R1 and R2 are resistors for dividing a DC voltage smoothed by the capacitor C2 to obtain a monitor voltage necessary for feedback control for stabilizing the output voltage of the piezoelectric transformer 6. The capacitor C3 acts as a filter for stabilizing the monitor voltage.

  The monitor voltage obtained from the resistors R1 and R2 is input to the (−) input terminal of the operational amplification comparator U3, and from the output terminal 21 of the control circuit unit 21 to the (+) input terminal of the operational amplification comparator U3. It is compared with the inputted reference voltage D / A.

  The base current of the transistor Q2 is controlled by the output voltage output from the operational amplification comparator U3, and the output voltage of the piezoelectric transformer 6 is stabilized. The resistors R12 and R13 and the capacitor C4 function as a filter.

  This feedback control can cope with stabilization of the output voltage of the piezoelectric transformer 6 against load fluctuations, input fluctuations, etc., but the natural resonance frequency of the piezoelectric transformer 6 varies greatly depending on the load current. It is impossible to cope with stabilization of the output voltage of the piezoelectric transformer 6 with respect to the fluctuation of the current.

  Therefore, the high-voltage power supply device 1 of the present embodiment is configured to perform the following operation control in order to stabilize the output voltage of the piezoelectric transformer 6 in response to fluctuations in the natural resonance frequency of the piezoelectric transformer 6.

  The sine wave load current output from the output terminal 6c of the piezoelectric transformer 6 is rectified to a half wave load current by the diode D1. Then, the half-wave load current flowing through the resistor R3 connected in series with the diode D1 is converted into the voltage signal Ri as follows. When a half-wave load current flows through the resistor R3, a negative voltage signal is generated on the diode D1 side of the resistor R3. The negative voltage signal is pulled up by the voltage Vcc of the power source 4a and the resistors R4 and R7, It is shifted into a positive voltage range and converted to a voltage signal Ri. And the voltage signal Ri shown in FIG.3 (c) converted from the half-wave load current is input into the (-) input terminal of comparator U2. The resistors R3, R4, R7 and the power source 4a correspond to voltage conversion means for converting the half-wave rectified load current into the voltage signal Ri.

  When the natural resonance frequency of the piezoelectric transformer 6 varies depending on the load current, as shown in timings B and C in FIGS. 3B and 3C, the phase difference between the drive signal DRi and the voltage signal Ri It can be seen that the drive signal DRi and the load current output from the piezoelectric transformer 6 are out of phase.

  Further, a reference voltage Vref obtained by dividing the voltage Vcc applied from the power supply 4a by the resistors R5 and R6 is input to the (+) input terminal of the comparator U2. In the comparator U2, the reference voltage Vref shown in FIG. 3C is compared with the voltage signal Ri, and the detection signal RiS shown in FIG. 3D is output from the output terminal of the comparator U2. The detection signal RiS is input to the reset input terminal R of the flip-flop 28 illustrated in FIG. 2 via the input terminal 23 of the control circuit unit 2.

  As shown in FIG. 2, the drive signal DRi is input from the frequency divider 26 to the set input terminal S of the flip-flop 28. As shown in FIGS. 3B, 3D, and 3E, in the flip-flop 28, the signal level of the drive signal DRi at the rising edge 31 in the drive signal DRi input to the set input terminal S. However, the held and generated gate signal RiG until the rising edge 32 of the detection signal RiS input to the reset input terminal R is detected is output from the output terminal Q. The gate signal RiG is input to the counter 27b of the phase comparison circuit unit 27.

  In the flip-flop 28, instead of the rising edge 31 of the drive signal DRi and the rising edge 32 of the detection signal RiS, the respective falling edges may be used.

  In the counter 27b of the phase comparison circuit unit 27, the number of one period of the clock signal CLK when the high level of the gate signal RiG input from the output terminal Q of the flip-flop 28 is counted. The count number of the gate signal RiG at the high level is input from the counter 27b to the comparison unit 27c.

  Further, in the counter 27a of the phase comparison circuit unit 27, the clock signal CLK is used, and the half time period between the high levels of the drive signal DRi input from the frequency dividing circuit unit 26 is equal to one cycle of the clock signal CLK. It is counted for the period. Then, the count number for a half hour of the high level of the drive signal DRi is input from the counter 27a to the comparison unit 27c.

  Subsequently, in the comparison unit 27c, the count number at the high level of the gate signal RiG input from the counter 27b is compared with the count number corresponding to the half level of the high level of the drive signal DRi.

  As shown in FIG. 4A and FIG. 4B, the comparison unit 27c, in the case of the timing A when the phase of the drive current DRi and the load current output from the piezoelectric transformer 6 match, Since the count number at the high level of the gate signal RiG matches the count number of the high level (time T) of the drive signal DRi for half an hour (time 1 / 2T), the frequency division circuit unit 26 corrects the division ratio. It is entered that the quantity CV is zero. Then, the frequency dividing circuit unit 26 divides the clock signal CLK based on a predetermined frequency dividing ratio set in advance in order to generate a frequency dividing ratio correction amount CV of zero value and a frequency near the natural resonance frequency. Thus, a new drive signal DRi (New) shown at timing A in FIG. 4C is generated. Then, a new drive signal DRi (New) shown at timing A in FIG. 4C with a duty ratio of 50% is input from the frequency divider 26 to the switching element Q1 via the output terminal 22 and the buffer amplifier U1. The

  Further, the comparison unit 27c increases the natural resonance frequency of the piezoelectric transformer 6 and the timing of the gate signal RiG in the case of the timing B when the phase of the load current output from the piezoelectric transformer 6 is advanced from the drive signal DRi. Since the count number at the high level is larger than the count number of half the time (time 1 / 2T) of the high level (time T) of the drive signal DRi, the count circuit portion 26 has time. A frequency division ratio correction amount CV of the count number corresponding to Td1 is input. Then, as shown at timing B in FIG. 4C, the frequency dividing circuit unit 26 is preset to generate a frequency division ratio correction amount CV for the count number for the time Td1 and a frequency in the vicinity of the natural resonance frequency. The clock signal CLK is divided based on the predetermined division ratio, and a new drive signal DRi (New) with a duty ratio of 50% is obtained by adding the time Td1 to the pulse width of the drive signal DRi at the high level. Is generated.

  At this time, the frequency of the new drive signal DRi (New) is lower than that of the previous drive signal DRi (FIG. 3B). Then, a new drive signal DRi (New) having a duty ratio of 50% shown at timing B in FIG. 4C is input from the frequency divider 26 to the switching element Q1 via the output terminal 22 and the buffer amplifier U1. The

  In addition, the comparison unit 27c reduces the intrinsic resonance frequency of the piezoelectric transformer 6 and the timing of the gate signal RiG in the case of the timing C when the phase of the load current output from the piezoelectric transformer 6 is delayed from the drive signal DRi. Since the count number at the high level is smaller than the count number for half an hour (time 1 / 2T) of the high level (time T) of the drive signal DRi, the time is given to the frequency divider 26. A frequency division ratio correction amount CV of the count number corresponding to Td2 is input. Then, as shown at timing C in FIG. 4C, the frequency dividing circuit section 26 is set in advance to generate the frequency division ratio correction amount CV of the count number for the time Td2 and the frequency in the vicinity of the natural resonance frequency. A new drive signal DRi (New) having a duty ratio of 50% obtained by dividing the clock signal CLK based on the predetermined division ratio and subtracting the time Td2 from the pulse width of the drive signal DRi at the high level. Is generated.

  At this time, the frequency of the new drive signal DRi (New) is higher than that of the previous drive signal DRi (FIG. 3B). Then, a new drive signal DRi (New) having a duty ratio of 50% shown at timing C in FIG. 4C is input from the frequency divider 26 to the switching element Q1 via the output terminal 22 and the buffer amplifier U1. The

  Therefore, if the pulse width of the drive signal DRi is varied by the frequency dividing circuit unit 26 based on the frequency division ratio correction amount CV and the predetermined frequency division ratio set in advance as described above, the cycle of the drive signal DRi is increased. As a result, the frequency also changes, and it becomes possible to input the drive signal DRi corresponding to the fluctuation due to the load current of the natural resonance frequency of the piezoelectric transistor 6 to the switching element Q1.

  As described above, the high-voltage power supply device 1 of the present embodiment includes the switching element Q1 that is connected to the power supply 3a and the inductance L1 and drives the piezoelectric transformer 6 by the input of the drive signal DRi controlled by the control circuit unit 2. , And a detection circuit unit 4 for detecting a sine wave load current output from the piezoelectric transformer 6. The detection circuit unit 4 is half-wave rectified with a diode D 1 for half-wave rectification of the load current. A voltage conversion unit that converts the load current into the voltage signal Ri; a comparator U2 that compares the voltage signal Ri with the reference voltage Vref to generate a detection signal RiS and inputs the detection signal RiS; The circuit unit 2 includes a transmission circuit unit 25 that generates the clock signal CLK, a frequency division ratio correction amount CV for correcting the phase difference between the drive signal DRi and the load current, and a preset value. Based on the predetermined frequency dividing ratio, the frequency dividing circuit unit 26 that generates the driving signal DRi from the clock signal CLK and inputs the driving signal DRi to the switching element Q1, the natural resonance frequency of the piezoelectric transformer 6 from the detection signal RiS and the driving signal DRi. From the flip-flop 28 generated by the gate signal RiG including information on the phase difference between the load current and the drive signal DRi accompanying the fluctuation of the drive signal DRi, and the difference between the count number for half an hour of the drive signal DRi and the count number of the gate signal RiG A phase comparison circuit unit 27 that obtains a frequency division ratio correction amount and inputs it to the frequency division circuit unit 26. However, even if the natural resonance frequency of the piezoelectric transformer 6 fluctuates due to fluctuations in the load current. A new drive signal DRi (New) is generated in the frequency divider 26 so that the drive signal DRi and the load current always maintain a constant phase difference, and the switching element Q1. Since the input, it is possible to drive the efficiency and accuracy of better piezoelectric transformer 6. Therefore, the high-voltage power supply device 1 of the present embodiment can input a stable output voltage to the load.

  In addition, the high-voltage power supply device 1 of the present embodiment has a configuration in which the gate signal RiG is generated by performing the set and reset by using the edges of the drive signal DRi and the detection signal RiS by the flip-flop 28. An error factor due to the amplitude fluctuation of the detection signal RiS accompanying the increase / decrease can be eliminated, and the gate signal RiG including the phase difference information with high accuracy can be generated.

  Note that the control circuit unit 2 of the high-voltage power supply device 1 of the present embodiment may be integrated. Further, the operation control may be controlled on the control circuit unit 2 by software. As a result, even if a plurality of piezoelectric transformers are mounted, it is possible to provide a high-voltage power source that is energy-saving, low-cost, and highly reliable.

  FIG. 5 is a schematic longitudinal sectional view of an image forming apparatus provided with the high-voltage power supply device 1 according to the present invention. As shown in FIG. 5, the high-voltage power supply device 1 according to the present embodiment is used as a high-voltage power supply device that supplies power to a transfer roller 55g that transfers a toner image on the surface of a photosensitive drum 55a to a sheet in the image forming apparatus 50. Also good. As a result, a good toner image can be stably formed on the paper. The configuration of the image forming apparatus shown in FIG. 5 is as follows.

  As shown in FIG. 5, the image forming apparatus 50 includes a document transport unit 51 that automatically transports a document, a document capture unit 52 that captures a document transported from the document transport unit 51 and generates image data, and an operation unit. An operation display unit 53 including a numeric keypad and a touch panel and a display unit (liquid crystal display, etc.), an image forming unit 55 for outputting an image to a sheet based on image data, and an image forming unit 55 are formed on the sheet. A fixing unit 56 that fixes the toner image on the paper, a paper feeding unit 54 that feeds the image to the image forming unit 55, and a paper discharge unit that is a paper discharge destination of the paper on which the fixing process of the toner image is completed by the fixing unit 56 57. Although not shown in the figure, the copying machine 1 is a ROM [which stores a central processing unit (hereinafter referred to as a CPU [Central Processing Unit]) that controls the operation of the entire apparatus and various control programs. Naturally, it has a memory unit such as a “Read Only Memory” or a RAM [Random Access Memory] used as a work area. Note that the solid line arrows in FIG. 5 indicate the sheet conveyance path.

  In addition, the image forming unit 55 includes a latent image carrier photosensitive drum 55a on which a toner image is formed on the drum surface based on image data, and a charger 55d that uniformly charges the surface of the photosensitive drum 55a to a predetermined potential. The exposure unit 55c that irradiates a laser beam based on the image data to form an electrostatic latent image on the surface of the photosensitive drum 55a, and the toner image from the electrostatic latent image on the surface of the photosensitive drum 55a on the surface of the photosensitive drum 55a. The developing device 55b to be formed, the transfer roller 55g for electrostatically transferring the toner image formed on the surface of the photosensitive drum 55a to the conveyed paper, and the toner remaining on the surface of the photosensitive drum 55a are removed and discarded. The toner image on the sheet is electrostatically transferred to the cleaning unit 55f that conveys and collects the toner, the neutralizer 5e that neutralizes the surface of the photosensitive drum 55a, and the transfer roller 55g. Comprising a, a high-voltage power supply apparatus 1 for supplying power to transfer.

  The high-voltage power supply device 1 provided in the image forming apparatus 50 shown in FIG. 5 is configured to supply power to the transfer roller 55g. However, at least one of the charger 55d, the developer 55b, the charge remover 55e, and the like. In addition, by supplying power from the high-voltage power supply device 1, it is possible to stably form a good toner image on the paper.

  The present invention can be widely applied to all high-voltage power supply devices used in image forming apparatuses such as printers and copying machines, and is particularly useful for preventing fluctuations in output voltage due to fluctuations in the natural resonance frequency of a piezoelectric transformer.

These are circuit diagrams which show an example of a structure of the high voltage power supply device which concerns on this embodiment. These are block diagrams which show an example of a control circuit part. These are figures which show the operation | movement waveform in the different timing of the high voltage power supply device 1 of this embodiment. These are the figure which shows the operation waveform for demonstrating the division ratio correction amount and the production | generation of the new drive signal DRi in a different timing. These are typical longitudinal cross-sectional views of the image forming apparatus provided with the high-voltage power supply device 1 according to the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 High voltage power supply device 2 Control circuit part 6c, 21, 22 Output terminal 23 Input terminal 24 Reference voltage circuit part 25 Oscillation circuit part 26 Dividing circuit part 27 Phase comparison circuit part 27a, 27b Counter 27c Comparison part 28 Flip-flop 3 Drive circuit Section 4 Detection circuit section 3a, 4a, 4b Power supply 5 Output voltage stabilization circuit section 6 Piezoelectric transformer 6a, 6b Terminal 7 Load 50 Image forming apparatus 51 Document transport section 52 Document fetch section 53 Operation display section 54 Paper feed section 55 Image Forming unit 55a Photosensitive drum 55b Developer 55c Exposure unit 55d Charger 55e Charger 55f Cleaning unit 55g Transfer roller 56 Fixing unit 57 Paper discharge unit C1 to C5 Capacitor D1 to D3 Diode D / A Reference voltage DRi Drive signal L1 Inductance Q1 Switching Element Q2 Transistor R ~R13 resistance Ri voltage signal RiS detection signal RiG gate signals U1 buffer amplifier U2 comparator U3 operational amplifier comparator

Claims (4)

A switching element to which a power supply is connected and a driving signal having a first state and a second state logical state controlled by the control means is input, and a sine wave load current passed through the load by the switching element is detected. A high-voltage power supply device comprising detection means,
The detection means includes a half-wave rectifier for half-wave rectifying the load current, a voltage conversion means for converting the load current half-wave rectified by the half-wave rectifier into a voltage signal, and a first state from the voltage signal. Comparing means for generating a detection signal having a logic state of a second state and inputting the detection signal to the control means;
The control means is based on an oscillation circuit unit that generates a clock signal, a division ratio correction amount for correcting a phase difference between the drive signal and the load current, and a predetermined division ratio that is set in advance. A frequency dividing circuit unit that generates the drive signal from the clock signal and inputs it to the switching element, and detects a transition of the drive signal to the first state and then detects a transition of the detection signal to the first state A waveform generation circuit unit for generating a signal waveform until the signal is obtained, and the division ratio correction amount comprising a difference between the count number of the drive signal in the first state for a half hour and the count number of the signal waveform is obtained. And a phase comparison circuit unit for inputting to the frequency divider circuit unit. A switching element for connecting a power source and an inductance and driving a piezoelectric transformer by input of a driving signal having a first state and a second state logically controlled by a control means, and a load of a sine wave output from the piezoelectric transformer A high-voltage power supply device comprising a detecting means for detecting current,
The detection means includes a half-wave rectifier for half-wave rectifying the load current, a voltage conversion means for converting the load current half-wave rectified by the half-wave rectifier into a voltage signal, and a first state from the voltage signal. Comparing means for generating a detection signal having a logic state of the second state and inputting the detection signal to the control means;
The control means is based on an oscillation circuit unit that generates a clock signal, a division ratio correction amount for correcting a phase difference between the drive signal and the load current, and a predetermined division ratio that is set in advance. A frequency dividing circuit unit that generates the drive signal from the clock signal and inputs it to the switching element, and detects a transition of the drive signal to the first state and then detects a transition of the detection signal to the first state A waveform generation circuit unit for generating a signal waveform until the signal is obtained, and the division ratio correction amount comprising a difference between the count number of the drive signal in the first state for a half hour and the count number of the signal waveform is obtained. And a phase comparison circuit unit for inputting to the frequency divider circuit unit.   3. The frequency of the drive signal generated by the frequency divider circuit unit is a natural resonance frequency that resonates with the piezoelectric transformer or a frequency in the vicinity of the natural resonance frequency. High-voltage power supply.   The high-voltage power supply device according to claim 1, wherein the high-voltage power supply device is used in an image forming apparatus.

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