JP2014007903A - High voltage power unit and image forming apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that, when performing feedback control on high voltage output while using a piezoelectric transformer, in the case where consolidation is performed under digital control, noise is easily mixed into a feedback signal line and when controlling a plurality of systems, stable control is difficult such as interfering the systems to each other.SOLUTION: A high voltage power unit comprises: a pulse output generator 403 which generates a driving pulse; a computing element 402 which outputs a frequency dividing value by correcting a preset frequency dividing value with a correction value; a piezoelectric transformer 211 which outputs a high voltage corresponding to a frequency and a level of a switching signal; a DC-DC converter 209 which outputs a variable voltage; a piezoelectric transformer drive circuit 210 which outputs to the piezoelectric transformer 211 the switching signal having a frequency of the driving pulse and a level of the variable voltage; an output voltage conversion circuit 213 which converts a high output voltage obtained by rectifying a high voltage into a boosted feedback voltage signal; and a feedback control circuit 214 which controls the variable voltage of the DC-DC converter 209 on the basis of a setting signal and the feedback voltage signal.

Description

  The present invention relates to a high-voltage power supply apparatus that controls output using a piezoelectric transformer and an image forming apparatus using the same.

  Conventionally, as this type of device, for example, there is a device that generates a piezoelectric transformer drive frequency by a digital circuit and corrects the piezoelectric transformer variation to perform frequency control (see, for example, Patent Document 1).

Japanese Patent Laying-Open No. 2011-50187 (paragraphs 0076 to 0080, FIG. 1)

  However, when integration is performed by digital control in a conventional apparatus, when there are a plurality of output systems, it is desirable to integrate the plurality of systems into one IC or LSI instead of every high-voltage output. In that case, control for a plurality of high-voltage outputs has to be concentrated in one place, and there is a problem that pattern design and wiring are restricted. In particular, when an AD converter is arranged in an integrated circuit and the output is feedback controlled according to the detected value of the AD converter, the AD converter input signal line must be wired so as not to contain noise, and a shield is provided. It was easy to receive restrictions such as short wiring.

  Further, in the case of frequency variable control, the drive frequency range is limited by the spurious frequency and the like, and the minimum output voltage becomes 100V to 200V or more, so there is a problem that a low voltage cannot be output. Furthermore, when driving a plurality of piezoelectric transformers in close proximity, if the driving frequency of each piezoelectric transformer is different from the adjacent frequencies, low-frequency ripples are generated due to interference with the secondary AC output. There was a problem that.

The high-voltage power supply device according to the present invention is
A frequency dividing means for generating a drive pulse obtained by dividing the operation clock signal based on an input frequency dividing value, a frequency dividing value holding means for holding a set frequency dividing value, and a correction value for correcting the set frequency dividing value Correction value holding means for holding the frequency division value setting means for outputting the frequency division value obtained by correcting the set frequency division value with the correction value to the frequency division means, and the frequency of the switching signal input to the primary side And a piezoelectric transformer that outputs a high voltage corresponding to the level from the secondary side, a DC-DC converter that outputs a variable voltage, the frequency based on the drive pulse, and the switching signal having the level based on the variable voltage. Piezoelectric transformer driving means for outputting to the piezoelectric transformer, rectifying means for rectifying the high voltage to form a high output voltage, output conversion means for converting the high output voltage into a feedback voltage signal obtained by stepping down the high output voltage, Feedback control means for controlling the variable voltage of the DC-DC converter so that the high-voltage output voltage approaches the target value based on the setting signal for determining the target value of the high output voltage and the feedback power signal. It is characterized by having and.

  According to the present invention, the piezoelectric transformer is driven by the driving pulse whose frequency is fixedly set, and the high output voltage is analog-controlled. For this reason, it is possible to wire the control loop short, and it is possible to easily prevent circuit oscillation due to the long control loop. Further, since the high output voltage control is not performed by the drive frequency, the drive at the spurious frequency can be avoided.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a main part configuration diagram schematically showing a main part configuration of a first embodiment of an image forming apparatus including a high voltage power supply device according to the present invention. 3 is a block diagram illustrating a circuit configuration of a control system in the image forming apparatus according to Embodiment 1. FIG. FIG. 3 is a block diagram illustrating a transfer bias generation unit in the first embodiment. FIG. 3 is a circuit diagram illustrating a circuit configuration of a high voltage generation unit according to the first embodiment together with a printer engine control unit, an ASIC, and the like. In Embodiment 1, it is the block diagram which blocked the structure of ASIC according to the function. (A), (b) is a signal waveform diagram which shows the signal waveform in each part of a high voltage | pressure production | generation part. (A), (b) is a signal waveform diagram which shows the signal waveform in each part of a high voltage | pressure production | generation part. (A), (b) shows each rising waveform of the high output voltage which is the output of a DC-DC converter and the output of a rectifier circuit which changes with drive frequency and output voltage. (A), (b) shows each rising waveform of the high output voltage which is the output of a DC-DC converter and the output of a rectifier circuit which changes with drive frequency and output voltage. (A), (b) shows each rising waveform of the high output voltage which is the output of a DC-DC converter and the output of a rectifier circuit which changes with drive frequency and output voltage. (A), (b) shows each rising waveform of the high output voltage which is the output of a DC-DC converter and the output of a rectifier circuit which changes with drive frequency and output voltage. 3 is a graph showing drive frequency characteristics of a piezoelectric transformer 211. 4 is a flowchart illustrating a procedure performed by a printer engine control unit when a DAC setting value for applying a predetermined high output voltage to four system output loads is set in the DAC in the first embodiment. 4 is a flowchart illustrating a procedure performed by a printer engine control unit for setting a division ratio setting value in four division ratio setting value registers in the first embodiment. 4 is a flowchart illustrating a procedure performed by a printer engine control unit for setting a division ratio correction value in four division ratio correction value registers in the first embodiment. It is a flowchart for demonstrating the process which an error holding register performs. 5 is a flowchart illustrating a procedure for testing a paper phenol single-sided board by a function tester and determining a division ratio correction value set in an ASIC division ratio correction register in the first embodiment. In Embodiment 1, it is a figure which shows the data format which E2PROM records. In Embodiment 1, it is a figure which shows the output example of the division ratio setting value and division ratio correction value which are output. FIG. 3 is a block diagram of a function tester for determining a frequency division ratio correction value in the first embodiment. FIG. 5 is a block diagram showing a circuit configuration of a control system of an image forming apparatus according to a second embodiment of the present invention. FIG. 10 is a block diagram for explaining a charging bias generator in the second embodiment. FIG. 6 is a circuit diagram illustrating a circuit configuration of a high voltage generation unit according to a second embodiment together with a printer engine control unit. FIG. 23 is a block diagram in which the configuration of an engine control LSI in the printer engine control unit shown in FIG. 9 is a flowchart illustrating a procedure in which the printer engine control unit sets the division ratio setting value and the division ratio correction value in the division ratio setting value register and the division ratio correction value register in the LSI according to the second embodiment. is there. 10 is a flowchart illustrating a procedure for testing a paper phenol single-sided board by a function tester and determining a division ratio correction value set in a division ratio correction value register in the engine control LSI in the second embodiment. It is a block diagram of a function tester for determining a division ratio correction value. It is a block diagram which shows the modification of this Embodiment.

Embodiment 1 FIG.
FIG. 1 is a main part configuration diagram schematically showing a main part configuration of Embodiment 1 of an image forming apparatus provided with a high-voltage power supply device according to the present invention.

  The image forming apparatus 11 includes, for example, a configuration as an electrophotographic color printer, and includes image forming units 12K, 12Y, 12M, and 12C that form four independent image forming units (if there is no need to distinguish between them, image forming is simply performed). Are sometimes arranged in order from the upstream side along the conveyance direction (arrow A direction) of the recording paper 30 as a recording medium. The image forming unit 12K forms a black (K) image, the image forming unit 12Y forms a yellow (Y) image, the image forming unit 12M forms a magenta (M) image, and the image forming unit 12C A cyan (C) image is formed. In addition to the recording paper 30, OHP paper, envelopes, copy paper, special paper, etc. can be used as the recording medium.

  Each of the image forming units 12K, 12Y, 12M, and 12C includes a photosensitive drum 13K, 13Y, 13M, and 13C (sometimes simply referred to as the photosensitive drum 13 if there is no need to distinguish between them) and a corresponding photosensitive member. Charging rollers 14K, 14Y, 14M, and 14C for uniformly and uniformly charging the surfaces of the drums 13K, 13Y, 13M, and 13C (may be simply referred to as the charging roller 14 if there is no need to distinguish between them). Development that forms a toner image of each color that is a visible image by attaching a developer (for example, toner) (not shown) to the electrostatic latent images formed on the surfaces of the corresponding photosensitive drums 13K, 13Y, 13M, and 13C. Rollers 16K, 16Y, 16M, and 16C (which may be simply referred to as developing roller 16 if there is no particular need to distinguish) and corresponding developing rollers 16K and 16 , 16M, 16C toner supply roller was pressed against the 18K, 18Y, 18M, 18C (if it is not necessary to distinguish in some cases simply referred to as toner supply roller 18) and are arranged.

  Each of the toner supply rollers 18K, 18Y, 18M, and 18C is a corresponding toner cartridge 20K, 20Y, 20M, and 20C that is detachably attached to the main body of the image forming unit. In other words, the toner is supplied to the corresponding developing rollers 16K, 16Y, 16M, and 16C. Corresponding developing blades 19K, 19Y, 19M, and 19C (which may be simply referred to as the developing blade 19 if there is no need to distinguish between them) are pressed against the developing rollers 16K, 16Y, 16M, and 16C, respectively. The developing blade 19 thins the toner supplied from the toner supply roller 18 on the developing roller 16. Here, the toner cartridge 20 is detachably attached to the main body of the image forming unit 12, but may be integrally formed.

  In each of the image forming units 12K, 12Y, 12M, and 12C, above the photosensitive drums 13K, 13Y, 13M, and 13C, respectively, the corresponding LED heads 15K, 15Y, 15M, and 15C (if there is no need to distinguish them, simply The LED head 15 may be referred to as a photosensitive drum 13K, 13Y, 13M, 13C. Each LED head 15 is a device that exposes the photosensitive drum 13 in accordance with image data of a corresponding color to form an electrostatic latent image.

  A transfer unit 21 is disposed below each photosensitive drum 13 of the four image forming units 12. The transfer unit 21 is stretched by transfer rollers 17K, 17Y, 17M, and 17C (which may be simply referred to as transfer roller 17 if it is not necessary to distinguish between them), a transfer belt driving roller 21a, and a transfer belt driven roller 21b. In this state, a transfer belt 26 is provided so as to be able to travel in the direction of arrow A in FIG. Each transfer roller 17 is disposed in pressure contact with the corresponding photosensitive drum 13 via the transfer belt 26, and the paper is charged to a polarity opposite to that of the toner at the nip portion, and is formed on the corresponding photosensitive drum 13. The toner images of the respective colors are sequentially transferred onto the recording paper 30.

  A paper feed mechanism for supplying paper to the transfer belt 26 is disposed below the image forming apparatus 11. The paper feed mechanism includes a hopping roller 22, a registration roller pair 23, a paper storage cassette 24, and the like.

  Further, a fixing device 28 is provided on the discharge side of the recording paper 30 by the transfer belt 26. The fixing device 28 includes a heating roller and a backup roller, and is a device that fixes the toner transferred onto the recording paper 30 by pressurizing and heating. The fixing device 28 is disposed along the paper guide 31 on the discharge side. A discharge roller, a paper stacker 29, and the like (not shown) are provided.

  A printing operation in the image forming apparatus 11 configured as described above will be briefly described. First, the recording paper 30 in the paper storage cassette 24 is fed out by the hopping roller 22 and sent to the registration roller pair 23 to correct skewing, and then sent from the registration roller pair 23 to the transfer belt 26. As the belt 26 travels, it is sequentially conveyed to the image forming units 12K, 12Y, 12M, and 12C. A sheet detection sensor 25 is disposed following the pair of registration rollers 23, detects the passage of the recording sheet 30 passing through it in a contact or non-contact manner, and outputs a detection signal to a printer engine control unit 153 (FIG. 2) described later.

  On the other hand, in each image forming unit 12, the surface of the photosensitive drum 13 is charged by the charging roller 14 and then exposed by the corresponding LED head 15, and an electrostatic latent image is formed on the surface by this exposure. In the portion where the electrostatic latent image is formed, the toner thinned on the developing roller 16 is electrostatically attached to form a corresponding color toner image. The toner images formed on the respective photosensitive drums 13 are sequentially transferred onto the recording paper 30 by the corresponding transfer rollers 17 to form a color toner image on the recording paper. After the transfer, the toner remaining on each photosensitive drum 13 is removed by a cleaning device (not shown).

  The recording paper 30 on which the color toner image is formed is sent to the fixing device 28. In the fixing device 28, the color toner image is fixed on the recording paper 30, and a color image is formed. The recording paper 30 on which the color image is formed is conveyed along a paper guide 31 by a discharge roller (not shown) and discharged to the paper stacker unit 29. A color image is formed on the recording paper 30 through the process described above. The residual toner adhering to the transfer belt 26 is accommodated in the belt cleaner container 33 by the belt cleaning blade 32.

  FIG. 2 is a block diagram illustrating a circuit configuration of a control system in the image forming apparatus 11.

  The host interface unit 150 transmits / receives data to / from the command / image processing unit 151, and the command / image processing unit 151 outputs image data to the LED head interface unit 152. The LED head interface unit 152 is controlled by the printer engine control unit 153 to control head drive pulses and the like, and causes the LED heads 15K, 15Y, 15M, and 15C to emit light.

  The printer engine control unit 153 sends a voltage setting signal to the charging bias generation unit 161, the development bias generation unit 162, and a transfer bias generation unit 163 configured using a piezoelectric transformer as will be described later. The charging bias generator 161 individually applies a charging bias voltage to the charging roller 14 (FIG. 1) of each image forming unit 12 for black (K), yellow (Y), magenta (M), and cyan (C). The developing bias generator 162 includes a developing roller 16 (FIG. 1), a toner supply roller 18 and a developing roller of each of the image forming units 12 for black (K), yellow (Y), magenta (M), and cyan (C). A bias voltage is individually applied to the blade 19 (FIG. 1). The transfer bias generator 163 will be described in detail later. The charging bias generation unit 161, the development bias generation unit 162, and the transfer bias generation unit 163 are each arranged on a single paper phenol single-sided substrate 180 as a high-voltage power supply device.

  The sheet detection sensor 25 (see FIG. 1) is used to adjust the bias voltage generation timing by the transfer bias generation unit 163, as will be described later. The printer engine control unit 153 includes a hopping motor 154 that drives the hopping roller 22, a registration motor 155 that drives the registration roller pair 23, a belt motor 156 that drives the transfer belt driving roller 21a, and a fixing that drives each roller of the fixing device 28. The four drum motors (K, Y, M, C) 158 that individually drive the rotary members such as the image forming motor 157 and the photosensitive drum 13 of the image forming unit 12 for each image forming unit are driven at a predetermined timing. The temperature of the fixing device heater 159 provided in the heating roller of the fixing device 28 is controlled by the printer engine control unit 153 according to the detection value of the thermistor 165 that detects the temperature of the heating roller.

  FIG. 3 is a block diagram illustrating the transfer bias generator 163 corresponding to the high voltage power supply device of the present invention.

  In the figure, an ASIC (Application Specific Integrated Circuit) 203 receives a reset signal 201 from the printer engine control unit 153 to the input port RESET, and receives cyan (C), magenta (M), yellow (Y), and black (K). ) Are received at the input ports ON_C, ON_M, ON_Y and ON_K, respectively, and the 2-bit serial communication signal 202 is received at the input port. . The serial communication signal 202 is simultaneously connected to and received by the nonvolatile memory E2PROM 204 and a digital / analog converter (hereinafter referred to as DAC) 205.

  Then, the ASIC 203 outputs four systems of piezoelectric transformer drive pulses from the output unit. Here, output ports OUT_C, OUT_M, OUT_Y, and OUT_K (particularly distinguished) are used to individually control the transfer bias voltages of the four systems of cyan (C), magenta (M), yellow (Y), and black (K). If there is no need to distinguish between the piezoelectric transformer driving circuits 210C, 210M, 210Y, and 210K corresponding to the output port OUT_, the piezoelectric transformer driving circuit 210 may be referred to. In other words, the piezoelectric transformer drive pulses 219C, 219M, 219Y, and 219K (in some cases, simply referred to as the piezoelectric transformer drive pulse 219 if there is no need to distinguish) are output.

  The ASIC 203 is sealed in a semiconductor package that can be flow-mounted on a paper phenol single-sided substrate. For example, a QFP package having a pin pitch of about 0.8 mn to about 0.5 mm and a pin count of about 44 to 64 pins.

  The serial communication signal 202 is configured to simultaneously assign specified addresses to the ASIC 203, the E2PROM 204, and the DAC 205, and to read and write data by specifying the internal address of each device by the address. The E2PROM 204 is a non-volatile memory that stores digital data and can be read and written by the printer engine control unit 153.

  According to the data transmitted from the printer engine control unit 153, the DAC 205 returns the corresponding feedback from the output ports DAC_C, DAC_M, DAC_Y, and DAC_K (which may be simply referred to as the output port DAC_ if there is no need to distinguish between them). Reference voltage signals 221C and 221M having 8-bit resolution (0 to 3.3V) are individually supplied to the control circuits 214C, 214M, 214Y, and 214K (in some cases, simply referred to as the feedback control circuit 214 if there is no need to distinguish them). 221Y and 221K are output.

  As will be described later, the operation clock oscillator 206 is an oscillation circuit including a crystal oscillator, a capacitor, and a resistor, and generates an operation clock of the ASIC 203, here 24.576 MHz. The 3.3 V LDO 207 is a step-down DC-DC converter, which converts a DC voltage from a 5 VDC power source supplied from a low voltage power source (not shown) into a 3.3 V DC voltage, a VCC input port of the ASIC 203, and a Vcc input of the E2PROM 204. The power is applied to the port and the Vcc input port of the DAC 205. A 24 VDC power source supplied from a low-voltage power source (not shown) is applied to the DC-DC converters 209C, 209M, 209Y, and 209K (if there is no need to distinguish between them, the DC-DC converter 209 is simply applied).

  Piezoelectric transformer driving circuits 210C, 210M, 210Y, and 210K as piezoelectric transformer driving means (sometimes simply referred to as the piezoelectric transformer driving circuit 210 when there is no need to distinguish between them), a variable voltage is applied by a DC-DC converter 209. The piezoelectric transformer driving pulse 219 is input from the output port OUT_ of the ASIC 203. Piezoelectric transformers 211C, 211M, 211Y, and 211K (which may be simply referred to as piezoelectric transformer 311 if they do not need to be distinguished) receive a half-wave sinusoidal drive signal as a switching signal from the piezoelectric transformer drive circuit 210. , Output a boosted high voltage output sine wave.

  The rectifier circuits 212C, 212M, 212Y, and 212K as rectifiers (in some cases, simply referred to as the rectifier circuit 212 when there is no need to distinguish between them) rectifies the input high-voltage AC voltage and outputs a high-voltage DC voltage. . This high output voltage is applied as a transfer bias voltage to the rotating shaft of the corresponding transfer roller 17 as an output load. The output voltage conversion circuits 213C, 213M, 213Y, and 213K as output conversion means (sometimes simply referred to as the output voltage conversion circuit 213 if there is no need to distinguish between them) are the high output voltages from the corresponding rectifier circuits 212. (Here, the transfer bias voltage) is converted to a low voltage feedback voltage signal (here, 3.3 V or less) 230M obtained by stepping down at a predetermined ratio, and feedback control circuits 214C, 214M, 214Y, 214K as feedback control means (in particular, If there is no need to distinguish between them, they are simply referred to as feedback control circuit 214).

  The feedback control circuit 214 sends a control signal of 0 to 24 V to the DC-DC converter 209 so that the feedback voltage signal 230 from the voltage conversion circuit 212 and the reference voltage signal 221 input from the output port DAC of the DAC 205 have the same value. Output. That is, the variable output voltage of the DC-DC converter 209 is controlled.

  The transfer bias generation unit 163 corresponds to cyan (C), magenta (M), yellow (Y), and black (K), and the high-voltage generation units 216C, 216M, 216Y, and 216K having the same configuration described above (need to be particularly distinguished). If there is no such, there is a case where it is simply referred to as a high voltage generation unit 216), and a DC high voltage output voltage generated by each is applied to the transfer rollers 17C, 17M, 17Y, and 17K as a transfer bias voltage. .

  Next, the circuit configuration of the high voltage generation unit 216 will be described. For simplicity, only the magenta (M) high voltage generation unit 216M is shown here as an example together with the printer engine control unit 153, the ASIC 203, etc., and the configuration thereof will be described below. It is the same. 4, the same components as those in FIG. 3 are denoted by the same reference numerals.

153 is a printer engine control unit, 203 is an ASIC, 204 is an E2PROM, 205 is a DAC, 206 is an operation clock oscillator, 209M is a magenta (M) DC-DC converter, and 210M is a magenta (M) piezoelectric transformer. The drive circuit, 211M is a magenta (M) piezoelectric transformer, 212M is a magenta rectifier circuit, 213M is an output voltage conversion circuit for magenta (M), 214M is a feedback control circuit for magenta (M), and 17M is magenta This is a transfer roller (M) for (M).
In the description of the image forming apparatus, when distinguishing cyan (C), magenta (M), yellow (Y), and black (K), it may be described as () system.

  The operation clock oscillator 206 includes a crystal oscillator 303, resistors 304 and 305, and capacitors 301 and 302, and generates an operation clock of the ASIC 203, 24.576 MHz.

  The DC-DC converter 209M includes an NPN transistor 313, resistors 311 and 312, and an electrolytic capacitor 314. The base of the NPN transistor 313 is connected to the output terminal of the operational amplifier 308 of the feedback control circuit 214M described later via the resistor 312. The 24 VDC voltage is applied to the collector of the NPN transistor 313 via a resistor 311, and the emitter of the NPN transistor 313 is grounded via an electrolytic capacitor 314 and via an autotransformer 324 of a piezoelectric transformer driving circuit 210M described later. It is connected to the drain of the N-channel power MOSFET 323 and, as will be described later, is controlled by the feedback control circuit 214M to output a DC voltage of about 0V to 22V to the piezoelectric transformer drive circuit 210M.

  The piezoelectric transformer driving circuit 210M includes resistors 315, 316, 318, 319, 320, 321, NPN transistors 317, 322, an N-channel power MOSFET (hereinafter referred to as FET) 323, an autotransformer 324, and a capacitor 325. Yes. The base of the transistor 317 is connected to the output port OUT_M of the ASIC 203 through the resistor 315 and is grounded through the resistor 316, the emitter of the transistor 317 is directly grounded, and the collector of the transistor 317 is connected to the output port OUT_M through the resistor 318. A 3V DC voltage is applied. The base of the transistor 322 is connected to the collector of the transistor 317 via the resistor 319 and grounded via the resistor 320, the emitter of the transistor 317 is directly grounded, and the collector of the transistor 317 is connected to the 24V DC voltage via the resistor 321. Is applied.

  The gate of the FET 323 is connected to the collector of the transistor 322, and the drain of the FET 323 is connected to the emitter of the NPN transistor 313, which is the output of the DC-DC converter 209, via the autotransformer 324 and Connected to the primary side input terminal 211a of the transformer 211M, the source of the FET 323 is grounded and connected to the drain via the capacitor 325.

  In the above configuration, when the piezoelectric transformer driving circuit 210M inputs the piezoelectric transformer pulse 219M from the output port OUT_M of the ASIC 203, the peak corresponds to the output voltage of the DC-DC converter 209 at the primary side input terminal 211a of the piezoelectric transformer 211M. Apply a sine half wave (switching signal) that changes. At this time, a boosted high voltage that changes in accordance with the switching frequency of the FET 323 and the output voltage of the DC-DC converter 209 is output from the secondary output terminal 211b of the piezoelectric transformer 211M.

  The rectifier circuit 212M includes diodes 326 and 327 and a capacitor 328, and converts the high voltage AC output from the piezoelectric transformer 211M into a DC high output voltage. This high output voltage is applied to the (M) transfer roller 17M as an output load via the output resistor 329 as an output of the high voltage generation unit 216M, that is, a transfer bias voltage here. The output voltage conversion circuit 213M divides the transfer bias voltage by the resistor 330 and the resistor 331 to obtain a low-voltage feedback voltage signal 230 (here, 3.3 V or less), and further smoothes it by the resistor 333 and the capacitor 334. And output to the negative input terminal of the operational amplifier 308 of the feedback control circuit 214M. A 3.3 V DC voltage is applied to the connection point between the voltage dividing resistors 330 and 331 via the pull-up resistor 332. Here, the resistor 330 is set to 100 MΩ, the resistor 331 is set to 47 kΩ, and the resistor 332 is set to 10 MΩ.

  The feedback control circuit 214M includes an operational amplifier 308, a resistor 310, and a capacitor 309. A capacitor 309 and a resistor 310 are connected in series between the negative input terminal and the output terminal of the operational amplifier 308 to function as an integration circuit. DC-DC so that the reference voltage signal 221M input from the output port DAC_M of the DAC 205 and the feedback voltage signal 230M input to the negative input terminal are input to the positive input terminal via the smoothing circuit formed by the capacitor 336. The output voltage of the converter 209 is controlled.

  FIG. 5 is a block diagram in which the configuration of the ASIC 203 shown in FIG. 3 is divided into blocks according to functions. The circuit is described in a logic description language or the like. In the same figure, the constituent elements described in the quadruple block are composed of four systems (K), (Y), (M), and (C), respectively, but generally perform the same operation. Therefore, in the figure, for the sake of convenience, it is described as a single system that is described in quadruple blocks and is not specified, and the four systems are described separately as necessary.

  In FIG. 5, the same components as those in FIG. That is, 153 is a printer engine control unit, 203 is an ASIC, 204 is an E2PROM, and 205 is a DAC.

  The memory 401 is configured by a flip-flop or the like. The frequency division ratio setting value registers 404 serving as the four frequency division value holding means each have a 24-bit (8 bits × 3) area, and output 19-bit output to the corresponding four arithmetic units 402. Have. Although it has a 5-bit unused area, it is because it corresponds to a transfer unit of 8 bits in the communication system, and is not particularly limited to this value. Similarly, the division ratio correction value register 405 serving as the four systems of correction value holding means has a 24 bit (8 bits × 3) area, and outputs 19 bits to the corresponding four systems of computing units 402. have. The frequency division ratio setting value register 404 and the frequency division ratio correction value register 405 have values set by the communication processing unit 412 that inputs the 2-bit serial communication signal 202 input from the printer engine control unit 153 to the input port SCI. Updated.

  The arithmetic units 402 serving as the four frequency division value setting means respectively divide ratio setting values input from the corresponding frequency division ratio setting value registers 404 and frequency division ratio correction values input from the frequency division ratio correction value register 405. Are set in the corresponding 19-bit registers 406 of the four systems.

  As will be described later, the pulse output generation unit 403 serving as the frequency dividing means has an average period (((19-bit frequency dividing ratio)) according to the 19-bit frequency dividing ratio value set by the arithmetic unit 402 and held by the 19-bit register 406. Value × 40.69nsec) / 2048), which generates a piezoelectric transformer drive pulse 219 with an on-duty of 30%, each comprising four systems of 19-bit register 406, 1 plus adder 408, frequency divider selector 409, error holding register 407, a frequency divider 410, and an output selector 411 are individually configured.

  In the 19-bit register 406, the arithmetic unit 402 sets the 19-bit division ratio value to be held as described above, and the higher 8 bits of the 19-bit division ratio value are divided by the frequency division selector 409 and the 1 plus adder. The lower 11 bits are output to the error holding register 407. The error holding register 407 adds the lower 11-bit value input at each rising edge of the pulse output from the frequency divider 410 to the 11-bit register holding value and sequentially updates the register holding value, and overflow occurs at the time of addition. If it occurs, a select signal that is “H”, otherwise “L” is output to the frequency divider selector 409.

  The frequency division selector 409 directly inputs the upper 8 (S) bit value of the 19 (N) bit division ratio value to one input unit, and the 19-bit division ratio value by the 1 plus adder 408 to the other input unit. When the select signal input from the error holding register 407 is “L”, the upper 8 bits of the directly input division ratio value are selected. In the case of “H”, an 8-bit value obtained by adding 1 by the 1 plus adder 408 is selected and output to the frequency divider 410.

  The frequency divider 410 counts the 8-bit value input from the frequency divider selector 409 and outputs a pulse signal with an on-duty of 30% to the output selector 411 at a cycle of (8-bit value × 40.69 nsec). 40.69 nsec is the period of the CLK signal formed by the operation clock oscillator 206 (FIG. 4). As will be described later, the output selector 411 outputs the pulse signal from the frequency divider 410 as a piezoelectric transformer drive pulse when the transfer bias instruction signal 220 input from the printer engine control unit 153 is “H”, and the transfer bias instruction signal is output. When 220 is off “L”, the output is 0 V (earth level). The pulse signal with an on-duty of 30% is the sum of the 1/4 value, 1/32 value, and 1/64 value of the 8-bit output value, that is, the 8-bit output of the frequency divider selector 409 is right-shifted by 2 bits and right According to the value obtained by shifting 5 bits and shifting right 6 bits.

The operation of the pulse output generation unit 403 will be further described. As described above, the frequency division selector 409 inputs the upper 8-bit value corresponding to the integer value of the 19-bit frequency division ratio value held by the 19-bit register 406, for example, D, to the other input unit. D + 1 is input to the input signal, and these two values are selected and output by a selection signal input from the error holding register 407. This selection is performed in the cycle of the pulse signal output from the frequency divider 410. By outputting D for 2048 times and (D + 1) for (2048-E) times during the 2048 pulses,
{D × E + (D + 1) × (2048−E)} / 2048
= Upper 8-bit value + (Lower 11-bit value / 2048)
= Control the frequency division ratio to be average. By controlling in this way, the average period during the generation of at least 2048 pulses of the pulse signal output from the 8-bit input frequency divider 410 is the 19-bit division ratio value held by the 19-bit register 406. Based on the above, the same condition (including a small number) is used, and the period of the pulse signal obtained by frequency division by a 19-bit input frequency divider is coincident.

  Therefore, the average period here is an average period during which the pulse signal output from the frequency divider 410 generates a predetermined number of pulses (here, 2048).

  FIG. 16 is a flowchart for explaining the processing executed by the error holding register 407 in order to derive E in the above equation. The error holding register 407 is actually realized by hardware.

  When the processing is started, the rising edge of the pulse signal output from the frequency divider 410 is monitored (step S401). When the rising edge of the pulse is detected (step S401, Yes), the lower 11-bit value of the 19-bit register 406 is detected. Whether the 12-bit value obtained by adding the 11-bit register holding value held by the error holding register 407 is larger than 7FF hex (step S402). If the 12-bit value is larger (step S402, Yes), the frequency divider selector 409 ( D + 1) is selected to select “H” (step S403), otherwise (step S402, No), the frequency divider selector 409 sets the selection signal to “L” to select (D) (step S403). S404). Then, the lower 11-bit value of the 19-bit register 406 is added to the 12-bit register holding value of the error holding register 407 to update it, and the process returns to step S101 to repeat the same operation.

  Through the above processing, the error holding register 407 increases the number of times that the selection signal becomes “H” as the lower 11-bit value of the 19-bit register 406 increases, for example, and the ratio at which the frequency divider selector 409 selects (D) is low. The selection signal having the same characteristics as E in the above equation can be output, and the average period of the pulse signal output from the 8-bit input frequency divider 410 can be increased to an accuracy equivalent to 19-bit input. Further, if the division ratio value held by the 19-bit register 406 does not change, the above operation is performed as described above. However, even if it changes, the value changes in less than 2048 pulse periods. Even in this case, the average values of the left side and the right side of the above equation per unit time are almost equal.

  In the above configuration, the outline of the printing operation of the image forming apparatus will be described first.

  The image forming apparatus 11 illustrated in FIG. 1 inputs print data described in PDL (Page Description Language) or the like from an external device (not illustrated) via the host interface unit 150 (FIG. 2). The input data is converted into bitmap data by the command / image processing unit 151 (FIG. 2). The image forming apparatus 11 starts the printing operation after setting the heating roller of the fixing device 28 to a predetermined temperature by controlling the temperature of the fixing device heater 159 according to the detection value of the thermistor 165 (FIG. 2).

  The recording paper 30 set in the paper storage cassette 24 is fed by the hopping roller 22, and the recording paper 30 is conveyed onto the transfer belt 26 by the registration roller pair 23 at a timing synchronized with an image forming operation described later. The four image forming units 12 form toner images on the internal photosensitive drum 13 by an electrophotographic process. At this time, an electrostatic latent image is formed on the photosensitive drum 13 by the LED head 15 that is turned on according to the bitmap data, and a toner image is formed by development by the developing roller 16.

  The toner image formed on the photosensitive drum 13 is transferred by each transfer bias voltage applied to the transfer rollers 17K, 17Y, 17M, and 17C disposed to face the photosensitive drums 13K, 13Y, 13M, and 13C. The images are sequentially superimposed and transferred onto the recording paper 30 conveyed on the belt 26. After the four color toner images are transferred onto the recording paper 30, the recording paper 30 is fixed by the fixing device 28, further conveyed, and discharged to the paper stacker 29.

  During the above-described printing operation, the printer engine control unit 153 shown in FIG. 2 sets a high-voltage output voltage according to a predetermined table value, and supplies the charging bias generation unit 161, the development bias generation unit 162, and the transfer bias generation unit 163 with a predetermined value. The voltage setting signal is output. The charging bias generator 161 individually applies a bias voltage to the charging roller 14 (FIG. 1) of each image forming unit 12 based on the voltage setting signal, and the developing bias generator 162 based on the voltage setting signal. A bias voltage is individually applied to the developing roller 16, the toner supply roller 18 and the developing blade 19 (FIG. 1) of each image forming unit 12, and the transfer bias generator 163 is configured to transfer each transfer roller based on the voltage setting signal. A transfer bias is supplied to 17.

  The operation of the transfer bias generator 163 at this time will be further described.

  In the block diagram of FIG. 3, the printer engine control unit 153 initializes the ASIC 203 by transmitting a reset signal 201 to the ASIC 203 at initialization to reset various settings in the ASIC 203, and then performs two-wire synchronous clock communication (2 A command is transmitted / received by a serial communication signal 202 by bit).

  First, the printer engine control unit 153 transmits data to the DAC 205 to set the 8-bit DAC setting value to 00 hex for all four systems. At this time, a D / A converted reference voltage signal 221 having a voltage value of 0 V is output from each output port DAC_ of the DAC 205. Subsequently, as will be described later, data is read from the E2PROM 204, and a read value corresponding to the transfer output voltage is transmitted to the ASIC 203 and set before starting the printing operation. At the start of printing, the transfer bias instruction signal 220, which is the output start signal of the transfer bias for each color output to the input port ON of the ASIC 203, is changed from “L” to “H”.

  The high voltage generation unit 216 inputs the piezoelectric transformer drive pulse 219 having a predetermined period when the transfer bias instruction signal 220 becomes “H”. However, since the reference voltage signal of the DAC 205 output is 0V, The high output voltage (transfer bias voltage here) of the high voltage generator 216 to be applied is also approximately 0V. The printer engine control unit 153 transmits a DAC setting value corresponding to each high-voltage output to the DAC 205 at a timing when the recording paper 30 reaches the nip portion, and the DAC 205 performs a D / A converted voltage value from each output port DAC_. Is output as a reference voltage signal 221.

  The high voltage generation unit 216 increases the output of the DC-DC converter 209 from 0 V until the reference voltage signal 221 input by the feedback control circuit and the feedback voltage signal 230 obtained by dividing the transfer bias voltage to become a low voltage are equal. The piezoelectric transformer drive circuit 210 increases the voltage of the half-wave sine wave applied to the primary side of the piezoelectric transformer 211 in proportion to the voltage supplied from the DC-DC converter 209. An AC boosted voltage is output to the secondary side of the piezoelectric transformer 211, and a high output voltage (transfer bias voltage) is applied to the transfer roller 17 as an output load via the output resistor 329 by the rectifier circuit 212. At the same time, the voltage is stepped down by the output voltage conversion circuit 213 and input to the feedback control circuit 214.

  Thereafter, the printer engine control unit 153 sets the 8-bit DAC setting value so that the reference voltage signal 221 output from the output port DAC_ of the DAC 205 becomes 0 V at the timing when the trailing edge of the recording paper 30 reaches the nip portion. Set it to 00 hex again. When the printing operation continues, the DAC setting value corresponding to the high voltage output is transmitted again to the DAC 205 at the timing when the leading edge of the next recording paper 30 reaches the nip portion, and thereafter the same operation is repeated. At the end of the printing operation, after the DAC_ output is set to 0 V, the transfer bias instruction signal 220 is set to “L”, and the piezoelectric transformer drive pulse output from the output port OUT_ of the ASIC 203 is also turned off.

  The operation of the transfer bias generator 163 will be further described with reference to FIG. As described above, the transfer bias generator 163 includes the high voltage generators 216C, 216M, 216Y, and 216K having the same configuration corresponding to cyan (C), magenta (M), yellow (Y), and black (K). Therefore, here, only the high-pressure generator 216M of magenta (M) is shown, and the four systems will be described separately as necessary.

  The ASIC 203 receives a 24.576 MHz clock signal from the reference clock oscillator 206 as an operation clock. The output of the DC-DC converter 209M is controlled by the potential output from the operational amplifier 308, and the NPN transistor 313 has its emitter potential determined by flowing a base current through the resistor 312. The resistor 311 is a resistor that protects the NPN transistor 313 from an inrush current, and is about several Ω to several tens Ω.

  The piezoelectric transformer drive circuit 210M switches the NPN transistor 317 by the piezoelectric transformer drive pulse output from the output port OUT_M of the ASIC 303, and inputs the inverted signal of the piezoelectric transformer drive pulse to the base of the NPN transistor 322. The two NPN transistors convert the 3.3V output of the ASIC 203 into a 24V output and generate the gate drive potential of the power MOSFET 323. The FET 323 is turned on and off by a gate signal having the same phase as the piezoelectric transformer drive pulse, drives a resonance circuit composed of the auto transformer 324, the capacitor 325, and the piezoelectric transformer 211M, and has a half-wave sine on the primary side of the piezoelectric transformer. Apply waves.

  FIG. 6 and FIG. 7 show signal waveforms in each part of the high voltage generation unit 216M. Waveforms indicated by arrows A, B, C, and D in the figure indicate signal waveforms at points A, B, C, and D in the circuit of the high-voltage generator 216M shown in FIG. 6A shows a case where the high output voltage (transfer bias voltage) at the point C is 1 kV, and FIG. 6B shows a case where the high output voltage at the point C is 2.5 kV. FIG. 6B shows waveforms when the high output voltage (transfer bias voltage) at point C is 5 kV, and FIG. 6B shows the waveforms when the high output voltage at point C is 6.5 kV.

  The waveform at point C is the output waveform of the rectifier circuit 212M and is measured with a 2000: 1 high voltage probe. The waveform at point A is the output waveform of the DC-DC converter 209M, the waveform at point D is the waveform at the drain portion of the power MOSFET 323, and the waveform at point B is the primary side input portion of the piezoelectric transformer 211. The potential at point D is boosted by the autotransformer 324. The high output voltage (transfer bias voltage) obtained at the point C is obtained according to the output voltage of the DC-DC converter 209M. 6 and 7 show signal waveforms at points A, B, C, and D in the circuit of the high voltage generator 216M shown in FIG. 4, and the levels of the waveforms are not accurately depicted.

  The secondary output of the piezoelectric transformer 211M is rectified by a rectifier circuit 212M including diodes 326 and 327 and a capacitor 328 to become a high DC output voltage (transfer bias voltage), and transferred as a transfer load via the output resistor 329. Applied to roller (M) 17M.

On the other hand, the output voltage conversion circuit 213M divides the high output voltage (transfer bias voltage) by the resistance 330 of 100 MΩ and the resistance 331 of 47 kΩ. For example, when the high output voltage at point C is 7000V output,
7000 × 47k / (100,000k + 47k) = 3.288
The voltage is stepped down to 3.288 V calculated by
The output voltage conversion circuit 213M divides 3.3V by the resistor 332 (10 MΩ) and the resistor 331 (47 kΩ).
3.3 × 47k / (10000k + 47k) = 0.015
Is obtained, and the output when the high output voltage (transfer bias voltage) is off is regulated not to be 0V. The resistor 333 and the capacitor 334 are CR filters for removing ripples.

  The feedback control circuit 214M operating as an integration circuit controls the output so that the potential of the reference voltage signal 221M output from the output port DAC_M of the DAC 205 is equal to the potential of the feedback voltage signal 230M output from the output voltage conversion circuit 213. To do. For example, when the DAC 205 sets the reference voltage signal 221M output from the output port DAC_M to 0 V corresponding to the input 8-bit DAC set value 00hex, the voltage of the feedback voltage signal 230M of the output voltage conversion circuit 213 is as described above. Therefore, the output of the operational amplifier 308 is 0V, the base current of the NPN transistor 313 does not flow, and the output of the DC-DC converter 209M and the high output voltage (transfer bias voltage) is also substantially 0V. Become.

  Here, the DAC 205 is set to output a DC voltage of 0 V to 3.3 V from the corresponding output port output port DAC_ when 0 to FFhex is input as a DAC setting value for each system. To do.

The DAC 205 inputs a DAC setting value of 02 hex or more, and from the output port DAC_M,
3.3 × 2/255 = 0.026
When the quasi-voltage signal 221M of 0.026V or more calculated by the above is output, the minimum voltage 0.015V or more is obtained, and the feedback control circuit 214M raises the output of the DC-DC converter 209M by negative feedback control, The output is controlled so that the potential of the voltage signal 221M and the potential of the feedback voltage signal 230 are equal. Therefore, when the DAC 205 inputs the DAC setting value 02 hex, the high output voltage (transfer bias voltage) at the point C is
0.026 × (100000 + 47) / 47 = 55
It is controlled to 55V calculated by

  Accordingly, when the DAC 205 receives the 8-bit DAC setting values 02 hex to FF hex, the high voltage generation unit 216M linearly controls the output of the high output voltage (transfer bias voltage) in the range of 55V to 7025V. .

  Here, the output of the DC-DC converter 209M has a loss of the NPN transistor 313 and saturates in the range of 0V to 20V to 22V with respect to the supply voltage of 24V. Therefore, when the high output voltage (transfer bias voltage) outputs 7025V, it is necessary to set the drive frequency of the piezoelectric transformer 211 in advance so that a step-up ratio capable of operating at an output of the DC-DC converter 209 of less than 20V is obtained. is there.

  The step-up ratio of the piezoelectric transformer 211M varies depending on the driving frequency of the piezoelectric transformer driving pulse output from the output port OUT_M of the ASIC 203, and the rise time varies depending on the driving frequency as described later. Therefore, when the high output voltage (transfer bias voltage) is at a predetermined level, which is 4985 V or less, the first step-up ratio is set so that there is still a margin up to the maximum step-up ratio and the output of the DC-DC converter 209 is operable at less than 20 V. When the drive frequency is set to be higher than 4985V, the rise time is set as much as possible by switching to the second drive frequency that can obtain a higher step-up ratio that enables the output of the DC-DC converter 209 to be operated at less than 20V even in this region. Is considered not to slow down. These will be described in more detail later.

  As described above, the operation of the (M) high voltage generation unit 216M has been described here, but the other (C), (Y), and (K) high voltage generation units operate in the same manner.

  Next, the operation of the ASIC 203 will be described with reference to FIG. The printer engine control unit 153 performs communication using the serial communication signal 202 and reads data from the E2PROM 204. The data here is recorded in the format shown in FIG. 18, and 31 bytes in the figure are stored in a memory (not shown) of the printer engine control unit 153. Here, a 3-byte division ratio value 1 corresponding to the first set division value is stored in addresses 00hex to 02hex, and a 3-byte division ratio corresponding to the second set division value is stored in addresses 03hex to 05hex. The value 2 is stored, and the switching value B5hex (DAC setting value) is stored in the address 1Ehex.

The switching value B5hex is a threshold value for switching the frequency of the piezoelectric drive pulse, and corresponds to 181 in decimal, and 3.3 × 181/255 = 2.342 in the output of the DAC 205.
Is equivalent to 2.342V calculated by the following equation, and at a higher output voltage (transfer bias voltage):
2.342 × (100000 + 47) / 47 = 4985
This corresponds to 4985V calculated by the following equation.

  When the DAC setting value of the DAC 205 is equal to or less than B5 hex (4985 V at a high output voltage), the printer engine control unit 153 selects 70000 hex with a division ratio value of 1 and outputs it to the ASIC 203, and the DAC setting value of the DAC 205 is B5 hex ( When the output voltage is higher than 4985V at a high output voltage, 70400 hex with a division ratio value of 2 is selected and output to the ASIC 203.

  The selection of the division ratio setting value is set in the ASIC 203 by the printer control unit 253 according to the value of the E2PROM 204. That is, the data is transmitted to the communication processing unit 412 of the ASIC 203 in a predetermined communication format based on the serial communication signal 202 and set in the frequency division ratio setting value register 404. The frequency division ratio setting value register 404 is for four systems, and is preset according to the DAC setting value for each system.

  Subsequently, among the correction values set in the addresses 06hex to 1Dhex of the E2PROM 204, when the division ratio value is 1, the correction value 1 is set. When the division ratio value is 2, the correction value 2 is set for each system. Similarly, it is transmitted and set in the division ratio correction value register 405. Here, each correction value is a 2's complement. After setting the values in the frequency division ratio setting value register 404 and the frequency division ratio correction value register 405, the transfer bias instruction signal 220 is set to “H”, and then the output of the DAC 205 is switched from 0 to a value corresponding to the target. .

  FIG. 13 shows a DAC setting value for applying a predetermined high output voltage (transfer bias voltage) to the transfer roller 17 as output loads of four systems (C), (M), (Y), and (K). 5 is a flowchart showing a procedure performed by the printer engine control unit 153 when setting is set in the DAC 205, and the contents will be described according to this flowchart.

First, the desired transfer bias voltages of the four systems (C), (M), (Y), and (K) are determined from a variety of conditions such as a printing medium and printing speed using a table stored in advance. (Step S101) It converts into four DAC setting values (Step S102). Here, the high output voltage (transfer bias voltage) when the reference voltage signal output from the DAC 205 is 3.3 V is:
3.3 × (100000k + 47k) / 47k = 7025
Therefore, the voltage step around the change of the DAC setting value 1 is
7025/255 = 27.55
Is calculated to be 27.55V. Therefore, a value obtained by dividing the transfer bias value of the desired value determined in step S101 by 27.55 is the DAC setting value.

  The division ratio setting value and the division ratio correction value corresponding to the DAC setting value are set in the division ratio setting value register 404 and the division ratio correction value register 405 of the ASIC 203 (step S103), and initial driving at the start of printing is performed. Is started, the transfer bias instruction signal 220 is set to “H” so that the output selector 411 (FIG. 5) can output the pulse signal from the frequency divider 410 as a piezoelectric transformer drive pulse (step S104). A set value is set (step S105).

  FIG. 14 is performed by the printer engine control unit 153 for setting the division ratio setting value in the four division ratio setting value registers 404 of (C), (M), (Y), and (K). It is a flowchart which shows a procedure, The content is demonstrated according to this flowchart.

  First, it is determined whether or not (C) the DAC setting value of the system is larger than the switching value B5hex, and if it is larger than B5hex (step S201: Yes), the division ratio setting value 70400hex is set to the division ratio setting value register 404C. (Step S202), and if it is B5 hex or less (step S201: No), the division ratio setting value 70000 hex is set in the division ratio setting value register 404C (step S203).

  Similarly, it is determined whether or not the DAC setting value of the (M) system is larger than the switching value B5hex, and if it is larger than B5hex (step S204: Yes), the frequency division ratio setting value 70400hex is set to the frequency division ratio setting value. If it is set in the register 404M (step S205) and is less than or equal to B5 hex (step S204: No), the division ratio setting value 70000 hex is set in the division ratio setting value register 404M (step S206).

  Similarly, it is determined whether or not the (Y) system DAC setting value is larger than the switching value B5hex. If the DAC setting value is larger than B5hex (step S207: Yes), the division ratio setting value 70400hex is set to the division ratio setting value. When the value is set in the register 404Y (step S208) and is less than or equal to B5 hex (step S207: No), the frequency division ratio setting value 70000 hex is set in the frequency division ratio setting value register 404Y (step S209).

  Similarly, it is determined whether or not the DAC setting value of the (K) system is larger than the switching value B5hex, and if it is larger than B5hex (step S210: Yes), the division ratio setting value 70400hex is set to the division ratio setting value. When the value is set in the register 404K (step S211) and is less than or equal to B5 hex (step S210: No), the frequency division ratio setting value 70000 hex is set in the frequency division ratio setting value register 404Y (step S212).

  FIG. 15 is performed by the printer engine control unit 153 for setting the division ratio correction value in the four division ratio correction value registers 405 of (C), (M), (Y), and (K). It is a flowchart which shows a procedure, The content is demonstrated according to this flowchart.

  First, it is determined whether or not the DAC setting value of the system (C) is larger than the switching value B5hex, and if it is larger than B5hex (step S301: Yes), the frequency division ratio correction value corresponding to the frequency division ratio setting value 70400hex. Here, 000006 hex (see FIG. 18) is set in the division ratio correction value register 405C (step S302), and if it is less than or equal to the switching value B5 hex (step S301: No), the amount corresponding to the division ratio set value 70000 hex. A frequency ratio correction value, here, 000005 hex (see FIG. 18) is set in the frequency division ratio correction value register 405C (step S303).

  Similarly, it is determined whether or not the DAC setting value of the (M) system is larger than the switching value B5hex. If the DAC setting value is larger than B5hex (step S304: Yes), the frequency division ratio corresponding to the frequency division ratio setting value 70400hex. A correction value, here, 000011hex (see FIG. 18) is set in the frequency division ratio correction value register 405M (step S305), and if it is equal to or lower than the switching value B5hex (step S304: No), it corresponds to the frequency division ratio setting value 70000hex. The division ratio correction value to be performed, here, 000010 hex (see FIG. 18) is set in the division ratio correction value register 405M (step S306).

  Similarly, it is determined whether or not the DAC setting value of the (Y) system is larger than the switching value B5hex. If the DAC setting value is larger than B5hex (step S307: Yes), the frequency division ratio corresponding to the frequency division ratio setting value 70400hex. A correction value, here FFFFFAhex (see FIG. 18) is set in the frequency division ratio correction value register 405Y (step S308), and if it is equal to or less than the switching value B5hex (step S307: No), it corresponds to the frequency division ratio set value 70000hex. The division ratio correction value to be set, here FFFFF8hex (see FIG. 18), is set in the division ratio correction value register 405Y (step S309).

  Similarly, it is determined whether or not the DAC setting value of the (K) system is larger than the switching value B5hex, and if it is larger than B5hex (step S310: Yes), the frequency division ratio corresponding to the frequency division ratio setting value 70400hex. A correction value, here 000000 hex (see FIG. 18) is set in the frequency division ratio correction value register 405K (step S311), and if it is less than or equal to the switching value B5 hex (step S310: No), it corresponds to the frequency division ratio set value 70000 hex. The division ratio correction value to be performed, here 000000 (see FIG. 18), is set in the division ratio correction value register 405Y (step S312). Data is transferred and held in the memory 401 of the ASIC 203 by the flow described above.

  The division ratio setting value register 404 and the division ratio correction value register 405 each receive and hold 24 bits (8 bits × 3) of data, but when sending the held data to the computing unit 402, the upper 5 bits The lower 19 bits of data are transmitted. This processing is because the value set from the outside is set to a multiple of 8 in accordance with data transmission / reception in units of 8 bits in serial communication or the like when inputting data. There is no limit to this. The value of 19 bits on the output side is not limited to this value and is set according to the required frequency resolution, and may take a value of 12 bits or 24 bits.

  The arithmetic unit 402 adds the 19-bit frequency division ratio setting value and the frequency division ratio correction value input from the frequency division ratio setting value register 404 and the frequency division ratio correction value register 405, and outputs the added data to the pulse output generation unit. The data is output to the 19-bit register 406 of 403.

  FIG. 19 shows values of the division ratio setting value and the division ratio correction value as output examples output here. In this case, in the (C) system, 70005 hex obtained by adding the division ratio setting value 70000 hex and the division ratio correction value 00005 hex is set in the 19-bit register 406C. Similarly, in the (M) system, the division ratio setting value 70000 hex and the frequency division are set. 70010 hex to which the ratio correction value 00010 hex is added is set in the 19-bit register 406M, and in the (Y) system, 6FFF8 hex in which the division ratio setting value 70000 hex and the division ratio correction value FFFF8 hex are added is set in the 19-bit register 406Y. In the system, 70000 hex obtained by adding the division ratio setting value 70000 hex and the division ratio correction value 00000 hex is set in the 19-bit register 406K.

  As described above, according to the 19-bit division ratio value held by the 19-bit register 406, the pulse output generation unit 403 has an average period of ((19-bit division ratio value × 40.69 nsec) / 2048), a piezoelectric transformer driving pulse 219 having an on-duty of 30% is generated.

  Here, the numerical data of (Y) system will be described as an example. In this case, the 19-bit register 406 holds 6FFF8hex, and outputs the upper 8 bits (DFhex) to the frequency divider selector 409 and the 1 plus adder 408, and the 1 plus adder 408 sends 1 plus E0hex to the frequency divider selector 409. Output. The error holding register 407 inputs the lower 11 bits (7F8 hex) of the 19-bit register 406, and the frequency divider 410 receives and counts the 8 bits (DF hex 68 or E0 hex) output from the frequency divider selector 409. A pulse signal having an on-duty of 30% is output to the output selector 412 at a cycle (input 8-bit value × 40.69 nsec). Here, 40.69 nsec is the period of the CLK signal formed by the reference clock oscillator 206 (FIG. 4).

  The error holding register 407 inputs the lower 11 bits (7F8 hex) of the 19-bit register, and adds the lower 11 bits (7F8 hex) every time the rising edge of the output pulse signal of the frequency divider 410 is detected. For example, 000, 7F8, In the process of adding 7F0, a select signal that becomes “H” is output to the frequency divider selector 409 at the timing when the carry occurs, such as 7F8 (11 bits) + 7F8 (11 bits) = FF0 (12 bits). The frequency divider selector 409 outputs the output E0hex of the 1 plus adder 408 to the frequency divider 410 only when the select signal is “H”. Therefore, the frequency divider 410 outputs a pulse signal in which a pulse signal having a frequency of 110.2063 kHz (223 × 40.69 nsec) and a pulse signal having a frequency of 109.7143 kHz (224 × 40.69 nsec) are mixed.

The average frequency division ratio of the mixed pulse signals at this time is, as described above, upper 8 bit value + (lower 11 bit value / 2048) = 223.996.
Thus, the average period is 9.114 μsec (223.996 × 40.69 nsec), and the average frequency is 109.7162 kHz.

  As described above, the pulse output generation unit 403 uses the 8-bit frequency divider 410 to divide the average period of the output pulse signal by using a 19-bit input frequency divider. However, since the detailed description of the operation is as described above, the detailed description is omitted here.

  The piezoelectric transformer driving pulse output from the pulse output generation unit 403 is a pulse signal in which the two frequencies (110.2063 kHz and 109.7143 kHz) output from the frequency divider 410 are mixed. Since the driven piezoelectric transformer 211 (FIG. 4) is mechanically oscillated, it vibrates substantially at the above-mentioned average frequency of 109.7162 kHz.

  As described above, here, the four pulse output generation units 403 have the piezoelectric transformer drive pulses with the drive frequencies set individually according to the division ratio setting value and the division ratio correction value set for each system. Are output from each output selector 411.

  8 to 11 show the rises of the output of the DC-DC converter 209 and the output of the rectifier circuit 212 shown in FIG. Waveform is shown.

  The rise time t is determined by the integration circuit time constant and the characteristics of the NPN transistor 313. When the same constant is used, the rise time t varies depending on the voltage value of the high output voltage and the driving frequency. FIG. 8A shows a rising characteristic when a high output voltage of 7 kV is output at a driving frequency of 109.7143 kHz (70000 hex) as the first driving frequency, and FIG. 8B shows a second driving frequency. The rising characteristics when a high output voltage of 7 kV is output at a driving frequency of 109.4699 kHz (70400 hex) are shown. FIG. 9A shows the rising characteristics when a high output voltage of 5 kV is output at the first driving frequency, and FIG. 9B shows the case of outputting a high output voltage of 5 kV at the second driving frequency. The rise characteristic of is shown. FIG. 10A shows the rising characteristics when a high output voltage of 2.5 kV is output at the first drive frequency, and FIG. 10B shows the high output voltage of 2.5 kV at the second drive frequency. The rise characteristics when output is shown. FIG. 11A shows a rising characteristic when a high output voltage 1 kV is output at the first drive frequency, and FIG. 10B shows a case where the high output voltage 1 kV is output at the second drive frequency. The rise characteristic of is shown.

  Comparing the time when the high output voltage rises to 90%, except when the high output voltage, which is saturated at the first drive frequency, is 7 kV, the drive is driven at the first drive frequency. The difference becomes larger as the time t is shorter and the high-voltage output voltage is lower.

  That is, when the high output voltage is 5 kV, the rise time t3 at the first drive frequency is 17 msec, the difference from the rise time t4 at the second drive frequency is 2 msec, and when the high output voltage is 2.5 kV, the first The rise time t5 at the drive frequency is 18.8 msec, the difference from the rise time t6 at the second drive frequency is 6.8 msec, and when the output voltage is 1 kV, the rise time t7 at the first drive frequency. Is 21.6 msec, and the difference from the rise time t8 at the second drive frequency is 11.2 msec.

  When the high output voltage driven at the first drive frequency is 7 kV, the output of the DC-DC converter 209 is saturated, so that there is no room to withstand load fluctuations as shown in FIG. To improve this, the DC-DC converter 209 is operated in a range not reaching the saturation region as shown in FIG. 8B by increasing the step-up ratio of the piezoelectric transformer 211 in place of the second drive frequency. Set to. The reason why the step-up ratio of the piezoelectric transformer 211 is increased by using the second drive frequency will be described later.

  From the above, in the present embodiment, as shown in the flowchart of FIG. 14, when the high output voltage is set to be larger than 4985 V (corresponding to the DAC set value B5hex), the drive frequency 109, which is the second drive frequency. When the high output voltage is set to 4985V or lower, the drive frequency is 109.7143 kHz (70000 hex), which is the first drive frequency. Accordingly, when the high output voltage is 4985V or less, the high voltage generator 216 is driven with priority on the rising speed, and when the high output voltage is higher than 4985V, the boosting ratio of the piezoelectric transformer 211 is increased to maintain normal operation. Thus, the high pressure generator 216 is driven.

  Next, a method for correcting the frequency division ratio setting value with the frequency division ratio correction value set in the frequency division ratio correction value register 405 will be described.

  FIG. 12 is a graph showing drive frequency characteristics of the piezoelectric transformer 211. This graph shows that in the DC-DC converter 209 shown in FIG. 4, the 24 VDC voltage is directly applied to the base of the NPN transistor 313 via the resistor 312 so that the NPN transistor 313 is substantially short-circuited, and the piezoelectric transformer driving pulse is driven. A high output voltage (transfer bias voltage) when the frequency is changed, that is, a frequency characteristic of the piezoelectric transformer is measured. Here, measurement is performed for four systems of piezoelectric transformers 211.

  As shown in the figure, the relationship between the driving frequency and the high output voltage varies among the four piezoelectric transformers 211. For example, when the high output voltage at the driving frequency of 110 kHz is compared, a difference of 1 kV or more occurs between the maximum and the minimum. However, since the curve characteristics of the respective piezoelectric transformers 211 are similar on the horizontal axis, substantially equal frequency characteristics can be obtained by appropriately correcting the drive frequency in accordance with the characteristics of each piezoelectric transformer 211. In the present embodiment, the variation in frequency characteristics for each piezoelectric transformer 211 is corrected by the frequency division ratio correction value.

  Below, the correction method of the dispersion | variation in the frequency characteristic of the piezoelectric transformer 211 is demonstrated.

  FIG. 20 is a block diagram of a function tester for determining a frequency division ratio correction value. The function tester 500 includes a microcomputer 501, an A / D (analog / digital) converter 502, a constant voltage source 503 for generating DC DC voltages of 24 V and 5 V from a commercial power supply AC 100 V, DC voltages 0 V to 24 V to DC voltages 0 V to 3. It is composed of a step-down circuit 504 for converting to 3 V and a 3.3 VLDO 505 which is a step-down type DC-DC converter.

  The function tester 500 is a device that tests the paper phenol single-sided substrate 180 that is formed with the transfer bias generator 163 and is incorporated in the image forming apparatus 11. As shown in FIG. 2, the paper phenol single-sided substrate 180 is connected to the printer engine control unit 153 in the image forming apparatus 11, but in the function test, it is connected to the function tester 500 as shown in FIG. , 24V, and a reset signal, a serial communication signal (SCI), a transfer bias instruction signal (ON), and the like as necessary.

  The function tester 500 uses the microcomputer 501 to store the two kinds of division ratio setting values 70000 hex (corresponding to the driving frequency 109.7143 kHz) and 70400 hex (corresponding to the driving frequency 109.4699 kHz) to the division ratio setting of the ASIC 203. It can be set in the value register 404 (FIG. 5). Also, as shown in FIG. 4, in order to check the output voltage of the DC-DC converter 209 of the transfer bias generator 163, the point indicated by point A in the same circuit is detected by connecting it with a probe or the like, and the step-down circuit 504 The voltage is stepped down to (3.3 / 24) and input to the A / D converter 502.

  As an initial setting, the microcomputer 501 first performs the following processing to store digital data as a reference value.

A paper phenol single-sided board incorporating a reference piezoelectric transformer is prepared and connected to the function tester 500, and digital data as a reference value is stored in the following procedure.
(1) The division ratio set value 70000 hex and the division ratio correction value 00000 are set in each memory, and the piezoelectric transformer drive pulse is output from the ASIC 203 to operate the piezoelectric transformer.
(2) The DAC set value B5hex is set, the voltage at the point A when the high output voltage (transfer bias voltage) is output 4985V is stepped down by the step-down circuit 504, and digitally converted by the A / D converter 502 The digital average value is stored in advance as a reference average value α.
next,
(3) A division ratio set value 70400 hex and a division ratio correction value 00000 are set in each memory, and a piezoelectric transformer drive pulse is output from the ASIC 203 to operate the piezoelectric transformer.
(4) The DAC set value FFhex is set, and the voltage at point A when the high output voltage (transfer bias voltage) is output at 7025 V is stepped down by the step-down circuit 504 and digitally converted by the A / D converter 502 The digital average value is stored in advance as a reference average value β.

  FIG. 17 shows the frequency division set in the division ratio correction register 405 of the ASIC 203 by testing the paper phenol single-sided substrate 180 (FIG. 2) actually used by the function tester 500 and referring to the reference average values α and β. It is a flowchart which shows the procedure which determines a ratio correction value. A method for determining the division ratio correction values for the four systems will be described with reference to the flowchart. This correction value determination processing is performed in the same manner for four systems of cyan (C), magenta (M), yellow (Y), and black (K). However, since the processing method is the same, the system is not specified here. I will explain it.

  When the paper phenol single-sided substrate 180 to be actually used is connected to the function tester 500 and the processing is started, first, the DAC setting value is set to B5 hex (corresponding to high output voltage 4985V), and the division ratio setting value is set to 70000 hex. The ratio correction value is set to 00000 hex (step S501), and driving of the piezoelectric transformer 211 is started (step S502). The drive start is started by setting the DAC set value after supplying the piezoelectric transformer drive pulse with the transfer bias instruction signal (ON signal) set to “H” as in the flow of FIG.

  It is monitored whether a predetermined time, 50 msec has elapsed since the start of driving (step S503). After 50 msec has elapsed, the output average of the DC-DC converter 209, that is, the voltage detection average at the point A shown in FIG. It is determined whether or not the value (digital average value stepped down by the step-down circuit 504 and digitally converted by the A / D converter 502) is equal to the reference average value α described above (step S504). It should be noted that the definition of equal here means that, when averaging, the values rounded by rounding multiple sampling averages are equal, or if the difference is within ± 1, it is considered equal. It is possible to have a width. This may be determined appropriately according to the A / D converter resolution of the function tester 500 or the like. This determination policy is the same in the determination at other steps in this flow.

  If they are not equal (step S504: No), it is determined whether or not this voltage detection average value is larger than the reference average value α (step S508). If it is larger (step S508: Yes), the step-up ratio of the piezoelectric transformer 211 is determined. Means that the step-up ratio of the piezoelectric transformer 211 is smaller than that of the reference piezoelectric transformer. Therefore, 1 is added to the frequency division ratio correction to lower the drive frequency to increase the boost ratio of the piezoelectric transformer 211 (see FIG. 12). When the voltage detection average value is less than or equal to the reference average value α (step S508: No), it means that the boost ratio of the piezoelectric transformer 211 is larger than the boost ratio of the reference piezoelectric transformer. Then, 1 is subtracted from the frequency division ratio correction to increase the drive frequency to lower the step-up ratio of the piezoelectric transformer 211 (see FIG. 12), so that the boost ratio of the standard piezoelectric transformer is reduced. Approach (step S510) and return to step S504. Thereafter, the same processing is repeated until it is determined in step S504 that they are equal.

  If it is determined that the voltage detection average value at the point A is equal to the reference average value α (step S504: Yes), the transfer bias instruction signal (ON signal) is set to “L”, and the DAC set value is set to 00hex. Then, the high output voltage (transfer bias voltage) is temporarily stopped (step S5506), and the frequency division ratio correction value set in the ASIC 203 is recorded in the E2PROM 204 (step S506). The frequency division ratio correction value at this time is recorded as the correction value 1 shown in FIG.

  Next, the DAC setting value is set to FF hex (corresponding to 7025V of high output voltage), the division ratio setting value is set to 70400 hex, and the division ratio correction value is set to the value (correction value 1) recorded in the E2PROM 204 in step S506. Then, the driving of the piezoelectric transformer 211 is started (step S511). The drive start is performed by setting the DAC set value after supplying the piezoelectric transformer drive pulse with the transfer bias instruction signal (ON signal) set to “H” as in the flow of FIG.

  It is monitored whether a predetermined time, 50 msec, has elapsed since the start of driving (step S512). After 50 msec, the output of the DC-DC converter 209, that is, the voltage detection average value at the point A shown in FIG. It is determined whether or not the digital average value that has been stepped down by the step-down circuit 504 and digitally converted by the A / D converter 502 is equal to the above-described reference average value β (step S513).

  If they are not equal (step S513: No), it is determined whether or not this voltage detection average value is larger than the reference average value β (step S515). If it is larger (step S515: Yes), the step-up ratio of the piezoelectric transformer 211 is determined. Means that the step-up ratio of the piezoelectric transformer 211 is smaller than that of the reference piezoelectric transformer. Therefore, 1 is added to the frequency division ratio correction to lower the drive frequency to increase the boost ratio of the piezoelectric transformer 211 (see FIG. 12). When it approaches the step-up ratio (step S516) and the voltage detection average value is equal to or less than the reference average value β (step S515: No), it means that the step-up ratio of the piezoelectric transformer 211 is larger than the step-up ratio of the reference piezoelectric transformer. Then, 1 is subtracted from the frequency division ratio correction to increase the drive frequency to lower the step-up ratio of the piezoelectric transformer 211 (see FIG. 12), so that the boost ratio of the standard piezoelectric transformer is reduced. It approaches (step S517) and returns to step S513. Thereafter, the same processing is repeated until it is determined in step S513 that they are equal.

  If it is determined that the voltage detection average value at the point A is equal to the reference average value β (step S513: Yes), the frequency division ratio correction value set in the ASIC 203 is recorded in the E2PROM 204 (step S514). The frequency division ratio correction value at this time is recorded as the correction value 2 shown in FIG. Thus, the process for determining the frequency division ratio correction value is completed.

  As described above, the flow of FIG. 17 has been described for one unspecified system, but actually, this correction value determination processing is performed using cyan (C), magenta (M), yellow (Y), and black (K). Repeat with the 4 systems. Further, the function tester 500 performs four correction values 1 corresponding to the division ratio value 1 (70000 hex), the division ratio value 2 (70400 hex), and the division ratio value 1 shown in FIG. The four correction values 2 and the switching values corresponding to the division ratio value 2 are recorded in the E2PROM 204.

  The division ratio correction value determined as described above is that the high voltage generator 216 adopting an unspecified piezoelectric transformer as the four systems of piezoelectric transformers 211 has a high output voltage (transfer bias voltage) of the same value (4985V or 7025V). ), The frequency division value set value is corrected so that the outputs of the DC-DC converter 209 are equal to adjust the drive frequency of the piezoelectric transformer drive pulse, so that the boost ratio is equal during actual operation. In this state, four piezoelectric transformers are used.

  Regardless of the setting, the DC-DC converter output and the drive frequency range have room for 0 to 7 kV output, so the frequency division ratio correction value including the constant variation of the components that make up the DC-DC converter is determined. Is done. By setting the frequency division ratio correction value, it is adjusted so that it is not driven at a driving frequency that is insufficient in the boost ratio, and is not driven at a frequency lower than the resonance frequency exceeding the upper limit of the boost ratio.

  In the present embodiment, as shown in FIG. 4, an 8-bit DAC 205 is used, and 3.3 V is applied to the feedback path via a 10 MΩ pull-up resistor 332, so that the DAC 205 has an 8-bit DAC set value. The example in which the high voltage generator 216 linearly controls the high output voltage (transfer bias voltage) in the range of 55V to 7025V when inputting 02 hex to FF hex has been shown. Instead, it is possible to output from a lower voltage as a resistor such as 20 MΩ, and the output resolution can be easily increased by making the DAC 205 a 10-bit DAC.

  In this embodiment, the configuration of the four systems of the transfer bias generation unit 163 has been described. However, the configuration of all the 12 systems of the transfer bias generation unit 163, the charging bias generation unit 161, and the development bias generation unit 162 is the same. This can be easily realized by juxtaposing various configurations. Also in this case, the ASIC 203 input / output port can be configured with a pulse output port 12 pins, VCC, GND, 0N signal input port 12 pins, SCI input port 2 pins and 44 pins or less. This can be realized with 20 pins or less. In addition to the ASIC 203, CPLD, FPGA and the like can be used.

  In the present embodiment, since the ASIC 203 outputs a piezoelectric transformer driving pulse whose frequency is fixedly set, a negative feedback by the operational amplifier 308 is not formed without forming a feedback loop between the ASIC 203 and the high voltage generator 216. Since the high voltage output is controlled by the control, the piezoelectric transformer 211 can be disposed in the immediate vicinity of the piezoelectric transformer driving circuit 210. Since the feedback loop is formed in the immediate vicinity of each drive circuit in this way, the effect of facilitating pattern design increases as the number of channels increases.

  As described above, according to the image forming apparatus of the present embodiment, the high voltage generation unit 216 analogizes the high output voltage based on the piezoelectric transformer drive pulse that is fixedly set by the external circuit. Because of the control, even when a plurality of high voltage generation units 216 are provided, each control loop can be wired short, and circuit oscillation due to the long control loop can be easily prevented. In addition, by changing the drive frequency of the piezoelectric transformer drive pulse, it is possible to avoid driving at a spurious frequency, which is a problem in the case of drive frequency variable control in which high output voltage is negatively feedback controlled.

  In the case of the drive frequency variable control, in order to obtain a low output voltage, the frequency is varied across the spurious frequency. In the embodiment, since negative feedback control is performed on the high output voltage while the drive frequency is fixed, such inconvenience does not occur.

  In addition, the drive frequency resolution is realized by combining pulses with different division ratios, so that the frequency adjustment resolution is high, and accurate drive frequency correction proportional to the piezoelectric transformer variation is possible, and the boost ratio close to the resonance frequency is high. Stable output is possible including the area. Further, by increasing the frequency resolution at a low clock frequency, it is possible to keep the radiation noise level low even if an ASIC is mounted on a paper phenol substrate frequently used for a high-voltage power supply substrate.

  Furthermore, since the optimum drive frequency is set depending on whether or not the high output voltage is greater than a predetermined value (4985 V in this case), when the voltage is less than the predetermined value, the high voltage generator 216 is driven with priority on the rising speed. When the output voltage is higher than a predetermined value, the high voltage generator 216 can be driven to maintain normal operation by increasing the step-up ratio of the piezoelectric transformer 211.

Embodiment 2. FIG.
FIG. 21 is a block diagram showing a circuit configuration of a control system of the image forming apparatus according to the second embodiment of the present invention.

  The image forming apparatus of the present embodiment that employs this control system is mainly different from the image forming apparatus of the first embodiment shown in FIG. 2 described above in that a printer engine control unit 1153, a paper phenol single-sided substrate 1180, and This is the configuration of the charging bias generator 1161. Therefore, in this image forming apparatus of the present embodiment, the same reference numerals are given to parts common to the image forming apparatus 11 (FIG. 1) of the first embodiment described above, or the description is omitted by omitting the drawing. , Explain different points with emphasis. The configuration of the main part of the image forming apparatus according to the present embodiment is the same as that of the main part of the image forming apparatus 11 according to the first embodiment shown in FIG. 1 except for the control system described above. refer.

  FIG. 22 is a block diagram illustrating a charging bias generator 1161 corresponding to the high voltage power supply device of the present invention.

  As shown in the figure, the charging bias generator 1161 corresponds to cyan (C), magenta (M), yellow (Y), black (K), and high voltage generators 1216C, 1216M, 1216Y, 1216K having the same configuration. (If there is no need to distinguish between them, they may be simply referred to as a high voltage generator 1216), and the generated high voltage DC voltage is applied to the charging rollers 14C, 14M, 14Y, and 14K as a charging bias voltage. It is configured.

  Next, a circuit configuration of the high voltage generation unit 1216 will be described. For this reason, only the high-pressure generator 1216M of magenta (M) is shown as an example in FIG. 23 together with the printer engine controller 1153, the signal distributor 1250, etc., and their configurations will be described below. In FIG. 23, the same components as those in FIG. The printer engine control unit 1153 outputs the piezoelectric transformer drive pulse 219 to the signal distribution unit 1250 and communicates with the charging bias generation unit 1161 using the serial communication signal 202.

  The signal distribution unit 1250 has a configuration in which the first-stage transistor 317 of the piezoelectric transformer drive circuit 210 of the high-voltage generation unit 216 of the first embodiment shown in FIG. 4 is moved, and the piezoelectric transformer drive pulse from the printer engine control unit 1153. Is input, and the four-stage piezoelectric transformer drive circuit 1210 in the subsequent stage is output so as to be driven simultaneously. For this reason, the resistance value of the resistor 1318 is changed to a lower value here than the resistor 318 of the first embodiment. In FIG. 23, only the (M) system is connected to the subsequent stage of the signal distribution unit 1250, but actually four systems are connected.

  The piezoelectric transformer drive circuit 1210M has a configuration excluding the first-stage transistor 317 with respect to the piezoelectric transformer drive circuit 210 of the high voltage generator 216 of the first embodiment shown in FIG. It is connected to the output of 1250 and operates in the same manner as the piezoelectric transformer drive circuit 210 of the first embodiment. Since the rectifier circuit 1212M rectifies to a negative bias, the diodes 1326 and 1327 are arranged so that the polarities are opposite to those of the diodes 326 and 327 of the rectifier circuit 212M of the first embodiment shown in FIG. Output the output voltage. This high output voltage is applied as a charging bias voltage to the rotating shaft of the charging roller 14 as an output load.

  The output voltage conversion circuit 1213 divides the negative high output voltage into a low voltage, and further outputs a low voltage feedback voltage signal 230 that is shifted so as to change between 0 and + 3.3V. Here, the negative high voltage output voltage (charging bias voltage) is different from the high voltage output voltage (transfer bias voltage) of the first embodiment in the absolute value level (usually small), so that the voltage dividing resistors 1330 and 1331 The resistance value is also different from the resistance value of the voltage dividing resistors 330 and 331 of the output voltage conversion circuit 213M of the first embodiment shown in FIG. The resistor 1332 is connected to the ground so that the output of the DC-DC converter 209M becomes 0V when the DAC set value of the DAC 205 is FFhex (3.3V at the output) when the output is off.

  The feedback control circuit 1214 performs negative feedback control on the output so that the reference voltage signal 221 output from the DAC 205 is equal to the low voltage feedback voltage signal 230. Here, since the directivity of the feedback voltage signal 230 is opposite to that of the first embodiment, the input to the operational amplifier 308 is opposite to that of the feedback control circuit of the first embodiment.

  Therefore, the high voltage generation unit 1216M here outputs a negative high voltage output voltage whose absolute value increases from 0V as the DAC setting value decreases from FFhex (3.3V in output), and the DAC setting value is 00hex ( When the output is 0 V), the output high voltage output voltage is set to the negative maximum voltage. The maximum output voltage is determined by the values of the voltage dividing resistors 1330 and 1331. Here, as will be described later, the maximum output voltage is set to be about −1500 V, and the amount of change in the DAC set value and the amount of change in the high-voltage output voltage during this period. Is proportional.

  FIG. 24 is a block diagram in which the configuration of the engine control LSI 1450 in the printer engine control unit 1153 shown in FIG.

  The engine control LSI 1450 includes, for example, a memory 401 constituting the ASIC 203 of the first embodiment shown in FIG. 5 in addition to the printer engine control circuit 1451 corresponding to the function of the printer engine control unit 153 of the first embodiment shown in FIG. A memory 1401, a calculator 1402, and a pulse output generator 1403 corresponding to the calculator 402 and the pulse output generator 403 are included. However, in the first embodiment, the memory 401, the arithmetic unit 402, and the pulse output generation unit 403 are configured to correspond to four systems, whereas in the present embodiment, the memory 1401, the arithmetic unit 1402, The pulse output generation unit 1403 is formed corresponding to one system.

  The memory 1401 includes a division ratio setting value register 1404 and a division ratio correction value register 1405. The pulse output generation unit 1403 includes a 19-bit register 1406, an error holding register 1407, a 1 plus adder 1408, and a frequency division selector 1409. , A frequency divider 1410, and an output selector 1411. Since these descriptions are the same as the contents described in the description of the ASIC 203 of the first embodiment, the description here is omitted.

  The engine control LSI 1450 is mounted on a circuit board constituting the printer engine control unit 1153 and mounted on a multilayer glass epoxy board. Therefore, in the paper phenol single-sided substrate 1180 of this embodiment, there are few restrictions on the pin pitch, the package, and the like due to the mounting of the ASIC 203 as in the first embodiment.

  In the above configuration, the operation of the image forming apparatus according to the present embodiment will be described. With reference mainly to FIGS. 21 to 24, mainly focusing on differences from the operation of the image forming apparatus according to the first embodiment. While explaining. Here, the four systems of high voltage generators 1216 operate in the same manner upon receiving a common pulse signal from the signal distributor 1250, so here, the (M) system of high voltage generators 1216M (FIG. 23) is taken as an example. I will explain.

  The printer engine control unit 1153 reads from the E2PROM 204 the division ratio setting value and the division ratio correction value corresponding to the piezoelectric transformer driving frequency when generating the charging bias voltage, and step S601 and step S601 in the flowchart shown in FIG. According to the processing of S602, the frequency division ratio setting value register 1404 and the frequency division ratio correction value register 1405 in the LSI 1450 are set. The frequency division ratio setting value set here is 70000 hex, but the frequency division ratio correction value is a preset value as will be described later.

  Subsequently, the initial value FFhex (3.3 V at output) is set in the DAC 205. As described above, the high voltage generation unit 1216 here is a negative high voltage output voltage (here, a charging bias voltage) whose absolute value increases from 0 V as the DAC setting value decreases from FFhex (3.3 V in output). Is output. After the DAC output, that is, the reference voltage signal 221 is set to 3.3 V, the engine control LSI 1450 of the printer engine control unit 1153 sets the transfer bias instruction signal (ON signal) 1220 to “H” at a predetermined timing, and the signal distribution unit 1250. The output of the piezoelectric transformer drive pulse 219 is started. The piezoelectric transformer drive circuit 1210M receives the inverted pulse signal output from the signal distributor 1250, and drives the piezoelectric transformer 211M in the same manner as the piezoelectric transformer drive circuit 210 of the first embodiment.

  In the initial state where the DAC setting value is FFhex, the output of the DC-DC converter 209M is 0V as described above, and thus the negative high voltage output voltage (charging bias voltage) of the high voltage generator 1216M is also approximately 0V. However, when the reference voltage signal 221 that is the output voltage of the DAC 205 is set lower than 3.3 V, the output of the DC-DC converter 209M rises so that a negative high voltage output voltage (charging bias voltage) is output at a high voltage. become. The feedback control circuit 1214M performs feedback control on the output of the DC-DC converter 209M so that the reference voltage signal 221M output from the DAC 205 is equal to the low voltage feedback voltage signal 230M.

  As shown in FIG. 23, the negative bias high-voltage output voltage (in this case, the charging bias voltage) is divided into a low voltage by the voltage dividing resistor 1330 and the voltage dividing resistor 1331 of the output voltage conversion circuit 1213 and shifted to the plus side. And converted into a feedback voltage signal 230M that changes between 0 and + 3.3V. For example, when the negative bias high-voltage output voltage changes from 0V to a higher value in absolute value, the feedback signal 230M decreases from 3.3V in accordance with the change. Precisely, since it is pulled down by the resistor 1332 in the initial state, the voltage is slightly lower than 3.3V.

  The pull-down to 0V by the resistor 1332 is the same as the reason why the output voltage conversion circuit 213 (FIG. 4) of the first embodiment is pulled up to 3.3V by the resistor 332, that is, when the output is off, the DC-DC converter 209. This is to make the output of 0V become 0V. This is because if the output of the DC-DC converter is close to 24V in the initial state, an excessive overrun occurs when the high voltage generator 1216 is started up, and the level cannot be ignored particularly at a low output.

  As described above, in the high-voltage power supply device according to the present embodiment, when the DAC set value set by the printer engine control unit 1153 changes between FFhex and 0, the negative high-voltage output voltages of the four high-voltage generation units 1216 It operates so that (the charging bias voltage here) changes linearly from 0 to minus maximum volt (-1500 V).

  Here, a setting method of the division ratio correction value in the present embodiment will be described.

  FIG. 27 is a block diagram of a function tester 1500 for determining a frequency division ratio correction value. The main difference between the function tester 1500 and the function tester 500 described in the first embodiment is that it has the configuration of the engine control LSI 1450 (FIG. 24) and directly outputs a piezoelectric transformer drive pulse.

  In this embodiment, as shown in FIG. 22, the four high voltage generators 1216 are driven at the same drive frequency, and therefore the adjustment is made with the division ratio correction value so that the boost ratio averages of the four piezoelectric transformers are uniform. . The charging bias voltage is usually about −800 V to −1200 V, and the absolute value level is lower than that of the transfer bias. Therefore, with respect to the drive frequency deviation, the piezoelectric transformer 211 described in the first embodiment is used. When using a piezoelectric transformer having the same frequency characteristics, there is a margin.

  The microcomputer 1501 first performs the following processing as an initial setting, and stores digital data as a reference value.

A paper phenol single-sided board incorporating a reference piezoelectric transformer is prepared and connected to the function tester 1500, and digital data as a reference value is stored in the following procedure.
(1) The division ratio set value 70000 hex and the division ratio correction value 00000 are set in each memory of the engine control LSI 1450 of the function tester 1500, and the piezoelectric transformer is driven to operate the piezoelectric transformer.
(2) A digital average obtained by setting the DAC setting value so that the high output voltage (charging bias voltage) is −1500 V, stepping down the voltage at point A by the step-down circuit 1504, and digitally converting it by the A / D converter 1502 The value is stored in advance as a reference average value γ.

  In FIG. 26, the function tester 1500 tests the actually used paper phenol single-sided substrate 1180 (FIG. 21), refers to the reference average value γ, and corrects the frequency division ratio in the engine control LSI 1450 of the printer engine control unit 1153. 10 is a flowchart showing a procedure for determining a frequency division ratio correction value set in a value register 1405; A method for determining the frequency division ratio correction value will be described with reference to the flowchart.

  The actually used paper phenol single-sided substrate 1180 is connected to the function tester 1500, the division ratio setting value is set to 70000 hex, and the division ratio correction value is set to FC000 hex (complement) (step S701), and the piezoelectric transformer 211 is driven. Is started (step S702). The drive start is started by first setting the DAC set value so that the DAC output becomes a voltage opposite to the target voltage from 3.3 V after the piezoelectric transformer drive pulse is output from the function tester 1500.

  It is monitored whether a predetermined time, 200 msec, has elapsed since the start of driving (step S703). After 200 msec, each output average of the four DC-DC converters 209, that is, the location of the point A shown in FIG. Here, the voltage detection average value for (M) system only) is calculated, and further, the total average value of four systems (the digital average value obtained by stepping down by the step-down circuit 1504 and digitally converting by the A / D converter 1502) is calculated. (Step S704).

  It is determined whether or not the total average value is equal to or less than the reference average γ (step S705). If the total average value is larger than the reference average value γ (step S705: No), the boost ratio of the four piezoelectric transformers 211 is the boost of the reference piezoelectric transformer. In order to mean that the ratio is smaller than the ratio, 1 is added to the frequency division ratio correction, the drive frequency is lowered, the average of the boost ratios of the four piezoelectric transformers 211 is increased, and the boost ratio of the piezoelectric transformer is brought close to the reference (step S707). Return to step S704. Thereafter, the same processing is repeated until it is determined in step S705 that they are equal.

  Here, in this flow, the initial setting of the frequency division ratio correction value is started as FC000 hex. That is, the division ratio value added by the calculator 1402 at this time is 6C000 hex, and the drive frequency of the piezoelectric transformer drive pulse 219 is 113.778 kHz. Therefore, referring to the output characteristics of the piezoelectric transformer 211 shown in FIG. 12, the boost ratio starts from a sufficiently low boost ratio level compared to the boost ratio of the division ratio set value 70000 hex (corresponding to 109.7143 kHz) when the reference average value γ is measured. doing. Therefore, by repeating step S704, step S705, and step S707, the average of the boost ratios of the four systems of piezoelectric transformers 211 rises while moving the characteristic curve of FIG. 12 to the left, and the reference transformer eventually has the drive frequency 113. It coincides with the step-up ratio obtained at 7778 kHz (step S705: Yes).

  That is, when the division ratio setting value is 70000 hex, the division ratio correction value is set so that the boost ratio average of the four systems of piezoelectric transformers 211 matches the boost ratio of the reference piezoelectric transformer (division ratio setting value 70000 hex). Then, this division ratio correction value is recorded in the E2PROM 204 (FIG. 22).

  Note that the division ratio setting value (here 70000 hex (corresponding to 109.7143 kHz)) when the reference average value γ is measured is four piezoelectrics whose characteristics vary when obtaining the division ratio correction value by the flow of FIG. All of the transformers are set sufficiently higher than the resonance frequencies of the piezoelectric transformers so as not to exceed the resonance frequency. If either exceeds the resonance frequency, the step-up ratio changes to the lower one, and the flow cannot be processed normally.

  As described above, the division ratio correction value to be set in the division ratio correction value register 1405 of the engine control LSI 1450 is determined and set, so that the paper phenol single-sided board provided with the four piezoelectric transformers 211 whose characteristics vary. Each device to which 1180 is attached can be operated in a state where the average of the step-up ratio of the piezoelectric transformer of each device is set to a desired value.

  FIG. 28 is a configuration diagram showing a modification of the present embodiment.

  In this modification, the division ratio correction value determined by the function tester 1500 is processed using a bar code instead of being recorded in the E2PROM 204 of the paper phenol single-sided substrate 1180.

  In FIG. 28, when the function tester 1500 determines the division ratio correction value of the paper phenol single-sided substrate 1180, the function tester 1500 performs bar code printing of a predetermined character string on the bar code label 1602 by the bar code label printer 1601 instead of recording it in the E2PROM 204. The barcode label 1602 is attached to the corresponding paper phenol single-sided substrate 1180. The data storage device 1600 stores the character string printed on the barcode label 1602 in pairs with the determined division ratio correction value.

  On the other hand, in the production line in which the paper phenol single-sided substrate 1180 is mounted on the image forming apparatus 11, the image forming apparatus test device 1603 is attached to the paper phenol single-sided substrate 1180 to be mounted by the barcode reader 1604. And the division ratio correction value corresponding to the character string is read from the data storage device 1600. Then, the secured frequency division ratio correction value is set in the frequency division ratio correction value register 1405 of the printer engine control unit 1153 of the image forming apparatus 11 on which the paper phenol single-sided substrate 1180 is mounted.

  As described above, according to the image forming apparatus of the present embodiment, since the piezoelectric transformer driving frequency is fixedly set, the paper phenol single-sided substrate 1180 including the high-voltage generating unit 1216 is routed from another substrate by a cable or the like. Thus, even if the drive frequency signal is supplied, stable voltage control (hard to oscillate the circuit) becomes possible. Further, since the plurality of piezoelectric transformers are driven at the same drive frequency, it is possible to prevent the occurrence of low-frequency ripple or the like caused by output interference even if the transformers are arranged close to each other.

  In addition, by setting the division ratio correction value, each image forming apparatus to which the paper phenol single-sided substrate 1180 provided with the four piezoelectric transformers 211 having variations in characteristics is attached to the boost ratio of the four piezoelectric transformers of each apparatus. The average can be operated with the desired value.

  Although the present invention has been described as a high-voltage power supply device for a color tandem image forming apparatus, it can also be applied to a monochrome image forming apparatus and an intermediate transfer type image forming apparatus. Applicable.

DESCRIPTION OF SYMBOLS 11 Image forming apparatus, 12 Image forming unit, 13 Photosensitive drum, 14 Charging roller, 15 LED head, 16 Developing roller, 17 Transfer roller, 18 Toner supply roller, 19 Developing blade, 20 Toner cartridge, 21 Transfer unit, 21a Transfer Belt driving roller, 21b transfer belt driven roller, 22 hopping roller, 23 registration roller pair, 24 paper storage cassette, 25 paper detection sensor, 26 transfer belt, 28 fixing device, 29 paper stacker section, 30 recording paper, 31 paper guide, 32 belt cleaning blade, 33 belt cleaner container, 150 host interface unit, 151 command / image processing unit, 152 LED head interface unit, 153 printer engine control unit, 154 hopping module 155 Registration motor, 156 Belt motor, 157 Fixer motor, 158 Drum motor (K, Y, M, C), 159 Fixer heater, 161 Charging bias generator, 162 Development bias generator, 163 Transfer bias generator 165 Thermistor 180 Paper phenol single side substrate 203 ASIC 204 Non-volatile memory E2PROM 205 DAC 206 Operation clock oscillator 207 3.3 VLDO 209 DC-DC converter 210 Piezoelectric transformer drive circuit 211 Piezoelectric transformer 212 Circuit, 213 output voltage conversion circuit, 214 feedback control circuit, 216 high voltage generator, 301 capacitor, 302 capacitor, 303 crystal oscillator, 304 resistor, 305 resistor, 308 operational amplifier, 309 capacitor 310 resistor, 311 resistor, 312 resistor, 313 NPN transistor, 314 electrolytic capacitor, 315 resistor, 316 resistor, 317 NPN transistor, 318 resistor, 319 resistor, 320 resistor, 321 resistor, 322 NPN transistor, 323 FET, 324 autotransformer, 325 capacitor, 326 diode, 327 diode, 328 capacitor, 330 resistor, 331 resistor, 332 resistor, 333 resistor, 334 capacitor, 335 resistor, 336 capacitor, 401 memory, 402 calculator, 403 pulse output generation unit, 404 division ratio Setting value register, 405 dividing ratio correction value register, 406 19-bit register, 407 error holding register, 408 1 plus adder, 409 dividing selector, 410 Frequency divider, 411 output selector, 412 communication processing unit, 500 function tester, 501 microcomputer, 502 A / D converter, 503 constant voltage source, 504 step-down circuit, 505 3.3 VLDO, 1153 printer engine control unit, 1161 charging bias generation 1180 paper phenol single-sided board, 1210 piezoelectric transformer drive circuit, 1212 rectifier circuit, 1213 output voltage conversion circuit, 1214 feedback control circuit, 1216 high voltage generation unit, 1250 signal distribution unit, 1318 resistor, 1326 diode, 1327 diode, 1330 minutes Voltage resistance, 1331 Voltage division resistance, 1332 resistance, 1401 Memory, 1402 Operation unit, 1403 Pulse output generation unit, 1404 Frequency division ratio setting value register, 1405 Frequency division ratio correction value register, 1406 1 Bit register, 1407 error holding register, 1408 1 plus adder, 1409 frequency divider selector, 1410 frequency divider, 1411 output selector, 1450 engine control LSI, 1451 printer engine control circuit, 1500 function tester, 1501 microcomputer, 1502 A / D Converter, 1503 constant voltage source, 1504 step-down circuit, 1505 3.3 VLDO, 1600 data storage device, 1601 barcode label printer, 1602 barcode label, 1603 image forming apparatus testing device, 1604 barcode reader.

Claims (13)

Frequency dividing means for generating a drive pulse obtained by dividing the operation clock signal based on the input frequency dividing value;
A division value holding means for holding a set division value;
Correction value holding means for holding a correction value for correcting the set frequency dividing value;
A frequency division value setting means for outputting a frequency division value obtained by correcting the set frequency division value with the correction value to the frequency division means;
A piezoelectric transformer that outputs a high voltage corresponding to the frequency and level of the switching signal input to the primary side from the secondary side;
A DC-DC converter that outputs a variable voltage;
Piezoelectric transformer driving means for outputting the switching signal having the frequency based on the driving pulse and the level based on the variable voltage to the piezoelectric transformer;
Rectifying means for rectifying the high voltage to form a high output voltage;
Output conversion means for converting the high output voltage into a feedback voltage signal obtained by stepping down the high output voltage;
Feedback control means for controlling the variable voltage of the DC-DC converter so that the high-voltage output voltage approaches the target value based on the setting signal for determining the target value of the high output voltage and the feedback power signal. And a high-voltage power supply device. The frequency dividing value setting means outputs the N-bit frequency dividing value to the frequency dividing means,
The dividing means alternatively selects a selected divided value corresponding to the upper S (S <N) bits of the divided value of N bits and a 1 plus selected divided value obtained by adding 1 to the selected divided value. The high-voltage power supply apparatus according to claim 1, wherein the drive pulse is generated by sequentially dividing the frequency based on the frequency division value of the selected S bit.   3. The high-voltage power supply apparatus according to claim 2, wherein the ratio to be selected is set in accordance with a value of a lower bit of the divided value of N bits.   The high-voltage power supply device according to claim 1, wherein the correction value is stored in a nonvolatile memory.   The piezoelectric transformer, the DC-DC converter, the piezoelectric transformer driving means, the rectifying means, the output converting means, and the feedback control means are provided in a plurality of systems, and the drive pulse is commonly applied to the piezoelectric transformer driving means of each system. The high-voltage power supply device according to any one of claims 1 to 4, wherein   5. The high-voltage power supply device according to claim 1, wherein the divided value output from the divided value setting unit is variable according to a target value of the high output voltage. Frequency dividing means for generating a drive pulse obtained by dividing the operation clock signal based on the input frequency dividing value;
A division value holding means for holding a set division value;
Correction value holding means for holding a correction value for correcting the set frequency dividing value;
A frequency dividing value setting means for outputting a frequency dividing value obtained by correcting the set frequency dividing value with the correction value to the frequency dividing means;
A piezoelectric transformer that outputs a high voltage corresponding to the frequency and level of the switching signal input to the primary side from the secondary side;
A DC-DC converter that outputs a variable voltage;
Piezoelectric transformer driving means for outputting the switching signal having the frequency based on the driving pulse and the level based on the variable voltage to the piezoelectric transformer;
Rectifying means for rectifying the high voltage to form a high output voltage;
Output conversion means for converting the high output voltage into a feedback voltage signal obtained by stepping down the high output voltage;
Feedback control means for controlling the variable voltage of the DC-DC converter so that the high-voltage output voltage approaches the target value based on the setting signal for determining the target value of the high output voltage and the feedback power signal. And an image forming apparatus.   The dividing means, the divided value holding means, the correction value holding means, and the divided value setting means are held in an integrated circuit, and the piezoelectric transformer, the DC-DC converter, the piezoelectric transformer driving means, The rectifying means, the output converting means, and the feedback control means are provided on the same substrate, the correction value is set in the correction value holding means based on the stored information stored in the storage means belonging to the same substrate, and the drive pulse The image forming apparatus according to claim 7, wherein:   9. The image forming apparatus according to claim 8, wherein the integrated circuit is mounted on a multilayer substrate, and the same substrate is constituted by a single-layer paper phenol substrate.   The image forming apparatus according to claim 8, wherein the storage unit is a nonvolatile memory.   The image forming apparatus according to claim 8, wherein the storage unit is a barcode label, and a correction value corresponding to the barcode of the barcode label is set in the correction value holding unit. The frequency division value holding means holds the first and second set frequency division values,
The correction value holding means holds the first and second correction values,
When the target value of the high output voltage is larger than a predetermined value, the frequency division value setting means outputs a second frequency division value obtained by correcting the second setting frequency division value with the second correction value. When the target value of the high output voltage is less than or equal to a predetermined value, a first frequency division value obtained by correcting the first set frequency division value with the first correction value is output. The image forming apparatus according to claim 7. The first correction value is set such that a step-up ratio when the piezoelectric transformer is driven by a drive pulse divided based on the first division value is a predetermined first step-up ratio, The second correction value is set so that the step-up ratio when the piezoelectric transformer is driven by a drive pulse divided based on the second divided value becomes a predetermined second step-up ratio. The image forming apparatus according to claim 12.

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