JP6031365B2 - Piezoelectric transformer driving apparatus and image forming apparatus - Google Patents

Description

  The present invention relates to a piezoelectric transformer driving device and an image forming apparatus.

  Conventionally, this type of apparatus is disclosed in Patent Document 1. In this device, a high-voltage control integrated circuit divides a clock to generate a plurality of channels of piezoelectric transformer drive frequencies, and drives the corresponding piezoelectric transformers with the generated piezoelectric transformer drive frequency signals, thereby positive and negative. Bias voltage is generated.

JP 2012-50282 A

  In the conventional technique, the high-voltage control integrated circuit is configured to communicate with the printer engine control unit and output drive frequency signals of a plurality of channels. Since the piezoelectric transformer drive frequency is 100 kHz or more, when drive frequency signals are output from pins adjacent to each other, there is an effect due to crosstalk or mutual interference, which tends to increase high voltage output ripple. When the output ripple increases, a stripe pattern with a ripple period may occur in the printed image. Therefore, measures have been taken such as pin assignment such as setting the adjacent pins to ground so that the drive frequency output pins of the integrated circuit are not adjacent to each other. However, when a part of the piezoelectric transformer control unit is formed in the same integrated circuit as the printer engine control unit, it is difficult to increase the number of pins because the printer engine control unit has a large number of signal inputs and outputs. There is a problem. Furthermore, for example, when the piezoelectric transformer drive signal is shielded by being surrounded by the ground, there is a problem that the number of pins of the package is further increased.

Pressure electric transformer driving apparatus of the present invention,
A plurality of piezoelectric transformers;
A plurality of piezoelectric transformer drive circuits;
An integrated circuit that generates a plurality of drive frequency signals;
The driving frequency signal is assigned to only one of the even-numbered pins and the odd-numbered pins among the consecutive pins of the integrated circuit,
Pin positioned between pins together for outputting said drive frequency signal, the output of the driving frequency signal, connected to the power source, and used for purposes other than connection to the ground,
A pin for outputting a pulse width modulation signal having a frequency lower than the frequency of the driving frequency signal is arranged between the pins for outputting the driving frequency signal,
It characterized in that the pulse width modulation device signals is used to control the voltage output from the piezoelectric transformer.

  According to the present invention, in the configuration in which the piezoelectric transformer control integrated circuit is integrated with the printer engine control integrated circuit, the interference between adjacent pins of the drive frequency signal output during the image forming operation is eliminated, and the output ripple is reduced. Can be reduced.

1 is a diagram illustrating a configuration of an image forming apparatus according to a first embodiment of the present invention. FIG. 2 is a block diagram showing a configuration of a control system according to Embodiment 1 of the present invention used in the image forming apparatus of FIG. 1. FIG. 3 is a block diagram showing a configuration of a circuit formed in a printer engine control board / high voltage board 301 in the control system of FIG. 2. FIG. 4 is a wiring diagram illustrating a circuit configuration of an oscillation circuit 331 in FIG. 3. FIG. 4 is a wiring diagram showing a circuit configuration of a charging bias generator 153 and an output voltage converter 319 in FIG. 3. FIG. 4 is a wiring diagram showing a circuit configuration of a primary transfer bias generator 151 in FIG. 3. FIG. 4 is a wiring diagram illustrating a circuit configuration of a secondary transfer bias generation unit 150 in FIG. 3. It is a figure which shows an example of arrangement | positioning of the main circuit components on the printer engine control board and high voltage board | substrate 301 in Embodiment 1 of this invention. It is an enlarged view of the part shown with the code | symbol E9 of FIG. FIG. 4 is a block diagram illustrating a part that generates one drive frequency signal in the printer engine control unit 253 of FIG. 3. FIG. 11 is a block diagram illustrating a configuration example of an error holding register 507 in FIG. 10. 11 is a table showing values of respective parts during operation of the fractional-N divider 530 of FIG. 10. (A) And (b) is a figure which shows the relationship of the output with respect to a drive frequency of the output of a piezoelectric transformer and a rectifier circuit. It is a flowchart which shows the operation | movement for the production | generation of the drive frequency signal used for generation | occurrence | production of a positive bias voltage. It is a flowchart which shows the operation | movement for the production | generation of the drive frequency signal used for generation | occurrence | production of a negative bias voltage. 6 is a timing chart for explaining the output timing of each bias voltage in the image forming apparatus. It is a figure which shows the other example of arrangement | positioning of the main circuit components on the printer engine control board and high voltage | pressure board | substrate 301 in Embodiment 1 of this invention. It is an enlarged view of the part shown with the code | symbol E18 of FIG. It is a figure which shows the structure of the image forming apparatus of Embodiment 2 of this invention. It is a figure which shows an example of arrangement | positioning of the main circuit components on the printer engine control board and high voltage | pressure board | substrate 301 in Embodiment 2 of this invention. It is a block diagram which shows the structure of the control system of Embodiment 3 of this invention used for the image forming apparatus of FIG. FIG. 22 is a block diagram showing a configuration of a circuit formed in a printer engine control board / high voltage board 301 in the control system of FIG. 21. FIG. 23 is a wiring diagram illustrating circuit configurations of a charging bias generator 1153 and an output voltage conversion unit 319 in FIG. 22. FIG. 23 is a wiring diagram showing a circuit configuration of a primary transfer bias generator 1151 in FIG. 22. FIG. 23 is a wiring diagram illustrating a circuit configuration of a secondary transfer bias generator 1150 of FIG. 22. (A) And (b) is a figure which shows the change of the output voltage with respect to a pulse width modulation signal while showing the relationship of the output with respect to a drive frequency of the output of a piezoelectric transformer and a rectifier circuit. It is a figure which shows an example of arrangement | positioning of the main circuit components on the printer engine control board and high voltage | pressure board | substrate 301 in Embodiment 3 of this invention. It is an enlarged view of the part shown with the code | symbol E28 of FIG. FIG. 10 is a block diagram illustrating a part of the printer engine control unit 1253 that generates one drive frequency signal and one pulse width modulation signal.

Embodiment 1 FIG.
FIG. 1 shows a configuration example of a color electrophotographic image forming apparatus.
The illustrated color electrophotographic image forming apparatus 101 is an intermediate transfer type four-cycle color image forming apparatus, and the developing devices 102C, 102M, 102Y, and 102K are detachably mounted on the rotary developing device support 111 integrally with a toner container. The

The photosensitive drum 132 is uniformly charged by the charging roller 136.
A latent image is formed on the charged photosensitive drum 132 by the light emission of the LED head 103, and the rotary developing device support 111 rotates in the direction of the arrow DOR in the order of the developing devices 102C, 102M, 102Y, and 102K. A toner image is formed on the photosensitive drum 132 that contacts the photosensitive drum 132 and rotates in the direction of the arrow DOQ.

  Each of the developing devices 102C, 102M, 102Y, and 102K has a toner container therein, and the supply rollers 133C, 133M, 133Y, and 133K supply the toner to the developing rollers 134C, 134M, 134Y, and 134K, and the developing blades 135C, 135M, and 135Y , 135K form a uniform toner layer on the surfaces of the developing rollers 134C, 134M, 134Y, 134K, and the toner image is selectively transferred to the photosensitive drum 132 by using the uniform toner layer. Formation (development) is performed.

  The cleaning blade 137 cleans the residual toner after the primary transfer, and the waste toner is accumulated in the waste toner container 138.

  The primary transfer roller 105 is arranged so that a bias can be applied to the transfer nip from the back surface of the intermediate transfer belt 108 conveyed in the direction of the arrow DOT.

  The transfer belt driving roller 106, the transfer belt driven roller 107, and the secondary transfer backup roller 120 stretch the intermediate transfer belt 108, and the secondary transfer roller 130 and the secondary transfer backup roller 120 with the intermediate transfer belt 108 in between. It is possible to transfer the toner onto the printing paper 115 that faces each other and passes between them. Before the sheet 115 passes, that is, when the three-color primary transfer images pass, the intermediate transfer belt 108 is separated.

  The paper cassette 113 is detachably attached to the image forming apparatus 101, and the paper 115 is stacked. The hopping roller 114 conveys the paper 115 as a transfer medium one by one from the paper cassette 113. A pair of registration rollers 116 and 117 conveys the paper 115 at a predetermined timing.

The fixing device 118 fixes the toner image on the paper 115 by heat and pressure. The sheet guide 119 discharges the sheet to the sheet discharge tray 121 face down.
The paper detection sensor 140 is a contact sensor or a non-contact optical sensor, and detects the passage of the paper 115.

The developing bias generator 152 supplies a negative bias to the developing rollers 134C, 134M, 134Y, and 134K and the supply rollers 133C, 133M, 133Y, and 133K.
The charging bias generator 153 supplies a negative bias to the charging roller 136.
The primary transfer bias generator 151 can supply a positive bias and a negative bias, and applies a positive bias to the primary transfer roller 105 when performing primary transfer and a negative bias when performing cleaning.
The secondary transfer bias generator 150 can also supply a positive bias and a negative bias. A positive bias is applied when performing secondary transfer, and a negative bias is applied to the secondary transfer roller 130 when performing cleaning. To do.

As described above, each bias generation unit is a high voltage generation circuit, and applies a high bias voltage to the rollers (136, 134, 133C, 105, and 130) that are rotating bodies.
A positive bias (first polarity voltage) is applied to the primary transfer roller 105 and the secondary transfer roller 130 during image formation, and a negative bias (second polarity voltage) during cleaning. ) Is applied.

FIG. 2 shows a control system in the image forming apparatus of FIG.
The host interface unit 250 transmits print data in a predetermined format described in PDL (page description language) or the like to the command / image processing unit 251.
The command / image processing unit 251 outputs bitmap format image data to the LED head interface unit 252.
The LED head interface unit 252 is controlled by the printer engine control unit 253 and outputs LED head drive pulses and the like to selectively cause the LEDs of the LED head 103 to emit light according to the bitmap format image data.

The printer engine control unit 253 is a one-chip integrated circuit formed in the printer engine control board / high-voltage board 301, and in the same board 301, the charging bias generation unit 153, the development bias generation unit 152, and the primary transfer bias. A generation unit 151 and a secondary transfer bias generation unit 150 are formed. The printer engine control unit 253 is also called an image forming apparatus control integrated circuit or an engine control integrated circuit.
The charging bias generation unit 153, the development bias generation unit 152, the primary transfer bias generation unit 151, and the secondary transfer bias generation unit 150 are circuits that generate a high voltage and supply it to each load as a bias voltage.

  The printer engine control unit 253 is configured by a one-chip integrated circuit, and includes a piezoelectric transformer control unit 262 and a storage unit 267 configured by a nonvolatile memory or the like.

The charging bias generator 153 generates a negative bias, applies it to the charging roller 136 that charges the photosensitive drum 132, and supplies it to the developing bias generator 152.
The developing bias generator 152 DC-DC converts the negative bias supplied from the charging bias generator 153 into a negative voltage having a smaller absolute value, and develops it as a developing bias via the contact of the developing device support 111. Applied to the devices 102K, 102Y, 102M, and 102C. In other words, the negative bias is sequentially applied to the developing devices 102K, 102Y, 102M, and 102C by the action of the contact point, and the negative bias is applied only to one developing device at each time point.

  The secondary transfer bias generator 150 can apply a positive / negative secondary transfer bias to the secondary transfer roller 130, and the primary transfer bias generator 151 applies a positive / negative primary transfer bias to the primary transfer roller 105. Is possible.

  As described above, the sheet detection sensor 140 detects the passage of the sheet, and is used to adjust the generation timing of the secondary transfer bias.

  The printer engine control unit 253 rotates a hopping motor 254 that drives the hopping roller 114, a registration motor 255 that rotates the registration rollers 116 and 117, a belt driving motor 256 that rotates the transfer belt driving roller 106, and a roller of the fixing device 118. The fixing device motor 257, the drum motor 258 for rotating the photosensitive drum 132, the rotation developing device motor 259 for rotating the developing device support 111, and the secondary transfer roller 130 are operated to bring the paper 115 into contact with the intermediate transfer belt 108. The secondary transfer roller solenoid 260 to be driven is driven to operate in a direction indicated by an arrow DOS at a predetermined timing.

  The temperature of the fixing device heater 261 is controlled according to the detection value of the thermistor 266. The temperature / humidity sensor 290 detects the operating environment temperature and humidity of the image forming apparatus.

  3 shows in more detail the configuration of the circuit formed in the printer engine control board / high-voltage board 301, and FIGS. 4 to 7 show the circuit configuration of each part of the circuit of FIG. In the circuit shown in FIG. 3, the piezoelectric transformer driving device is configured by a portion other than the output load.

  The power supplies 302 and 303 are supplied with power from a low-voltage power supply that converts AC 100 to 230 V (not shown) into DC voltage. The 3.3V power supply 302 is connected to the printer engine control unit 253, the output voltage detection means 320, 322, and 324, and the output voltage conversion means 319. The 24V power supply 303 is a piezoelectric transformer drive circuit 304, 305, 306. , 307, and 308, and the output voltage conversion means 319. The output voltage conversion means 319 constitutes the developing bias generator 152.

  For example, as illustrated in FIG. 4, the oscillation circuit 331 includes a crystal resonator 402, capacitors 401 and 403, and resistors 404 and 410. The first and second electrodes of the crystal resonator 402 include capacitors 401 and 403, respectively. The two resistors 410 and 404 are connected in series between the first and second electrodes, the first electrode is connected to the terminal 331a, and the connection point between the resistor 410 and the resistor 404 is connected to the terminal 331b. It is connected.

The terminals 331a and 331b of the oscillation circuit 331 are connected to the ports OSC_IN and OSC_OUT of the printer engine control unit 253, respectively. The clock signal generation unit 330 is configured together with the inverter 411 in the printer engine control unit 253. The means 330 generates a clock signal CLK.
The oscillation frequency is, for example, 50 MHz, but may be other values, for example, 100 MHz, 200 MHz, or the like.

  Various circuits in the printer engine control unit 253 operate in synchronization with the clock signal CLK generated by the clock signal generation unit 330.

The piezoelectric transformer control unit 262 includes a synchronous clock circuit (synchronous circuit), and drive frequency signals (drive pulse signals) DFS1 to DFS5 obtained by dividing the 50 MHz clock generated by the clock signal generation unit 330. Are output from the output ports OUT1 to OUT5.
The output voltage of each of the output ports OUT1 to OUT5 is set to the H level when no high voltage output is generated from the corresponding bias generator (when the high voltage output is off).

For example, when the charging bias generator 153 generates a bias voltage, a driving frequency signal (a driving pulse having a frequency obtained by dividing the clock CLK) DFS1 is output from the output port OUT1, and the charging bias generator 153 is output. When the output (high voltage output) is turned off, the voltage of the output port OUT1 is set to the H level.
Similarly, when generating a positive bias voltage in the primary transfer bias generator 151, the drive frequency signal DFS2 is output from the output port OUT2, and when turning off the positive bias output of the primary transfer bias generator 151, The voltage of the output port OUT2 is set to H level.
Similarly, when the negative bias voltage is generated in the primary transfer bias generator 151, the drive frequency signal DFS3 is output from the output port OUT3, and when the negative bias output of the primary transfer bias generator 151 is turned off, The voltage of the output port OUT3 is set to H level.
Similarly, when generating a positive bias voltage in the secondary transfer bias generator 150, the drive frequency signal DFS4 is output from the output port OUT4, and when turning off the positive bias output of the secondary transfer bias generator 150, The voltage of the output port OUT4 is set to H level.
Similarly, when the negative bias voltage is generated in the secondary transfer bias generator 150, the drive frequency signal DFS5 is output from the output port OUT5, and when the negative bias output of the secondary transfer bias generator 150 is turned off, The voltage of the output port OUT5 is set to H level.

FIG. 5 shows specific circuit configurations of the charging bias generator 153 and the output voltage conversion means 319. As shown in FIG. 3 and FIG.
The charging bias generation unit 153 receives the drive frequency signal DFS1 from the port OUT1 of the piezoelectric transformer control unit 262, generates a charging bias based on the driving frequency signal DFS1, and supplies it to the charging roller as the load 136.
The charging bias generator 153 includes a piezoelectric transformer drive circuit 304, a piezoelectric transformer 309, a negative bias rectifier circuit (negative rectifier circuit) 314, and an output voltage detector 320.
The voltage VB1 detected by the output voltage detector 320 of the charging bias generator 153 is fed back to the port ADC1 of the printer engine controller 253.

The piezoelectric transformer drive circuit 304 includes a gate drive circuit 408, an N-channel power MOSFET 424, an inductor 423, and a capacitor 425, as shown in FIG. The gate drive circuit 408 includes resistors 419, 420, and 421 and an NPN transistor 422.
One end of the resistor 421 is connected to the 24V power source, the other end of the resistor 421 is connected to the collector of the NPN transistor 422 and the gate of the MOSFET 424, one end of the inductor 423 is connected to the 24V power source, and the other end of the inductor 423 is The drain of the MOSFET 424 is connected.
The inductor 423, the capacitor 425, and the N-channel power MOSFET 424 constitute a resonance circuit, and drives the primary side of the piezoelectric transformer 309. For driving, the drain and source of the MOSFET 424 are connected to the first and second electrodes 309a and 309b of the piezoelectric transformer 309 via the output terminals 304b and 304c.
The secondary electrode 309 c of the piezoelectric transformer 309 is connected to the negative bias rectifier circuit 314.
As shown in FIG. 5, the negative bias rectifier circuit 314 includes a high voltage rectifier diode 426 whose anode is connected to the output electrode 309c, a high voltage rectifier diode 427 whose cathode is connected to the output electrode 309c, and the anode of the diode 427. A high-voltage capacitor 428 connected between the cathode of the diode 426 is included, and a negative bias is output from the anode of the diode 427.

  The input terminal 304 a of the piezoelectric transformer driving circuit 304 is connected to the output port OUT 1 of the piezoelectric transformer control unit 262. When the high-voltage output (negative bias voltage output) is turned off, an H level signal is supplied from the port OUT1, so that the NPN transistor 422 is turned on. As a result, the gate voltage of the N-channel power MOSFET 424 becomes L level, and the piezoelectric The transformer driving circuit 304 is turned off.

When the high voltage output is turned on, the drive frequency signal is output from the port OUT1, the NPN transistor 422 is switched, the level of the drive frequency signal is converted from the 3.3V range to the 24V range, and the N-channel power MOSFET 424 is switched.
A half-wave sine wave voltage is applied to the primary side of the piezoelectric transformer 309 by a resonance circuit including the inductor 423, the capacitor 425, and the piezoelectric transformer 309.
As a result, a boosted AC output is generated on the secondary side of the piezoelectric transformer 309.

  As shown in FIG. 5, the output voltage detection means 320 includes a resistor 429 having one end connected to the output of the negative bias rectifier circuit 314 and a resistor 430 having one end connected to the 3.3V power supply. The connection point of the resistor 430 is connected to the port ADC1, and the output voltage of the negative bias rectifier circuit 314 is divided by the resistor 429 and the resistor 430 and fed back to the port ADC1 as the detection voltage VB1. For example, when the resistance 429 is 100 MΩ and the resistance 430 is 200 kΩ, when the charging bias is −1000 V, the detection voltage VB1 obtained as a result of voltage division by the resistors 429 and 430 is 1.297 V.

  As shown in FIG. 5, the output voltage conversion means 319 receives a negative bias output from the negative bias rectifier circuit 314 of the charging bias generator 153, and further outputs a pulse width modulation signal PWS0 from the output port PWM0 of the piezoelectric transformer controller 262. The developing bias is generated and supplied to the developing roller (as one of 134C, 134M, 134Y, and 134K) and the supply roller (as one of 133C, 133M, 133Y, and 133Y) as the load 133. . This pulse width modulation signal has a relatively low frequency of 10 to 20 kHz, that is, a frequency lower than that of the driving frequency signals DFS1 to DFS5.

The output voltage conversion means 319 includes resistors 431, 432, 433, 436, 437, 439, 440, 441, 444, an operational amplifier (operational amplifier) 434, a capacitor 435, PNP transistors 438, 442, and a Zener diode 443. .
The RC filter including the resistor 431 and the capacitor 432 smoothes the pulse width modulation signal output from the port PWM0. The smoothed signal is applied to the non-inverting input terminal (+) of the operational amplifier 434. This applied voltage is in the range of 0 to 3.3V.
On the other hand, the voltage applied to the load 133 is divided by the resistors 433 and 439 and applied to the inverting input terminal (−) of the operational amplifier 434. The inverting input terminal (−) is connected to a 3.3 V power source 302 via a resistor 433.

The operational amplifier 434 and the capacitor 435 constitute a difference integration circuit that integrates the difference between the two inputs so that the difference becomes zero (so that the two inputs are equal to each other).
The base current of the PNP transistor 438 is passed,
As a result, the base current of the NPN transistor 442 is controlled by the collector current of the PNP transistor 438 that flows. As a result, the collector current of the NPN transistor 442 flows to the resistor 441, and the voltage applied to the load 133 depends on the magnitude of the current flowing to the resistor 441. Be controlled.
The resistors 441, 440, 436, and 437, the PNP transistor 438, and the NPN transistor 442 constitute a step-down DC-DC converter (step-down circuit).

Zener diode 443 and resistor 444 constitute a step-down DC-DC converter (step-down circuit).
A bias voltage having a predetermined potential difference with respect to the bias voltage to the load 133 is applied to the load 134 by the Zener diode 443.

  The resistor 444 is inserted to stabilize the potential on the cathode side of the Zener diode 443, that is, to keep the potential constant regardless of the load.

FIG. 6 shows a specific circuit configuration of the primary transfer bias generator 151.
As shown in FIGS. 3 and 6, the primary transfer bias generator 151 receives the drive frequency signals DFS2 and DFS3 from the ports OUT2 and OUT3 of the piezoelectric transformer controller 262, and generates the primary transfer bias based on these signals. Then, it is supplied to the primary transfer roller as the load 105.
The primary transfer bias generator 151 includes piezoelectric transformer drive circuits 305 and 306, piezoelectric transformers 310 and 311, a positive bias rectifier circuit (positive rectifier circuit) 315, a negative bias rectifier circuit (negative rectifier circuit) 316, and a positive bias. An output voltage detecting means 321 for detecting, and an output voltage detecting means 322 for detecting a negative bias are included.

As shown in FIG. 6, each of the piezoelectric transformer drive circuits 305 and 306 is configured in the same manner as the piezoelectric transformer drive circuit 304 of the charging bias generator 153 and operates in the same manner.
Similarly, each of the rectifier circuits 315 and 316 is configured similarly to the rectifier circuit 314 of the charging bias generator 153, and the positive bias rectifier circuit 315 is connected to the secondary side of the piezoelectric transformer 310 and the negative bias rectifier circuit 316. Is connected to the secondary side of the piezoelectric transformer 311. However, the rectifier circuit 315 generates a positive bias, and the direction of the diode is reversed. The anode of the diode 452 of the rectifier circuit 315 is connected to the output node A1 of the rectifier circuit 316, and the node A1 is connected to the output node B1 of the rectifier circuit 315 via the resistor 456.

  The positive bias rectifier circuit 315 and the negative bias rectifier circuit 316 are connected to each other. That is, the output of the positive bias rectifier circuit 315 is applied to the load 105 via the node B1, and the output of the negative bias rectifier circuit 316 is applied to the load 105 via the resistor 456 and the node B1.

Each of the output voltage detection means 321 and 322 is configured in the same manner as the output voltage detection means 320 of the charging bias generator 153, and the voltages VB2 and VB3 detected by the output voltage detection means 321 and 322 are the printers. It is fed back to the detection voltage input ports ADC2 and ADC3 of the engine control unit 253.
However, the output voltage detection means 321 is connected to the ground instead of 3.3V. That is, as shown in FIG. 6, the output voltage detecting means 321 includes a resistor 457 having one end connected to the output of the positive bias rectifier circuit 315 and a resistor 458 having one end connected to the ground. Is connected to the port ADC2, and the output voltage of the positive bias rectifier circuit 315 is divided by the resistors 457 and 458 and fed back to the port ADC2 as the detection voltage VB2.

  On the other hand, as shown in FIG. 6, the output voltage detection means 322 includes a resistor 469 having one end connected to the output of the negative bias rectifier circuit 316 and a resistor 470 having one end connected to a power supply of 3.3V. The connection point between the resistor 470 and the resistor 470 is connected to the port ADC3, and the output voltage of the negative bias rectifier circuit 316 is divided by the resistor 469 and the resistor 470 and fed back to the port ADC3 as the detection voltage VB3.

  As shown in FIG. 6, at the time of positive bias output, the potential of the node B1 is divided by the resistor 457 and the resistor 458, and is applied to the detection voltage input port ADC2 as the detection voltage VB2.

The output current of the positive bias rectifier circuit 315 is supplied from the 3.3V power supply 302 via the resistor 470 and the resistor 469. Therefore, at the time of positive bias output, the node A1 becomes a negative voltage.
At the time of negative bias output, the potential of the node A1 is divided by the resistors 469 and 470 and applied to the detection voltage input port ADC3 as the detection voltage VB3.

FIG. 7 shows a specific circuit configuration of the secondary transfer bias generator 150.
As shown in FIGS. 3 and 7, the secondary transfer bias generator 150 receives the drive frequency signals DFS4 and DFS5 from the ports OUT4 and OUT5 of the piezoelectric transformer controller 262, and generates a secondary transfer bias based on them. To the secondary transfer roller as the load 130.
The secondary transfer bias generator 150 includes piezoelectric transformer drive circuits 307 and 308, piezoelectric transformers 312 and 313, a positive bias rectifier circuit (positive rectifier circuit) 317, a negative bias rectifier circuit (negative rectifier circuit) 318, and a positive bias. An output voltage detecting unit 323 for detecting, and an output voltage detecting unit 324 for detecting a negative bias are included.

The secondary transfer bias generator 150 has the same configuration as the primary transfer bias generator 151 and operates in the same manner.
That is, as shown in FIG. 7, each of the piezoelectric transformer drive circuits 307 and 308 is configured in the same manner as the piezoelectric transformer drive circuit 304 of the charging bias generator 153 and operates in the same manner.
Similarly, each of the rectifier circuits 317 and 318 is configured similarly to the rectifier circuit 314 of the charging bias generator 153, and the positive bias rectifier circuit 317 is connected to the secondary side of the piezoelectric transformer 312, and the negative bias rectifier circuit 318. Is connected to the secondary side of the piezoelectric transformer 313. However, the rectifier circuit 317 generates a positive bias, and the direction of the diode is reversed. The anode of the diode 478 of the rectifier circuit 317 is connected to the output node A2 of the rectifier circuit 318, and the node A2 is connected to the output node B2 of the rectifier circuit 317 via the resistor 482.

  The positive bias rectifier circuit 317 and the negative bias rectifier circuit 318 are connected to each other. That is, the output of the positive bias rectifier circuit 317 is applied to the load 130 via the node B2, and the output of the negative bias rectifier circuit 318 is applied to the load 130 via the resistor 482 and the node B2.

Each of the output voltage detection means 323 and 324 is configured in the same manner as the output voltage detection means 320 of the charging bias generator 153, and the voltages VB4 and VB5 detected by the output voltage detection means 323 and 324 are the printers. It is fed back to the detection voltage input ports ADC4 and ADC5 of the engine control unit 253.
However, the output voltage detection means 323 is connected to the ground instead of 3.3V. That is, as shown in FIG. 7, the output voltage detection means 323 includes a resistor 482 having one end connected to the output of the positive bias rectifier circuit 317 and a resistor 483 having one end connected to the ground, and the resistor 482 and the resistor 483. Is connected to the port ADC4, and the output voltage of the positive bias rectifier circuit 317 is divided by the resistor 482 and the resistor 483 and fed back to the port ADC4 as the detection voltage VB4.

  On the other hand, as shown in FIG. 7, the output voltage detecting means 324 includes a resistor 494 having one end connected to the output of the negative bias rectifier circuit 318 and a resistor 495 having one end connected to the power supply of 3.3V. The connection point of 494 and the resistor 495 is connected to the port ADC5, and the output voltage of the negative bias rectifier circuit 318 is divided by the resistor 494 and the resistor 495 and fed back to the port ADC5 as the detection voltage VB5.

  As shown in FIG. 7, at the time of positive bias output, the potential of the node B2 is divided by the resistor 482 and the resistor 483 and applied to the detection voltage input port ADC4 as the detection voltage VB4.

The output current of the positive bias rectifier circuit 317 is supplied from the 3.3V power supply 302 via the resistor 495 and the resistor 494. Therefore, at the time of positive bias output, the node A2 becomes a negative voltage.
At the time of negative bias output, the potential of the node A2 is divided by the resistors 495 and 494 and applied to the detection voltage input port ADC5 as the detection voltage VB5.

  As described above, the secondary transfer bias generation unit 150 and the primary transfer bias generation unit 151 are configured in the same manner, but the values of the resistance, the inductor, and the like are not necessarily the same according to the respective output voltages. Each is appropriately selected.

  FIG. 8 shows an arrangement of main circuit components on the printer engine control board / high-voltage board 301. As will be described later, during image formation, the piezoelectric transformers 309, 310, and 312 may operate simultaneously, while the piezoelectric transformers 311 and 313 do not operate. By arranging the piezoelectric transformers 311 and 313 that do not operate during the image forming operation between the piezoelectric transformers 309, 310, and 312 that may operate during the image forming operation, adjacent piezoelectric transformers do not operate simultaneously. The bias generator including the adjacent piezoelectric transformers does not perform high voltage generation at the same time.

  The integrated circuit constituting the printer engine control unit 253 has a plurality of pins of numbers # 1 to # 120 in the illustrated example. Among them, for example, as shown in FIG. 9, pins # 55 to # 60 are pins of output ports PWM0, OUT1, OUT3, OUT2, OUT5, OUT4, and signals PWS0, DFS1, DFS3, output from these ports, respectively. It is assigned to DFS2, DFS5, and DFS4, and constitutes an output unit for these signals.

  In this way, the pins # 55 to # 60 for outputting the signals PWS0 and DFS1 to DFS5 are arranged in the vicinity of each other, that is, to be continuous with each other, and as described above, the pin # for outputting the signal DFS2 58 and pin # 57 for outputting signal DFS3 are arranged adjacent to each other, and pin # 60 for outputting signal DFS4 and pin # 59 for outputting signal DFS5 are arranged adjacent to each other. ing.

  The wirings WLP0, WLD1 to WLD5 for these signals PWS0 and DFS1 to DFS5 are partially arranged side by side. Specifically, in the range LR1, the wirings WLP0, WLP0, WLD1 to WLD5 for the signals PWS0, DFS1 to DFS5 are arranged in the order of WLP0, WLD1, WLD3, WLD2, WLD5, and WLD4. Wiring lines for DFS1 to DFS5 are arranged in the order of WLD1, WLD3, WLD2, WLD5, and WLD4. In the range LR3, wiring lines for signals DFS2 to DFS5 are arranged in the order of WLD3, WLD2, WLD5, and WLD4. In the range LR4, wirings for the signals DFS2, DFS4, and DFS5 are arranged in the order of WLD2, WLD5, and WLD4. In the range LR5, wirings for the signals DFS4 and DFS5 are arranged in the order of WLD5 and WLD4.

  Further, signal lines (for example, signal lines WLD1, WLD2, and WLD4 from the ports OUT1, OUT2, and OUT4) that transmit a driving frequency signal to the piezoelectric transformer driving circuit for driving the simultaneously operating piezoelectric transformer are not adjacent to each other, Other signal lines (signal lines WLD3 and WLD5 from OUT3 and OUT5) are interposed therebetween.

  In the example of FIG. 8, the output timing of the drive frequency signal is different in all of the pair (set) of pins composed of adjacent pins, but the output timing of the drive frequency signal is different in at least one pair. If this is the case, interference can be avoided between the pair of pins. For example, the output timing may be different only for the drive frequency signal in which interference is a problem.

  In addition, the above “different timing” is not only in the case where one is on, but the other is not on. In the period when one is on, the other part is on in the first part and the last part. The relationship may be For example, during the period when the leading margin portion (the portion where printing is not actually performed) or the trailing margin portion of the paper 115 passes through the secondary transfer portion, the above-described overlap is generated. Also good. This is because printing is not performed in the margin portion, and no problem occurs even if there is interference between drive frequency signals.

FIG. 10 shows a part for generating the drive frequency signal DFSi, with the detection voltage VBi (i is one of 1 to 5) as an input, among the circuits formed in the printer engine control unit 253.
In the printer engine control unit 253, five circuits similar to those shown in FIG. 10 are provided for receiving the detection voltages VB1 to VB5 and generating the drive frequency signals DFS1 to DFS5, respectively.
In the circuit shown in FIG. 10, the comparator 501, the timer 504, the fractional-N frequency divider 530, the output selector 509, and the inverter 512 constitute a part of the piezoelectric transformer control unit 262.

The fractional-N divider 530 includes a 19-bit register 505, an error holding register 507, an adder 506, and a divider 508.
Hereinafter, a case where i = 1, that is, a case where the circuit of FIG. 10 is a circuit that supplies a drive frequency signal to the charging bias generator 153 will be described.

In this case, the detection voltage VB1 fed back from the output voltage detection means 320 of the charging bias generator 153 is input as the detection voltage VBi.
The 10-bit analog-to-digital converter 414 converts the detection voltage VB1 of 0 to 3.3V into a 10-bit detection voltage value (detection voltage value data) dVB1 of 0 to 1023, and outputs it to the comparator 501 in the piezoelectric transformer control unit 262. Supply.

  The target value instructing means 510 supplies a 10-bit target value (target value data) tVB1 corresponding to a predetermined high voltage target voltage according to the image forming conditions to the comparator 501.

  The target value stored in the target value indicating means 510 is set to a value obtained by digitally converting the detection voltage VB1 when the charging bias is equal to the target voltage.

  The comparator 501 outputs L when the voltage detection value dVB1 is larger than the target value tVB1 (when dVB1> tVB1), and outputs when the voltage detection value dVB1 is smaller than the target value tVB1 (when dVB1 <tVB1). Becomes H.

The timer 504 outputs a signal for starting a control operation to the 19-bit register 505 at a predetermined control cycle. This control cycle is, for example, several microseconds to several hundred microseconds. The timer 504 is constituted by a preset counter that counts the clock CLK, for example.
The control cycle by the timer 504 may be changeable according to the difference between the detected voltage value and the target value.
A 19-bit register 505 is a register that holds a digital value representing a frequency division ratio.

  The upper limit register 502 stores the upper limit value set in the 19-bit register 505. The lower limit register 503 stores the lower limit value set in the 19-bit register 505.

The 19-bit register 505 increases the 19-bit register value by 1 in the range from the lower limit value to the upper limit value according to the signal input from the comparator 501 when the rising edge of the signal from the timer 504 is received. Or decrease. Here, “1” is the minimum unit of fractional value (decimal part). For example, when 1 is added in a state where the 19-bit value is 4B200 hex, 4B201 hex is obtained, and when 1 is subtracted, 4B1FFhex is obtained.
Specifically, when the output of the comparator 501 is H (when the voltage detection value is smaller than the target value), it is increased by 1, and when the output of the comparator 501 is L (the voltage detection value is larger than the target value). When) is decreased by one.

  The error holding register 507 receives the lower 10 bits of the 19-bit register 505 as an input, and each time a pulse is output from the frequency divider 508 (described later) (at the rising edge of the pulse), the error value is stored in the error value in the lower 10 bits of the register 505. The value is added to the value held in the holding register 507. By repeating such processing, the error holding register 507 accumulates the lower 10 bits of the register 505.

FIG. 11 is a block diagram illustrating the error holding register 507.
The error holding register 507 adds the lower 10-bit value of the 19-bit register 505 and the lower 10-bit of the register 507a by the adder 507b, and replaces the addition result with the lower 11 bits (bits 0 to 10) of the register 507a.

  The addition in the adder 507b is triggered by the rising edge of the pulse output from the frequency divider 508, and the value of bit10 is shifted to bit11 simultaneously with the addition. Bit 10 is cleared to 0 after being shifted.

  The value of the fractional part (the lower 10 bits of the output of the 19-bit register 505) is added to the value held in the register 507a of the error holding register 507 every time the output pulse of the frequency divider 508 rises, and the addition result is stored in the register 507a. Retained. When the register 507a overflows, the signal D507 is output H, otherwise it is L.

  The adder 506 adds 1 to the upper 9 bits which are the integer part of the 19-bit register 505, or outputs the result without adding. That is, 1 is added when the signal D507 output from the error holding register 507 is H, and 0 is added when the signal D507 is L. The addition result is output to frequency divider 508 as a value representing the frequency division ratio. Assuming that the value of the integer part 9 bits of the 19-bit register 505 is N, when the signal D507 is H, the output of the adder 506 is N + 1, and when the signal D507 is L, the output of the adder 506 is N.

  The frequency divider 508 outputs a pulse having a duty of about 35% with the 9-bit value (N or N + 1) supplied from the adder 506 and the product of one cycle of the clock CLK as one cycle.

  In order to obtain a drive frequency signal with a duty of about 35%, the drive frequency signal may be turned ON only during a period obtained by adding 1/4 of one cycle of the drive frequency signal, 1/16, and 1/32. The sum of the 2-bit shift value (1/4), 4-bit shift value (1/16), and 5-bit shift value (1/32) of one period (= division ratio / clock frequency) of the frequency signal (= 1/4 + 1 / 16 + 1/32 = 11 / 32≈0.343745≈0.35) may be set as the ON period.

  The 19-bit register 505, the error holding register 507, the adder 506, and the frequency divider 508 constitute a fractional-N frequency divider 530.

  The output selector 509 selects and outputs one of the two inputs according to the input of the ON / OFF signal 511. That is, when the ON / OFF signal 511 is H, the output of the frequency divider 508 is selected, and when the ON / OFF signal 511 is L, the L level signal is selected.

  The inverter 512 inverts the output. The output of the inverter 512 is output as a drive frequency signal via the output port OUT1.

The operation of the frequency divider 530 will be described with reference to FIG. The example shown in FIG. 12 shows the operation when the 19-bit register lower 10-bit value is 12 Chex. (12 Chex is equivalent to 300/1024 = about 0.3.) In FIG. 12, “frequency divider output period” indicates a count value of pulses output from the frequency divider 508. This count value is incremented by one every time a pulse is output from the frequency divider 508. In FIG. 12, when the count value reaches 15, it then returns to 0. Changes in the output of the error holding register 507, the lower 10 bits of the 19-bit register, and the adder 506 while the count value repeats from 0 to 15 are shown.
The value of the error holding register 12bit is 000 hex in the initial state.

  The error holding register value is updated as shown in the figure for each pulse output, and 0 (L) or 1 (H) is output to the adder 506. Bit 11 of the error holding register is provided for explanation, but may be saved. An error is added to the fractional value, and when a carry occurs, it is added to the division value integer part. As a result, the average frequency division ratio converges to the value indicated by the 19-bit register.

  As described above, FIG. 12 shows the operation when the low-order 10-bit value of the 19-bit register is 12 Chex. In the period in which the pulse from the frequency divider 508 is output 16 times, the value of the error holding register 507 and the input of the adder 506 are input. The change of the value goes around. When the lower 10-bit value of the 19-bit register is 200 hex, the above value changes once in the cycle in which the pulse is output from the frequency divider 508, and when the lower 10-bit value of the 19-bit register is 001 hex, the frequency divider From the period 508, the above-mentioned change of the value is completed in a cycle in which the pulse is output 1024 times.

  When the ON / OFF signal 511 becomes H (true), the output selector 509 selects the output of the frequency divider 508 and supplies it to the inverter 512.

  In a short time, the cycle is switched between N division and N + 1 division. For example, when the division ratio instruction value is 300.5 and the setting value of the 19-bit register 505 is 300.5 × 1024 = 307712, and therefore 4B200 hex, 300 Divided, 166.6667 kHz and 301 divided pulses, 166.113 kHz pulses are output alternately, and the piezoelectric transformer vibrates at its average frequency of 166.39 kHz.

  In this embodiment, the fractional part is 10 bits and the clock frequency is 50 MHz. However, the number of bits in the fractional part can be arbitrarily selected, and the clock frequency can also be arbitrarily selected. Although the fractional frequency divider is described as a fractional system, a threshold matrix may be used or a random number may be used if a plurality of frequency division ratios can be switched in a short time.

  Print data is input to the image forming apparatus 101 of FIG. 1 from an external device (not shown) via the host interface unit 250 of FIG. The input data is converted into bitmap data by the command / image processing unit 251.

  The image forming apparatus 101 causes the heat fixing roller of the fixing device 118 to reach a predetermined temperature by controlling the fixing device heater 261 according to the detection value of the thermistor 266, and starts the printing operation.

  The paper 115 set in the paper cassette 113 in FIG. 1 is fed one by one by the hopping roller 114.

  The sheet 115 is conveyed by registration rollers 116 and 117 at a timing that matches an image forming operation described later, and is formed by the secondary transfer roller 130 and the secondary transfer backup roller 120 in synchronization with the toner image on the intermediate transfer belt 108. The nip portion 125 is conveyed.

  The developing units 102C, 102M, 102Y, and 102K are sequentially rotated and contacted by the developing unit support 111, and sequentially form toner images on the photosensitive drum 132 by an electrophotographic process. At this time, the LEDs of the LED head 103 are selectively turned on according to the bitmap data supplied from the LED head interface unit 252, and an electrostatic latent image is formed on the photosensitive drum 132.

A toner image corresponding to the electrostatic latent image is formed on the photosensitive drum 132 by the developing units 102C, 102M, 102Y, and 102K. The formed toner images are sequentially transferred onto the intermediate transfer belt 108 by the positive bias applied by the primary transfer bias generator 151 to the primary transfer roller 105.
After the transfer of the fourth color, that is, the black toner image to the intermediate transfer belt 108 is started, the sheet 115 is subjected to the secondary transfer in accordance with the timing at which the image on which the four color toner images are superimposed reaches the secondary transfer nip 125. The paper 115 is conveyed so as to reach the nip 125.

  The secondary transfer roller 130 is brought into contact with the intermediate transfer belt 108 immediately before the paper 115 reaches the secondary transfer nip 125, and a positive bias is applied from the secondary transfer bias generator 150 at the timing of transferring the toner image. The toner images for four colors are transferred to the paper 115 by the positive bias.

  After the secondary transfer, the paper 115 is fixed by the fixing device 118 and discharged.

After the completion of the secondary transfer, the secondary transfer bias generator 150 applies positive and negative bias alternately for each rotation in accordance with the rotation timing of the secondary transfer roller 130 to transfer the toner attached to the secondary transfer roller 130. Reverse transfer to the belt 108 is performed.
Further, the primary transfer bias generation unit 151 subsequently applies a negative bias to the primary transfer roller 105 to apply the reverse transfer toner attached to the intermediate transfer belt 108 and the residual toner transferred to the paper 115 to the photosensitive drum 132. Reverse transcription to
The toner reversely transferred to the photosensitive drum 132 is scraped off by the cleaning blade 137 that is in contact with the photosensitive drum 132.

  The developing units 102C, 102M, 102Y, and 102K are detachable cartridges, and are integrated with a toner container.

  The printer engine control unit 253 sets a target voltage for each bias voltage in accordance with a predetermined table value (a target value corresponding to the target voltage is set in a circuit portion that generates a drive frequency signal for generating each bias voltage). Drive frequency signals DFS1 to DF5 having frequencies corresponding to the respective target voltages to the charging bias generator 153, the primary transfer bias generator 151, and the secondary transfer bias generator 150. Output.

  The charging bias generator 153 supplies a negative bias to the charging roller 136 and the developing bias generator 152.

The developing bias generator 152 DC-DC converts the charging bias supplied from the charging bias generator 153 to generate a lower (smaller absolute value) negative bias. , 134Y, 134K) and a supply roller (any one of 133C, 133M, 133Y, 133K) as a load 133.
This negative bias is selectively applied only to the four developing devices 102C, 102M, 102Y, and 102K that are in contact with the photosensitive drum 132 via the contacts.

  As described above, the primary transfer bias generator 151 supplies a bias to the primary transfer roller 105, and the secondary transfer bias generator 150 supplies a bias to the secondary transfer roller 130.

Next, the operation of the printer engine control unit 253 for generating the charging bias will be described with reference to FIGS. 3, 5, and 10.
The printer engine control unit 253 initializes the internal register of the synchronous clock circuit constituting the piezoelectric transformer control unit 262.

  Subsequently, a drive frequency signal is output from the output port OUT1 at a predetermined timing. The initial value of the frequency of this drive frequency signal is determined in advance. The output drive frequency signal is applied to the input terminal 304a of the piezoelectric transformer drive circuit 304, and a half-wave sine wave drive voltage is applied from the output terminals 304b and 304c of the piezoelectric transformer drive circuit 304 to the primary side of the piezoelectric transformer 309. The

  A boosted AC output is output from the secondary side of the piezoelectric transformer 309, rectified by the negative bias rectifier circuit 314, and a negative bias is applied to the charging roller as the load 136.

  The negative high voltage output from the negative bias rectifier circuit 314 is converted to a positive voltage VB1 in the range of 0 to 3.3 V by the output voltage detection means 320 and input to the detection voltage input port ADC1 of the printer engine control unit 253. The

  The printer engine control unit 253 converts the analog voltage VB1 input to the detection voltage input port ADC1 into a 10-bit digital value dVB1 by the AD converter 414 in FIG. 10 and outputs the converted value to the piezoelectric transformer control unit 262.

The piezoelectric transformer control unit 262 sets the frequency of the drive frequency signal DFS1 (the frequency of the signal output from the output port OUT1) so that the detection value dVB1 is equal to the target value tVB1 supplied from the target value indicating unit 510. Control.
For example, if the target voltage of the charging bias is −1000 V and the detection voltage corresponding to this target voltage (the voltage division value by the resistors 429 and 430) is 1.297 V,
(1.297 / 3.3) × 1023 = 402,
192 hex obtained by converting “402” obtained by the above formula into a hexadecimal number is set as a target value tVB1 corresponding to the target voltage of the charging bias in the target value indicating means 510 so that the detected value dVB1 becomes equal to the target value tVB1. The frequency of the drive frequency signal is controlled.

  The above value is an example, and a value corresponding to the value of the voltage to be output from the charging bias generator 153 is selected.

  As shown in FIG. 13A, the piezoelectric transformer 309 has a characteristic that the output voltage changes according to the drive frequency. Accordingly, the negative bias voltage obtained by rectifying the output of the piezoelectric transformer 309 has the relationship shown in FIG. 13B with respect to the drive frequency.

  As shown in FIGS. 13A and 13B, the absolute value of the output voltage becomes maximum at the frequency fx. This maximum value is indicated by symbols HV2 and HV2 '. The initial value of the driving frequency is set to fy (= fstart), driving is started at the frequency fy (output voltages at that time are indicated by symbols HV1 and HV1 ′), and the frequency is gradually lowered as indicated by an arrow RIF. Control is performed so that the output voltage becomes the target voltage. In FIGS. 13A and 13B, the lower limit of the variable range of the frequency is indicated by the symbol fend. The lower limit fend of the variable range is set to a frequency slightly higher than the frequency fx at which the absolute value of the output voltage is maximum. The reason why the lower limit fend is set in this way is that, as a property of the piezoelectric transformer, there is a high possibility of failure if it is driven for a long time at the frequency fx where the absolute value of the output voltage is maximum.

  As an example, in the present embodiment, a piezoelectric transformer having characteristics of fx of 165 kHz and fy of 180 kHz and its drive circuit are used.

  Since the relationship between the drive frequency of the piezoelectric transformer and the output voltage is not uniquely determined by the load, the manufacturing variation of the piezoelectric transformer, the temperature of the piezoelectric transformer, etc., the output voltage is set to a desired value in this embodiment by adjusting the drive frequency. The control is done.

  The photosensitive drum is charged by applying the charging bias thus obtained to the charging roller.

Next, the operation of the output voltage conversion means 319 will be described with reference to FIG.
The output voltage conversion means 319 receives the negative bias output from the charging bias generation unit 153 and the pulse width modulation signal PWS0 output from the output port PWM0 of the piezoelectric transformer control unit 262, and applies the negative bias to the pulse width modulation. A voltage stepped down according to the duty of the signal PWS0 is generated. The voltage stepped down according to the duty of the pulse width modulation signal PWS0 is a voltage proportional to the duty of the pulse width modulation signal PWS0. This voltage is applied to a supply roller as the load 133.

  Further, by dividing the “proportional voltage” by the series circuit of the Zener diode 443 and the resistor 444 shown in FIG. 5, a voltage obtained by subtracting a constant voltage (the Zener voltage) from the “proportional voltage” is output. To do. The step-down voltage obtained as a result of such processing is applied to the developing roller as the load 134.

Next, the primary transfer bias will be described.
After the latent image formed on the photosensitive drum 132 by exposure by the LED head 103 becomes a toner image by development, a positive primary transfer bias is applied where the photosensitive drum 132 and the intermediate transfer belt 108 are in contact with each other, and the toner The image is transferred to the intermediate transfer belt 108.

  In order to generate the positive primary transfer bias, a drive frequency signal is output from the output port OUT2. With this drive frequency signal, the piezoelectric transformer drive circuit 305 drives the piezoelectric transformer 310, and the secondary AC output is rectified by the positive bias rectifier circuit 315 and applied to the primary transfer roller as the load 105. The initial value of the frequency of the drive frequency signal is set to a predetermined value.

The positive high voltage output from the positive bias rectifier circuit 315 is converted into a voltage VB2 in the range of 0 to 3.3 V by the output voltage detection unit 321 and input to the detection voltage input port ADC2 of the printer engine control unit 253. .
Thereafter, the frequency of the drive frequency signal is controlled in the same manner as the control of the charging bias generator 153. However, the relationship between the output voltage of the positive bias rectifier circuit 315 and the frequency is as shown in FIG.

  The output of the output port OUT3, the piezoelectric transformer drive circuit 306, the piezoelectric transformer 311, the negative bias rectifier circuit 316, and the output voltage detection means 322 are the same as those described with respect to the charging bias generator 153, and the negative bias rectifier circuit 316 is A negative bias is output to the primary transfer roller 105.

The negative bias from the negative bias rectifier circuit 316 is for reversely transferring the residual toner after transfer from the intermediate transfer belt 108 to the photosensitive drum 132.
However, unlike the charging bias generator 153, the negative bias from the negative bias rectifier circuit 316 is output via a resistor 456 added to the positive bias rectifier circuit 315.

Next, the secondary transfer bias will be described.
The output of the output port OUT4, the piezoelectric transformer drive circuit 307, the piezoelectric transformer 312, the positive bias rectifier circuit 317, and the output voltage detection means 323 are the same as described for the portion of the primary transfer bias generator 151 that generates the positive bias. Yes, the positive bias rectifier circuit 317 outputs a positive bias to the secondary transfer roller 130.

The output of the output port OUT5, the piezoelectric transformer drive circuit 308, the piezoelectric transformer 313, the negative bias rectifier circuit 318, and the output voltage detection means 324 are the same as described for the portion that generates the negative bias of the primary transfer bias generator 151. The negative bias rectifier circuit 318 outputs a negative bias to the secondary transfer roller 130.
The negative bias from the negative bias rectifier circuit 318 is output via a resistor 481 added to the positive bias rectifier circuit 317.

Hereinafter, control of the positive bias voltage generated from the secondary transfer bias generator 150 will be described with reference to FIG. 10 as well as FIG.
In the above description, FIG. 10 shows the portion for generating the drive frequency signal DFS1, but as described above, the portion for generating the drive frequency signal DFS4 is also configured in the same manner. This will be described with reference to FIG.
As for the positive bias voltage, when the resistance 482 in FIG. 7 is 100 MΩ and the resistance 483 is 100 kΩ, and the target voltage is +2000 V, the divided voltage (detection voltage VB4) is 1.998 V,
Therefore (1.998 / 3.3) × 1023 = 619,
That is, a 10-bit value representing 26 Bhex is set in the target value indicating unit 510 as a daily target value.
In the upper limit value register 502, a 19-bit value representing 4571Chex is set.

Of the 19-bit value representing 4571 Chex, the upper 9 bits are the integer part 115 hex, and the lower 10 bits are 31 Chex and become the fractional part.
{(Upper 9 bits) + (Lower 10 bits / 1023)}
Becomes the division ratio value.

115 hex = 277,
Since 31 Chex = 796, the division ratio is 277 + 796/1023 = 277.7781,
Since 50 MHz has a clock cycle of 20 ns, 1000 / (277.7781 × 0.02) = 180, and the initial frequency setting value is 180 kHz.

  Similarly, 4B3A4hex is set as the lower limit value in the lower limit register 503, and the lower limit frequency is limited to 166 kHz.

Next, in the printer engine control unit 253, the division ratio control in the part that generates the drive frequency signals DFS2 and DFS3 or the part that generates the drive frequency signals DFS4 and DFS5 is negative and negative. A description will be given with reference to FIG. 14 and FIG.
14 and 15 show the operations in the flowcharts, but in actuality, they are configured as a synchronous clock circuit in the hardware description language.

  FIG. 14 illustrates a flow in the case of positive bias output. In the case of a positive bias output, in the present embodiment, the detection voltage is 000 hex when the high voltage is off, and the detection voltage value increases as the output increases.

Operation starts in step S700.
In step S701, the value of the lower limit register 503 is set in the 19-bit register 505.
In step S702, it is determined whether the ON / OFF signal 511 is true (H level).
If true (H level), the process proceeds to step S703; otherwise, the process returns to step S701.

In step S703, it is determined whether or not the rising edge of the output signal of the timer 504 has been detected. If detected, the process proceeds to step S704, and if not, the process returns to step S703.
In step S704, the comparator 501 determines whether or not the detected voltage is smaller than the target value. If the detected voltage is smaller, the process proceeds to step S705, and if not, the process proceeds to step S706.
In step S705, it is determined whether or not the value of the 19-bit register 505 is not equal to the value of the upper limit register 502 (whether it has not reached the upper limit). If not, the process proceeds to step S707. Otherwise, the process proceeds to step S702. move on.

In step S706, it is determined whether or not the value of the 19-bit register 505 is not equal to the value of the lower limit register 503. If not, the process proceeds to step S708. Otherwise, the process proceeds to step S702.
In step S707, the adder 506 adds 1 to the value of the 19-bit register 505.
In step S708, the adder 506 subtracts 1 from the value of the 19-bit register 505.
After step S707 or S708, the process returns to step S702, and thereafter the same processing is repeated.

  FIG. 15 illustrates a flow in the case of a negative bias output. In the case of a negative bias output, in the present embodiment, the detection voltage is 3FF hex (10 bits) when the high voltage is off, and the detection voltage decreases as the output increases.

Operation starts in step S800.
In step S801, the value of the lower limit register 503 is set in the 19-bit register 505.
In step S802, it is determined whether the ON / OFF signal 511 is true (H level).
If true (H level), the process proceeds to step S803; otherwise, the process returns to step S801.

In step S803, it is determined whether or not the rising edge of the output signal of the timer 504 has been detected. If detected, the process proceeds to step S804, and if not, the process returns to step S803.
In step S804, the comparator 501 determines whether or not the detected voltage is greater than the target value. If it is greater, the process proceeds to step S805, and if not, the process proceeds to step S806.
In step S805, it is determined whether or not the value of the 19-bit register 505 is not equal to the value of the upper limit register 502 (whether it has not reached the upper limit). If not, the process proceeds to step S807. Otherwise, the process proceeds to step S802. move on.

In step S806, it is determined whether the value of the 19-bit register 505 is not equal to the value of the lower limit register 503. If not, the process proceeds to step S808, and if not, the process proceeds to step S802.
In step S807, the adder 506 adds 1 to the value of the 19-bit register 505.
In step S808, 1 is subtracted from the value of the 19-bit register 505 by the adder 506.
After step S707 or S708, the process returns to step S702, and thereafter the same processing is repeated.

  Although the present embodiment is configured by hardware, it can also be realized by software, that is, by a program. When implemented by a program, general-purpose registers are used instead of dedicated registers as registers such as the 19-bit register 505, and general-purpose ports are used as detection voltage input ports and output ports instead of dedicated ports.

FIGS. 16A to 16G show the timing of each high-voltage output.
FIG. 16A shows the output timing of the pulse width modulation signal PWS0 from the output port PWM0. Development is performed in the order of cyan, magenta, yellow, and black by outputting the pulse width modulation signal PWS0 within the period when the charging bias is ON. In the state where the pulse width modulation signal PWS0 is not output, the output port PWM0 is kept at the H level.

  FIGS. 16B to 16F show “charging bias”, “primary transfer negative bias”, “primary transfer positive bias”, “secondary transfer negative bias”, and “secondary transfer positive bias”, respectively. Indicates the timing of occurrence. These timings are timings when the ON / OFF signal 511 in the circuit (FIG. 10) that generates the drive frequency signal for generating each bias in the printer engine control unit 253 is turned on.

  FIG. 16G shows the timing at which the secondary transfer roller solenoid 260 drives the secondary transfer roller 130 to bring the paper 115 into contact with the intermediate transfer belt 108.

  Prior to the image forming operation, charging bias output is started simultaneously with driving of each motor. Therefore, output of the drive frequency signal DFS1 from the output port OUT1 is started, and the piezoelectric transformer 309 is driven.

  Subsequently, the pulse width modulation signal PWS0 starts to output a pulse width modulation signal having a duty corresponding to the target voltage from the H output in the initial state. The duty of the pulse width modulation signal PWS0 is controlled separately for each toner color to be developed.

  As the primary transfer bias, a negative bias is applied until immediately before the start of the primary transfer, and the piezoelectric transformer 311 is driven.

The primary transfer negative bias is turned off simultaneously with the start of development of the first color cyan, and the primary transfer positive bias is turned on simultaneously with the developed toner image reaching the primary transfer nip 125.
The primary transfer positive bias is kept on while the four color toner images are formed.

In this embodiment, the primary transfer positive bias is maintained at a constant value, but the value of the primary transfer positive bias may be changed for each color of toner to be subjected to primary transfer. In that case, the target value set in the target value setting means 510 may be switched in accordance with the switching of the toner color.
In that case, the output remains on.

  A four-color superimposed toner image is formed on the intermediate transfer belt 108, and the secondary transfer roller solenoid 260 is driven immediately before reaching the secondary transfer nip 125, and the sheet 115 is transferred to the intermediate transfer belt 108 by the secondary transfer roller 130. Simultaneously with the contact, a secondary transfer positive bias is applied (tsp).

  After the completion of the secondary transfer, a secondary transfer negative bias and a secondary transfer positive bias are alternately applied every cycle of the secondary transfer roller 130 (Tpn). At this time, the drive frequency signal may be overlapped at the time of on / off as shown in FIG. That is, the last part of the period in which one drive frequency signal is generated may overlap with the first part of the period in which the other drive frequency signal is generated.

  Since the positive bias rectifier circuit 317 and the negative bias rectifier circuit 318 are connected in series even if they are overlapped, either the positive or negative bias is applied to the secondary transfer roller 130. The effect of overlapping is to shorten the output rise and fall times.

  During the image forming operation (period Tif in FIG. 16), the piezoelectric transformer 309 for the negative bias output of the charging bias generator 153, the piezoelectric transformer 310 for the positive bias output of the primary transfer bias generator, and the generation of the secondary transfer bias Only the piezoelectric transformer 312 for the positive bias output of the unit 150 is driven, the piezoelectric transformer 311 for the negative bias output of the primary transfer bias generator 151 and the piezoelectric for the negative bias output of the secondary transfer bias generator 150. The transformer 313 is turned off.

  Therefore, the output port PWM0 and the output ports OUT1 to OUT5 of the printer engine control unit 253 are arranged in the order of PWM0, OUT1, OUT3, OUT2, OUT5, and OUT4 as shown in FIG. Components and circuit components constituting the charging bias generation unit 153, the primary transfer bias generation unit 151, and the secondary transfer bias generation unit 150, in particular, NPN transistors and MOSFETs are arranged as shown in FIG. Thus, it is possible to suppress interference between adjacent wirings.

  In particular, during the image forming operation, the NPN transistor 462 of the piezoelectric transformer driving circuit 306 that drives the piezoelectric transformer for generating negative bias of the primary transfer bias generating unit 151, and the piezoelectric for generating negative bias of the secondary transfer bias generating unit 150. The signals DFS3 and DFS5 (signals from the ports OUT3 and OUT5) to the NPN transistor 486 of the piezoelectric torus driving circuit 308 for driving the transformer become H level, and at this time, the piezoelectric transformers 309, 310 and 312 are driven. The drive signals DFS1, DFS2, and DFS4 (signals from the ports OUT1, OUT2, and OUT4) supplied to the piezoelectric transformer drive circuits 304, 305, and 307 are not affected by crosstalk.

  Further, as shown in FIG. 8, the piezoelectric transformers that are driven at the same time are not adjacent to each other and are arranged so that another (not driven at the same time) intervenes between them. The distance between the transformers can be increased, and fluctuations in the output voltage due to mutual interference between the piezoelectric transformers can be prevented.

  Further, unlike the image output at the time of cleaning bias output, cleaning is performed without any trouble even if the influence of mutual interference or crosstalk occurs. The secondary transfer roller 130 is reliably cleaned by several rotations of cleaning (FIGS. 16E and 16F) and cleaning of the belt several times by the primary transfer roller 105 (FIG. 16C). Is done.

  Furthermore, since the pulse width modulation signal given to the voltage conversion means 319 has a low frequency of 10 to 20 kHz, there is no influence on the driving of the piezoelectric transformer 309.

  FIG. 17 shows a modification of the arrangement shown in FIG. As shown in FIG. 17, the same effect can be obtained by replacing the primary transfer bias generator 151 and the secondary transfer bias generator 150 as shown in FIG. That is, in the configuration of FIG. 17, the ports having the signal output pins of the printer engine control unit 253 are in the order of PWM0, OUT1, OUT5, OUT4, OUT3, and OUT2, as shown in FIG. The drive circuits are arranged in the order of 304, 306, 305, 308, 307 as in FIG. The wirings WLD4 and WLD5 connected to the ports OUT4 and OUT5 intersect with the wirings WLD2 and WLD3 connected to the ports OUT2 and OUT3. The crossing is performed, for example, by straddling one wiring with jumper resistors (0Ω chip resistors) 601 to 604.

Embodiment 2. FIG.
FIG. 19 shows an image forming apparatus according to the second embodiment of the present invention.
The image forming apparatus shown in FIG. 19 is generally the same as the image forming apparatus shown in FIG. 1 except that the primary transfer negative bias is eliminated and a primary transfer cleaning blade 650 and a waste toner container 651 are provided instead.

  Instead of eliminating the primary transfer negative bias, as shown in FIG. 19, a primary transfer cleaning blade 650 and a waste toner container 651 that can move as indicated by an arrow DOB are provided.

  In this case, as shown in FIG. 20, a circuit for generating the primary transfer negative bias becomes unnecessary. Therefore, in FIG. 8, the space where the circuit components for generating the primary transfer negative bias, particularly the piezoelectric transformer 311, the inductor 463, the MOSFET 464, and the NPN transistor 462 are left unoccupied. There is sufficient space between

  As described above, while the pins for outputting a plurality of driving frequency signals are adjacent to each other, the signal lines for outputting the driving frequency signals at the same time when the image is formed are allocated to pins that are not adjacent to each other (for example, the printer engine control unit 253). Are assigned to even-numbered pins of the integrated circuit constituting the circuit), the pins of the integrated circuit can be used effectively, and the influence of interference and crosstalk can be eliminated. In this embodiment, the pins are arranged on even pins, but can be arranged on odd pins.

  As described above, the drive frequency signal output during the image forming operation is output from only one of the even-numbered pins and the odd-numbered pins among the output pins of the integrated circuit. A uniform image can be obtained by eliminating interference and reducing output ripple.

  Further, it has become possible to integrate a conventional piezoelectric transformer control integrated circuit (part corresponding to the piezoelectric transformer control unit 262 of the present embodiment) separately from the printer engine control integrated circuit.

  Further, it is not necessary to have a configuration in which a ground line is interposed between driving frequency signals in the integrated circuit, and an increase in output pins due to such a configuration can be avoided.

As described above, in the first embodiment, pins and wires for transmitting drive frequency signals for driving simultaneously driven piezoelectric transformers are not adjacent to each other, and simultaneously driven piezoelectric transformers are driven. pins and wiring for transmitting the driving frequency signals that have to be interposed.

  In addition, the output from the first piezoelectric transformer (310) is imaged more than the change in the output waveform of the second output unit (OUT3) when the output from the first piezoelectric transformer (for example, 310) is not used for image formation. Changes in the output waveform of the second output portion (for example, OUT3) when used for formation are reduced.

  A first wiring (for example, WLD2) that supplies a signal from the first output unit (OUT2) to the first piezoelectric transformer driving circuit, and a signal from the second output unit (OUT3) to the second piezoelectric transformer driving circuit. Of the second wiring (WLD3) to be supplied, at least part of the first wiring (WLD2) and the second wiring (WLD3) are wired side by side, and the output of the first piezoelectric transformer (310) is used as a load. The change in the output waveform of the second output unit (OUT3) when the output of the first piezoelectric transformer (310) is supplied to the load rather than the change of the output waveform of the first output unit (OUT2) when supplied. The output of the second piezoelectric transformer (311) is supplied to the load less than the change in the output waveform of the second output unit (OUT3) when the output of the second piezoelectric transformer (311) is supplied to the load. When the first output unit ( It is to reduce the change of the output waveform of the UT2).

Integrated circuit (25 3) is to the second output section when the output of the first polarity of the voltage supplied to the load by using the first piezoelectric transformer (310) an output waveform of (OUT3) in the vicinity of 0V The output waveform of the first output section (OUT2) when the output of the voltage of the second polarity is supplied to the load using the second piezoelectric transformer (311) is set in the vicinity of 0V.

Embodiment 3 FIG.
Embodiment 3 of the present invention will be described below. The same parts as those in the first embodiment are given the same reference numerals.

  FIG. 21 shows a control system in the third embodiment. The control system of FIG. 21 is generally the same as the control system of FIG. 2, and the same reference numerals are given to the same parts. The control system of FIG. 21 differs from the control system of FIG. 2 in the following points.

First, a printer engine control unit 1253 is provided instead of the printer engine control unit 253. Similarly to the printer engine control unit 253, the printer engine control unit 1253 is configured by a single chip integrated circuit.
Instead of the piezoelectric transformer control unit 262, a piezoelectric transformer control unit 1262 is provided.
Similarly to the piezoelectric transformer control unit 262, the piezoelectric transformer control unit 1262 includes a synchronous clock circuit.
Instead of the charging bias generator 153, the primary transfer bias generator 151, and the secondary transfer bias generator 150, a charging bias generator 1153, a primary transfer bias generator 1151, and a secondary transfer bias generator 1150 are provided. Yes.

22 shows in more detail the configuration of the circuit formed in the printer engine control board and high-voltage board 301 used in the third embodiment, and FIGS. 23 to 25 show the circuit configuration of each part of the circuit of FIG. Show. In the circuit shown in FIG. 22, the piezoelectric transformer driving device is configured by portions other than the output load.
The same places as in FIGS. 3 and 4 to 25 described in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

The oscillation circuit 331 in FIG. 22 is the same as that shown in FIG.
In addition to the circuit block shown in FIG. 3, voltage conversion means 1350, 1351, 1352, 1353, and 1354 are provided on the printer engine control board / high-voltage board 301 of FIG.

The piezoelectric transformer control unit 1262 shown in FIG. 22 is similar to the piezoelectric transformer control unit 262 of FIG. 3, and the output ports OUT1 to OUT5 that output the drive frequency signals DFS1 to DFS5 and the output port that outputs the pulse width modulation signal PWS0. In addition to PWM0, output ports PWM1 to PWM5 for outputting pulse width modulation signals PWS1 to PWM5 are provided.
On the other hand, the detection voltage ports ADC1 to ADC5 are not provided.

  In the first embodiment, the drive frequency signals DFS1 to OUT5 are controlled so that the digital value obtained by AD converting the detection voltages ADC1 to ADC5 matches the target value generated by the target value indicating means 510. However, in the third embodiment, the pulse width modulation signals PWM1 to PWM5 having the duty corresponding to the target value are generated, and the detection voltage is applied to the analog target value obtained by smoothing the pulse width modulation signals PWS1 to PWM5. Control is performed in each bias voltage generator so that VB1 to VB5 coincide.

Pulse width modulation signals PWS1 to PWM5 have a duty corresponding to the target value of the output voltage of each bias generator.
The drive frequency signals DFS1 to OUT5 have the same frequency fd. As shown in FIG. 26 (a), this frequency fd is a frequency somewhat higher than the frequency at which the output voltage of the piezoelectric transformer is maximum, that is, the output voltage (absolute value) of the piezoelectric transformer with respect to the decrease in frequency. ) Is set to a value close to the lower limit of the range. The frequency fd is, for example, 166 kHz.

  FIG. 23 shows specific circuit configurations of the charging bias generator 1153 and the output voltage converter 319. As shown in FIGS. 22 and 23, the charging bias generator 1153 receives the drive frequency signal DFS1 from the port OUT1 of the piezoelectric transformer controller 1262 and the pulse width modulation signal PWS1 from the port PWM1, and based on these signals. Then, a charging bias is generated and supplied to a charging roller as a load 136.

  The charging bias generator 1153 includes a voltage converter 1350, a piezoelectric transformer drive circuit 1304, a piezoelectric transformer 309, a negative bias rectifier circuit (negative rectifier circuit) 314, and an output voltage detector 320.

As shown in FIG. 23, the voltage conversion means 1350 includes an operational amplifier 1423, an NPN transistor 1426, resistors 1420, 1424, 1427, 1428, capacitors 1421, 1422, 1425, and an electrolytic capacitor 1429.
The emitter of the NPN transistor 1426 becomes the output of the voltage conversion means 1351.

  The resistor 1424 is inserted to discharge the capacitor 1425 when the output is off (when the bias generator does not output a high voltage) so that the emitter potential of the NPN transistor 1426 becomes 0V. The resistor 1428 is a resistor for discharging the electric charge of the electrolytic capacitor 1429 when the output is off.

The piezoelectric transformer drive circuit 1304 has the same configuration as that of the piezoelectric transformer drive circuit 304 in FIG. 5, but one end of the inductor 423 is connected to the output of the voltage conversion means 1350 (emitter of the NPN transistor 1426) instead of the 24V power supply 303. ing.
The rectifier circuit 314 and the output voltage detection means 320 are the same as those shown in FIG.
The output voltage conversion means 319 is the same as that shown in FIG.

  The detection voltage VB1 detected by the output voltage detection unit 320 is input to the detection voltage input port DAC1 of the printer engine control unit 253 in the first embodiment, but is input to the voltage conversion unit 1350 in the third embodiment. The

  The voltage conversion means 1350 is also called a dropper circuit (step-down circuit), and supplies the piezoelectric transformer drive circuit 1304 with a lower output voltage of the 24V power supply 303. As a result, the piezoelectric transformer drive circuit 1304 is supplied. Drives the piezoelectric transformer 309 with a driving voltage in the range of 0 to 22V.

  The detection voltage VB1 obtained by voltage division by the resistors 429 and 430 of the output voltage detection means 320 is input to the non-inverting input terminal (+) of the operational amplifier 1423 after being smoothed by the capacitor 1425. On the other hand, the pulse width modulation signal PWS 1 is input to the inverting input terminal (−) of the operational amplifier 1423 after being smoothed by the RC filter of the resistor 1420 and the capacitor 1421.

  The emitter current is controlled by controlling the base current of the NPN transistor 1426 by a differential integration circuit including the operational amplifier 1423 so that the potential of the non-inverting input terminal (+) becomes equal to the potential of the inverting input terminal (−). Control is performed (so that the smoothed detection voltage VB1 is equal to the smoothed pulse width modulation signal PWS1).

  As a result, the output voltage (absolute value) of the piezoelectric transformer 309 changes as indicated by the vertical arrow Vva in FIG. 26A. Therefore, the negative bias obtained by rectifying the output voltage of the piezoelectric transformer 309 is obtained. The voltage changes as shown by an arrow Vad in FIG. That is, the negative bias voltage is controlled so as to coincide with the target voltage indicated by the duty of the pulse width modulation signal.

  That is, in the first embodiment, the high voltage output voltage is changed by changing the drive frequency while the supply voltage to the piezoelectric transformer is fixed at 24 V. However, in the third embodiment, the drive frequency has a high boost ratio. The high voltage output voltage is changed by fixing the frequency (fd) and changing the supply voltage.

FIG. 24 shows a specific circuit configuration of the primary transfer bias generator 1151.
As shown in FIGS. 22 and 24, the primary transfer bias generation unit 1151 receives the drive frequency signals DFS2 and DFS3 from the ports OUT2 and OUT3 of the piezoelectric transformer control unit 1262, and the pulse width modulation signal from the ports PWM2 and PWM3. Based on these, a positive primary transfer bias and a negative primary transfer bias are generated and supplied to a primary transfer roller as a load 105.

  The primary transfer bias generator 1151 includes voltage converters 1351 and 1352, piezoelectric transformer drive circuits 1305 and 1306, piezoelectric transformers 310 and 311, a positive bias rectifier circuit (positive bias rectifier circuit) 315, and a negative bias rectifier circuit (negative polarity). Rectifier circuit) 316 and output voltage detecting means 321, 322.

As shown in FIG. 24, the voltage conversion unit 1351 includes an operational amplifier 1435, an NPN transistor 1436, resistors 1430, 1431, 1437, 1438, capacitors 1432, 1433, 1434, and an electrolytic capacitor 1439.
The emitter of the NPN transistor 1436 becomes the output of the voltage conversion means 1350.

  The piezoelectric transformer drive circuit 1305 has the same configuration as the piezoelectric transformer drive circuit 305 of FIG. 6, but one end of the inductor 449 is connected to the output of the voltage conversion unit 1351 instead of the 24 V power source 303. The rectifier circuit 315 and the output voltage detection means 321 are the same as those shown in FIG.

  The operational amplifier 1435 of the voltage conversion means 1351 receives a signal obtained by smoothing the pulse width modulation signal PWS2 at its non-inverting input terminal (+), and a signal obtained by smoothing the detection voltage VB2 at the inverting input terminal (−). Input, so that the potential of the inverting input terminal (−) is equal to the potential of the non-inverting input terminal (+) (the smoothed detection voltage VB2 is equal to the smoothed pulse width modulation signal PWS2). Control).

As shown in FIG. 24, the voltage conversion unit 1352 includes an operational amplifier 1445, an NPN transistor 1446, resistors 1440, 1442, 1447, 1448, capacitors 1441, 1443, 1444, and an electrolytic capacitor 1449.
The emitter of the NPN transistor 1446 becomes the output of the voltage conversion means 1352.

  The piezoelectric transformer drive circuit 1306 has the same configuration as that of the piezoelectric transformer drive circuit 306 in FIG. 6, but one end of the inductor 463 is connected to the output of the voltage conversion unit 1352 instead of the power supply 303 of 24V. The rectifier circuit 316 and the output voltage detection means 322 are the same as those shown in FIG.

  The operational amplifier 1445 of the voltage conversion unit 1352 receives a signal obtained by smoothing the pulse width modulation signal PWS3 at its inverting input terminal (−), and a signal obtained by smoothing the detection voltage VB3 at the non-inverting input terminal (+). Input, so that the potential of the non-inverting input terminal (+) becomes equal to the potential of the inverting input terminal (−) (the smoothed detection voltage VB3 is equal to the smoothed pulse width modulation signal PWS3) Control).

FIG. 25 shows a specific circuit configuration of the secondary transfer bias generator 1150.
As shown in FIGS. 22 and 24, the secondary transfer bias generator 1150 receives the drive frequency signals DFS4 and DFS5 from the ports OUT4 and OUT5 of the piezoelectric transformer controller 1262, and the pulse width modulation signal from the ports PWM4 and PWM5. Based on these, a positive secondary transfer bias and a negative secondary transfer bias are generated and supplied to a secondary transfer roller as a load 130.

  The secondary transfer bias generator 1150 includes voltage converters 1353 and 1354, piezoelectric transformer drive circuits 1307 and 1308, piezoelectric transformers 312 and 313, a positive bias rectifier circuit (positive bias rectifier circuit) 317, and a negative bias rectifier circuit (negative polarity). Rectifier circuit) 318 and output voltage detection means 323 and 324.

  As shown in FIG. 25, the voltage conversion means 1353 includes an operational amplifier 1455, an NPN transistor 1456, resistors 1450, 1451, 1457, 1458, capacitors 1452, 1453, 1454, and an electrolytic capacitor 1459. The emitter of the NPN transistor 1465 becomes the output of the voltage conversion means 1353.

The piezoelectric transformer drive circuit 1307 has the same configuration as the piezoelectric transformer drive circuit 307 of FIG. 7, but one end of the inductor 475 is connected to the output of the voltage conversion means 1353 instead of the 24 V power supply 303.
The rectifier circuit 317 and the output voltage detection means 323 are the same as those shown in FIG.

  The operational amplifier 1455 of the voltage converting means 1353 receives a signal obtained by smoothing the pulse width modulation signal PWS4 at its non-inverting input terminal (+), and a signal obtained by smoothing the detection voltage VB4 at its inverting input terminal (−). Input, so that the potential of the inverting input terminal (−) is equal to the potential of the non-inverting input terminal (+) (the smoothed detection voltage VB4 is equal to the smoothed pulse width modulation signal PWS4). Control).

As illustrated in FIG. 25, the voltage conversion unit 1354 includes an operational amplifier 1465, an NPN transistor 1466, resistors 1460, 1462, 1467, 1468, capacitors 1461, 1463, 1464, and an electrolytic capacitor 1469.
The emitter of the NPN transistor 1466 becomes the output of the voltage conversion means 1354.

  The piezoelectric transformer drive circuit 1308 has the same configuration as the piezoelectric transformer drive circuit 308 of FIG. 7, but one end of the inductor 488 is connected to the output of the voltage conversion means 1354 instead of the 24 V power source 303. The rectifier circuit 318 and the output voltage detection means 324 are the same as those shown in FIG.

  The operational amplifier 1465 of the voltage conversion means 1354 receives a signal obtained by smoothing the pulse width modulation signal PWS5 at its inverting input terminal (−), and a signal obtained by smoothing the detection voltage VB5 at the non-inverting input terminal (+). Input, so that the potential of the non-inverting input terminal (+) becomes equal to the potential of the inverting input terminal (−) (the smoothed detection voltage VB5 is equal to the smoothed pulse width modulation signal PWS5) Control).

FIG. 27 shows the arrangement of main circuit components on the printer engine control board / high-voltage board 301 of the third embodiment.
For example, as shown in FIG. 28, even-numbered pins # 50, # 52, # 54, # 56, # 58, and # 60 have a drive frequency corresponding to the pulse width modulation signals PWS0, PWS1, PWS2, PWS3, PWS4, and PWS5. Odd pins # 51, # 53, # 55, # 57, and # 59 are assigned to the signals DFS1, DFS2, DFS3, DFS4, and DFS5.
That is, when assigning pins of the printer engine control unit 1253 configured by an integrated circuit, both adjacent ones are not assigned to the drive frequency signal, and between the pins assigned to the drive frequency signal are converted to pulse width modulation signals. Assignment is performed so that the assigned pin is located.

The high voltage output timing during the image forming operation is the same as that described in connection with the first embodiment with reference to FIGS.
During the image forming operation, the piezoelectric transformer 309 for charging bias output, the piezoelectric transformer 310 for primary transfer positive bias output, and the piezoelectric transformer 312 for secondary transfer bias are simultaneously driven.
The drive frequency signal of 166 kHz of each transformer is not influenced by each other because the 10 kHz pulse width modulation signal is sandwiched between them. Since the piezoelectric transformers are also spaced apart from each other, they are not affected by the mutual output interference.

FIG. 29 shows a part for generating the drive frequency signal DFSi (i is any one of 1 to 5) and the pulse width modulation signal PWSi in the circuit formed in the printer engine control unit 1253. In the printer engine control unit 1253, five circuits similar to those shown in FIG. 29 are provided for generating drive frequency signals DFS1 to DFS5 and pulse width modulation signals PWS1 to PWM5, respectively.
In the circuit shown in FIG. 29, the pulse width modulation signal generation unit 1512, the fractional-N frequency divider 530 , the output selector 509, and the inverter 512 form part of the piezoelectric transformer control unit 1262.
The fractional-N divider 530 includes a 19-bit register 505 , an error holding register 507, an adder 506, and a divider 508.

The circuit portion shown in FIG. 29 further includes a set value register 1503, a duty instruction unit 1510, and a cycle instruction unit 1511.
A set value register 1503 holds a set value of the frequency division ratio. This frequency division ratio is represented by 19 bits and includes an integer part and a fractional part.

The cycle instruction unit 1511 sets the cycle of the pulse width modulation signal PWMi.
As the period of the pulse width modulation signal, a value represented by the number of periods of the 50 MHz clock is used. For example, when the frequency of the pulse width modulation signal PWMi is 10 kHz, a hexadecimal number 1388 hex corresponding to 5000 (50 MHz / 10 kHz) is set in the cycle instruction means 1511. The set period is supplied to the pulse width modulation signal generation unit 1512.

  The duty instruction means 1510 outputs a duty value 0 to 5000 corresponding to the target value (target voltage) of the bias voltage to be output by the corresponding bias voltage generator to the pulse width modulation signal generator 1512.

  The pulse width modulation signal generation unit 1512 outputs a signal of H, that is, a duty of 100% in an initial state when a negative bias is applied, and outputs a signal of L, that is, a duty of 0%, in an initial state when a positive bias is applied. ing. On the other hand, after the ON / OFF signal 511 becomes true and the output of the corresponding dynamic frequency signal DFSi is started (of the drive frequency signal DFSi supplied to the same bias generator as the pulse width modulation signal PWSi is supplied). After the output is started), output of a pulse width modulation signal having a duty corresponding to the target voltage is started.

The division value is stored in the set value register 1503, and the division ratio of the set value register 1503 is set as a division ratio in the 19-bit register 505 at the time of initialization. The frequency division ratio is, for example, 4B3A4hex.
In the third embodiment, the value of the 19-bit register 505 operates while maintaining the fixed value.
The operation of the fractional-N frequency divider 530 is the same as that of the first embodiment.

  As shown in FIG. 23, the output port OUT1 (an example of OUTi) outputs a drive frequency signal of 166 kHz. Since the output of this drive frequency signal is inverted by the inverter 512, the H level duty of the output of the port OUT1 is about 65%. The N-channel power MOSFET 424 is switched by a pulse of 166 kHz having an H level duty of about 35%. The pulse width modulation signal port PWM1 outputs a pulse width modulation signal PWS1 corresponding to the target value.

  The voltage obtained by smoothing the detection voltage of the output voltage detection means 320 by the operation of the voltage conversion means 1350, the piezoelectric transformer drive circuit 1304, the piezoelectric transformer 309, the rectification circuit 314, and the output voltage detection means 320 is a pulse width modulation signal. Control is performed such that the bias voltage output from the rectifier circuit 314 matches the target voltage so as to match the signal obtained by smoothing PWS1.

  Similarly to the charging bias generator, the other bias generators output a bias voltage controlled to a value corresponding to the duty of the pulse width modulation signal.

  As described above, by outputting only from the odd-numbered pins for outputting the drive frequency signal, interference between adjacent piezoelectric transformers can be eliminated, output ripple can be reduced, and a uniform image can be obtained. .

  Furthermore, it has become possible to integrate a conventional piezoelectric transformer control integrated circuit which is separate from the printer engine control integrated circuit.

  Further, by alternately arranging a driving frequency signal of 100 kHz or more and a pulse width modulation signal having a low output control frequency, it is possible to improve the efficiency of the integrated circuit by arranging the same type of signal outputs while suppressing interference of the driving frequency signals. Became.

In the third embodiment, pins and wirings for transmitting drive frequency signals DFS1 to OUT5 for driving the piezoelectric transformer are prevented from being mutually connected, and a pulse width modulation signal for controlling the output voltage level of the piezoelectric transformer is provided. Pins and wiring for transmission were interposed.
In other words, pins and wiring for transmitting a drive frequency signal with a large change in output waveform and pins and wiring for transmitting a pulse width modulation signal with a small change in output waveform are alternately arranged, resulting in a large change in the output waveform. Pins and wirings for transmitting the drive frequency signal are prevented from being in contact with each other.

  Although the present invention has been described as an image forming apparatus of a color four-cycle intermediate transfer system, it can be applied to a monochrome image forming apparatus or a tandem image forming apparatus.

  150 Secondary transfer bias generation unit 151 Primary transfer bias generation unit 152 Development bias generation unit 153 Charging bias generation unit 253 Printer engine control unit 262 Piezoelectric transformer control unit 304 to 308 Piezoelectric transformer drive circuit 309 to 313 Piezoelectric transformer, 314, 316, 318 Negative bias rectifier circuit, 315, 317 Positive bias rectifier circuit, 320 to 324 Output voltage detection means, 1253 Printer engine control unit, 1262 Piezoelectric transformer control unit, 1304 to 1308 Piezoelectric transformer drive circuit, 1350 to 1354 Voltage conversion means, OUT1 to OUT5 output port, PWM0 to PWM5 output port, WLD1 to WLD5 wiring, WLP0 to WLP5 wiring, # 1 to # 120 pins.

Claims (4)

A plurality of piezoelectric transformers;
A plurality of piezoelectric transformer drive circuits;
An integrated circuit that generates a plurality of drive frequency signals;
The driving frequency signal is assigned to only one of the even-numbered pins and the odd-numbered pins among the consecutive pins of the integrated circuit,
Pins located between pins for outputting the drive frequency signal are used for purposes other than the output of the drive frequency signal, connection to a power source, and connection to ground,
A pin for outputting a pulse width modulation signal having a frequency lower than the frequency of the driving frequency signal is arranged between the pins for outputting the driving frequency signal,
Pressure electric transformer driving apparatus you characterized in that the pulse width modulation signal is used to control the voltage output from the piezoelectric transformer. Applying a synchronous clock signal to the integrated circuit by a clock signal generating means;
The piezoelectric transformer driving device according to claim 1 , wherein the driving frequency signal and the pulse width modulation signal are generated by dividing the synchronous clock signal. The piezoelectric transformer driving device according to claim 1 or 2 ,
Said integrated circuit, an image forming apparatus control integrated circuit,
In the image forming apparatus control integrated circuit,
A drive frequency generation circuit for generating the drive frequency signal;
An image forming apparatus comprising: a pulse width modulation signal generation unit configured to generate the pulse width modulation signal. The piezoelectric transformer driving device according to claim 1 or 2,
The piezoelectric transformer driving device includes:
Formed in the same printed circuit board
The integrated circuit;
A high voltage generation circuit including the piezoelectric transformer driving circuit as a part thereof;
The integrated circuit is an engine control integrated circuit;
The engine control integrated circuit includes:
A driving frequency signal generating circuit for generating a drive frequency signal to drive the piezoelectric transformer,
A pulse width modulation signal generation circuit for generating a pulse width modulation signal,
The piezoelectric transformer is
A piezoelectric transformer for output of positive polarity bias;
Including a piezoelectric transformer for output of negative polarity bias,
Images formed equipment piezoelectric transformer you characterized in that it is arranged to be positioned alternately on the printed circuit board for the piezoelectric transformer and the negative polarity bias output for the output of the positive polarity bias .

Images