JP5769538B2 - High voltage power supply device and image forming apparatus - Google Patents

Description

  The present invention relates to a high-voltage power supply device that outputs a high-voltage direct current (hereinafter referred to as “DC”) voltage by controlling a piezoelectric transformer, and an image forming apparatus using the same.

  Conventionally, as a high-voltage power supply device used in an electrophotographic image forming apparatus, for example, in Patent Document 1 below, a high-voltage DC voltage obtained by rectifying an output voltage on a secondary side of a piezoelectric transformer is stepped down by an output voltage conversion unit. It is described that the low-voltage DC voltage is compared with the triangular wave voltage as the target setting means, and the frequency division ratio and the frequency division ratio change width are controlled according to the comparison result. In Patent Document 1, control at the time of starting up a high-voltage DC voltage is performed with a predetermined control gain.

JP 2010-16052 A

  However, the conventional high-voltage power supply device and image forming apparatus have the following problems (a) to (d) because the control at the time of starting the high-voltage DC voltage is performed with a predetermined control gain. .

(A) Due to variations in the step-up ratio and frequency characteristics of the piezoelectric transformer, the rising waveform of the high-voltage DC voltage may greatly overshoot, or the rising time of the high-voltage DC voltage may become long.

  (B) When the step-up ratio of the piezoelectric transformer is reduced under a low-temperature environment temperature, a large overshoot occurs in the rising waveform of the high-voltage DC voltage, or the rising time of the high-voltage DC voltage is increased. There is.

  (C) If an excessive overshoot occurs in the high-voltage DC voltage, it will deviate from the favorable range of the transfer bias in the image forming apparatus, resulting in density unevenness in printing immediately after the start of printing.

  (D) If the control gain is set too small so that no overshoot occurs in the high-voltage DC voltage, the transfer bias in the image forming apparatus does not rise to an appropriate voltage, and the print density immediately after the start of printing becomes light.

The high-voltage power supply apparatus of the present invention includes an oscillator that generates a clock signal, frequency dividing means that divides the clock signal by an input division ratio value and outputs a control signal, and a high-voltage that receives the control signal. Switching means for outputting a pulse signal, a piezoelectric transformer for inputting the high-voltage pulse signal and outputting a predetermined high-voltage AC (hereinafter referred to as “AC”) voltage, and converting the high-voltage AC voltage into a high-voltage DC voltage for output Rectifying means, output voltage converting means for converting the high voltage DC voltage into low voltage DC voltage, target value setting means for setting a target value corresponding to the high voltage DC voltage output from the rectifying means, and the target value And a frequency division ratio value control means for controlling the frequency division ratio value so as to be equal to the low voltage DC voltage and outputting the same to the frequency division means .

The frequency division ratio value control means raises the high voltage DC voltage with the control gain of the frequency division ratio value as a predetermined value when the high voltage DC voltage output from the rectifier means is raised for the first time. It is determined whether or not the overshoot amount of the DC voltage exceeds a threshold value. If the overshoot amount exceeds the threshold value, the control gain of the division ratio value is set at the next rise of the high voltage DC voltage. If the overshoot amount does not exceed the threshold value, the division ratio value is controlled to increase the control gain of the division ratio value at the next rise of the high-voltage DC voltage. Output.

The image forming apparatus of the present invention includes a high-voltage power supply apparatus of the invention, and forming an image by operating in the high DC voltage output from the high-voltage power supply apparatus to the storage medium.

According to the high-voltage power supply device of the present invention, the frequency division ratio value control means sets the control gain of the frequency division ratio value to the predetermined value and sets the high voltage DC voltage when the high voltage DC voltage output from the rectification means is raised for the first time. The division ratio value is controlled so that the control gain of the division ratio value is changed when the next high voltage DC voltage is raised depending on whether the amount of overshoot of the high voltage DC voltage exceeds the threshold. Yes. Therefore, even if the step-up ratio and frequency characteristics of the piezoelectric transformer vary, there is an effect that adaptive control is performed with a good rising waveform of the high-voltage DC voltage.

According to the image forming apparatus of the present invention, by providing a high-voltage power supply apparatus of the invention, startup characteristics of the high voltage DC voltage at the high voltage power supply, so that is adaptively controlled in a good start-up waveforms. Therefore, without the transfer bias or the like in an image forming apparatus deviates from the good range, there is an effect that can be maintained from immediately after the start of the image forming print density of the image in a good condition.

FIG. 1 is a block diagram showing an outline of a high-voltage power supply device according to Embodiment 1 of the present invention. FIG. 2 is a circuit diagram showing a detailed configuration example of the high-voltage power supply apparatus 70 of FIG. FIG. 3 is a configuration diagram illustrating the image forming apparatus 1 using the high-voltage power supply device according to the first embodiment of the present invention. FIG. 4 is a block diagram showing the configuration of the control circuit in the image forming apparatus 1 of FIG. FIG. 5 is a block diagram showing the configuration of the control unit 72 in FIG. FIG. 6 is a diagram showing an example of the table register 83 in FIG. FIG. 7 is a diagram showing an example of the table register 84 in FIG. FIG. 8 is a flowchart showing the flow of processing in the computing unit 82 in FIG. FIG. 9 is a flowchart showing the flow of processing in the arithmetic unit 91 in FIG. FIG. 10 is a timing chart showing the operation timing in the first embodiment. FIG. 11A is a diagram illustrating the relationship between the control target voltage and the output of the table register 84. FIG. 11B is a diagram illustrating the relationship between the frequency characteristics of the piezoelectric transformer and the output of the table register 83. FIG. 12 is a block diagram showing the configuration of the control circuit in the image forming apparatus 1 according to the second embodiment of the present invention. FIG. 13 is a block diagram showing an outline of a high-voltage power supply device 70A in Embodiment 2 of the present invention. FIG. 14 is a circuit diagram showing a detailed configuration example of the high-voltage power supply device 70A of FIG. FIG. 15 is a diagram showing the temperature set value generation means 53b in FIG. FIG. 16 is a block diagram showing a detailed configuration of the control unit 72A in FIG. FIG. 17A is a diagram illustrating an example of the table register 83A in FIG. 17-2 is a diagram showing an example of the table register 83A in FIG.

  Modes for carrying out the present invention will become apparent from the following description of the preferred embodiments when read in light of the accompanying drawings. However, the drawings are only for explanation and do not limit the scope of the present invention.

(Configuration of image forming apparatus)
FIG. 3 is a configuration diagram illustrating an image forming apparatus using the high-voltage power supply device according to the first embodiment of the present invention.

The image forming apparatus 1 is, for example, an electrophotographic color image forming apparatus, and a black developing device 2K, a yellow developing device 2Y, a magenta developing device 2M, and a cyan developing device 2C are detachably inserted. The developing units 2K, 2Y, 2M, and 2C are uniformly charged by the charging rollers 36K, 36Y, 36M, and 36C of the respective colors that are in contact with the photosensitive drums 32K, 32Y, 32M, and 32C of the respective colors. The charged photosensitive drums 32K, 32Y, 32M, and 32C are respectively latentized by light emission from the black light emitting element (hereinafter referred to as “LED”) head 3K, yellow LED head 3Y, magenta LED head 3M, and cyan LED head 3C. An image is formed.

Each color supply roller 33K, 33Y, 33M, 33C in each developing device 2K, 2Y, 2M, 2C supplies toner to each developing roller 34K, 34Y, 34M, 34C , and each color developing blade 35K, 35Y, 35M. , 35C uniformly form a toner layer on the surface of each developing roller 34K, 34Y, 34M, 34C, and develop a toner image on each photosensitive drum 32K, 32Y, 32M, 32C . The cleaning blades 37K, 37Y, 37M, and 37C in the developing devices 2K, 2Y, 2M, and 2C for the respective colors clean the residual toner after the transfer.

The black toner cartridge 4K, the yellow toner cartridge 4Y, the magenta toner cartridge 4M, and the cyan toner cartridge 4C are detachably attached to the developing devices 2K, 2Y, 2M, and 2C , and the internal toner is supplied to the developing devices 2K, 2Y, and 2C , respectively. It has a structure that can be supplied to 2M and 2C. The black transfer roller 5K, the yellow transfer roller 5Y, the magenta transfer roller 5M, and the cyan transfer roller 5C are arranged so that a bias can be applied from the back surface of the transfer belt 8 to the transfer nip. The transfer belt driving roller 6 and the transfer belt driven roller 7 have a structure capable of conveying the paper 15 as a recording medium by stretching the transfer belt 8 and driving the roller.

  The transfer belt cleaning blade 11 can scrape off the toner on the transfer belt 8, and the toner thus scraped off is accommodated in the transfer belt cleaner container 12. The paper cassette 13 is detachably attached to the image forming apparatus 1 and loaded with paper 15. The hopping roller 14 conveys the paper 15 from the paper cassette 13. The registration rollers 16 and 17 convey the paper 15 to the transfer belt 8 at a predetermined timing. The fixing device 18 fixes the toner image on the paper 15 by heat and pressure. The paper guide 19 discharges the paper 15 to the paper discharge tray 20 face down.

A sheet detection sensor 40 is provided in the vicinity of the registration rollers 16 and 17. This paper detection sensor 40 detects the passage of the paper 15 in contact or non-contact, and the transfer rollers 5K, 5Y, and 5M are determined from the time determined from the relationship between the distance from the sensor position to the transfer nip and the paper conveyance speed. , 5C determine the transfer bias application timing by the high-voltage power supply device 1 when the transfer is performed.

FIG. 4 is a block diagram showing the configuration of the control circuit in the image forming apparatus 1 of FIG.
The control circuit includes a host interface unit 50, and the host interface unit 50 transmits and receives data to and from the command / image processing unit 51. The command image processing unit 51 outputs image data to the LED head interface unit 52. The LED head interface unit 52 is controlled by the printer engine control unit 53 for head drive pulses and the like, and causes the LED heads 3K, 3Y, 3M, and 3C to emit light.

The printer engine control unit 53 receives a detection signal from the paper detection sensor 40 and sends control values such as a charging bias, a developing bias, and a transfer bias to the high voltage control unit 60. The high voltage controller 60 sends signals to the charging bias generator 101, the development bias generator 102, and the transfer bias generator 103. The charging bias generating unit 101 and the developing bias generating unit 102 include the charging rollers 36K, 36Y, 36M, and 36C and the developing rollers 34K of the black developing unit 2K, the yellow developing unit 2Y, the magenta developing unit 2M, and the cyan developing unit 2C. , 34Y, 34M, and 34C are biased. The control unit in the high-voltage control unit 60 and the transfer bias generation unit 103 constitute the high-voltage power supply device 70 according to the first embodiment of the present invention.

The printer engine control unit 53 drives the hopping motor 54, registration motor 55, belt motor 56, fixing device heater motor 57, and drum motors 58K, 58Y, 58M, and 58C for each color at predetermined timings. The temperature of the fixing device heater 59 is controlled by the printer engine control unit 53 in accordance with the detection value of the thermistor 65.

(Configuration of high-voltage power supply)
FIG. 1 is a block diagram showing an outline of a high-voltage power supply device 70 in Embodiment 1 of the present invention.

  The high-voltage power supply device 70 includes a control unit in the high-voltage control unit 60 and the transfer bias generation unit 103 in FIG. 4, and is provided for each color transfer roller 5 (= 5K, 5Y, 5M, 5C). . Since each color high-voltage power supply 70 has the same circuit configuration, only one circuit will be described below.

  The high-voltage power supply device 70 outputs a control signal output from the printer engine control unit 53 (for example, a reset signal RESET, an ON signal ON, and a target value of the output voltage of the high-voltage DC voltage, for example, a digital value of 8 bits (bit). Is input to the load ZL, which is the transfer roller 5, by generating the high voltage DC voltage S76.

  The printer engine control unit 53 includes target value setting means 53a for outputting a target value setting signal DATA, and a reset signal RESET, an ON signal ON, and a target value setting signal from a plurality of output terminals OUT2, OUT3, and OUT4, respectively. It has a function of outputting DATA to the control unit 72 in the high-voltage power supply device 70.

  The high-voltage power supply device 70 includes an oscillator 71 that generates a reference clock (hereinafter simply referred to as “clock”) S71 having a constant frequency (for example, 50 MHz), and the clock S71 is supplied to the control unit 72.

  The control unit 72 operates in synchronization with the 50 MHz clock S71, and generates the clock S71 supplied from the oscillator 71 based on the reset signal RESET, the ON signal ON, and the target value setting signal DATA supplied from the printer engine control unit 53. This circuit divides the frequency and outputs a piezoelectric transformer drive pulse (hereinafter simply referred to as “drive pulse”) S72 as a control signal. The control unit 72 includes an input terminal CLK_IN for inputting a clock S71, an input terminal IN1 for inputting a low voltage DC voltage S77, an input terminal IN2 for inputting a reset signal RESET, an input terminal IN3 for inputting an ON signal ON, and a target value setting signal DATA. Input terminal IN4 and an output terminal OUT1 for outputting a drive pulse S72.

  In the controller 72, the setting is initialized by the input reset signal RESET, and the on / off of the drive pulse S72 output from the output terminal OUT1 is controlled by the input on signal ON.

  In addition, instead of inputting the reset signal RESET at the input terminal IN2, it is also possible to omit the input of the ON signal ON to the input terminal IN3 by inputting a signal combining the reset signal RESET and the ON signal ON. It is. In the first embodiment, the 8-bit target value setting unit 53a is provided in the printer engine control unit 53. However, the target value setting unit 53a is provided on the control unit 72 side, and the target value setting signal DATA is transmitted to the control unit. It is also possible to use 72 internal signals.

The control unit 72 is, for example, an ASIC (Application Specific Integrated Circuit ; ASIC ) that is an integrated circuit in which a plurality of functional circuits are integrated into one for a specific application, a microprocessor with a central processing unit ( CPU ), or It is configured by a field programmable gate array ( FPGA ), which is a kind of gate array into which a user can write a unique logic circuit.

Switching means (for example, a piezoelectric transformer drive circuit) 74 is connected to the output terminal OUT1 of the controller 72 and the DC power source 73 that outputs DC 24V. The piezoelectric transformer drive circuit 74 is a circuit that outputs a high-voltage pulse signal S74 using a switching element, and a piezoelectric transformer 75 is connected to the output side. The piezoelectric transformer 75 performs a boosting use to drive voltage a resonance phenomenon of a piezoelectric vibrator such as ceramics, a transformer for outputting a high AC voltage S75, rectifying means to the output side (e.g., rectifier circuit) 76 It is connected.

  The rectifier circuit 76 is a circuit that converts the high-voltage AC voltage S75 output from the piezoelectric transformer 75 into a high-voltage DC voltage S76 and supplies it to the load ZL, and an output voltage conversion means 77 is connected to this output side.

The output voltage conversion means 77 is a circuit that converts the high-voltage DC voltage S76 into a low-voltage DC voltage S77. The low-voltage DC voltage S77 is supplied to an analog-digital converter (hereinafter referred to as “ADC”) 72b in the control unit 72. Has been.

1 is arranged in parallel for each color transfer roller 5 (= 5K, 5Y, 5M, 5C), that is, for each channel, but a part is shared by the plurality of channels. You may make it the structure to carry out. For example, the piezoelectric transformer 75 and the rectifier circuit 76 are required for a plurality of channels, but the oscillator 71 and the control unit 72 can share one set. In this case, the control unit 72 includes as many input / output terminals as the number of channels. The control unit 72 is provided in the high-voltage power supply 70, but may be provided in a large-scale integrated circuit ( LSI ) in the printer engine control unit 53.

FIG. 2 is a circuit diagram showing a detailed configuration example of the high-voltage power supply device 70 in FIG.
The oscillator 71 is, for example, a crystal oscillator, and operates by DC 3.3V supplied from the power supply 71a to generate a clock S71 having an oscillation frequency of 50 MHz. The oscillator 71 has a power supply voltage input terminal VDD, an output enable terminal OE, a clock output terminal CLK_OUT, and a ground terminal GND. The clock output terminal CLK_OUT is connected to the input terminal CLK_IN of the controller 72 via the resistor 71b.

  The controller 72 operates in synchronization with the clock S71, and outputs a drive pulse S72 from the output terminal OUT1 to the piezoelectric transformer drive circuit 74. A DC power source 73 is connected to the piezoelectric transformer drive circuit 74. The DC power source 73 is, for example, a DC 24V power source that is supplied by transforming and rectifying a commercial power source AC 100V (not shown).

The piezoelectric transformer drive circuit 74 includes resistors 74a and 74b that divide the drive pulse S72 input from the controller 72 , and a switching element (for example, an N-channel power MOSFET, hereinafter simply referred to as “NMOS”) that inputs the divided drive pulse S72. 74d), and an inductor 74c and a capacitor 74e that constitute a resonance circuit. In the piezoelectric transformer drive circuit 74, when the drive pulse S72 is input to the gate of the NMOS 74d via the resistors 74a and 74b, the DC 24V of the DC power source 73 is switched by the NMOS 74d, and this is a resonance composed of the inductor 74c and the capacitor 74e. A high voltage pulse signal S74 having a sine pulse wave having a peak of about AC 100 V is output by being resonated by the circuit.

  An input terminal 75a of the piezoelectric transformer 75 is connected to the output side of the resonance circuit of the piezoelectric transformer driving circuit 74. A high-voltage AC voltage S75 of 0 to several kV is output from the output terminal 75b of the piezoelectric transformer 75 according to the switching frequency of the NMOS 74d. Is output.

A rectifier circuit 76 is connected to the output terminal 75 b of the piezoelectric transformer 75. The rectifier circuit 76 is a circuit that converts the high-voltage AC voltage S75 output from the secondary-side output terminal 75b of the piezoelectric transformer 75 into a high-voltage DC voltage S76, and is configured by diodes 76a and 76b and a capacitor 76c. Yes. The transfer roller 5 as the load ZL is connected to the output side of the rectifier circuit 76 through the resistor 76d, and the output voltage conversion means 77 is connected.

The output voltage conversion means 77 is composed of resistors 77a, 77b, 77c, a capacitor 77d, and a voltage follower circuit 77e composed of an operational amplifier (hereinafter referred to as "op-amp"), and receives a high voltage DC voltage S76 and receives a low voltage DC. voltage (for example, the following low voltage DC 3.3V) and outputs the S77 to ADC72b in the control unit 72. When the high-voltage DC voltage S76 is input to one terminal of the resistor 77a, the divided DC voltage divided by the resistor 77a and the resistor 77b is input to one terminal of the resistor 77c, and the connection between the resistor 77c and the capacitor 77d. The DC voltage from which the ripple has been removed from the point is input to the voltage follower circuit 77e, and the low voltage DC voltage S77 is output from the output terminal of the voltage follower circuit 77e.

  In this output voltage conversion means 77, for example, the resistance value of the voltage dividing resistor 77a is 100 MΩ, the resistance value of the voltage dividing resistor 77b is 33 kΩ, and the high voltage DC voltage S76 output from the rectifier circuit 76 is about 3.3 / 10000. The low voltage DC voltage S77 is output.

The operational amplifier 77e, is DC24V is applied from the DC power supply 73, low DC voltages S77 to output of the voltage follower circuit comprising the operational amplifier 77e is adapted to Ru is supplied to the ADC 72b in the control unit 72.

(Configuration of control unit in high-voltage power supply)
FIG. 5 is a block diagram showing the configuration of the control unit 72 in FIG.

The ADC 72 b converts the analog low-voltage DC voltage S 77 input from the output voltage conversion unit 77 into a 12-bit value of a digital signal and outputs the digital signal to the calculator 82, the comparator 86, and the comparator 94. The calculator 82 receives the 12-bit value output from the ADC 72b and the target value 8bit value of the target value setting signal DADA, performs a predetermined process, and outputs a 5-bit value to the table register 83.

  The table register 83 has a function of outputting an 8-bit value corresponding to the 5-bit value input from the computing unit 82 to the multiplier 85. The table register 84 provided in the vicinity of the table register 83 has a function of outputting an 8-bit value corresponding to the input 7-bit value to the multiplier 85.

  The multiplier 85 multiplies the 8-bit value input from the table register 83 and the 8-bit value input from the table register 84 to generate a 16-bit value, and supplies it to the computing unit 91.

  The comparator 86 receives the upper 8 bits of the 12-bit value output from the ADC 72b and the 8 bits of the target value setting signal DATA, and outputs the H level or the L level to the calculator 91 depending on the relationship between both input values.

  The period value register 87 is a register for holding a pulse period value, and sets a 13-bit value period value in the timer 88. The timer 88 subtracts the set 13-bit value period value and outputs a signal that rises every time the count value of the timer 88 becomes 0 to the ADC 81 and the arithmetic unit 91.

  The counter lower limit register 89 and the counter upper limit register 90 are registers that respectively hold the division ratio value setting lower limit value and the division ratio value setting upper limit value. The counter lower limit value register 89 and the counter upper limit value register 90 are Each of the 9-bit value division ratio value setting lower limit value and the division ratio value setting upper limit value is configured to be output to the calculator 91.

  The calculator 91 calculates and updates the value of the 19-bit register 92 in accordance with signals input from the multiplier 85, the timer 88, the comparator 86, the counter lower limit register 89, and the counter upper limit register 90.

  The 19-bit register 92 is a 19-bit register in which the upper 9 bits are the division ratio value integer part and the lower 10 bits are the fractional part. The lower 7-bit value is output to the table register 84. The 19-bit register 92 receives the 19-bit value updated by the calculator 91 at a predetermined timing, and outputs the updated 19-bit value to the calculator 96.

  The calculator 93 outputs to the comparator 94 an 8-bit value obtained by adding 1/16 of the input value to the target value 8-bit value input at the rising edge of the ON signal ON. The calculation of adding 1/16 of the input value to the input value is equivalent to setting a threshold corresponding to the target value.

  The comparator 94 compares the upper 8-bit value of the 12-bit value output from the ADC 72b with the 8-bit value output from the calculator 93 during the period when the input of the ON signal ON is at the H level, and based on the result, compares the H level or the L level. Is output to the correction value register 95.

  The correction value register 95 is a register that corrects the value of the 19-bit register 92, and outputs an 8-bit value to the arithmetic unit 96 based on the H level or L level signal input from the comparator 94 and the ON signal ON.

  The arithmetic unit 96 inputs the 19-bit value updated by the operation output from the 19-bit register 92 and the 8-bit value output from the correction value register 92, and outputs the upper 9-bit value to the 1 adder (+1) 97 and the frequency divider selector 98. At the same time, the lower 10 bits (bits 9 to 0) are output to the error holding register 99.

  The error holding register 99 adds the 10-bit value output from the arithmetic unit 96 in synchronization with the rising edge of the divided pulse signal, and outputs an H level to the frequency dividing selector 98 when a carry occurs.

The 1 adder (+1) 97 outputs a 9-bit value obtained by adding 1 to the upper 9-bit value input from the computing unit 96 to the frequency divider selector 98. Dividing selector 98, based on the input signal from the error holding register 99, division of one 9bit value among the 9bit value input from 9bit value and 1 adder (+1) 97 which is inputted from the arithmetic unit 96 The ratio value is output to the frequency divider 100.

The frequency divider 100 outputs the input frequency division pulse signal having a 9-bit value period to the error holding register 99 and the output selector 101. The output selector 101 outputs the divided pulse signal output from the frequency divider 100 when the ON signal ON is at the H level, and outputs the L level when the ON signal ON is at the L level. In FIG. 5, a part constituted by a 19-bit register 92, an arithmetic unit 96, an adder (+1) 97, a frequency divider selector 98, an error holding register 99, a frequency divider 100, and an output selector 101 surrounded by a broken line is shown in FIG. The frequency division ratio binarization processing unit 102 is a frequency division ratio value setting unit that generates a frequency division ratio value and outputs a drive pulse.

FIG. 6 is a diagram illustrating an example of the table register 83 in FIG.
The table register 83 stores an 8-bit value corresponding to the 5-bit value input from the arithmetic unit 82, reads the 8-bit value corresponding to the 5-bit value input from the arithmetic unit 82, and outputs it to the multiplier 85. In FIG. 6, for example, if the input 5-bit value is 0 Bhex, the table register 83 outputs an 8-bit value of 06 hex.

FIG. 7 is a diagram showing an example of the table register 84 in FIG.
The table register 84 converts the inputted 7-bit value into an 8-bit value and outputs the converted value to the multiplier 85. The table register 84 stores an output value 8 bits and a division ratio integer part corresponding to an input value 7 bits in the range of 00 hex to 7 Fhex. For example, if the input value 7 bits is 0 Bhex, 54 hex is output as the output value 8 bits. The division ratio integer part is composed of 9 bits, the upper 2 bits in the division ratio integer part 9 bits are always “1” and “1”, and the lower 7 bits in the division ratio integer part 9 bits are the input value 7 bits. It corresponds to.

  In FIG. 5, the parts excluding the ADC 72b and the frequency divider 100 from the configuration of the frequency divider 100 and the control unit 72 correspond to the frequency dividing means 72a and the frequency division ratio value control means 72c in FIG.

(Overall operation of image forming apparatus)
3 and 4, when image data described in PDL (Page Description Language) or the like is input from an external device (not shown) via the host interface unit 50, the image forming apparatus 1 performs this printing. The data is converted into bitmap data (image data) by the command / image processing unit 51 and sent to the LED head interface unit 52 and the printer engine control unit 53. The printer engine control unit 53 controls the heater 59 in the fixing unit 18 according to the detection value of the thermistor 65, the heat fixing roller in the fixing unit 18 reaches a predetermined temperature, and the printing operation is started.

The paper 15 set in the paper feed cassette 13 is fed by the hopping roller 14. The sheet 15 is conveyed onto the transfer belt 8 by the registration rollers 16 and 17 at a timing synchronized with the image forming operation described below. In the developing devices 2K, 2Y, 2M, and 2C for the respective colors, toner images are formed on the photosensitive drums 32K, 32Y, 32M, and 32C by an electrophotographic process. At this time, the LED heads 3K, 3M, 3Y, and 3C are turned on according to the bitmap data. Each color developing unit 2K, 2Y, 2M, toner image developed by 2C is high-voltage power supply apparatus each transfer roller 5K from 70, 5Y, 5M, the DC bias of the high voltage applied to 5C, the upper transfer belt 8 It is transferred to the conveyed paper 15. After the four color toner images are transferred to the paper 15, they are fixed by the fixing device 18 and discharged.

(Operation of high-voltage power supply)
The operation of the high-voltage power supply device 70 will be described with reference to FIG.

  In the first embodiment, a four-output transfer high-voltage power supply device is used. Since four outputs have the same configuration, only one output will be described.

When the reset signal RESET is set to L level, the printer engine control unit 53 initializes the settings of the registers and the like in the control unit 72. Next, the printer engine control unit 53 outputs a target value setting signal DATA to the control unit 72. The 8-bit digital value of the target value setting signal DATA is in the range of 00 to FFhex, and this digital value range corresponds to the output voltage range of 0V to 10 kV.

  The printer engine control unit 53 turns on the ON signal while the sheet 15 in FIG. 3 is between the transfer rollers 5K, 5Y, 5M, and 5C and the photosensitive drums 32K, 32Y, 32M, and 32C at a predetermined timing. To H level. The presence or absence of the paper 15 is recognized by measuring a predetermined time corresponding to the paper transport speed from the detection timing by the paper detection sensor 40.

  When the ON signal ON becomes H level, the control unit 72 immediately outputs the drive pulse S72 from the output terminal OUT1.

  The piezoelectric transformer driving circuit 74 switches DC24V of the DC power source 73 by the driving pulse S72 input from the control unit 72, and applies a half-wave sine wave voltage to the input terminal 75a of the piezoelectric transformer 75. As a result, a sine wave high-voltage AC voltage S75 is output from the output terminal 75b of the piezoelectric transformer 75.

  The rectifier circuit 76 smoothes and rectifies the high-voltage AC voltage S75, and applies the high-voltage DC voltage S76 to the output load ZL, that is, the shafts of the transfer rollers 5K, 5Y, 5M, and 5C. The output voltage conversion unit 77 converts the high voltage DC voltage S76 into a low voltage DC voltage S77 in the range of 0 to 3.3 V, and supplies the low voltage DC voltage S77 to the ADC 72b of the control unit 72 via the input terminal IN1. .

  The frequency division ratio value control means 72c in the control unit 72 controls the frequency of the drive pulse S72 so that the 8-bit digital value of the target value setting signal DATA is equal to the upper 8-bit value of the converted value of the ADC 72b.

Based on FIG. 2, the operation of the circuit of the high-voltage power supply 70 will be described in detail.
The crystal oscillator 71 oscillates when 3.3 V is input to the input terminal VDD and the output enable terminal OE, and outputs a 50 MHz clock S71 from the clock output terminal CLK_OUT. The clock S71 is input to the input terminal CLK_IN of the control unit 72 via the resistor 71b.
The control unit 72 operates in synchronization with the clock S71, and outputs a drive pulse S72 with a 30% on duty obtained by dividing 50 MHz from the output terminal OUT1. The output drive pulse S72 is input to the gate of the NMOS 74d, and the DC 24V of the DC power source 73 is switched through the inductor 74c. A half-wave sine wave voltage is applied to the input terminal 75a of the piezoelectric transformer 75 by a resonance circuit including the inductance 74c, the capacitor 74e, and the piezoelectric transformer 75. As a result, a high- voltage AC voltage S75 corresponding to the switching frequency of the NMOS 74d is output from the output terminal 75b of the piezoelectric transformer 75 . The high voltage AC voltage S75 is rectified and smoothed by the diodes 76a and 76b and the capacitor 76c of the rectifier circuit 76, and outputs the high voltage DC voltage S76 to the resistor 76d and the output voltage conversion means 77.

  The high-voltage DC voltage S76 input to the output voltage converting means 77 is divided into about 3.3 / 100000 by a resistor 77a having a resistance value of 100 MΩ and a resistor 77b having a resistance value of 33 kΩ, and is subjected to an RC filter by a resistor 77c and a capacitor 77d. The ripple is removed, the impedance is converted by the operational amplifier 77e, and the converted signal is input to the ADC 72b via the input terminal IN1 of the control unit 72.

  The high voltage DC voltage S76 applies a bias to the load ZL via the resistor 76d. At this time, the controller 72 starts driving from a frequency of 384 (180 hex) at 130.21 kHz, that is, 50 MHz. While the detection value of the ADC 72b is less than the 8-bit digital value of the target value setting signal DATA, the drive frequency is lowered. When the target voltage is reached, the drive frequency is increased or decreased alternately. However, since there is a control delay, the drive voltage is controlled to a substantially constant average drive frequency, and the high-voltage DC voltage S76 is stabilized at a constant voltage.

(Operation of control unit in high-voltage power supply)
Based on FIG. 5, the operation of the control unit 72 in the high-voltage power supply 70 will be described.

  In the period value register 87, 13 bits of 1B58 hex and 7000 are set. The timer 88 counts down the value 7000 set by the period value register 87 with the clock S71 of 50 MHz until the value becomes 0, and when the count value becomes 0, it is set to 7000 again, and the count value of the timer 88 becomes 0. Every time, a signal having a period of 140 μsec that rises is output to the ADC 71b and the calculator 91.

  The ADC 72b AD-converts the low-voltage DC voltage S77 at the timing of the signal output from the timer 88, and outputs the resulting 12-bit value to the calculator 82 and the comparator 86.

FIG. 8 is a flowchart showing the flow of processing in the computing unit 82 in FIG.
In step S1, when the processing of the calculator 82 is started, the process proceeds to step S2. In step S2, it is determined whether or not the 8-bit target set value is 00 hex. If the target set value is 00 hex, the process proceeds to step S3. If the target set value is not 00 hex, the process proceeds to step S4.

  In step S3, it is determined whether or not the detected value of the ADC 72b is 020 hex or more. If the detected value of the ADC 71b is 020 hex or more, the process proceeds to step S5. If the detected value of the ADC 72b is less than 020 hex, the process proceeds to step S6.

  In step S4, it is determined whether or not a value obtained by dividing the detected value 12 bits of the ADC 72b by the target set value 8 bits is equal to or greater than 020 hex. If so, the process proceeds to step S7, and if smaller, the process proceeds to step S8.

  In step S5, the 5-bit output value of the calculator 82 is set to 1Fhex, and the process proceeds to step S9. In step S6, the 5-bit output value of the calculator 82 is set to the lower 5 bits of the detection value 12 bits of the ADC 72b, and the process proceeds to step S9. In step S7, the 5-bit output value of the calculator 82 is set to 1Fhex, and the process proceeds to step S9. In step S8, the 5-bit output value of the calculator 82 is set to a value obtained by dividing the detected value of the ADC 72b by the target set value, and the process proceeds to step S9. In step S9, the processing of the calculator 82 is terminated.

  In FIG. 5, the 5-bit output value output from the calculator 82 is input to the table register 83. As shown in FIG. 6, the table register 83 outputs an 8-bit value corresponding to a 5-bit value input.

  The table register 84 receives the 7-bit value (bit 16 to bit 10) output from the 19-bit register 92, and outputs an output 8-bit value corresponding to the input 7-bit value to the multiplier 85 as shown in FIG. The multiplier 85 multiplies the 8-bit value output from the table register 83 and the 8-bit value output from the table register 84 and outputs a 16-bit value to the computing unit 91.

The comparator 86 always outputs the L level when the L level of the ON signal ON is input, and the upper 8 bits of the target value 8 bits and the ADC 72b output while the H level of the ON signal ON is input. Depending on the value, the following H level or L level is output.
Target value 8bit value> H level when ADC72b output upper 8bit value Target value 8bit value ≤ ADC72b output upper 8bit value L level

FIG. 9 is a flowchart showing the flow of processing in the arithmetic unit 91 in FIG.
The calculator 91 updates the value of the 19-bit register 92. Although there is shown in the flowchart, the circuit is realized by hardware is described by the logic description language or the like.

  In step S21, when the processing of the calculator 91 is started, the process proceeds to step S22. In step S22, by inputting the reset signal RESET, 180 bits that are 9 bits set in the counter lower limit register 89 are set in the upper 9 bits of the 19-bit register 92, and 000 hex, that is, 60000 hex is set in the lower 10 bits. Proceed to step S23.

  In step S23, it is determined whether or not the rising edge of the timer 88 is detected. When the rising edge of the timer 88 is detected, the process proceeds to step S24, and when the rising edge of the timer 88 is not detected, the rising edge of the timer 88 is detected. The process of step S23 is repeated until an edge is detected.

  In step S24, it is determined whether or not the output signal of the comparator 86 is at the H level. If the output signal of the comparator 86 is at the H level, the process proceeds to step S25, and if the output of the comparator 86 is at the L level, step S24 is performed. Proceed to S26.

  In step S25, the arithmetic unit 91 adds the output 16-bit value of the multiplier 85 to the 19-bit value of the 19-bit register 92, and proceeds to step S27. Of the 19-bit output of the 19-bit register 93, the table register 84 receives a 7-bit value of bits 16 to 10 and outputs an 8-bit value. The 8-bit value of each of the table register 83 shown in FIG. 6 and the table register 84 shown in FIG. 7 is multiplied by the multiplier 85 and output as a 16-bit value.

  In step S26, the output 16-bit value of the multiplier 85 is subtracted from the 19-bit value of the 19-bit register 92, and the process proceeds to step S29.

  In step S27, if the upper 9 bits of the 19-bit value in the 19-bit register 92 is larger than the upper limit value 1CFhex of the counter upper limit value register 90, that is, 73C00 hex, the process proceeds to step S28. The process proceeds to step S31.

  In step S28, the upper 9 bits of the 19-bit value of the 19-bit register 92 are set to the upper limit value of the counter upper-limit value register 90, that is, 1CFhex, and the lower 10 bits are set to 3FFhex. That is, the 19-bit value is set to 73FFF hex, and the process proceeds to step S31.

  In step 29, if the upper 9 bits of the 19-bit value in the 19-bit register 92 is smaller than the lower limit value 180 hex of the counter lower-limit value register 89, that is, if the 19-bit value is less than 60000 hex, the process proceeds to step S30. Is greater than or equal to the lower limit value 180 hex of the counter lower limit value register 89, the process proceeds to step S31.

  In step S30, the upper 9 bits of the 19-bit value of the 19-bit register 92 is set to the lower limit value 180 hex of the counter lower-limit value register, and the lower 10-bit value is set to 000 hex, that is, the 19-bit value is set to 60000 hex.

  In step S31, the 19-bit value of the calculation result of the calculator 91 is set in the 19-bit register 92, and the process returns to step S23.

  By the processing of the arithmetic unit 91 described above, the 19-bit register value of the 19-bit register 92 is controlled in the range of 60000 to 73FFF.

  In FIG. 5, the arithmetic unit 93 outputs an 8-bit value obtained by adding 1/16 of the input value to the target value 8-bit value input at the rising edge of the ON signal ON to the comparator 94. For example, when 40 hex is input, 44 hex is output. The arithmetic unit 93 inputs a target value of 8 bits, and outputs an 8 bit value obtained by adding 1/16 of the input value to the comparator 94. This corresponds to the target set value of 8 bits. This corresponds to outputting 1.0625 times the value.

The comparator 94 inputs the upper 8 bits of the 12-bit value output from the ADC 72b, the 8-bit value output from the arithmetic unit 93, and the ON signal ON.
ADC72b output upper 8bit value ≧ operator 93 output 8bit value and
When the ON signal ON = H level, the H level is output to the correction value register 95, and otherwise, the L level is output to the correction value register 95.

  Here, when the output upper 8 bit value of the ADC 72b ≧ the output 8 bit value of the calculator 93, the overshoot amount at the rising of the high voltage DC voltage S76 in the high voltage power supply device 70 is 1.0625 times the set target value voltage. This is equivalent to exceeding the voltage (threshold).

  The correction value register 95 is an 8-bit register, is initialized to 00hex by the input of the reset signal RESET, the output signal of the comparator 94 and the ON signal ON are input, and the ON signal ON is in the H level period. When the output signal of the comparator 94 becomes H level, the H level is latched, and when the H level is latched at the falling edge of the ON signal ON, 1 is added to the 8-bit value, otherwise 1 is set. Subtract. Further, the correction value register 95 clears the H level latched at the falling edge of the ON signal ON.

FIG. 10 is a timing chart illustrating the operation timing in the first embodiment.
In FIG. 10, the horizontal axis is the time axis, and shows the timing of the reset signal RESET, the ON signal ON, the target value 8 bits, the output value of the calculator 93, the output signal of the comparator 94, and the correction value 8 bits.

  At the timing when the reset signal RESET falls from the H level to the L level, the correction value 8 bits of the correction value register 95 is initialized to 00 hex. Next, in a period in which the ON signal ON is at the H level, for example, in the period T <b> 1, the arithmetic unit 93 receives the target value 8 bit value “40 hex” and outputs “44 hex” to the comparator 94.

In the example of FIG. 10, in the period T1 of the ON signal ON at the H level, the output upper 8 bit value of the ADC 72b ≧ the output 8 bit value of the calculator 93 and the ON signal ON = H level. A level pulse 94a is output. Correction value register 95, so to latch the H level pulses 94a, by adding 1 to the initialization correction value 8bit value 00hex, the correction value 8bit to 01 hex.

  In the period T2 of the H level of the ON signal ON, the output upper 8 bit value of the ADC 72b <the output 8 bit value of the arithmetic unit 93, and therefore the H level output signal pulse 94b is not output from the comparator 94. Therefore, the correction value register 95 subtracts 1 from the previous correction value 8 bit value 01 hex and sets the correction value 8 bit to 00 hex. The same applies to the H level period T3 of the ON signal ON.

The comparator 94, the output value of the arithmetic unit 93 compares the 8bit value of the output voltage equivalent value detected by ADC72b, the ON signal ON is H level, i.e., a period that is on the high DC voltage S76 On the other hand, when the overshoot amount is 6.25% or more with respect to the target value voltage, the H level is output to the correction value register 95. The correction value register 95 adds 1 to the correction value when the overshoot amount is 6.25% or more with respect to the target value voltage, and subtracts 1 from the correction value otherwise.

  The 8-bit value in the correction value register 95 is a signed value. For example, it is −2 for FEhex, +2 for 0 hex, and is supplied to the arithmetic unit 96. The computing unit 96 calculates the 8-bit value of the correction value register 95 for the 19-bit value input from the 19-bit register 92, and performs addition / subtraction of the 8-bit value to the bit 18-8 of the 19-bit value. In the computing unit 96, for example, when the 19-bit value is 70000 hex and the 8-bit value is 01 hex, the sum is 70100 hex. If the 19-bit value is 70000 hex and the 8-bit value is FF hex, the value is subtracted to 6FF00 hex.

  The arithmetic unit 96 outputs the upper 9 bits of the operation result to the 1 adder (+1) 97 and the frequency divider selector 98. The frequency divider selector 98 receives the upper 9-bit value of the arithmetic unit 96 and the output 9-bit value of the 1 adder (+1) 97. Further, the lower 10 bits of the arithmetic unit 96 are input to the error holding register 99, and the error holding register 99 accumulates for each rising edge of the output signal of the frequency divider 100. As a result of the accumulation in the error holding register 99, a carry occurs, and when the 11th bit becomes 1, an H level selection signal Select is input to the frequency division selector 98.

  The frequency division selector 98 divides the output 9 bit value of the 1 adder (+1) 97 when the H level selection signal Select is input from the error holding register 99, and the output 9 bit value of the arithmetic unit 96 otherwise. Output to the peripheral 100. The frequency divider 100 outputs a drive pulse S72 obtained by dividing the clock S71 to the output selector 101 using the 9-bit value input from the frequency divider selector 98 as a frequency division ratio value.

  The output selector 101 outputs the drive pulse S72 output from the frequency divider 100 when the ON signal ON is at the H level, and outputs the L level when the ON signal ON is at the L level.

  Through the above processing, the upper 9-bit value of the 19-bit register 92 and the value obtained by adding 1 to the upper 9-bit are alternately output, and the average of the division ratio value is (upper 9-bit value) + (lower 10-bit / 1024).

  FIG. 11A is a diagram illustrating a relationship between the ratio of the high-voltage DC voltage S76 to the control target voltage and the output 8-bit value of the table register 84. FIG. 11B is a diagram illustrating a relationship between the frequency characteristic of the piezoelectric transformer 75 and the output value of the table register 83.

  In FIG. 11A, the horizontal axis represents time, and the vertical axis represents the ratio of the high-voltage DC voltage S76 to the control target voltage. A curve P is a curve that conceptually depicts the rising characteristics until the ON signal ON becomes H level and the high-voltage DC voltage S76 reaches the control target voltage.

  The 8-bit output value of the table register 84 for the range (1) to (16) of the ratio of the high-voltage DC voltage S76 to the control target voltage is described at the right position corresponding to the range (1) to (16). From FIG. 11A, it can be seen that the output value 8 bits of the table register 84 is varied depending on the ratio to the control target voltage. For example, when the control target voltage range is (1) to (5), the output value 8 bits of the table register 84 is a large value, for example, 80 hex, and the control target voltage range is (6) to (16). In this case, the output value 8 bits of the table register 84 changes from 60 hex to 01 hex as the number increases. From this, it can be seen that when the control target voltage is small, the control frequency fluctuation range is large, and when the control target voltage is close to the control target voltage, the control frequency fluctuation range is small.

  Furthermore, as shown in FIG. 11-2, the output characteristic Q with respect to the driving frequency of the piezoelectric transformer 75 depends on the frequency. When the output characteristic Q is in the vicinity of the peak, the change in the output voltage with respect to the frequency change is large. The change in output voltage is reduced.

  The table register 83 outputs a large value, for example, 80 hex, in a region where the change in the output voltage with respect to the frequency change is small, and outputs a small value, for example, 20 hex, in a region where the change in the output voltage is large. Further, since the control frequency value is shifted by the correction value register 95, the output value of the table register 83 is substantially shifted, and when added by the correction value, the table register 83 at the actual control frequency. The output value of the table register 83 at the actual control frequency becomes small when the output value is subtracted.

  As a result, a change occurs in the control gain, and the amount of overshoot is adjusted. If the overshoot amount exceeds 6.25%, the control gain is decreased, otherwise the control gain is increased. As a result, during continuous printing, the amount of overshoot is always adjusted to around 6.25% of the target set voltage.

(Modification of Example 1)
In the first embodiment, the gain correction amount is initialized by the reset signal RESET. However, the gain correction amount may be stored in a nonvolatile memory or the like and may be started from the previous correction amount.

  In the first embodiment, the overshoot amount is controlled to be around 6.25% with respect to the set target voltage. However, the value is not limited to this value, and other values such as 3% and 5% are used. It is also possible to adopt a configuration that can be varied according to the output target voltage instead of a fixed value.

(Effect of Example 1)
According to the first embodiment, there are the following effects (1) and (2).

  (1) According to the first embodiment, the control gain is increased or decreased depending on whether or not the overshoot amount exceeds the threshold in the output voltage rise control. For this reason, the control gain at the time of rising of the output voltage is optimally adjusted, and it becomes possible to control to a constant output voltage rising overshoot amount regardless of variations in the output voltage of the piezoelectric transformer 75.

  (2) It is possible to provide the high-voltage power supply device 70 that is always controlled to a constant output voltage rising overshoot amount regardless of variations in the output voltage of the piezoelectric transformer 75. As a result, the image forming apparatus 1 can maintain the image print density in a good state immediately after the start of image formation.

  The second embodiment of the present invention is the same as the configuration of the image forming apparatus 1 in FIG. 3 in the first embodiment, and the high-voltage power supply 70 in FIGS. 1 and 2 in the first embodiment and the control circuit in FIG. 4 are different. Hereinafter, a control circuit and a high voltage power supply device of the image forming apparatus according to the second embodiment will be described.

(Configuration of control circuit of image forming apparatus)
FIG. 12 is a block diagram illustrating a configuration of a control circuit in the image forming apparatus 1 according to the second embodiment of the present invention. Elements common to the elements in FIG. 4 illustrating the control circuit according to the first embodiment are denoted by common reference numerals. It is attached.

  In the control circuit of the second embodiment, a temperature detecting means (for example, a temperature sensor) 120 is added to the control circuit of the first embodiment shown in FIG. The temperature sensor 120 detects the environmental temperature of the place where the image forming apparatus 1 is installed, and supplies the detected temperature value to the printer engine control unit 53A having a configuration different from that of the printer engine control unit 53 of the first embodiment.

  In addition to the configuration of the printer engine control unit 53 of the first embodiment, the printer engine control unit 53A generates a temperature set value according to the temperature value obtained from the temperature sensor 120, and is different from the high pressure control unit 60 of the first embodiment. It has a function of outputting to the high voltage controller 60A having a different configuration.

  In addition to the function of the high-voltage control unit 60 of the first embodiment, the high-voltage control unit 60A has a function of correcting the control gain at the time of starting up the output voltage according to the environmental temperature of the place where the image forming apparatus 1 is installed. doing. The control unit in the high-voltage control unit 60A and the transfer bias generation unit 103 constitute the high-voltage power supply device 70A of the second embodiment. Other configurations are the same as those of the first embodiment shown in FIG.

(Configuration of high-voltage power supply)
FIG. 13 is a block diagram illustrating an outline of a high-voltage power supply device 70A according to the second embodiment. Elements common to the elements in FIG. 1 illustrating the high-voltage power supply device 70 according to the first embodiment are denoted by the same reference numerals. .

  FIG. 14 is a circuit diagram showing a detailed configuration example of the high-voltage power supply device 70A of FIG. 13, and the same reference numerals are used for elements common to the elements in FIG. 2 showing the circuit diagram of the high-voltage power supply device 70 of the first embodiment. Is attached.

  A printer engine control unit 53A having a configuration different from that of the printer engine control unit 53 of the first embodiment is connected to the high voltage power supply apparatus 70A of the second embodiment. In the printer engine control unit 53A, a temperature set value generation unit 53b is added to the target value setting unit 53a having the same configuration as that of the first embodiment.

The temperature set value generation means 53b has a function of outputting a 3-bit value of the temperature set value signal TMP corresponding to the range of the temperature value of the environmental temperature detected by the temperature sensor 120 to the control unit 72A in the high voltage power supply device 70A. ing. In the second embodiment, the temperature setting value generation unit 53b is provided in the printer engine control unit 53. However, the temperature setting value generation unit 53b is provided on the control unit 72A side, and the temperature setting value 3 bits is supplied to the control unit 72. It is also possible to use an internal signal.

In the control unit 72A, an input terminal IN5 is added to the input terminals CLK_IN , IN1, IN2, IN3, IN4, and the output terminal OUT1 of the control unit 72 of the first embodiment. The controller 72A includes a frequency dividing means 72a and an ADC 72b having the same configuration as in the first embodiment, and a frequency dividing ratio value controlling means 72c in the first embodiment instead of the frequency dividing ratio value controlling means 72c in the first embodiment. A frequency division ratio value control means 72d having a different configuration is provided.

The division ratio value control means 72d is a 12-bit value output from the ADC 72b, an 8-bit value of the target value setting signal DATA input from the target value setting means 53a, and a temperature setting value signal TMP input from the temperature setting value generation means 53b. The 3-bit value is input, and the division ratio value that is updated and controlled according to the input value is output to the frequency dividing means 72a.

Other configurations of the high-voltage power supply device 70A are the same as those of the high-voltage power supply device 70 of the first embodiment.
FIG. 15 is a diagram showing the temperature set value generation means 53b in FIG.

The temperature set value generation means 53b is provided in the printer engine control unit 53A, and outputs a 3-bit value of the temperature set value signal TMP corresponding to the temperature value range of the environmental temperature detected by the temperature sensor 120. For example, when the environmental temperature is in the range of 10 ° C. to 19 ° C., the 3-bit value of the temperature set value signal TMP is 3 hex.

(Configuration of control unit in high-voltage power supply)
FIG. 16 is a block diagram illustrating a detailed configuration of the control unit 72A in FIG. 13. Elements common to the elements in FIG. 5 illustrating the control unit 72 of the first embodiment are denoted by common reference numerals. .

  In the control unit 72A of the second embodiment, the table register 83, the correction value register 95, and the frequency division ratio binarization processing unit 102 of the first embodiment are replaced with a table register 83A having a different configuration from the above, and a correction value. A register 95A and a frequency division ratio binarization processing unit 102A are provided.

The correction value register 95A receives the 3-bit value of the temperature setting value signal TMP, the output signal of the comparator 94, and the ON signal ON, and outputs the temperature correction value 3-bit value to the table register 83A.

  The table register 83A selects one input / output table from among a plurality of input / output tables based on the input temperature correction value 3bit value, and inputs the output 5-bit value of the calculator 82 based on the selected input / output table. Are output to the multiplier 85.

  The frequency division ratio binarization processing unit 102A is provided with a 19-bit register 92A having a configuration different from those of the 19-bit register 92 and the arithmetic unit 96 of the first embodiment.

The 19-bit register 92A is a 19-bit register in which the upper 9 bits are the integer part of the division ratio value and the lower 10 bits are the fractional part. The lower 7-bit value is output to the table register 84. When the 19-bit value updated by the arithmetic unit 91 is input to the 19-bit register 92A , the higher-order 9 bits of the 19-bit value are output to the 1 adder (+1) 97 and the frequency divider selector 98, and the 19-bit register 92A. The lower 10 bits (bits 9 to 0) of the value are output to the error holding register 99.

17A and 17B are diagrams illustrating an example of the table register 83A in FIG.
The table register 83A is composed of eight input / output tables, and based on the input / output table selected by the temperature correction value 3bit value in the range of 0 hex to 7hex output from the correction value register 95A, the input value 5bit value. The output value corresponding to 8 bits is output. For example, when the temperature correction value 3 bit value output from the correction value register 95A is 3 hex, if the 5 bit value output from the computing unit 82 is 0 hex, an 8 bit value 04 hex is output.

Other configurations of the control unit 72A are the same as those of the control unit 72 of the first embodiment.
In the above configuration, the second embodiment is the same as the first embodiment except for the operation of the control unit 72A in the high-voltage power supply device 70A. Hereinafter, the operation of the control unit 72A in the high-voltage power supply device 70A, which is different in operation from the first embodiment, will be described.

(Operation of control unit in high-voltage power supply)
Based on FIG. 16, the operation of the controller 72A will be described.

The temperature set value generation means 53b in the pulling engine control unit 53 generates a 3-bit value temperature set value signal TMP as shown in FIG. 15 according to the temperature value obtained from the temperature sensor 120, and sends it to the control unit 72A. Output.

The correction value register 95A is set with the 3-bit value of the temperature setting value signal TMP input from the temperature setting value generating means 53b when the reset signal RESET changes from the H level to the L level. Similarly to the first embodiment, the correction value register 95A calculates the temperature correction value 3bit value by adding or subtracting the set temperature setting value 3bit value depending on whether or not the overshoot amount exceeds the threshold value. A 3-bit value is output to the table register 83A.

  The correction value register 95A performs addition only when the temperature correction value 3 bit value becomes the minimum temperature correction value 0hex, and holds 0hex at the time of subtraction. The correction value register 95A performs subtraction only when the temperature correction value 3 bit value reaches the maximum temperature correction value 7hex, and holds 7hex at the time of addition. As a result, the correction value register 95A outputs the temperature correction value 3 bit value of eight kinds of values from 0 hex to 7 hex to the table register 83A.

The addition / subtraction method is the same as that of the first embodiment except that the number of temperature correction value bits is changed from 8 bits to 3 bits and the value becomes an unsigned integer.

(Effect of Example 2)
According to the second embodiment, since the input / output table in the table register 83A is selected according to the environmental temperature, in addition to the effects of the first embodiment, the following (3) to (5) There is a great effect.

(3) According to the second embodiment, the correction value register 95A outputs the temperature correction value 3 bit value corresponding to the environmental temperature to the table register 83A, and the input / output in the table register 83A according to the temperature correction value 3 bit value. A table is selected. Therefore, the high-voltage power supply device 70A can start up the high-voltage DC voltage S76 with little overshoot even immediately after starting at a low temperature environment temperature.

  (4) During the period when the ON signal ON is at the H level, the comparator 94 determines whether or not the overshoot amount of the low-voltage DC voltage S77 exceeds the threshold value, and the temperature is set by adding or subtracting the temperature set value 3 bit value based on this determination. A correction value of 3 bits is calculated. Therefore, the high-voltage power supply device 70A can start up the high-voltage DC voltage S76 immediately after startup under a low-temperature environment temperature and during continuous driving.

  (5) The control gain for raising the output voltage is switched depending on whether or not the overshoot amount exceeds the threshold and the environmental temperature. As a result, it is possible to control the start-up of the optimum output voltage regardless of the environmental temperature, and it is possible to form an image with a stable quality immediately after starting and during continuous driving.

(Other variations)
Although the present invention has been described as the transfer high-voltage power supply of the color tandem image forming apparatus 1, the present invention is not limited to color, and is also applicable to other image forming apparatuses such as monochrome and monochrome image forming apparatuses. Is possible. The high voltage power supply devices 70 and 70A for transfer can also be applied to other high voltage power supplies such as charging.

DESCRIPTION OF SYMBOLS 1 Image forming apparatus 53, 53A Printer engine control part 53a Target voltage setting means 53b Temperature set value generation means 70, 70A High voltage power supply 71 Oscillator 72, 72A Control part 72a Frequency dividing means 72b ADC
72c, 72d Frequency division ratio control means 74 Piezoelectric transformer drive circuit 75 Piezoelectric transformer 76 Rectifier circuit 77 Output voltage conversion means

Claims (6)

An oscillator for generating a clock signal;
Frequency dividing means for dividing the clock signal by the inputted division ratio value and outputting a control signal;
Switching means for inputting the control signal and outputting a high voltage pulse signal;
A piezoelectric transformer that inputs the high-voltage pulse signal and outputs a predetermined high-voltage AC voltage;
Rectifying means for converting the high-voltage AC voltage into a high-voltage DC voltage and outputting it;
Output voltage conversion means for converting the high-voltage DC voltage into a low-voltage DC voltage;
Target value setting means for setting a target value corresponding to the high-voltage DC voltage output from the rectifying means ;
Frequency division ratio value control means for controlling the frequency division ratio value so that the target value and the low-voltage DC voltage are equal to each other and outputting the same to the frequency division means,
The frequency division ratio value control means includes:
When the high-voltage DC voltage output from the rectifier is first raised, the high-voltage DC voltage is raised with the control gain of the division ratio value set to a predetermined value, and the overshoot amount of the high-voltage DC voltage reaches a threshold value. When the overshoot amount exceeds the threshold, the control gain of the division ratio value is reduced at the next rise of the high-voltage DC voltage, and the overshoot amount is If the threshold value is not exceeded, the division ratio value is controlled and output so as to increase the control gain of the division ratio value at the next rise of the high voltage DC voltage. Power supply. The frequency division ratio value control means further includes
Frequency division ratio value setting means for setting the frequency division ratio value to be output to the frequency dividing means;
Lower limit value setting means for setting a lower limit value of the division ratio value,
The high-voltage power supply apparatus according to claim 1, wherein the division ratio value is increased or decreased based on the lower limit value. The control gain is
Held as a digital value,
The change of the control gain is
3. The high-voltage power supply device according to claim 1, wherein the high-voltage power supply device is performed by adding and subtracting the frequency division ratio value. The control gain is
Held in multiple tables as multiple digital values,
The change of the control gain is
The high-voltage power supply device according to claim 1, wherein the high-voltage power supply device is performed by switching and reading the plurality of tables. The high-voltage power supply device according to claim 4 further includes:
Having temperature detection means for detecting the ambient temperature and outputting the detected temperature;
According to the detected temperature, the control gain is corrected by reading the digital value from a table selected from the plurality of tables. A high-voltage power supply device according to any one of claims 1 to 5,
An image forming apparatus that operates by the high-voltage DC voltage output from the high-voltage power supply device to form an image on a storage medium.

Images