JP5944171B2 - Piezoelectric transformer drive device, high-voltage power supply device, and image forming apparatus - Google Patents

Description

  The present invention relates to a piezoelectric transformer driving device for driving a piezoelectric transformer, a high-voltage power supply device using the piezoelectric transformer, and an image forming apparatus having the high-voltage power supply device.

  2. Description of the Related Art Conventionally, a piezoelectric transformer driving device of a high-voltage power supply device used in an image forming apparatus has a high voltage by boosting a low voltage using a resonance phenomenon of a piezoelectric vibrator, as described in Patent Document 1 below, for example. The piezoelectric transformer for obtaining the above is driven by digital control to output a high voltage. This piezoelectric transformer driving apparatus drives a piezoelectric transformer by generating a drive pulse by dividing a reference clock signal (hereinafter simply referred to as “clock”) by a fractional value based on a divided value consisting of an integer value and a decimal value. ing.

JP 2010-178464 A

  However, the piezoelectric transformer driving device of the high voltage power supply device used in the conventional image forming apparatus realizes high resolution frequency control by fractional frequency division, but the driving frequency is frequency-modulated by one clock cycle. As a result, there is a problem that a low-frequency ripple in a high-voltage direct current (hereinafter referred to as “DC”) output voltage increases as compared with the case of driving at an unmodulated frequency.

A piezoelectric transformer driving device according to the present invention is a piezoelectric transformer driving device that applies a driving voltage to a piezoelectric transformer that is driven by an intermittent driving voltage and outputs a high output voltage, and generates an oscillation. Means, the clock, the detection value corresponding to the output voltage, and the target value of the output voltage are input, the detection value and the target value are compared, and the detection value and the target value become equal As described above, N (where N is an integer) and N + 1 divided values are generated, each consisting of an integer value and a decimal value , and updated every pulse of a fixed period. Fractional frequency dividing means for generating a control pulse by dividing the clock by a fraction; pulse output means for inputting the control pulse , averaging the phase difference between the frequency division values of N and N + 1, and outputting a drive pulse; The drive pulse And a, a piezoelectric transformer driving means for outputting a driving voltage to be applied to the piezoelectric transformer is more driven.
The pulse output means compares the control pulse generated by the divided values of N and N + 1 with the drive pulse and outputs a phase comparison signal, and smoothes the phase comparison signal. And a voltage-controlled oscillator that updates the frequency of the drive pulse for each control pulse based on the control voltage.

The high-voltage power supply device of the present invention includes the piezoelectric transformer, the piezoelectric transformer driving device, output detection means for detecting the output voltage and supplying the detection value to the fractional frequency dividing means, and a target for setting the target value. with a value setting means, characterized by Rukoto.

The image forming apparatus of the present invention is driven by the output voltage output from the high-voltage power supply device, and forms an image on a recording medium .

According to the piezoelectric transformer driving device, the high-voltage power supply device, and the image forming apparatus of the present invention, the fractional frequency dividing means generates the frequency division values N and N + 1 based on the detection value corresponding to the output voltage and the target value, The pulse output means averages the phase difference between the N divided value and the N + 1 divided value, outputs a drive pulse, and continuously variably controls the output frequency. Thereby, the low frequency ripple in the high voltage output voltage output from the piezoelectric transformer can be reduced.

FIG. 1 is a block diagram showing the configuration of the high-voltage power supply device in FIG. 3 according to Embodiment 1 of the present invention. FIG. 2 is a configuration diagram illustrating the image forming apparatus according to the first exemplary embodiment of the present invention. FIG. 3 is a block diagram showing a configuration of a control circuit in the image forming apparatus of FIG. FIG. 4 is a circuit diagram showing a configuration example of the high-voltage power supply device of FIG. FIG. 5 is a circuit block diagram showing the PLL circuit and loop filter in FIG. FIG. 6 is a circuit block diagram showing the configuration of the high voltage control unit in FIG. FIG. 7 is a characteristic diagram showing output voltage / frequency in the piezoelectric transformer in FIG. FIG. 8 is a block diagram showing the error holding register in FIG. FIG. 9 is a diagram showing the relationship among the frequency divider pulse period, the error holding register value, the lower 10-bit value of the 18-bit (hereinafter referred to as “bit”) register, and the adder input signal in FIG. FIG. 10 is a circuit diagram showing peripheral circuits in the PLL circuit in FIG. FIG. 11 is a flowchart showing the operation of the high voltage controller in FIG. FIG. 12 is a waveform diagram showing a driving voltage applied to the piezoelectric transformer in the comparative example. FIG. 13 is a schematic diagram illustrating a drive voltage applied to the piezoelectric transformer in the comparative example. FIG. 14 is a waveform diagram showing a drive voltage applied to the piezoelectric transformer of FIG. 4 in Embodiment 1 of the present invention. FIG. 15 is a block diagram showing a configuration of a control circuit in Embodiment 2 of the present invention. FIG. 16 is a block diagram showing a configuration example of the high-voltage power supply device in FIG. FIG. 17 is a circuit diagram showing a configuration example of the high-voltage power supply device of FIG. FIG. 18 is a circuit block diagram showing the configuration of the high voltage control unit in FIG. FIG. 19 is a diagram illustrating the counter, the lower 8 bits of the 18-bit register, and the comparator in FIG. FIG. 20 is a diagram showing the relationship between the divided pulse period, the counter replacement output 8 bits, the lower 10-bit value of the 18-bit register, and the adder input signal in FIG.

  Modes for carrying out the present invention will become apparent from the following description of the preferred embodiments when read in light of the accompanying drawings. However, the drawings are only for explanation and do not limit the scope of the present invention.

(Configuration of image forming apparatus)
FIG. 2 is a configuration diagram illustrating the image forming apparatus 1 according to the first exemplary embodiment of the present invention.

The image forming apparatus 1 is, for example, an electrophotographic color image forming apparatus, and a plurality of color developing devices 2 (for example, a black developing device 2K, a yellow developing device 2Y, a magenta developing device 2M, and a cyan developing device 2C). And a light emitting diode (hereinafter referred to as “LED”) head 3 (for example, a black LED head 3K, a yellow LED head 3Y, a magenta LED head 3M, and a cyan LED head 3C) as a multi-color exposure apparatus. . In each color developing device 2 (= 2K, 2Y, 2M, 2C), each color toner cartridge 4 (= 4K, 4Y, 4M, 4C), each color charging roller 5 (= 5K, 5Y, 5M, 5C) , Each color supply roller 6 (= 6K, 6Y, 6M, 6C), each color developing roller 7 (= 7K, 7Y, 7M, 7C), each color developing blade 8 (= 8K, 8Y, 8M, 8C), each color Photoconductor drums 9 (= 9K, 9Y, 9M, 9C) and cleaning blades 10 (= 10K, 10Y, 10M, 10C) for the respective colors are provided.

Each developing device 2 is uniformly charged by each charging roller 5 in contact with each internal photosensitive drum 9 . An electrostatic latent image is formed on each charged photosensitive drum 9 by the light emission of each LED head 3. Each supply roller 6 supplies toner as a developer to each developing roller 7. When each developing blade 8 uniformly forms a toner layer on the surface of each developing roller 7, a toner image is developed on each photosensitive drum 9. Each cleaning blade 10 cleans residual toner after transfer. Each toner cartridge 4 is detachably mounted in each developing device 2 and is configured to supply the internal toner to each developing device 2.

  Below each developing device 2, a transfer roller 11 (= 11K, 11Y, 11M, 11C) for each color, a transfer belt driving roller 12, and a transfer belt driven roller 13 are provided. Each transfer roller 11 is arranged so that a bias voltage (hereinafter simply referred to as “bias”) can be applied from the back surface of the transfer belt 14 to the transfer position. The transfer belt driving roller 12 and the transfer belt driven roller 13 are configured such that a transfer belt 14 is stretched and a recording medium (for example, paper) can be conveyed by driving the rollers 12 and 13.

  A cleaning blade 15 and a cleaner container 16 are provided in the vicinity of the transfer belt 14, and a paper cassette 17 is detachably attached below the transfer belt 14. The cleaning blade 15 can scrape off the toner on the transfer belt 14, and the toner thus scraped off is stored in the cleaner container 16. Sheets 17 a are stacked in the sheet cassette 17.

  A paper feed roller 18, a paper guide 19, and a pair of registration rollers 20 and 21 are disposed between the front end of the paper cassette 17 and the transfer belt driving roller 12. The paper feed roller 18 takes out the paper 17 a from the paper cassette 17 and feeds it to the paper guide 19. The fed paper 17a is conveyed along the paper guide 19 and abutted against the pair of stopped registration rollers 20 and 21 to be skew-corrected (deviation corrected). The pair of registration rollers 20 and 21 are driven at a predetermined timing after the skew correction of the sheet 17 a and are configured to convey the sheet 17 a to the transfer belt 14.

  A fixing device 22 is disposed on the downstream side of the transfer belt driven roller 13. The fixing device 22 has a pair of heat fixing rollers 23 and 24, and fixes the toner image on the paper 17a by heat and pressure. A pair of discharge rollers 25 and 26, a paper guide 27, and a paper discharge tray 28 are provided on the downstream side of the fixing device 22. The sheet 17 a is transported along a sheet guide 27 by a pair of discharge rollers 25 and 26 and is discharged face-down to a sheet discharge tray 28.

  FIG. 3 is a block diagram showing a configuration of a control circuit in the image forming apparatus 1 of FIG.

  The control circuit has a host interface unit 31, and the host interface unit 31 transmits and receives data to and from the command / image processing unit 32. The command image processing unit 32 outputs image data to the LED head interface unit 33. The LED head interface unit 33 is controlled by the printer engine control unit 34 with a head drive pulse or the like, and causes the LED heads 3K, 3Y, 3M, and 3C to emit light.

  The printer engine control unit 34 sends control values such as a charging bias, a developing bias, and a transfer bias to a fractional frequency dividing means (for example, a high voltage control unit) 41. The high voltage control unit 41 sends a signal to the charging bias generation unit 42, the development bias generation unit 43, and the transfer bias generation unit 44. The charging bias generating unit 42 and the developing bias generating unit 43 include the charging rollers 5K, 5Y, 5M, and 5C and the developing rollers 7K of the black developing unit 2K, the yellow developing unit 2Y, the magenta developing unit 2M, and the cyan developing unit 2C. , 7Y, 7M, 7C are biased. The high voltage controller 41 and the transfer bias generator 44 constitute a high voltage power supply device according to the first embodiment of the present invention.

  The printer engine control unit 34 drives the hopping motor 51, registration motor 52, belt motor 53, fixing device heater motor 54, and drum motors 55K, 55Y, 55M, and 55C for each color at predetermined timings. The temperature of the fixing device heater 22b is controlled by the printer engine control unit 34 in accordance with the detection value of the thermistor 22a.

(Configuration of high-voltage power supply)
FIG. 1 is a block diagram showing a configuration of the high-voltage power supply device 60 in FIG. 3 according to the first embodiment of the present invention.

  The high-voltage power supply device 60 includes the high-voltage controller 41 and the transfer bias generator 44 in FIG. 3, and is provided for each color transfer roller 11 (= 11K, 11Y, 11M, 11C). Since each color high-voltage power supply 60 has the same circuit configuration, only one circuit will be described below.

  The high-voltage power supply 60 includes an on / off signal ON / OFF (hereinafter simply referred to as “signal ON / OFF”) supplied from the output port OUT1 of the printer engine control unit 34 and a reset signal supplied from the output port OUT2. RESET (hereinafter, simply referred to as “signal RESET”) is input, and target data DATA representing an 8-bit target value is input from the output port OUT3 of the printer engine control unit 34, which is target value setting means, and DC high This is a device that generates a voltage and supplies it to an output load 83 as the transfer roller 11.

The high voltage power supply device 60 includes a piezoelectric transformer driving device 70, a piezoelectric transformer 80, a rectifier circuit 81 as a rectifier, an output voltage converter 82 as an output detector, and the like.

  The piezoelectric transformer driving device 70 is a device for driving the piezoelectric transformer 80, and includes a high voltage control unit 41, an oscillation circuit 71 as an oscillation means, a phase lock loop (hereinafter referred to as "PLL") circuit 72, a loop filter 73, a DC power source. 74, and a piezoelectric transformer driving circuit 75 as piezoelectric transformer driving means. The oscillation circuit 71 is a circuit that is composed of a crystal oscillator and generates a clock CLK having a constant frequency (for example, 25 MHz), and a high voltage control unit 41 is connected to the output side.

The high voltage control unit 41 is a circuit that operates in synchronization with the clock CLK supplied from the oscillation circuit 71, for example, and outputs a control pulse S41a under the control of the printer engine control unit 34. The clock input for inputting the clock CLK Port CLKIN, input port IN11 for inputting the signal ON / OFF output from the output port OUT1 of the printer engine control unit 53, input port IN12 for inputting the signal RESET output from the output port OUT2 of the printer engine control unit 34, printer The input port IN13 for inputting the target data DATA output from the output port OUT2 of the engine control unit 34, the input port IN14 for inputting the detection signal S82 representing the detection value, and the output port for outputting the control pulse S41aS to the PLL circuit 72 OUT11 And to the PLL circuit 72 has an output port OUT12 of outputting a prohibition pulse S41b.

In the high voltage control unit 41, ON / OFF of the output in the control pulse S41a from the output port OUT11 and the inhibition pulse S41b from the OUT12 is controlled by the input signal ON / OFF, and the high voltage control unit is controlled by the input signal RESET. The registers in 41 are initialized.

  The high-voltage control unit 41 is configured by, for example, an ASIC (Application Specific Integrated Circuit, hereinafter referred to as “ASIC”) that is an integrated circuit in which a plurality of functional circuits are integrated into one for a specific application.

  A PLL circuit 72 that outputs a drive pulse S72 synchronized with the control pulse S41a is connected to the output ports OUT11 and OUT12 of the high voltage controller 41. The PLL circuit 72 includes, for example, an integrated circuit (hereinafter referred to as “IC”) such as HC4046 provided by semiconductor manufacturers. A loop filter 73 is connected to the PLL circuit 72.

A piezoelectric transformer drive circuit 75 is connected to the output side of the PLL circuit 72. The piezoelectric transformer drive circuit 75 is a circuit that outputs a drive voltage S75 using a switching element, and a piezoelectric transformer 80 is connected to the output side. The piezoelectric transformer 80 is a transformer that boosts the driving voltage by using a resonance phenomenon of a piezoelectric vibrator such as ceramic and outputs an AC output voltage S80 that is a high voltage of alternating current (hereinafter referred to as “AC”). Rectifying means (for example, a rectifier circuit) 81 is connected to the output side. The rectifier circuit 81 is a circuit that converts the AC output voltage S80 output from the piezoelectric transformer 80 into a DC output voltage S81 that is a high DC voltage, and supplies the DC output voltage S81 to the output load 83. Is connected.

The output voltage conversion means 82 is a circuit that converts the DC output voltage S81 output from the rectifier circuit 81 into a low voltage. This output side is an 8-bit analog-digital converter (hereinafter referred to as “8-bit ADC”) via the input port IN14 of the high-voltage controller 41. ))) 91. The output voltage converter 82 outputs a low DC voltage to the 8-bit ADC 91 in the high voltage controller 41 as a detection signal S82.

Incidentally, high-voltage power supply apparatus 60 of FIG. 1, the transfer roller 11 of each color (= 11K, 11Y, 11M, 11C) each, that is, juxtaposed in each channel, a shared part with respect to the plurality of channels You may make it the structure to carry out. For example, the piezoelectric transformer 80 and the rectifier circuit 81 are required for a plurality of channels, but the oscillation circuit 71 and the high voltage controller 41 can be shared by one set. In this case, the high voltage controller 41 includes as many input / output ports as the number of channels. The high voltage control unit 41 is provided in the high voltage power supply device 60, but may be provided in a large scale integrated circuit (hereinafter referred to as “LSI”) in the printer engine control unit 34.

FIG. 4 is a circuit diagram showing a configuration example of the high-voltage power supply device 60 of FIG.
The oscillation circuit 71 has a crystal oscillator 71 a, and one end of the crystal oscillator 71 a is connected to one end of the capacitor 71 b and the clock input port CLKIN of the high voltage controller 41. The other end of the capacitor 71b is connected to one end of the capacitor 71c, and the other end of the capacitor 71c is connected to the other end of the crystal oscillator 71a and one end of the resistor 71d. The other end of the resistor 71d is connected to one end of the resistor 71e and the clock output port CLKOUT of the high voltage control unit 41. The other end of the resistor 71e is connected to one end of the crystal oscillator 71a and the clock input port CLKIN.

  The oscillation circuit 71 oscillates at a frequency determined by the crystal oscillator 71 a and has a function of supplying the clock CLK to the high voltage control unit 41. In the first embodiment, the crystal oscillator 71a is used, but another oscillator such as a ceramic oscillator may be used. Constants are determined for the capacitors 71b and 71c and the resistors 71d and 71e in accordance with matching with the high voltage control unit 41.

  The output port OUT11 of the high voltage control unit 41 is connected to the input port SIGNIN of the PLL circuit 72, and the output port OUT12 of the high voltage control unit 41 is connected to the input port INH of the PLL circuit 72.

The high voltage control unit 41 is configured to input the target data DATA as an 8-bit parallel signal at the input port IN13. The target data DATA is not limited to 8 bits, and may be composed of 10 bits or 12 bits, or may be a serial signal. The high voltage control unit 41 receives the detection signal S82 in the 8-bit ADC 91 and converts it into a conversion detection signal S91 which is an 8-bit digital signal. When the signal ON / OFF is at a high level (hereinafter referred to as “H”). The control pulse 41a is controlled so that the target data DATA and the conversion detection signal S91 are equal. When the high voltage control unit 41 inhibits the output of the PLL circuit 72, the inhibition pulse S41b is set to H from the output port OUT12 and outputted.

  The PLL circuit 72 is supplied with a voltage of 5 V from the DC power source 76. In the PLL circuit 72, the control pulse S41a input from the input port SIGIN and the piezoelectric transformer drive pulse (hereinafter referred to as “drive pulse”) output from the output port VCOOUT. .) S72 is input to the input port COMPIN for comparison, and the compared phase comparison signal is output from the output port PC2OUT to the loop filter 63. The input port VCOIN receives the smoothed signal from the loop filter 73.

  When the inhibition pulse S41b becomes a low level (hereinafter referred to as “L”), the PLL circuit 72 is activated, and the drive pulse S72 is output from the output port VCOOUT. The drive pulse S72 is synchronized with the control pulse S41a input to the input port SIGIN.

  The loop filter 73 includes a resistor 73a and a capacitor 73b. One end of the resistor 73a is connected to the output port PC2OUT of the PLL circuit 72, and the other end of the resistor 73a is one end of the capacitor 72b and the input port of the PLL circuit 72. Connected to VCOIN. The other end of the capacitor 72b is connected to the ground GND.

  A piezoelectric transformer drive circuit 75 is connected to the output port VCOOUT of the PLL circuit 72, and a DC power source 74 is connected to the piezoelectric transformer drive circuit 75. The DC power source 74 is, for example, a DC 24V power source that is supplied by transforming and rectifying AC1OOV that is a commercial power source from a low-voltage power supply device (not shown).

  The piezoelectric transformer drive circuit 75 includes a resistor 75a, a power transistor (for example, an N-channel power MOSFET, hereinafter referred to as “NMOS”) 75b that is a switching element, and an inductor 75c and a capacitor 75d that form a resonance circuit. Yes. The output port VCOOUT of the PLL circuit 72 is connected to the gate of the NMOS 75b. The inductor 75c and the NMOS 75b are connected in series between the DC power supply 74 and the ground GND, and the capacitor 75d is connected in parallel to the NMOS 75b between the drain and source of the NMOS 75b.

  In the piezoelectric transformer drive circuit 75, the drive pulse S72 output from the PLL circuit 72 is input to the gate of the NMOS 75b via the resistor 75a. Then, the DC power source 74DC24V is switched by the NMOS 75b, and this is resonated by the inductor 75d and the capacitor 75c of the resonance circuit, so that a half-wave sine wave drive voltage S75 is output.

  In the first embodiment, the inductor 75c has been described. However, an autotransformer or the like can be used. Moreover, it is realizable not only by NMOS but also by bipolar transistor. If the load is large and the current flowing between the drain and source of the NMOS 75b is large, a gate drive circuit may be provided between the output port VCOOUT and the NMOS 75b.

The primary side input terminal 80a of the piezoelectric transformer 80 is connected to the output side of the resonance circuit. From the secondary side output terminal 80b of the piezoelectric transformer 80, AC voltage of 0 to several KV is selected according to the switching frequency of the NMOS 75b. An output voltage S80 is output. As shown in FIG. 7, the output voltage characteristics of the output terminal 80b on the secondary side vary depending on the frequency, and the boost ratio is determined by the switching frequency of the NMOS 75b.

  A rectifier circuit 81 for AC / DC conversion is connected to the secondary-side output terminal 80 b of the piezoelectric transformer 80. The rectifier circuit 81 is a circuit that converts the AC output voltage S80 output from the output terminal 80b on the secondary side of the piezoelectric transformer 80 into a DC output voltage S81 and outputs the DC output voltage S81. Yes. In the first embodiment, the output of the rectifier circuit 81 is a positive bias output. However, if the anodes and cathodes of the diodes 81a and 81b are mounted in opposite directions, a negative bias can be easily output. The DC high voltage signal is smoothed by the capacitor 81 c and a bias is applied to the output load 83 via the resistor 84.

An output voltage conversion means 82 is connected to the output side of the rectifier circuit 81. The output voltage conversion means 82 divides the DC output voltage S81 of the rectifier circuit 81 and converts it to a DC low voltage, voltage dividing resistors 82a and 82b, a resistor 82c and a capacitor 82d constituting a filter circuit, and the filter circuit. And an operational amplifier (hereinafter referred to as “op-amp”) 87e for inputting a DC low voltage.

The DC output voltage S81 of the rectifier circuit 81 is divided by the resistor 82a and the resistor 82b, and the ripple component is removed by the filter circuit constituted by the resistor 82c and the capacitor 82d. Then, the impedance is converted by the operational amplifier 82e, and is input to the 8-bit ADC 91 as the detection signal S82 via the input port IN14 of the high voltage controller 41. For example, when the resistor 82a is 100 MΩ and the resistor 82b is 100 kΩ, the DC high voltage is converted into a DC low voltage at 100 / (100 + 100000). For example, when the DV high voltage is 5000V, the DC low voltage is 5V. When the detection signal S82 input to the ADC 91 is controlled to be FF hex (hex; indicating a hexadecimal number), the DC high voltage is 5000V. For example, if 80 hex is set as the target data DATA and control is performed so that the 8-bit ADC input value becomes 80 hex, the DC high voltage becomes 2510V. This numerical value is an example, and the constant may be changed according to the output voltage range.

  FIG. 5 is a circuit block diagram showing the PLL circuit 72 and the loop filter 73 in FIG.

The PLL circuit 72 and the loop filter 73 constitute pulse output means . The pulse output means compares the control pulse S41a with the drive pulse S72, outputs a phase comparison signal S72a, receives the phase comparison signal S72a, smoothes it, and outputs a control voltage S73. It has a loop filter 73 and a voltage controlled oscillator (hereinafter referred to as “VCO”) 72b that changes the frequency of the drive pulse S72 based on the control voltage S73.

(Configuration of the high voltage control unit in the high voltage power supply)
FIG. 6 is a circuit block diagram showing a configuration of the high voltage control unit 41 in FIG. FIG. 7 is a characteristic diagram showing output voltage / frequency in the piezoelectric transformer 80 in FIG. FIG. 8 is a block diagram showing the error holding register 98 as the second register in FIG. Further, FIG. 9 is a diagram showing the relationship among the frequency divided pulse S99 period in FIG. 6, the error holding register 98, the lower 10-bit value of the 18-bit register 96 as the first register, and the adder input signal.

  The clock CLK is a 25 MHz clock signal input from the oscillation circuit 71, and the internal circuit operates in synchronization with this signal. The 8-bit ADC 91 has a function of converting an analog signal of 0 to 5 V, which is the detection signal S82 input from the output voltage conversion means 82 at a predetermined conversion cycle, into an 8-bit digital signal of 00 hex to FF hex. The conversion cycle may be on the order of microseconds (hereinafter referred to as “μsec”) and does not need to be synchronized with the control cycle.

  The comparator 92 compares the 8-bit target data DATA input from the printer engine control unit 34 with the 8-bit detection signal S82. If the target data DATA is larger than the detection signal S82, H is not large. Has a function of outputting L to the 18-bit register 96.

  The 18-bit register 96 increases or decreases the set value of the 18-bit register 96 according to the signal from the comparator 92 at the input of the rising edge of the pulse input from the timer 95.

The piezoelectric transformer 80 has characteristics as shown in FIG. That is, the piezoelectric transformer 80 obtains the maximum step-up ratio at the resonance frequency fx, and the step-up ratio becomes the minimum near the frequency fy. In the first embodiment, the frequency is controlled in the range from the start frequency fstart to the frequency fend higher than the resonance frequency fx.

  For example, in the first embodiment, fy is about 130 kHz, fx is about 107 kHz, and the drive frequency range is set to 130 (fstart) to 108 (fend) kHz.

  The upper limit register 93 is set to 39DEBhex when converted to a value obtained by multiplying 231.48, which is a frequency division value corresponding to 108 kHz (9.259 μsec in period), by 1024, 237053, and a hexadecimal number.

  In the lower limit register 94, 30133 hex is set when converted into a value obtained by multiplying a frequency division value of 192.3 by 1024, 196915, and a hexadecimal number corresponding to 130 kHz (with a period of 7.692 μsec).

The timer 95 has a frequency divider, divides the clock CLK, and outputs a pulse. This pulse period becomes the control period. For example, a pulse of 250 clock cycles is output if it is 10 μsec, and a clock cycle of 2500 clock cycles is output if it is 100 μsec. The control cycle is preferably 200 μsec or less, but is appropriately adjusted for mounting. While a first embodiment the fixed period, it may be added signal for setting the control period from the printer engine control unit 34.

  The 18-bit register 96 is a register for setting a frequency division value. The upper 8 bits are an integer part for storing an integer value, and the lower 10 bits are a fractional part for storing a decimal value. (Upper 8 bits) + (Lower 10 bits) / 1024 is the average frequency division value. When the signal RESET becomes H, the 18-bit value of the lower limit register 94 is set in the 18-bit register 96. The 18-bit register 96 is configured to increase or decrease the set value of the 18-bit register 96 based on the signal from the comparator 92 at the input of the rising edge of the pulse input from the timer 95.

The 18-bit register 96, the adder 97, the error holding register 98, and the frequency divider 99 constitute a fractional frequency divider as a fractional frequency dividing means .

The fractional frequency divider is a fractional N frequency divider, and the value of the fractional part is accumulated in the error holding register 98. When the added value of the fractional part value overflows, the error holding register 98 outputs the overflow signal of the first logic (for example, H) to the adder 97, and otherwise the second logic value (for example, L) . It has a function of outputting an overflow signal. The adder 97 receives the upper 8-bit value S96b which is an integer part of the 18-bit register 96, adds 1 when the output signal of the error holding register 98 is H, and adds 0 when the output signal is L. The function of outputting to the device 99 is provided.

The frequency divider 99 inputs N or N + 1 when the value of 8 bits, which is the integer part of the 18-bit register 96, is N (where N is an integer), and outputs a divided pulse S99 with a 50% duty N or N + 1 frequency division. It is designed to output.

  In FIG. 8, the error holding register 98 receives an error holding register body 98a that holds the addition result of the lower 10-bit value S96a of the 18-bit register 96, and a lower 10-bit value S96a of the 18-bit register 96, and the value of the error holding register body 98a. And an adder 98b for storing the addition result in the error holding register main body 98a.

The adder 98b adds the lower 10-bit value S96a of the error holding register 98 to the value of the error holding register main body 98a, and replaces the addition result with bits 0-10 and the lower 11 bits of the error holding register 98. The addition is performed using the rising edge of the divided pulse S99 output from the frequency divider 99 as a trigger, and the value of bit10 is shifted to bit11 simultaneously with the addition. Bit10 is cleared to 0 after the value is shifted to bit11. Although bit 11 of the error holding register in FIG. 8 is provided for explanation, it may be omitted.

In FIG. 9, the period of the frequency divider pulse S99 indicates the count of pulses output from the frequency divider 99. The 12-bit value of the error holding register 98 is 000 hex in the initial state. The lower 10-bit value S96a of the 18-bit register is, for example, 12 Chex. This value is 300/1024 = about 0.3. The error holding register value is updated as shown in FIG. 9 every time the divider 99 outputs the divided pulse S99 , and L or H is output to the adder 97. Yes. An error is added to the fractional value, and when a carry occurs, the fractional value is added to the division value integer part. As a result, the average frequency converges to the value specified by the 18-bit register 96 .

In FIG. 6, the output selector 100 outputs a control pulse S41a to the PLL circuit 72 when the signal ON / OFF becomes H. At the same time, the inhibition signal S41b obtained by inverting the signal ON / OFF via the inverter 101 is input to the input port INH of the PLL circuit 71. The PLL circuit 72 outputs a drive pulse S72 having a frequency synchronized with the control pulse S41a to the piezoelectric transformer drive circuit 75. In the control pulse S41a, the cycle is switched between N frequency division and N + 1 frequency division in a short time, but the signal input to the VCOIN port of the PLL circuit 72 is smoothed by the loop filter 73. From the PLL circuit 72, the 18 bit register A drive pulse S72 having a frequency corresponding to the digital value set to 96 is output.

  For example, when the target data DATA is 300.5 and the set value of the 18-bit register 96 is 220.5 × 1024 = 2255792, that is, 37200 hex, the frequency is 220 divided, 113.63 kHz (25 MHz / 220) and 221 divided, 113. A 12 kHz pulse is alternately output from the high voltage control unit 41, but a 113.38 kHz pulse is output from the PLL circuit 72 to the piezoelectric transformer drive circuit 75.

  In the first embodiment, the fraction part is 10 bits and the reference frequency is 25 MHz. However, the number of bits in the fraction part can be arbitrarily selected, and the reference frequency can also be arbitrarily selected. Further, although the fractional frequency divider has been described by the fractional N method, a threshold matrix may be used or a random number may be used if a plurality of frequency division ratios can be switched in a short time.

FIG. 10 is a circuit diagram showing a peripheral circuit in PLL circuit 72 in FIG.
The PLL circuit 72 is an IC such as HC4046, for example. The resistor 73a and the capacitor 73b constitute a loop filter 73. In the first embodiment, the loop filter is described as a lag filter, but other filters such as a lag lead filter may be used. A capacitor 73 c that is a bypass capacitor of the DC power source 76 is connected to the input port Vcc of the DC power source 76. The capacitor 100 and the resistors 73d and 73e are elements that determine the oscillation frequency range of the VCO 72b, and are adjusted so that the oscillation frequency range includes the piezoelectric transformer driving range of 100 to 130 kHz of the first embodiment. Since the oscillation frequency variable range of the VCO 72b has a range of 100 times or more, the minimum frequency is adjusted to about 10 kHz.

(Overall Operation of Image Forming Apparatus of Embodiment 1)
With reference to FIG. 2 and FIG. 3, the schematic operation of the entire image forming apparatus in the first embodiment will be described.

  In the image forming apparatus 1 of FIG. 2, the host interface unit 31 in FIG. 3 inputs print data described in PDL (Page Description Language) from an external device (not shown). The input print data is converted into bitmap data by the command / image processing unit 32 and output to the LED head interface unit 33 and the printer engine control unit 34. Then, the printer engine control unit 34 controls the LED head interface unit 33, the motor control unit 35, the high voltage control unit 36, and the like. The printer engine control unit 34 controls the fixing device heater 22b in accordance with the detection signal of the thermistor 22a provided in the fixing device 22 to bring the pair of heat fixing rollers 23 and 24 in the fixing device 22 to a predetermined temperature. Thereafter, the printing operation is started.

When the paper feed roller 18 is driven by the hopping motor 51 controlled by the printer engine control unit 34, the paper 17 a stacked in the paper cassette 17 is taken out one by one and fed to the paper guide 19. The fed paper 17 a is conveyed along the paper guide 19, abutted against the pair of stopped registration rollers 20 and 21, and skew is corrected by driving the registration motor 52. Next, the passage of the sheet 17a is detected by a sheet detection sensor (not shown), and this detection signal is sent to the printer engine control unit 34. Under the control of the printer engine control unit 34, the belt motor 53 is synchronized with the image forming operation. The plurality of drum motors 55K, 55Y, 55M, and 55C for driving the fixing device heater motor 54 and the plurality of photosensitive drums 9 (= 9K, 9Y, 9M, and 9C) start driving. At the same time, a plurality of LED heads 3 (= 3K, 3Y, 3M, 3C) are driven by the operation of the LED head interface unit 33, and the charging bias generating unit 42 and the developing bias generating unit controlled by the high voltage control unit 41. The plurality of developing devices 2 (= 2K, 2Y, 2M, 2C) starts to be driven by the operation of 43, and further, the plurality of transfer rollers 11 are operated by the operation of the transfer bias generating unit 44 controlled by the high voltage control unit 41. (= 11K, 11Y, 1h1M, 11C) starts driving.

  When the driving of the belt motor 53 is started, the paper 17 a is conveyed onto the transfer belt 14 by the pair of registration rollers 20 and 21.

  Each developing device 2 (= 2K, 2Y, 2M, 2C) forms a toner image on each internal photosensitive drum 9 (= 9K, 9Y, 9M, 9C) by an electrophotographic process. At this time, each LED head 3 (= 3K, 3Y, 3M, 3C) is turned on according to the bitmap data. The four color toner images developed by the developing devices 2 (= 2K, 2Y, 2M, 2C) by the transfer bias applied to the transfer rollers 11 (= 11K, 11Y, 11M, 11C) are transferred to the transfer belt 14. The image is transferred onto the paper 17a conveyed on the top. The paper 17a on which the four color toner images are transferred is fixed by pressing and heating the four color toner images by the fixing device 22, and then along the paper guide 27 by the pair of discharge rollers 25 and 26. The paper is conveyed and discharged to the paper discharge tray 28 face down.

(Operation of the high-voltage power supply device of Example 1)
An outline of the operation of the high-voltage power supply device 90 of FIG. 1 will be described.

  The transfer bias in the first embodiment controls the four colors of the image forming apparatus 1, that is, the four channels of the high voltage output independently, but the configuration and operation of each control are the same. Only the operation will be described.

The printer engine control unit 34 sequentially turns on the transfer bias of four colors (K, Y, M, C) at a predetermined timing with reference to a paper detection signal from a paper detection sensor (not shown), that is, outputs it from the output port OUT1. The signal ON / OFF is set to H to turn on the transfer bias. The timing of the transfer bias off is the timing at which the paper 17a passes over the transfer rollers 11 (= 11K, 11Y, 11M, 11C) of each color with reference to the paper detection signal from the paper detection sensor. When the transfer bias application, and outputs a signal RESET of L to the input port IN12 of the high voltage controller 41 from the output port OUT2 of the printer engine control unit 34 initializes the various settings in the high-pressure control unit 41.

Next, the printer engine control unit 34 outputs the 8-bit target data DATA for the high-voltage DC output voltage S81 from the output port OUT3 to the input port IN13 of the high-voltage control unit 41 .

  The printer engine control unit 34 changes the signal ON / OFF output from the output port OUT1 from L to H at the timing of applying the transfer bias after outputting the target data DATA from the output port OUT3.

In the 8-bit ADC 91, the high-voltage controller 41 receives the detection signal S82 and converts it into a conversion detection signal S91 that is an 8-bit digital signal. When the signal ON / OFF is H, the target data DATA and the conversion detection signal S91 are converted. The control pulse S41a is controlled so as to be equal. When prohibiting the output of the PLL circuit 72, the high voltage controller 41 sets the prohibit pulse S41b to H from the output port OUT12 and outputs it. The drive pulse S72 output from the PLL circuit 72 is input to the piezoelectric transformer drive circuit 75.

The piezoelectric transformer drive circuit 75 switches DC24V supplied from the DC power supply 74 and applies a drive voltage S75 of a sine half wave voltage to the primary side input terminal 80a of the piezoelectric transformer 80. When the driving voltage S75 is input to the primary side input terminal 80a , the piezoelectric transformer 80 vibrates and boosts the high voltage AC output voltage S80 according to the driving frequency from the secondary side output terminal 80b to the rectifier circuit 81. Output. The rectifier circuit 81 rectifies the input high-voltage AC output voltage S80, outputs a positive-polarity high-voltage DC output voltage S81, and supplies it to the output load 83 and the output voltage conversion means 82.

  The output voltage converter 82 converts the high-voltage DC output voltage S81 into a DC-converted voltage in the range of 0 to 5.0 V, and outputs it as a detection signal S82 to the ADC 91 via the input port IN14 of the high-voltage controller 41.

(Detailed operation of the high-voltage power supply device of Example 1)
The operation of the high-voltage power supply device 60 of FIG. 4 will be described in detail.

The 25 MHz clock CLK generated by the oscillation circuit 71 is input to the clock input port CLKIN of the high voltage controller 41. When the signal RESETH input from the printer engine control unit 34 to the input port IN12 becomes L, the high voltage control unit 41 initializes various settings of the internal circuit. When the signal ON / OFF input from the printer engine control unit 34 to the input port IN11 changes from L to H, the high voltage control unit 41 divides the clock CLK by a fraction by a division value composed of an integer value and a decimal value. The control pulse S41a is output from the output port OUT11.

The control pulse S41a is input to the input port SIGIN in the PLL circuit 72. The PLL circuit 72 is supplied with a voltage of 5 V from the DC power source 76 , and the control pulse S41a input from the input port SIGIN and the drive pulse S72 output from the output port VCOOUT are input to the input port COMP and compared. The phase comparison signal S72a is output from the output port PC2OUT to the loop filter 73. The loop filter 73 smoothes the phase comparison signal S72a and outputs it to the input port VCOIN of the PLL circuit 72. When the inhibition pulse S41b becomes L, the PLL circuit 72 is activated and outputs a drive pulse S72 from the output port VCOOUT. The drive pulse S72 is phase-synchronized with the control pulse S41a input to the input port SIGIN by the PLL circuit 72.

The drive pulse 72 is applied to the gate of the NMOS 75b via the resistor 55a of the piezoelectric transformer drive circuit 75, and the NMOS 75b is turned on / off. By the on / off operation of the NMOS 75b, the resonance circuit constituted by the inductor 75c and the capacitor 75d is driven, and a driving voltage S75 having a sine half-wave voltage is applied to the primary side input terminal 80a of the piezoelectric transformer 80, and this piezoelectric The transformer 80 vibrates. As a result, a high-voltage AC output voltage S80 is output from the output terminal 80b on the secondary side of the piezoelectric transformer 80.

  The high-voltage AC output voltage S80 is rectified by the rectifier diodes 81a and 81b and the capacitor 81c in the rectifier circuit 81, and a high-voltage DC output voltage S81 that is a positive bias is output. The output high-voltage DC output voltage S81 is supplied to the output load 84 via the resistor 84.

  The output voltage conversion means 82 connected to the output side of the rectifier circuit 81 divides the high-voltage DC output voltage SS81 into about 1/1000 by, for example, a 100 MΩ resistor 82a and a 100 kΩ resistor 82b, and the resistor 82c and The detection signal S82 is supplied to the ADC 91 through the voltage follower of the operational amplifier 145.

(Operation of the high-pressure control unit of Example 1)
The operation of the high voltage control unit 41 in FIG. 6 will be described with reference to FIGS. 7, 8, and 9.

  The high voltage control unit 41 in FIG. 6 operates in synchronization with the 25 MHz clock CLK output from the oscillation circuit 71 in FIG. When the signal ON / OFF input from the input port IN11 changes from L to H, the comparator 92 operates, and the output selector 100 is switched to the frequency divider 99 side using the signal ON / OFF as the selection signal Select. A control pulse S41a is output from the output selector 99. The selection signal Select is simultaneously inverted by the inverter 101 and output to the PLL circuit 72 as the inhibition signal S41b.

  The high voltage control unit 41 inputs an L signal RESET output from the printer engine control unit 34 from the input port IN12.

  The 8-bit ADC 91 converts the 0 to 5 V analog signal, which is the detection signal S82 input from the output voltage conversion means 82, at a predetermined conversion cycle into a conversion detection signal S91 that is an 8-bit digital signal from 00 hex to FF hex.

  The comparator 92 compares the 8-bit target data DATA input from the printer engine control unit 34 with the conversion detection signal S91. If the target data DATA is larger than the conversion detection signal S91, H is set to be not large. Outputs L to the 18-bit register 96.

  The 18-bit register 96 increases or decreases the set value of the 18-bit register 96 according to the signal from the comparator 92 at the input of the rising edge of the pulse input from the timer 95.

  The 18-bit register 96 is a register for setting a frequency division value, and the upper 8 bits indicate an integer value and the lower 10 bits indicate a fractional value. The average frequency division ratio is (upper 8 bits) + (lower 10 bits) / 1024. When the signal RESET becomes H, the 18-bit value of the lower limit register 94 is set in the 18-bit register 96. The 18-bit register 96 increases or decreases the set value of the 18-bit register 96 based on the signal from the comparator 92 at the input of the rising edge of the pulse input from the timer 95.

  The fractional value is accumulated in the error holding register 98. When the addition value of the fractional value overflows, the error holding register outputs H to the adder 97, and outputs L otherwise. The adder 97 receives the upper 8-bit value S96b which is an integer part of the 18-bit register 96, adds 1 when the output signal of the error holding register 98 is H, and adds 0 when the output signal is L. The function of outputting to the device 99 is provided.

  The frequency divider 99 inputs N or N + 1, where N is an 8-bit value that is an integer part of the 18-bit register 96, and outputs a 50% duty N or N + 1 frequency-divided pulse. The 50% duty value is calculated from a 7-bit value obtained by shifting an 8-bit value to the right by 1 bit.

In FIG. 8, the adder 98b adds the lower 10-bit value S96a of the error holding register 98 to the value of the error holding register main body 98a, and replaces the addition result with bits 0-10 and the lower 11 bits of the error holding register 98. The addition is performed using the rising edge of the divided pulse S99 output from the frequency divider 99 as a trigger, and the value of bit10 is shifted to bit11 simultaneously with the addition. Bit10 is cleared to 0 after the value is shifted to bit11.

The output selector 100 outputs a control pulse S41a to the PLL circuit 72 when the signal ON / OFF becomes H. At the same time, the inhibition signal S41b obtained by inverting the signal ON / OFF via the inverter 101 is output to the input port INH of the PLL circuit 71.

  In FIG. 9, 12Chex is set in the lower 10 bits of the 18-bit register. When the period of the frequency-divided pulse S99 is 0, no overflow occurs, so that an L overflow signal is input to the adder 98b. In FIG. 9, L is represented by 0 and H is represented by 1. When the frequency of the divided pulse S99 is 1, the value of the 18-bit register lower 10-bit signal S96a is accumulated in the error holding register 98 to be 12 Chex. As a result, since no overflow occurs, an L overflow signal is input to the adder 98b. Similarly, when the period of the divided pulse S99 is 1 to 3, no overflow occurs.

When the frequency of the divided pulse S99 is 4, the value of the lower 10-bit value S96a of the 18-bit register is accumulated in the error holding register 98 to become 4B0 hex. As a result, an overflow occurs, and an H overflow signal is input to the adder 98b.

FIG. 11 is a flowchart showing the operation of the high voltage control unit 41 in FIG.
The high voltage control unit 41 is composed of an ASIC, and is realized by hardware described in a logical description language. However, the configuration of the first embodiment can be realized by software instead of hardware.

When the signal RESET becomes H, this process is started.
In step ST1, the set value of the lower limit register 94 is set in the 18-bit register 96. In step ST2, it is determined whether the signal RESET is L or not. When it is H (N), it returns to step ST1, and when it is L (Y), it proceeds to step ST3.

In step ST3, it is determined whether or not the rising edge of the timer 95 has been detected. If detected (Y), the process proceeds to step ST4. If not detected (N) , the process returns to step ST3. In step ST4, it is determined whether or not the conversion detection signal S91 output from the ADC 91 is smaller than the target data DATA. When the conversion detection signal S91 is smaller than the target data DATA (Y), the process proceeds to step ST5, and when not smaller (N), the process returns to step ST2.

  In step ST5, it is determined whether or not the value of the 18-bit register 96 is equal to the upper limit register 93. When equal (Y), the process returns to step ST2, and when not equal (N), the process proceeds to step ST6. In step ST6, 1 is added to the value of the 18-bit register 96. In step ST7, it is determined whether or not the value of the 18-bit register 96 is equal to the lower limit register 94. When equal (Y), the process returns to step ST2, and when not equal (N), the process proceeds to step ST8. In step ST8, the value of the 18-bit register 96 is subtracted by 1.

  In the first embodiment, the value of the 18-bit register 96, which is the set value of the frequency division value, is added or subtracted one by one. However, the amount of frequency change during frequency control by changing the amount of addition or subtraction according to the difference from the target value. The variable width may be changed. Various frequency control methods have been proposed by publicly known documents.

(Comparison between Comparative Example and Example 1)
FIG. 12 is a waveform diagram showing a drive voltage applied to the piezoelectric transformer in the comparative example. FIG. 13 is a schematic diagram illustrating a driving voltage applied to the piezoelectric transformer in the comparative example. Further, FIG. 14 is a waveform diagram showing drive voltages applied to the piezoelectric transformer of FIG. 4 in Embodiment 1 of the present invention.

  In FIG. 12, the upper waveform is the waveform of the drive voltage S75, and the lower waveform is the waveform of the drive pulse S72. In the waveform of the drive voltage S75, one scale represents 20.0V, and in the waveform of the drive pulse S72, one scale represents 5.00V. The horizontal axis represents the time axis and one scale represents 10.0 μsec. The same notation is used in FIG.

A drive voltage S75 is applied to the input terminal 80a of the piezoelectric transformer 80. Since the drive pulse S72 of the piezoelectric transformer 80 has a slight phase difference with respect to the vibration of the piezoelectric transformer 80 , the wave height of the drive voltage S75 is not uniform. The piezoelectric transformer 80 vibrates at an average frequency even when driven by pulses with different frequency division values in order to vibrate mechanically. However, a phase difference with respect to each pulse is generated by driving with an integer frequency division value with respect to the vibration of the average frequency, and the peak voltage of the resonance waveform varies as shown in FIG.

As shown in the schematic diagram of FIG. 13, the primary drive waveform (drive voltage S75) is boosted, and the AC output voltage S80 is output to the secondary side. Although the output AC output voltage S80 is rectified, a ripple having a low frequency different from the ripple of the drive frequency is generated as in the waveform of the rectified waveform (DC output voltage S81) shown in FIG. The drive frequency of the drive voltage S75 of the piezoelectric transformer 80 is as high as about 100 kHz and the ripple period is about 10 μsec. Therefore, even in an image forming apparatus in which a sheet is conveyed at a speed of, for example, 300 mm / sec, the ripple period is
300/10 ⁵ = 0.003 mm
It is not recognized on the image. However, the low-frequency ripple is recognized as striped unevenness in the image. When the conventional fractional frequency divider is used and the number of bits in the fractional part is N bits, the low frequency ripple is (drive frequency period) × 2 ^N
Appears at a cycle that is an integral multiple of the drive frequency cycle.

  According to the first embodiment of the present invention, driving is performed by canceling the phase difference of each pulse by the loop filter 73, so that the low-frequency ripple can be reduced as shown in FIG.

(Effect of Example 1)
According to the first embodiment, the PLL circuit 72 and the loop filter 73 are provided on the output side of the high-voltage control unit 41 that outputs the control pulse S41a, the phase is synchronized with the control pulse S41a, and the frequency matches the average frequency of the control pulse S41a. The drive pulse S72 is output. Since the piezoelectric transformer drive circuit 75 is driven by the drive pulse S72, there is an effect of reducing the low-frequency ripple of the high-voltage DC output voltage S81 output from the piezoelectric transformer 80 via the rectifier circuit 81. .

  Furthermore, since the average frequency of the control pulse S41a and the frequency of the drive pulse S72 are equal, the frequency variable period can be set to 10 μsec to several hundred μsec. Therefore, the high voltage power supply device 60 having a quick rise time can be realized.

(Configuration of Example 2)
In the second embodiment of the present invention, the image forming apparatus 1 in FIG. 2 is the same as that in the first embodiment, and the configurations of the high voltage control unit 41A and the transfer bias generating unit 44A in FIG.

  FIG. 15 is a block diagram illustrating a configuration of a control circuit according to the second embodiment of the present invention. Elements common to those in FIG. 3 illustrating the first embodiment are denoted by common reference numerals.

  In FIG. 15, the configurations of the high-voltage control unit 41A and the transfer bias generation unit 44A are different from those of the first embodiment, and other configurations are the same as those of the first embodiment.

  FIG. 16 is a block diagram illustrating a configuration example of the high-voltage power supply device 60A in FIG. 15. Elements common to the elements in FIG.

In FIG. 16, the configuration of the high voltage control unit 41A is different from that of the first embodiment, and the PLL circuit 72 of the first embodiment is integrated with the high voltage control unit 41A. Other configurations are the same as those of the first embodiment. For example, an ASIC 1260 is used as the high-pressure control unit 41A .

  FIG. 17 is a circuit diagram showing a configuration example of the high-voltage power supply device 60A of FIG. 16. Elements common to those in FIG. 4 showing the first embodiment are denoted by common reference numerals.

  In FIG. 17, the configuration of the loop filter 73A is different from that of the first embodiment. In addition to the configuration of the loop filter 73 of the first embodiment, the loop filter 73A is different from the first embodiment in that the loop filter 73A includes a resistor 73f having one end connected to the capacitor 73b and the other end connected to the ground GND. Other configurations are the same as those of the first embodiment.

  FIG. 18 is a circuit block diagram showing a configuration of the high voltage control unit 41A in FIG. 17, and common elements to those in FIG. 6 showing the first embodiment are denoted by common reference numerals.

  In FIG. 18, the configurations of an 18-bit register 96A, an adder 97A, a comparator 98A, and a frequency divider 99A are different from those in the first embodiment, and a counter 102, a phase comparator 103, a VCO 104, 1 / A quarter divider 105 is added. Other configurations are the same as those of the first embodiment. Among these, the phase comparator 103, the VCO 104, and the ¼ frequency divider 105 constitute a PLL circuit corresponding to the PLL circuit 72 of the first embodiment.

A drive pulse S72, which is an output signal of the VCO 104, is output to the piezoelectric transformer drive circuit 75 via the output selector 100 and simultaneously input to the 1/4 frequency divider 105 to be divided by four. . In the second embodiment, the frequency is divided by 4, but the output pulse cycle of the 1/4 frequency divider 105 may be designed to be shorter than the control cycle for changing the target data DATA set in the 18-bit register 96A. Other frequency division values may be used. The timer 95 determines the frequency instruction value variable cycle. In order for the output frequency of the VCO 104 to linearly follow the instruction value variable,
The output pulse period of the timer 95 needs to be equal to or greater than the output pulse period of the 1/4 frequency divider. Both periods need not be synchronized.

The pulse input to the phase comparator 103 is a quarter of the frequency of the drive pulse S72 , and is 27 to 32.5 kHz with respect to the drive frequency of 108 to 130 kH. Since the 18-bit register 96A has an integer part of 10 bits and a decimal part of 8 bits, the set value is equal to that in the first embodiment. Unlike the first embodiment, the fractional frequency division in the second embodiment uses a threshold matrix. The operation of the frequency divider 99A is the same as that of the frequency divider 99 of the first embodiment, but the frequency division pulse S99A output from the frequency divider 99A is counted by the counter 102. The counter 102 is a 8-bit counter and has a function of counting from 00 to FFhex. When counting to FF hex, it returns to 00 hex.

  FIG. 19 is a diagram illustrating the counter, the lower 8 bits of the 18-bit register, and the comparator in FIG.

In FIG. 19, the value of the counter 102 is changed from bit7 → bit0, bit6 → bit1, bit5 → bit2, bit4 → bit3, bit3 → bit4, bit2 → bit5, bit1 → bit6, bit0 → bit7, and the counter replacement value is the comparator. 98A is input. In the comparator 98A, the counter replacement output is compared with the lower 8 bits which are the fractional part of the 18-bit register 96A.
When the value of lower 8 bits ≧ counter replacement value, the comparator 98A outputs H to the adder 97A, and otherwise outputs L.

  FIG. 20 is a diagram illustrating the relationship among the frequency-divided pulse S99A period, the counter replacement output 8 bits, the lower 10 bits of the 18-bit register, and the adder input signal in FIG.

The counter replacement value constitutes a threshold matrix, and is compared with the value of the fractional part, and N division and N + 1 division are selected. In the second embodiment, the counter 102 that counts the divided pulse S99A is used. However, the threshold matrix may be configured as an 8 bit × 256 table. Quadrupled pulse of the divided pulses S99A output from the frequency divider 99A is adapted to be outputted from the VCO 104.

(Operation of Example 2)
In the second embodiment, the overall operation of the image forming apparatus 1 is the same as that of the first embodiment. Therefore, the operation of the high-voltage control unit 41A different from the first embodiment will be described with reference to FIGS. To do.

The output signal of the VCO 104 is output to the piezoelectric transformer drive circuit 80 via the output selector 100 and simultaneously input to the 1/4 frequency divider 105 and divided by four. The timer 95 determines the frequency instruction value variable cycle. In order for the output frequency of the VCO 104 to linearly follow the instruction value variable,
The output pulse period of the timer 95 needs to be equal to or greater than the output pulse period of the 1/4 frequency divider. Both periods need not be synchronized.

The pulse input to the phase comparator 103 is a quarter of the frequency of the drive pulse 72 of the piezoelectric transformer drive circuit 75 , and is 27 to 32.5 kHz with respect to the drive frequency of 108 to 130 kH. The 18-bit register 96A has an integer part 10 bits and a decimal part 8 bits, and the same set value as that in the first embodiment is set. Unlike the first embodiment, a threshold value matrix is used for fractional frequency division. The operation of the frequency divider 99A is the same as that of the frequency divider 99 of the first embodiment. The divided pulse S99A output from the frequency divider 99A is counted by the counter 102. The counter 102 is an 8-bit counter and counts from 00 to FFhex. When counting to FF hex, it returns to 00 hex.

In FIG. 19, the value of the counter 102 is changed from bit7 → bit0, bit6 → bit1, bit5 → bit2, bit4 → bit3, bit3 → bit4, bit2 → bit5, bit1 → bit6, bit0 → bit7, and the counter replacement value is the comparator. It is input to 98A. In the comparator 98A, the counter replacement value is compared with the lower 8 bits which are the fractional part of the 18-bit register 96A.
When the value of lower 8 bits ≧ counter replacement value, the comparator 98A outputs H to the adder 97A, and otherwise outputs L.

  FIG. 20 is a diagram showing the relationship among the frequency divider pulse S99A period in FIG. 19, the counter replacement output 8 bits, the value of the lower 10 bits of the 18 bit register, and the adder input signal.

The counter replacement value constitutes a threshold matrix, and is compared with the value of the fractional part, and N division and N + 1 division are selected.

In the second embodiment, the counter 102 that counts the divided pulse S99A is used. However, a threshold matrix may be configured as an 8 bit × 256 table. The VCO 104 outputs a pulse obtained by multiplying the divided pulse S99A output from the frequency divider 99A by four.

(Effect of Example 2)
According to the second embodiment, in addition to the effects of the first embodiment, the frequency of the control pulse S41a can be lowered by dividing the output pulse of the VCO 104 by 1/4 and comparing the phase. Therefore, since it is possible with this to reduce the number of bits fractional value at the same resolution, it has become possible to reduce the noise of the control pulse S41a.

Furthermore, it is possible to obtain the drive pulse S72 with high accuracy, and it is possible to ensure a necessary control cycle because the frequency of the pulse input to the PLL circuit is not drastically reduced by fractional frequency division.

(Modification)
In Examples 1 and 2, the piezoelectric transformer driving apparatus 70,70A for driving the piezoelectric transformer 80, high-voltage power supply apparatus using it, and have been described color image forming apparatus 1 of the electrophotographic type using it, to It is not limited. For example, the present invention can be applied to various image forming apparatuses such as a color printer, a color copying machine, a facsimile machine, or a color multifunction machine having these functions.

DESCRIPTION OF SYMBOLS 1 Image forming apparatus 34 Printer engine control part 41, 41A High voltage control part 70, 70A Piezoelectric transformer drive device 72 PLL circuit 73 Loop filter 75 Piezoelectric transformer drive circuit 80 Piezoelectric transformer 96 , 96A 18 bit register 98 Error holding register 99 , 99A frequency division DATA Target data S41a Control pulse S72 Drive pulse S75 Drive voltage S81 DC output voltage S82 Detection signal

Claims (8)

A piezoelectric transformer drive device that applies the drive voltage to a piezoelectric transformer that is driven by an intermittent drive voltage and outputs a high-voltage output voltage,
An oscillating means for generating a clock signal;
The clock signal, the detection value corresponding to the output voltage, and the target value of the output voltage are input, and the detection value and the target value are compared so that the detection value and the target value are equal. , N (where N is an integer) and N + 1 divided values that are updated every pulse of a constant period, and the clock signal is generated based on the divided values of N and N + 1. Fractional frequency dividing means for generating a control pulse by dividing frequency by
Pulse output means for inputting the control pulse, averaging the phase difference between the divided values of N and N + 1, and outputting a drive pulse;
Piezoelectric transformer driving means that is driven by the driving pulse and outputs a driving voltage applied to the piezoelectric transformer;
With
The pulse output means includes
A phase comparator that compares the control pulse generated by the divided values of N and N + 1 with the drive pulse and outputs a phase comparison signal;
A filter for smoothing the phase comparison signal and outputting a control voltage;
A voltage controlled oscillator that updates the frequency of the drive pulse for each control pulse based on the control voltage;
A piezoelectric transformer driving device comprising: The fractional dividing means is
2. The apparatus according to claim 1, further comprising a fractional-N divider that outputs a divided pulse by dividing the clock signal by a fraction by the divided value based on a comparison result between the detected value and the target value. The piezoelectric transformer drive device described. The fractional N divider is
A first register for holding the divided value;
The decimal value is accumulated in a predetermined cycle, and when the accumulated result exceeds a threshold value, a first logic overflow signal is output, and when the accumulated result is less than the threshold value, a second logic overflow signal is output. A second register to output;
When the integer value of the divided value held by the first register is inputted and the overflow signal of the first logic is inputted, the clock signal is divided and outputted by a value obtained by changing the integer value. A frequency divider that divides and outputs the clock signal by the integer value when the second logic overflow signal is input;
The piezoelectric transformer driving device according to claim 2, comprising: The first register is:
This is a multi-bit register in which the upper and lower register values are set.
The second register is:
An error holding register for holding the decimal value of the register value in the first register;
The piezoelectric transformer driving device according to claim 3. The fractional dividing means is
2. The piezoelectric transformer driving device according to claim 1, further comprising a frequency divider using a threshold matrix. A piezoelectric transformer according to claim 1;
A piezoelectric transformer driving device according to any one of claims 1 to 5,
Output detection means for detecting the output voltage and providing the detected value to the fractional frequency dividing means;
Target value setting means for setting the target value ;
High-voltage power supply apparatus comprising: a. The high-voltage power supply device according to claim 6 further includes:
Rectifying means for rectifying the output voltage consisting of an AC voltage output from the piezoelectric transformer into a DC voltage;
The output detection means includes
Outputting the detected value obtained by stepping down the DC voltage;
A high-voltage power supply device characterized by that. 8. An image forming apparatus driven by the output voltage output from the high voltage power supply apparatus according to claim 6 or 7 to form an image on a recording medium.

Images