JP5320844B2 - Pre-underfill bonding type semiconductor device and manufacturing method thereof - Google Patents

Pre-underfill bonding type semiconductor device and manufacturing method thereof Download PDF

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JP5320844B2
JP5320844B2 JP2008161411A JP2008161411A JP5320844B2 JP 5320844 B2 JP5320844 B2 JP 5320844B2 JP 2008161411 A JP2008161411 A JP 2008161411A JP 2008161411 A JP2008161411 A JP 2008161411A JP 5320844 B2 JP5320844 B2 JP 5320844B2
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sealing resin
resin
semiconductor chip
semiconductor device
underfill
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JP2010003879A (en
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泰治 酒井
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Fujitsu Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83909—Post-treatment of the layer connector or bonding area
    • H01L2224/83951—Forming additional members, e.g. for reinforcing, fillet sealant

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Description

本発明は先アンダーフィル接合方式半導体装置及びその製造方法に関するものであり、例えば、先アンダーフィル方式で半導体チップと回路基板とをフリップチップ接続して樹脂封止する半導体装置の耐湿性及び耐熱性等の信頼性を向上するための構成に関するものである。 BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pre-underfill bonding type semiconductor device and a manufacturing method thereof, for example, moisture resistance and heat resistance of a semiconductor device in which a semiconductor chip and a circuit board are flip-chip connected and sealed by a pre-underfill method. The present invention relates to a configuration for improving the reliability.

従来より、半導体素子を回路基板に実装する際に、半導体素子を回路基板上にフリップチップ接合したのち、半導体素子と回路基板との間に封止樹脂を注入する後アンダーフィル方式が採用されてきた。   Conventionally, when a semiconductor element is mounted on a circuit board, after the semiconductor element is flip-chip bonded onto the circuit board, an underfill method has been employed in which a sealing resin is injected between the semiconductor element and the circuit board. It was.

しかし、近年、携帯機器、特に携帯電話市場における小型化の要求に伴い、搭載される半導体素子のフリップチップ接続において半導体素子と回路基板のギャップが小さくなり、フリップチップ接合後に半導体素子と回路基板との間に封止樹脂を後入れで注入することが困難になってきている。また個々の半導体素子それぞれに封止樹脂を注入するためコスト上昇の問題がある。   However, in recent years, with the demand for miniaturization in the mobile device market, particularly in the mobile phone market, the gap between the semiconductor element and the circuit board is reduced in flip chip connection of the mounted semiconductor element. It has become difficult to inject the sealing resin later. In addition, since the sealing resin is injected into each individual semiconductor element, there is a problem of an increase in cost.

このため、後アンダーフィル方式を改善する方式として、予め半導体素子が形成されたウエハに半硬化の封止樹脂層を一括して形成しておき、ダイシング、チップ化後に電極と封止樹脂を一括してフリップチップ接合する先アンダーフィル方式のニーズが高まってきている（例えば、特許文献１参照）。
特開平１１−２１４４４０号公報 For this reason, as a method for improving the post-underfill method, a semi-cured sealing resin layer is collectively formed on a wafer on which semiconductor elements are formed in advance, and the electrode and the sealing resin are collectively formed after dicing and chip forming. Thus, there is an increasing need for a pre-underfill method for flip chip bonding (see, for example, Patent Document 1).
JP-A-11-214440

しかし、先アンダーフィル方式においては、封止樹脂が加圧により同心円状に押し出されるため、半導体素子のコーナー部の樹脂量が不足するという問題があるので、図６を参照してこの事情を説明する。図６は、従来の先アンダーフィル方式による半導体装置の概念的平面図であり、半導体素子５２を回路基板５１に封止樹脂５３ごと圧接してフリップチップ接合する際に、封止樹脂５３が半導体素子５２の外周からはみでる。   However, in the first underfill method, since the sealing resin is extruded concentrically by pressurization, there is a problem that the amount of resin at the corner portion of the semiconductor element is insufficient, so this situation will be described with reference to FIG. To do. FIG. 6 is a conceptual plan view of a conventional semiconductor device based on the prior underfill method. When the semiconductor element 52 is pressed against the circuit board 51 together with the sealing resin 53 and is flip-chip bonded, the sealing resin 53 is a semiconductor. It protrudes from the outer periphery of the element 52.

この封止樹脂５３が半導体素子５２からはみだした部分はフィレット部と呼ばれ、信頼性の点から重要である。特に、半導体素子５２のコーナー部は、応力が大きいために十分な量のフィレット部を形成しなくてはならないが、上述のように半導体素子５２のコーナー部で樹脂量が不足して信頼性が低下するという問題がある。   The portion where the sealing resin 53 protrudes from the semiconductor element 52 is called a fillet portion, which is important from the viewpoint of reliability. In particular, since the corner portion of the semiconductor element 52 has a large stress, a sufficient amount of fillet portions must be formed. However, as described above, the corner portion of the semiconductor element 52 has a lack of resin amount and reliability. There is a problem of lowering.

また、先アンダーフィル方式の別の問題として、フリップチップ接合時の位置合わせのために封止樹脂５３は光透過性のものに限られるということが挙げられる。一般的に、封止樹脂に耐熱性や吸湿性などの信頼性を持たせるためには数種類の樹脂成分およびシリカフィラーを混合する必要があり、混合の結果、光透過性が失われることになる。したがって、先アンダーフィル方式においては、信頼性の高い封止樹脂を使用できないという問題がある。   Another problem with the pre-underfill method is that the sealing resin 53 is limited to a light-transmitting material for alignment during flip chip bonding. In general, it is necessary to mix several types of resin components and silica filler in order to provide the sealing resin with reliability such as heat resistance and moisture absorption. As a result, the light transmission is lost. . Therefore, in the first underfill method, there is a problem that a highly reliable sealing resin cannot be used.

したがって、本発明は、先アンダーフィル接合方式において、半導体素子のコーナー部に十分な封止樹脂を設け、かつ信頼性の高い不透明な封止樹脂を使用したフリップチップ接合を可能にすることを目的とする。   Accordingly, an object of the present invention is to provide a flip chip bonding using a highly reliable opaque sealing resin and providing a sufficient sealing resin at a corner portion of a semiconductor element in a pre-underfill bonding method. And

本発明の一観点からは、半導体チップと前記半導体チップを搭載する回路基板上との間に充填する第１の封止樹脂が前記半導体チップの外周からはみ出しており、且つ、前記半導体チップの少なくとも４隅において前記第１の封止樹脂を覆うように第２の封止樹脂が設けられた半導体装置であって、前記第１の封止樹脂の耐湿性及び耐熱性が前記第２の封止樹脂の耐湿性及び耐熱性より優れているとともに、前記第１の封止樹脂は可視光及び赤外光に対して不透明であり且つ前記第２の封止樹脂は可視光或いは赤外光に対して透過性を有する先アンダーフィル接合方式半導体装置が提供される。 From one aspect of the present invention, the first sealing resin filled between the semiconductor chip and the circuit board on which the semiconductor chip is mounted protrudes from the outer periphery of the semiconductor chip, and at least the semiconductor chip A semiconductor device provided with a second sealing resin so as to cover the first sealing resin at four corners, wherein the moisture resistance and heat resistance of the first sealing resin are the second sealing It is superior to the moisture resistance and heat resistance of the resin, the first sealing resin is opaque to visible light and infrared light, and the second sealing resin is not visible or infrared light. Thus, a pre-underfill junction type semiconductor device having transparency is provided.

また、本発明の別の観点からは、半導体チップの回路面上に第１の封止樹脂を塗布して半硬化させる工程、前記第１の封止樹脂層上であって、前記半導体チップの少なくとも４隅を含むようにパターンニングされた第２の封止樹脂層を選択的に形成して半硬化させる工程と、前記第１の封止樹脂層及び第２の封止樹脂層を設けた半導体チップを回路基板に対して圧接してフリップチップ接合する工程とを有する先アンダーフィル接合方式半導体装置の製造方法が提供される。 Further, from another aspect of the present invention, a step of applying a first sealing resin on a circuit surface of a semiconductor chip and semi-curing, the first sealing resin layer, A step of selectively forming and semi-curing a second sealing resin layer patterned so as to include at least four corners; and the first sealing resin layer and the second sealing resin layer. There is provided a method of manufacturing a pre-underfill bonding type semiconductor device having a step of flip-chip bonding by pressing a semiconductor chip against a circuit board.

開示の半導体装置によれば、半導体素子に予め封止樹脂を形成しておく先アンダーフィル方式において、従来は困難であった半導体素子コーナー部にも十分な量のフィレット部を形成でき、接合信頼性を大幅に高めることができる。   According to the disclosed semiconductor device, a sufficient amount of fillet portions can be formed at the corner portion of the semiconductor element, which is difficult in the prior art, in the first underfill method in which the sealing resin is previously formed on the semiconductor element. The sex can be greatly improved.

また、第２の封止樹脂の形成、露光、現像プロセスが追加となるが、全てチップ化の前のウエハ段階で処理できるために生産性は高く、半導体素子１つ１つに追加でフィレット用封止樹脂を形成する場合と比較し、大幅にプロセスタイムを低減させることができる。   In addition, the formation, exposure, and development processes of the second sealing resin are added, but since all can be processed at the wafer stage before chip formation, the productivity is high, and for each fillet added to each semiconductor element. Compared with the case of forming the sealing resin, the process time can be greatly reduced.

また、第１の封止樹脂をフィラー入りおよびフラックス機能入りとし、第２の封止樹脂を位置合わせ用マーク形成用と機能を分離することによって、接合信頼性を犠牲にすることなく位置合わせ容易な先アンダーフィル方式のフリップチップ接合を実現することができる。   In addition, the first sealing resin is filled with a filler and a flux function, and the second sealing resin is separated from an alignment mark forming function and a function, thereby easily aligning without sacrificing bonding reliability. A tip-underfill flip-chip bonding can be realized.

ここで、図１及び図２を参照して、本発明の実施の形態を説明する。図１は、本発明の実施の形態のフリップチップ接合前の構成説明図であり、図１（ａ）は概念的平面図であり、図１（ｂ）は図１（ａ）におけるＡ−Ａ′を結ぶ一点鎖線に沿った概念的断面図である。図に示すように、パッド１２上に接続電極１３を設けた半導体素子１１の回路面上に接続電極１３の表面を覆うように全面に耐湿性及び耐熱性に優れた第１の封止樹脂１４を半硬化状態で設ける。この第１の封止樹脂１４上に可視光に対して透明で且つ感光性を有する第２の封止樹脂１５を半硬化状態で選択的に設ける。なお、接続電極１３は特に制約などはなく、半田電極、Ａｕメッキバンプ、Ｃｕメッキバンプ、Ａｕボールバンプなどを用いれば良い。   Here, with reference to FIG.1 and FIG.2, embodiment of this invention is described. FIG. 1 is an explanatory diagram of a configuration before flip chip bonding according to an embodiment of the present invention, FIG. 1 (a) is a conceptual plan view, and FIG. 1 (b) is an AA in FIG. 1 (a). It is a conceptual sectional view along the alternate long and short dash line connecting ′. As shown in the figure, a first sealing resin 14 having excellent moisture resistance and heat resistance is provided on the entire surface so as to cover the surface of the connection electrode 13 on the circuit surface of the semiconductor element 11 provided with the connection electrode 13 on the pad 12. Is provided in a semi-cured state. A second sealing resin 15 that is transparent to visible light and has photosensitivity is selectively provided on the first sealing resin 14 in a semi-cured state. The connection electrode 13 is not particularly limited, and a solder electrode, an Au plating bump, a Cu plating bump, an Au ball bump, or the like may be used.

この場合、第１の封止樹脂１４は、シート状のフィルムをラミネートによって貼付しても良いし、或いは、液状樹脂を印刷もしくはスピンコートにより形成した後、乾燥し半硬化状態としても良い。この第１の封止樹脂１４は、シリカなどの無機フィラーまたはゴム状樹脂などの有機フィラーを含むエポキシ系樹脂またはウレタン系樹脂またはフェノキシ樹脂またはシアネートエステル系樹脂を主成分とし、さらに有機酸を含有させてフラックス機能を持たせたものである。この内では、シリカなどの無機フィラーを含んだエポキシ系樹脂が耐熱性及び弾性の観点から好適である。   In this case, the first sealing resin 14 may be formed by laminating a sheet-like film, or may be dried and semi-cured after a liquid resin is formed by printing or spin coating. The first sealing resin 14 is mainly composed of an epoxy resin, a urethane resin, a phenoxy resin, or a cyanate ester resin containing an inorganic filler such as silica or an organic filler such as a rubber-like resin, and further contains an organic acid. It is made to have a flux function. Among these, an epoxy resin containing an inorganic filler such as silica is preferable from the viewpoint of heat resistance and elasticity.

一方、第２の封止樹脂１５は、シート状のフィルムをラミネートによって貼付しても良いし、或いは、液状樹脂を印刷もしくはスピンコートにより形成、乾燥させる工程によって半硬化状態にしたのち、露光・現像によってパターンニングする工程によって形成される。   On the other hand, the second sealing resin 15 may be formed by laminating a sheet-like film, or after the liquid resin is formed into a semi-cured state by printing or spin coating and drying, then exposure / It is formed by a patterning process by development.

この場合の第２の封止樹脂１５のパターンは、図１（ａ）に示すように、半導体素子１１の４隅にのみ選択的に設けても良い。或いは、半導体素子１１の中心から放射状に伸びる複数のストライプ状パターンで構成するとともに、ストライプ状パターンのうち、半導体チップ１１の４隅方向に伸びるストライプ状パターンの幅が、その他の方向に伸びるストライプ状パターンの幅より広くなるパターンとしても良い。   In this case, the pattern of the second sealing resin 15 may be selectively provided only at the four corners of the semiconductor element 11 as shown in FIG. Alternatively, the stripe pattern is configured by a plurality of stripe patterns extending radially from the center of the semiconductor element 11, and of the stripe patterns, the width of the stripe pattern extending in the four corner directions of the semiconductor chip 11 extends in other directions. The pattern may be wider than the pattern width.

第２の封止樹脂１５を半導体素子１１の４隅にのみ選択的に設ける場合には、各コーナーにおける占有面積が半導体素子１１の面積の２〜１０％となり、且つ、樹脂が押し出されてフィレット部を構成した場合に、各コーナーにおける第２の封止樹脂１５によるフィレット部が０．１〜１．０ｍｍ3 の樹脂量になるように厚さを規定する。 When the second sealing resin 15 is selectively provided only at the four corners of the semiconductor element 11, the occupied area at each corner is 2 to 10% of the area of the semiconductor element 11, and the resin is extruded to fillet. When the portion is configured, the thickness is defined so that the fillet portion by the second sealing resin 15 at each corner has a resin amount of 0.1 to 1.0 mm 3 .

第２の封止樹脂１５を放射状パターンとして設ける場合にも、各コーナーにおける第２の封止樹脂１５によるフィレット部が０．１〜１．０ｍｍ3 の樹脂量になるようにストライプ状パターンの幅及び厚さを規定する。 Even when the second sealing resin 15 is provided as a radial pattern, the width of the stripe pattern so that the fillet portion of the second sealing resin 15 at each corner has a resin amount of 0.1 to 1.0 mm 3. And specify the thickness.

また、このパターンニングされた第２の封止樹脂層には、パターン工程において、図１（ａ）に示すように少なくとも２つの位置合わせ用マーク１６がパターンニングされる。この位置合わせ用マーク１６は３つ設けて半導体チップの方向性を示すようにしても良いし、また、スクライブラインを同時にパターニングしても良い。   Further, in the patterning step, at least two alignment marks 16 are patterned on the patterned second sealing resin layer as shown in FIG. Three alignment marks 16 may be provided to indicate the direction of the semiconductor chip, or the scribe lines may be patterned simultaneously.

この第２の封止樹脂は、フィラーを含まないエポキシ系樹脂またはウレタン系樹脂またはフェノキシ樹脂またはシアネートエステル系樹脂を主成分とし、且つ、感光剤を含有させて感光性を持たせたものであり、耐熱性及び耐湿性に劣るものの可視光に対して透明である。この透明性は、ウェハの周辺部に形成したアライメント用パターンを認識するために必要となる。   This second sealing resin is mainly composed of an epoxy resin, a urethane resin, a phenoxy resin, or a cyanate ester resin that does not contain a filler, and contains a photosensitizer to make it photosensitive. Although it is inferior in heat resistance and moisture resistance, it is transparent to visible light. This transparency is necessary for recognizing the alignment pattern formed on the periphery of the wafer.

図２は、本発明の実施の形態のフリップチップ接合後の構成説明図であり、図２（ａ）は概念的平面図であり、図２（ｂ）は図２（ａ）におけるＡ−Ａ′を結ぶ一点鎖線に沿った概念的断面図である。図に示すように、パッド２２を設けた回路基板２１に、封止樹脂を形成した半導体素子１１を、封止樹脂の軟化温度まで加熱した状態で圧接することによってフリップチップ接合する。この時、カメラにより位置あわせ用マーク１６を確認しながら位置合わせしてフリップチップ接合する。なお、図における符号２３はソルダーレジストである。   FIG. 2 is a configuration explanatory view after flip-chip bonding according to the embodiment of the present invention, FIG. 2 (a) is a conceptual plan view, and FIG. 2 (b) is an AA in FIG. 2 (a). It is a conceptual sectional view along the alternate long and short dash line connecting ′. As shown in the figure, the flip-chip bonding is performed by press-contacting the semiconductor element 11 formed with the sealing resin to the circuit substrate 21 provided with the pads 22 while being heated to the softening temperature of the sealing resin. At this time, positioning is performed while confirming the alignment mark 16 with a camera, and flip chip bonding is performed. Reference numeral 23 in the figure denotes a solder resist.

図に示すように、第２の封止樹脂１５は完全に半導体素子１１の外周の外へ押し出されてフィレット部１８を構成するとともに、第１の封止樹脂１４の一部も半導体素子１１の外周の外へ押し出されてフィレット部１７を構成する。この時、第２の封止樹脂１５からなるフィレット部１８は、半導体素子１１のコーナー部における樹脂量の不足を補うことになる。   As shown in the figure, the second sealing resin 15 is completely pushed out of the outer periphery of the semiconductor element 11 to form the fillet portion 18, and a part of the first sealing resin 14 is also formed on the semiconductor element 11. The fillet portion 17 is formed by being pushed out of the outer periphery. At this time, the fillet portion 18 made of the second sealing resin 15 compensates for the shortage of the resin amount at the corner portion of the semiconductor element 11.

このように、本発明の実施の形態においては、アンダーフィル樹脂の主要部を耐熱性及び耐湿性に優れたフィラー入りの樹脂で構成しているので半導体素子の信頼性が低下することはない。また、アンダーフィル樹脂の補足部を透明な樹脂で半導体素子のコーナー部に設けているので、ウェハの周辺部に形成したアライメント用パターンの認識に支障が生ずることはなく、且つ、半導体素子のコーナー部における樹脂量の不足を補うことができる。   As described above, in the embodiment of the present invention, since the main part of the underfill resin is made of the resin containing filler excellent in heat resistance and moisture resistance, the reliability of the semiconductor element is not lowered. In addition, since the underfill resin supplementary portion is provided in the corner portion of the semiconductor element with a transparent resin, it does not hinder the recognition of the alignment pattern formed on the peripheral portion of the wafer, and the corner of the semiconductor element Insufficient resin amount in the part can be compensated.

以上を前提として、次に、本発明の実施例１の半導体装置の製造工程を説明する。まず、図３（ａ）に示すように、例えば、約１００μｍΦ、１００μｍの厚さのＳｎ−２．６Ａｇからなる半田電極（図示は省略）を２５０μｍピッチでアレイ状に形成したウェハ３１を用意する。   Based on the above, next, the manufacturing process of the semiconductor device of Example 1 of the present invention will be described. First, as shown in FIG. 3A, for example, a wafer 31 is prepared in which solder electrodes (not shown) made of Sn-2.6Ag having a thickness of about 100 μmΦ and 100 μm are formed in an array at a pitch of 250 μm. .

次いで、図３（ｂ）に示すように、シリカフィラーを含有するとともにカルボン酸を含有してフラックス機能を持たせたエポキシ樹脂を主成分とする第１の封止樹脂３２をスピンコートによって形成する。スピンコート条件は、５００ｒｐｍで５秒間保持したのち、７００ｒｐｍで３０秒間保持してウェハ３１の全面に均一に塗布する。   Next, as shown in FIG. 3B, a first sealing resin 32 mainly composed of an epoxy resin containing a silica filler and containing a carboxylic acid and having a flux function is formed by spin coating. . As for the spin coating condition, after holding at 500 rpm for 5 seconds, it is held at 700 rpm for 30 seconds and uniformly applied to the entire surface of the wafer 31.

次いで、ウェハ３１のエッジから３〜５ｍｍ、例えば、５ｍｍの第１の封止樹脂３２の周辺部を例えば、メチルエチルケトンによって１５００ｒｐｍで２０秒間洗浄することで除去する。この除去工程において、後述する第２の封止樹脂を露光する際のアライメント用パターン３３が露出されることになる。   Next, the peripheral portion of the first sealing resin 32 having a thickness of 3 to 5 mm, for example, 5 mm, is removed from the edge of the wafer 31 by washing with, for example, methyl ethyl ketone at 1500 rpm for 20 seconds. In this removal step, the alignment pattern 33 when exposing a second sealing resin described later is exposed.

次いで、図３（ｃ）に示すように、オーブンで、例えば、１２０℃で３０分間熱処理することによりＢステージ（半硬化）状態とした。熱処理後の第１の封止樹脂３２の膜厚は約１１０μｍであった。   Next, as shown in FIG. 3C, a B stage (semi-cured) state was obtained by heat treatment in an oven, for example, at 120 ° C. for 30 minutes. The film thickness of the first sealing resin 32 after the heat treatment was about 110 μm.

次いで、図４（ａ）に示すように、感光性エポキシ系樹脂、例えば、ＷＰＲＳ１９６Ｐ（ＪＳＲ社製商品型番）を用いて第２の封止樹脂３４をスピンコートによって形成する。スピンコート条件は、５００ｒｐｍで５秒間保持したのち、１５００ｒｐｍで３０秒間保持してウェハ３１の全面に均一に塗布する。   Next, as shown in FIG. 4A, the second sealing resin 34 is formed by spin coating using a photosensitive epoxy resin, for example, WPRS196P (product model number manufactured by JSR). As for the spin coating condition, after being held at 500 rpm for 5 seconds, it is held at 1500 rpm for 30 seconds and uniformly applied to the entire surface of the wafer 31.

次いで、図４（ｂ）に示すように、オーブンで、例えば、１１０℃で５分間熱処理することによりＢステージ（半硬化）状態とした。熱処理後の第２の封止樹脂３４の膜厚は約５０μｍであった。   Next, as shown in FIG. 4B, a B stage (semi-cured) state was obtained by heat treatment in an oven, for example, at 110 ° C. for 5 minutes. The film thickness of the second sealing resin 34 after the heat treatment was about 50 μm.

次いで、図４（ｃ）に示すように、露光機を用いてウエハ３１の外周部に形成されたアライメント用パターン３３を参照して位置合わせを行い、紫外線を例えば１５００ｍＪ／ｃｍ2 照射したのち、現像液ＮＭＤ−３（東京応化工業株式会社社製商品型番）に約３．５分間浸積して第２の封止樹脂パターン３５を形成する。 Next, as shown in FIG. 4C, alignment is performed with reference to the alignment pattern 33 formed on the outer peripheral portion of the wafer 31 using an exposure machine, and after irradiation with, for example, 1500 mJ / cm 2 of ultraviolet rays, A second sealing resin pattern 35 is formed by immersing in developer NMD-3 (product model number, manufactured by Tokyo Ohka Kogyo Co., Ltd.) for about 3.5 minutes.

この場合、各第２の封止樹脂パターン３５のサイズは、第２の封止樹脂パターン３５の膜厚にも依存するが半導体チップ３６の面積の２〜１０％になるようにする。また、このパターニング工程において、フリップチップ接合時の位置合わせ用として、十字状のマーク３７を半導体チップ３６の対角に形成する。   In this case, the size of each second sealing resin pattern 35 is set to be 2 to 10% of the area of the semiconductor chip 36 although it depends on the film thickness of the second sealing resin pattern 35. Further, in this patterning step, a cross-shaped mark 37 is formed on the diagonal of the semiconductor chip 36 for alignment at the time of flip chip bonding.

以降は、上記の図２に示したように、半導体チップ３６を回路基板に対向させ、例えば、２３０℃で１０秒間加熱し、半導体チップ３６に形成したＳｎ−２．６Ａｇからなる半田電極を溶融させるとともに、第１の封止樹脂３２及び第２の封止樹脂パターン３５を軟化させた状態で、例えば、２ＭＰａで圧接することによってフリップチップ接合する。この時、加圧により軟化した第１の封止樹脂３２及び第２の封止樹脂パターン３５は半導体チップ３６の外周部から押し出されててフィレットを形成する。   Thereafter, as shown in FIG. 2 above, the semiconductor chip 36 is opposed to the circuit board and heated at 230 ° C. for 10 seconds, for example, to melt the solder electrode made of Sn-2.6Ag formed on the semiconductor chip 36. At the same time, in a state where the first sealing resin 32 and the second sealing resin pattern 35 are softened, the flip chip bonding is performed, for example, by press-contacting at 2 MPa. At this time, the first sealing resin 32 and the second sealing resin pattern 35 softened by pressurization are pushed out from the outer peripheral portion of the semiconductor chip 36 to form a fillet.

その後、例えば、１８０℃で２時間熱処理をすることによって、アンダーフィル状態の第１の封止樹脂３２と、第１の封止樹脂３２及び第２の封止樹脂パターン３５が押し出されて形成したフィレットを完全硬化させることによって本発明の実施例１の半導体装置の基本構成が完成する。   Thereafter, for example, the first sealing resin 32 in the underfill state, the first sealing resin 32, and the second sealing resin pattern 35 are extruded and formed by heat treatment at 180 ° C. for 2 hours. By completely curing the fillet, the basic configuration of the semiconductor device according to the first embodiment of the present invention is completed.

このように、本発明の実施例１においては、封止樹脂の主要部を耐熱性及び耐湿性に優れた第１の封止樹脂で構成するとともに、半導体チップのコーナー部における樹脂量の不足を補うために感光性を有する透明な第２の封止樹脂を半導体チップのコーナー部に選択的に設けているので半導体装置の信頼性を高めることができる。   Thus, in Example 1 of the present invention, the main part of the sealing resin is constituted by the first sealing resin excellent in heat resistance and moisture resistance, and the resin amount in the corner part of the semiconductor chip is insufficient. In order to compensate, the transparent second sealing resin having photosensitivity is selectively provided in the corner portion of the semiconductor chip, so that the reliability of the semiconductor device can be improved.

次に、図５を参照して、本発明の実施例２の半導体装置を説明するが、第２の封止樹脂パターンが異なるだけで基本的な製造工程は上記の実施例１と同様であるので、素子構成のみ説明する。なお、図５（ａ）はフリップチップ接合前の半導体チップの回路面側の概念的平面図であり、図５（ｂ）はフリップチップ接合後の半導体チップ側からみた概念的平面図である。   Next, referring to FIG. 5, the semiconductor device according to the second embodiment of the present invention will be described. The basic manufacturing process is the same as that of the first embodiment except that the second sealing resin pattern is different. Therefore, only the element configuration will be described. 5A is a conceptual plan view on the circuit surface side of the semiconductor chip before flip chip bonding, and FIG. 5B is a conceptual plan view seen from the semiconductor chip side after flip chip bonding.

まず、図５（ａ）に示すように、半導体チップの回路面側に、上記の実施例１と同様に、シリカフィラーを含有するとともにカルボン酸を含有してフラックス機能を持たせたエポキシ樹脂を主成分とする第１の封止樹脂３２をスピンコートによって形成したのち、半硬化状態にする。なお、この場合の第１の封止樹脂３２の軟化温度は１２０℃とする。   First, as shown in FIG. 5A, on the circuit surface side of the semiconductor chip, an epoxy resin containing a silica filler and containing a carboxylic acid and having a flux function is provided in the same manner as in Example 1 above. After the first sealing resin 32 as the main component is formed by spin coating, it is brought into a semi-cured state. In this case, the softening temperature of the first sealing resin 32 is 120 ° C.

次いで、感光性エポキシ系樹脂、例えば、ＷＰＲＳ１９６Ｐ（ＪＳＲ社製商品型番）を用いて第２の封止樹脂をスピンコートによって形成したのち、オーブンで熱処理することによりＢステージ（半硬化）状態する。なお、この場合の第２の封止樹脂の軟化温度は第１の封止樹脂３２の軟化温度である１５０℃より低い１２０℃とする。   Next, a second sealing resin is formed by spin coating using a photosensitive epoxy resin, for example, WPRS196P (product model number manufactured by JSR), and then heat-treated in an oven to be in a B stage (semi-cured) state. In this case, the softening temperature of the second sealing resin is 120 ° C. lower than 150 ° C., which is the softening temperature of the first sealing resin 32.

次いで、露光機を用いてウエハの外周部に形成されたアライメント用パターン３３を参照して位置合わせを行い、紫外線を照射したのち、現像液で現像することにより、放射状のストライプパターンからなる第２の封止樹脂パターン３８を形成するとともに、位置合わせ用のマーク３７を形成する。   Next, alignment is performed with reference to the alignment pattern 33 formed on the outer peripheral portion of the wafer using an exposure machine, and after irradiation with ultraviolet rays, development is performed with a developing solution, whereby a second stripe pattern having a radial stripe pattern is formed. The sealing resin pattern 38 is formed, and the alignment mark 37 is formed.

この場合、第２の封止樹脂パターン３８を構成するストライプ状パターンのうち、半導体チップの４隅方向に伸びるストライプ状パターンの幅が、その他の方向に伸びるストライプ状パターンの幅より広くなるパターンとする。例えば、各コーナーにおける第２の封止樹脂パターン３８によるフィレット（図５（ｂ）の４１）が０．１〜１．０ｍｍ3 の樹脂量になるようにストライプ状パターンの幅及び厚さを規定する。 In this case, among the stripe patterns constituting the second sealing resin pattern 38, the width of the stripe pattern extending in the four corner directions of the semiconductor chip is wider than the width of the stripe pattern extending in the other direction; To do. For example, the width and thickness of the stripe pattern are defined so that the fillet (41 in FIG. 5B) by the second sealing resin pattern 38 at each corner has a resin amount of 0.1 to 1.0 mm 3. To do.

以降は、図５（ｂ）に示すように、半導体チップ３６を回路基板３９に対向させ、例えば、第２の封止樹脂の軟化温度である１５０℃以上に加熱したのち、加圧して第２の封止樹脂をチップ外周まで押し出すことによりフィレット４１が形成される。   Thereafter, as shown in FIG. 5B, the semiconductor chip 36 is opposed to the circuit board 39, and heated to, for example, 150 ° C. or more, which is the softening temperature of the second sealing resin, and then pressurized to the second The fillet 41 is formed by extruding the sealing resin to the outer periphery of the chip.

次いで、第２の封止樹脂の軟化温度である１５０℃以上、例えば、２３０℃まで昇温して１０秒間加熱し、半導体チップ３６に形成したＳｎ−２．６Ａｇからなる半田電極を溶融させるとともに、第１の封止樹脂３２を軟化させた状態で、例えば、２ＭＰａで圧接することによってフリップチップ接合する。この時、加圧により軟化した第１の封止樹脂３２の一部も半導体チップ３６の外周部から押し出されててフィレット４０を形成する。   Next, the temperature is raised to 150 ° C. or higher, which is the softening temperature of the second sealing resin, for example, 230 ° C. and heated for 10 seconds to melt the solder electrode made of Sn-2.6Ag formed on the semiconductor chip 36. In a state in which the first sealing resin 32 is softened, the flip chip bonding is performed, for example, by press-contacting at 2 MPa. At this time, a part of the first sealing resin 32 softened by pressurization is also pushed out from the outer peripheral portion of the semiconductor chip 36 to form the fillet 40.

その後、例えば、１８０℃で２時間熱処理をすることによって、アンダーフィル状態の第１の封止樹脂３２と、フィレット４０，４１を完全硬化させることによって本発明の実施例２の半導体装置の基本構成が完成する。   After that, for example, by performing a heat treatment at 180 ° C. for 2 hours, the first sealing resin 32 in the underfill state and the fillets 40 and 41 are completely cured, whereby the basic configuration of the semiconductor device according to the second embodiment of the present invention. Is completed.

この本発明の実施例２においては、信頼性の劣る第２の封止樹脂は第１の封止樹脂が軟化していない状態における最初の加圧工程で大部分が半導体チップ３６の外周部に押し出されて半導体チップ３６の直下には存在しないため、信頼性が向上する。   In the second embodiment of the present invention, the second sealing resin with low reliability is mostly in the outer periphery of the semiconductor chip 36 in the first pressurizing step in the state where the first sealing resin is not softened. Since it is pushed out and does not exist directly under the semiconductor chip 36, the reliability is improved.

以上、本発明の各実施例を説明してきたが、本発明は、各実施例に示した条件に限られるものではない。例えば、第２の封止樹脂を露光する際のアライメント用パターン露出方法として、周辺部をメチルエチルケトンによる洗浄を用いているが、レーザー加工によってウエハ外周部の少なくとも２カ所の樹脂を除去しても良い。   As mentioned above, although each Example of this invention was described, this invention is not restricted to the conditions shown in each Example. For example, as a pattern exposure method for alignment when exposing the second sealing resin, the peripheral portion is cleaned with methyl ethyl ketone. However, at least two resins on the outer peripheral portion of the wafer may be removed by laser processing. .

或いは、予め保護フィルムを外周部に貼付して、第１の封止樹脂後に保護フィルムを除去することで位置合わせマークを露出させることも可能である。または、露光装置に赤外線で樹脂を透過させることで位置合わせを行う機能があれば、外周部の樹脂を除去する必要なく第２の封止樹脂を位置合わせすることが可能である。またこの場合には、第２の封止樹脂に透過性のある樹脂を用いなくても本願の製造方法は達成可能である。   Alternatively, it is also possible to expose the alignment mark by pasting a protective film on the outer periphery in advance and removing the protective film after the first sealing resin. Alternatively, if the exposure apparatus has a function of performing alignment by transmitting the resin with infrared rays, it is possible to align the second sealing resin without having to remove the resin on the outer peripheral portion. In this case, the manufacturing method of the present application can be achieved without using a permeable resin for the second sealing resin.

ここで、実施例１及び実施例２を含む本発明の実施の形態に関して、以下の付記を開示する。
（付記１） 半導体チップと前記半導体チップを搭載する回路基板上との間に充填する第１の封止樹脂が前記半導体チップの外周からはみ出しており、且つ、前記半導体チップの少なくとも４隅において前記第１の封止樹脂を覆うように第２の封止樹脂が設けられた半導体装置であって、前記第１の封止樹脂の耐湿性及び耐熱性が前記第２の封止樹脂の耐湿性及び耐熱性より優れているとともに、前記第１の封止樹脂は可視光及び赤外光に対して不透明であり且つ前記第２の封止樹脂は可視光或いは赤外光に対して透過性を有する先アンダーフィル接合方式半導体装置。
（付記２） 前記第１の封止樹脂は、無機フィラー或いは有機フィラーのいずれかを含むエポキシ系樹脂、無機フィラー或いは有機フィラーのいずれかを含むウレタン系樹脂、無機フィラー或いは有機フィラーのいずれかを含むシアネートエステル系樹脂、或いは、無機フィラー或いは有機フィラーのいずれかを含むフェノキシ樹脂のいずれかを主成分とするとともに、フラックス機能を有する有機酸を含んでいる付記１に記載の先アンダーフィル接合方式半導体装置。
（付記３） 前記の第２の封止樹脂は、感光性を有するとともに、可視光に対して透過性を有する付記１または付記２に記載の先アンダーフィル接合方式半導体装置。
（付記４）
前記第２の樹脂は、フィラーを含まないエポキシ系樹脂、フィラーを含まないウレタン系樹脂、フィラーを含まないフェノキシ樹脂或いはフィラーを含まないシアネートエステル系樹脂のいずれかを主成分とすることを特徴とする付記３に記載の先アンダーフィル接合方式半導体装置。
（付記５） 半導体チップの回路面上に第１の封止樹脂を塗布して半硬化させる工程、前記第１の封止樹脂層上であって、前記半導体チップの少なくとも４隅を含むようにパターンニングされた第２の封止樹脂層を選択的に形成して半硬化させる工程と、前記第１の封止樹脂層及び第２の封止樹脂層を設けた半導体チップを回路基板に対して圧接してフリップチップ接合する工程とを有する先アンダーフィル接合方式半導体装置の製造方法。
（付記６） 前記第２の封止樹脂層をパターニングする工程において、前記第２の封止樹脂層に、少なくとも２つの位置合わせ用のマークをパターニングする付記５に記載の先アンダーフィル接合方式半導体装置の製造方法。
（付記７） 前記第１の封止樹脂層は、シート状のフィルムをラミネートによって貼付する工程、或いは、液状樹脂を印刷もしくはスピンコートのいずれかにより塗布した後、乾燥し半硬化状態とする工程のいずれかによって形成される付記５または付記６に記載の先アンダーフィル接合方式半導体装置の製造方法。
（付記８） 前記第２の封止樹脂層は、シート状のフィルムをラミネートによって貼付する工程、或いは、液状樹脂を印刷もしくはスピンコートのいずれかにより塗布した後、乾燥し半硬化状態とする工程のいずれかによって形成したのち、露光・現像によってパターンニングする工程によって選択的に形成される付記５乃至付記７のいずれか１に記載の先アンダーフィル接合方式半導体装置の製造方法。
（付記９） 前記露光・現像によってパターンニングする工程において、前記第２の封止樹脂層を、前記半導体チップの４隅のみに選択的に設ける付記８に記載の先アンダーフィル接合方式半導体装置の製造方法。
（付記１０） 前記露光・現像によってパターンニングする工程において、前記第２の封止樹脂層を、前記半導体チップの中心から放射状に伸びる複数のストライプ状パターンで構成するとともに、前記ストライプ状パターンのうち、前記半導体チップの４隅に伸びるストライプ状パターンの幅が、その他の方向に伸びるストライプ状パターンの幅より広くする付記８に記載の先アンダーフィル接合方式半導体装置の製造方法。 Here, the following supplementary notes are disclosed regarding the embodiment of the present invention including Example 1 and Example 2.
(Additional remark 1) The 1st sealing resin with which it fills between a semiconductor chip and the circuit board which mounts the said semiconductor chip has protruded from the outer periphery of the said semiconductor chip, and the said semiconductor chip has at least four corners. A semiconductor device provided with a second sealing resin so as to cover the first sealing resin, wherein the moisture resistance and heat resistance of the first sealing resin are moisture resistance of the second sealing resin. And the first sealing resin is opaque to visible light and infrared light, and the second sealing resin is transparent to visible light or infrared light. A pre-underfill bonding type semiconductor device.
(Additional remark 2) Said 1st sealing resin is either the epoxy resin containing either an inorganic filler or an organic filler, the urethane type resin containing either an inorganic filler or an organic filler , an inorganic filler, or an organic filler. The pre-underfill bonding method according to supplementary note 1, comprising a cyanate ester-based resin or a phenoxy resin containing either an inorganic filler or an organic filler as a main component and an organic acid having a flux function Semiconductor device.
(Additional remark 3) The said 2nd sealing resin is a tip underfill junction system semiconductor device of Additional remark 1 or Additional remark 2 which has the transparency with respect to visible light while having photosensitivity.
(Appendix 4)
The second resin is mainly composed of an epoxy resin not containing a filler, a urethane resin not containing a filler, a phenoxy resin not containing a filler, or a cyanate ester resin not containing a filler. The pre-underfill junction type semiconductor device according to appendix 3.
(Supplementary Note 5 ) A step of applying and semi-curing a first sealing resin on a circuit surface of a semiconductor chip, on the first sealing resin layer so as to include at least four corners of the semiconductor chip A step of selectively forming and semi-curing a patterned second sealing resin layer, and a semiconductor chip provided with the first sealing resin layer and the second sealing resin layer on a circuit board And a method of manufacturing a pre-underfill bonding type semiconductor device including a step of pressure-bonding and flip-chip bonding.
(Supplementary note 6 ) The pre-underfill junction type semiconductor according to supplementary note 5 , wherein in the step of patterning the second sealing resin layer, at least two alignment marks are patterned on the second sealing resin layer. Device manufacturing method.
(Appendix 7 ) The first sealing resin layer is a step of laminating a sheet-like film, or a step of applying a liquid resin by either printing or spin coating and then drying to make it a semi-cured state The manufacturing method of the tip underfill junction type semiconductor device according to appendix 5 or appendix 6 , which is formed by any of the above .
(Appendix 8 ) The second sealing resin layer is a step of applying a sheet-like film by lamination, or a step of applying a liquid resin by either printing or spin coating, and then drying to make it a semi-cured state 8. The method of manufacturing a pre-underfill junction type semiconductor device according to any one of appendix 5 to appendix 7 , wherein the semiconductor device is selectively formed by a patterning process by exposure / development after forming by any of the above .
(Supplementary Note 9 ) In the step of patterning by exposure / development, the first underfill junction type semiconductor device according to Supplementary Note 8 , wherein the second sealing resin layer is selectively provided only at four corners of the semiconductor chip. Production method.
(Supplementary Note 10 ) In the step of patterning by exposure / development, the second sealing resin layer is constituted by a plurality of stripe patterns extending radially from the center of the semiconductor chip, and among the stripe patterns 9. The manufacturing method of a pre-underfill junction type semiconductor device according to appendix 8 , wherein the width of the stripe pattern extending to the four corners of the semiconductor chip is wider than the width of the stripe pattern extending in the other direction.

本発明の実施の形態のフリップチップ接合前の構成説明図である。It is structure explanatory drawing before the flip-chip joining of embodiment of this invention. 本発明の実施の形態のフリップチップ接合後の構成説明図である。It is structure explanatory drawing after the flip-chip joining of embodiment of this invention. 本発明の実施例１の半導体装置の製造工程の途中までの説明図である。It is explanatory drawing to the middle of the manufacturing process of the semiconductor device of Example 1 of this invention. 本発明の実施例１の半導体装置の製造工程の図３以降の説明図である。FIG. 4 is an explanatory diagram of the semiconductor device manufacturing process of Example 1 of the present invention after FIG. 3. 本発明の実施例２の半導体装置の製造方法における第２封止樹脂パターンの説明図である。It is explanatory drawing of the 2nd sealing resin pattern in the manufacturing method of the semiconductor device of Example 2 of this invention. 従来の先アンダーフィル方式による半導体装置の概念的平面図である。It is a conceptual top view of the semiconductor device by the conventional tip underfill system.

符号の説明Explanation of symbols

１１ 半導体素子
１２ パッド
１３ 接続電極
１４ 第１の封止樹脂
１５ 第２の封止樹脂
１６ 位置合わせ用マーク
１７，１８ フィレット部
２１ 回路基板
２２ パッド
２３ ソルダーレジスト
３１ ウェハ
３２ 第１の封止樹脂
３３ アライメント用パターン
３４ 第２の封止樹脂
３５ 第２の封止樹脂パターン
３６ 半導体チップ
３７ マーク
３８ 第２の封止樹脂パターン
３９ 回路基板
４０，４１ フィレット
５１ 回路基板
５２ 半導体素子
５３ 封止樹脂 DESCRIPTION OF SYMBOLS 11 Semiconductor element 12 Pad 13 Connection electrode 14 1st sealing resin 15 2nd sealing resin 16 Mark 17 for alignment, 18 Fillet part 21 Circuit board 22 Pad 23 Solder resist 31 Wafer 32 1st sealing resin 33 Alignment pattern 34 Second sealing resin 35 Second sealing resin pattern 36 Semiconductor chip 37 Mark 38 Second sealing resin pattern 39 Circuit boards 40, 41 Fillet 51 Circuit board 52 Semiconductor element 53 Sealing resin

Claims (6)

半導体チップと前記半導体チップを搭載する回路基板上との間に充填する第１の封止樹脂が前記半導体チップの外周からはみ出しており、且つ、前記半導体チップの少なくとも４隅において前記第１の封止樹脂を覆うように第２の封止樹脂が設けられた半導体装置であって、前記第１の封止樹脂の耐湿性及び耐熱性が前記第２の封止樹脂の耐湿性及び耐熱性より優れているとともに、前記第１の封止樹脂は可視光及び赤外光に対して不透明であり且つ前記第２の封止樹脂は可視光或いは赤外光に対して透過性を有する先アンダーフィル接合方式半導体装置。 A first sealing resin filled between a semiconductor chip and a circuit board on which the semiconductor chip is mounted protrudes from the outer periphery of the semiconductor chip, and the first sealing resin is at least at four corners of the semiconductor chip. A semiconductor device provided with a second sealing resin so as to cover the stop resin, wherein the moisture resistance and heat resistance of the first sealing resin are higher than the moisture resistance and heat resistance of the second sealing resin. with excellent, above underfill having transparency the first sealing resin is opaque to visible light and infrared light and the second sealing resin to visible light or infrared light Junction semiconductor device. 前記第１の封止樹脂は、無機フィラー或いは有機フィラーのいずれかを含むエポキシ系樹脂、無機フィラー或いは有機フィラーのいずれかを含むウレタン系樹脂、無機フィラー或いは有機フィラーのいずれかを含むシアネートエステル系樹脂、或いは、無機フィラー或いは有機フィラーのいずれかを含むフェノキシ樹脂のいずれかを主成分とするとともに、フラックス機能を有する有機酸を含んでいる請求項１に記載の先アンダーフィル接合方式半導体装置。 The first sealing resin is an epoxy resin containing either an inorganic filler or an organic filler, a urethane resin containing either an inorganic filler or an organic filler, or a cyanate ester containing either an inorganic filler or an organic filler. 2. The pre-underfill junction type semiconductor device according to claim 1 , comprising a resin or an organic acid having a flux function as a main component and one of a phenoxy resin containing either an inorganic filler or an organic filler . 前記第２の樹脂は、フィラーを含まないエポキシ系樹脂、フィラーを含まないウレタン系樹脂、フィラーを含まないフェノキシ樹脂或いはフィラーを含まないシアネートエステル系樹脂のいずれかを主成分とすることを特徴とする請求項２に記載の先アンダーフィル接合方式半導体装置。The second resin is mainly composed of an epoxy resin not containing a filler, a urethane resin not containing a filler, a phenoxy resin not containing a filler, or a cyanate ester resin not containing a filler. The pre-underfill junction type semiconductor device according to claim 2. 半導体チップの回路面上に第１の封止樹脂を塗布して半硬化させる工程、前記第１の封止樹脂層上であって、前記半導体チップの少なくとも４隅を含むようにパターンニングされた第２の封止樹脂層を選択的に形成して半硬化させる工程と、前記第１の封止樹脂層及び第２の封止樹脂層を設けた半導体チップを回路基板に対して圧接してフリップチップ接合する工程とを有する先アンダーフィル接合方式半導体装置の製造方法。 A step of applying and semi-curing a first sealing resin on the circuit surface of the semiconductor chip, the first sealing resin layer being patterned to include at least four corners of the semiconductor chip A step of selectively forming and semi-curing the second sealing resin layer, and pressing the semiconductor chip provided with the first sealing resin layer and the second sealing resin layer against the circuit board A method of manufacturing a pre-underfill bonding type semiconductor device including a step of flip chip bonding. 前記第２の封止樹脂層を、前記半導体チップの４隅のみに選択的に設ける請求項４に記載の先アンダーフィル接合方式半導体装置の製造方法。 The method for manufacturing a pre-underfill junction type semiconductor device according to claim 4, wherein the second sealing resin layer is selectively provided only at four corners of the semiconductor chip. 前記第２の封止樹脂層を、前記半導体チップの中心から放射状に伸びる複数のストライプ状パターンで構成するとともに、前記ストライプ状パターンのうち、半導体チップの４隅に伸びるストライプ状パターンの幅を、その他の方向に伸びるストライプ状パターンの幅より広くする請求項４に記載の先アンダーフィル接合方式半導体装置の製造方法。 The second sealing resin layer is constituted by a plurality of stripe patterns extending radially from the center of the semiconductor chip, and the width of the stripe pattern extending to the four corners of the semiconductor chip among the stripe patterns, 5. The method of manufacturing a pre-underfill junction type semiconductor device according to claim 4, wherein the width is wider than the width of the stripe pattern extending in the other direction.
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