JP2004281899A - Semiconductor device, manufacturing method thereof, circuit board, and electronic appliance - Google Patents

Semiconductor device, manufacturing method thereof, circuit board, and electronic appliance Download PDF

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JP2004281899A
JP2004281899A JP2003073928A JP2003073928A JP2004281899A JP 2004281899 A JP2004281899 A JP 2004281899A JP 2003073928 A JP2003073928 A JP 2003073928A JP 2003073928 A JP2003073928 A JP 2003073928A JP 2004281899 A JP2004281899 A JP 2004281899A
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semiconductor chip
semiconductor device
manufacturing
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Hideo Miyasaka
英男 宮坂
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Seiko Epson Corp
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Seiko Epson Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

<P>PROBLEM TO BE SOLVED: To improve the reliability of a semiconductor device. <P>SOLUTION: The semiconductor device is manufactured (a) by so subjecting via a first resin 30 a semiconductor chip 10 having electrodes 12 on its front surface 14 to face-down bonding to a board 20 having formed wiring patterns 22 to connect electrically the electrodes 12 with the wiring patterns 22, and (b) by providing a second resin 40 by covering therewith the corner portions of the semiconductor chip 10 to expose to the external at least a portion of a rear surface 18 of the semiconductor chip 10. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体装置及びその製造方法、回路基板並びに電子機器に関する。
【０００２】
【従来の技術】
【０００３】
【特許文献１】
特開２００１−２５７２３２号公報
【０００４】
【発明の背景】
半導体装置の構造として、配線パターンが形成された基板に、異方性導電材料からなる接着剤を使用して、半導体チップをフェースダウン実装する構造が知られている。従来の形態によれば、接着剤が半導体チップの角部にまで流れ込むように、接着剤の材質及び量を決めていたが、そうした場合であっても、実際の工程では、半導体チップの角部（電極が形成された面側の角部）が接着剤から露出する場合があり、温度サイクル試験などの環境試験を行なうと半導体チップの角部からクラックが発生する可能性があった。
【０００５】
本発明の目的は、半導体装置の信頼性を高めることにある。
【０００６】
【課題を解決するための手段】
（１）本発明に係る半導体装置の製造方法は、（ａ）表面に電極を有する半導体チップを、第１の樹脂を介して、配線パターンが形成された基板にフェースダウンボンディングすることによって、前記電極と前記配線パターンとを電気的に接続すること、
（ｂ）第２の樹脂を、前記半導体チップの裏面の少なくとも一部が露出するように、前記半導体チップの角部を覆って設けること、
を含む。本発明によれば、第２の樹脂を、半導体チップの角部を覆うように設ける。これによって、半導体チップの角部に加わるダメージを軽減することができ、角部を起点として、半導体チップが割れるのを防止することができる。したがって、半導体装置の信頼性を高めることができる。
（２）この半導体装置の製造方法において、
前記（ａ）工程後に、前記（ｂ）工程を行ってもよい。これによれば、第２の樹脂を設ける工程を、半導体チップをフェースダウンボンディングした後に行うので、第２の樹脂によって、ボンディング後の半導体チップの角部を確実に覆うことができる。
（３）この半導体装置の製造方法において、
前記（ｂ）工程を、前記第１の樹脂の硬化後に行ってもよい。これによれば、第１及び第２の樹脂が混合しない又は混合する量が少ないので、第２の樹脂が半導体チップの電極付近に流れ込むのを防止し、電極と配線パターンとの電気的導通が図れなくなることを防止することができる。
（４）この半導体装置の製造方法において、
前記（ａ）工程は、
（ａ１）前記半導体チップ及び前記基板の少なくともいずれか一方に前記第１の樹脂を設けること、
（ａ２）前記半導体チップを前記基板にフェースダウンボンディングすること、
を含んでもよい。
（５）この半導体装置の製造方法において、
前記（ａ１）工程で、前記第１の樹脂を、前記半導体チップの平面形状を含む大きさの平面領域を有するように設け、
前記（ｂ）工程で、前記第２の樹脂を、前記第１の樹脂上に設けてもよい。これによれば、第２の樹脂によって、半導体チップの角部を覆いやすくすることができる。
（６）この半導体装置の製造方法において、
前記（ａ１）工程で、シート状の前記第１の樹脂を設け、
前記（ｂ）工程で、ペースト状の前記第２の樹脂を設けてもよい。これによれば、第１の樹脂の取り扱いに優れるとともに、第２の樹脂を半導体チップの角部に密着して設けることができる。
（７）この半導体装置の製造方法において、
前記半導体チップは、平面位置の異なる複数の前記角部と、隣り合う前記角部同士の間の側面と、を有し、
前記（ｂ）工程で、前記第２の樹脂を、前記側面に付着させないで、前記角部付近に付着させて設けてもよい。
（８）この半導体装置の製造方法において、
前記半導体チップの前記角部は、前記半導体チップの前記電極が形成された前記表面と、前記表面に接する２つの側面と、が交わる頂点の部分であり、
前記（ｂ）工程で、
前記第１の樹脂は、前記半導体チップの前記電極が形成された前記表面に密着しており、
前記第２の樹脂を、前記半導体チップの前記表面側の前記角部を覆うように設けてもよい。これによれば、半導体チップの電極が形成された表面側の角部からの割れを防止することができる。
（９）この半導体装置の製造方法において、
前記（ｂ）工程開始時に、前記第１の樹脂は、前記角部に対応する部分が他の部分よりも薄くなっていてもよい。
（１０）この半導体装置の製造方法において、
前記（ｂ）工程で、前記第２の樹脂を、前記半導体チップの前記裏面までの高さよりも低くなるように設けてもよい。
（１１）この半導体装置の製造方法において、
前記第１の樹脂における接着時の流動性は、前記第２の樹脂における接着時の流動性よりも低くてもよい。
（１２）この半導体装置の製造方法において、
前記第１の樹脂は、導電粒子を含む異方性導電接着剤であってもよい。
（１３）この半導体装置の製造方法において、
前記第２の樹脂は、導電粒子を含まない絶縁性接着剤であってもよい。
（１４）本発明に係る半導体装置は、表面に電極を有する半導体チップと、
配線パターンが形成され、半導体チップがフェースダウンボンディングされた基板と、
前記電極と前記配線パターンを電気的に接続する導電粒子を有し、前記半導体チップと前記基板との間に設けられた異方性導電接着剤と、
前記半導体チップの裏面の少なくとも一部が露出するように、前記半導体チップの角部を覆って設けられた絶縁性接着剤と、
を含む。本発明によれば、絶縁性接着剤が、半導体チップの角部を覆うように設けられている。これによって、半導体チップの角部に加わるダメージを軽減することができ、角部を起点として、半導体チップが割れるのを防止することができる。したがって、半導体装置の信頼性を高めることができる。
（１５）本発明に係る半導体装置は、表面に電極を有する半導体チップと、
配線パターンが形成され、半導体チップがフェースダウンボンディングされた基板と、
前記半導体チップと前記基板との間に設けられた第１の樹脂と、
前記半導体チップの裏面の少なくとも一部が露出するように、前記半導体チップの角部を覆って設けられた第２の樹脂と、
を含む。本発明によれば、第２の樹脂が、半導体チップの角部を覆うように設けられている。これによって、半導体チップの角部に加わるダメージを軽減することができ、角部を起点として、半導体チップが割れるのを防止することができる。したがって、半導体装置の信頼性を高めることができる。
（１６）本発明に係る半導体装置は、表面に電極を有する半導体チップと、
配線パターンが形成され、前記半導体チップがフェースダウンボンディングされた基板と、
前記半導体チップの前記電極が形成された前記表面に密着してなる第１の樹脂と、
前記半導体チップの前記電極が形成された前記表面と、前記表面に接する２つの側面と、が交わる角部を覆うとともに、前記半導体チップの裏面の少なくとも一部が露出するように設けられた第２の樹脂と、
を含む。本発明によれば、第２の樹脂が、半導体チップの角部を覆うように設けられている。これによって、半導体チップの角部に加わるダメージを軽減することができ、角部を起点として、半導体チップが割れるのを防止することができる。したがって、半導体装置の信頼性を高めることができる。
（１７）この半導体装置において、
前記第１の樹脂は、前記半導体チップの平面形状を含む大きさの平面領域を有し、
前記第２の樹脂は、前記第１の樹脂上に、前記第１の樹脂の硬化反応を終えた後に設けられていてもよい。これによれば、第１及び第２の樹脂が混合しない又は混合する量が少ないので、第２の樹脂が半導体チップの電極付近に流れ込むのを防止し、電極と配線パターンとの電気的導通が図れなくなることを防止することができる。
（１８）この半導体装置において、
前記第１の樹脂は、前記角部に対応する部分が他の部分よりも薄くなっていてもよい。
（１９）この半導体装置において、
前記第２の樹脂は、前記半導体チップの前記裏面までの高さよりも低くなるように設けられていてもよい。
（２０）本発明に係る回路基板には、上記半導体装置が実装されている。
（２１）本発明に係る電子機器は、上記半導体装置を有する。
【０００７】
【発明の実施の形態】
以下、本発明の実施の形態について図面を参照して説明する。図１〜図３は、本実施の形態に係る半導体装置の製造方法を示す図である。図４は、本実施の形態に係る半導体装置の平面図であり、図５は、図４のＶ−Ｖ線断面図である。本実施の形態では、半導体チップ１０を基板２０に実装する。
【０００８】
半導体チップ１０は、集積回路チップである。半導体チップ１０は、内部の集積回路に電気的に接続された複数の電極１２を有する。電極１２は、半導体チップ１０の表面１４に露出している。表面１４は、いわゆる能動面と呼ばれる面であってもよい。電極１２は、パッドを含む。半導体チップ１０がフェースダウンボンディングされる場合には、電極１２は、パッド上のバンプをさらに含むことが多い。半導体チップ１０の表面１４には、電極１２を避けて、図示しないパッシベーション膜（例えばシリコン酸化膜など）が形成されてもよい。
【０００９】
半導体チップ１０は、複数の角部を有する。半導体チップ１０は、多面体形状をなし、複数の角部は、３面以上（図１では３面）が交わる頂点の部分であってもよい。半導体チップ１０が直方体形状をなす場合、半導体チップ１０は８つの角部（表面１４側の４つの角部１６と、裏面１８側の４つの角部）を有する。半導体チップ１０の表面１４側の角部１６とは、電極１２が形成された表面１４と、表面１４に接する２つの側面１７と、が交わる頂点の部分を指す。なお、半導体チップ１０の角部１６とは、尖っている場合のみならず、丸く削れている場合や一部が欠けている場合も含む。
【００１０】
基板２０の材料は、有機系（例えばポリイミド樹脂、エポキシ樹脂）又は無機系（例えばセラミック、ガラス）のいずれの材料であってもよく、これらの複合構造からなるものであってもよい。基板２０は、半導体パッケージ用のインターポーザであってもよい。絶縁樹脂と配線パターンを積層して構成されるビルドアップ多層構造の基板や、複数の基板が積層された多層基板を使用してもよい。
【００１１】
基板２０には、配線パターン２２が形成されている（図５参照）。配線パターン２２は、電子部品（例えば半導体チップ１０）との電気的な接続部（例えばランド）と、配線と、を有する。配線パターン２２は、導電材料（例えば銅などの金属）で形成され、表面にメッキ層（例えば金層）が形成されることが好ましい。基板２０にスルーホール（図示しない）を形成し、両面の電気的な接続を図ってもよい。
【００１２】
図１に示すように、基板２０に第１の樹脂３０を設ける。第１の樹脂３０は、接着剤である。第１の樹脂３０は、所定のエネルギー（例えば熱、光）によって、接着力が発現し、その後硬化する性質を有してもよい。第１の樹脂３０は、熱硬化性樹脂（又は光硬化性樹脂）であってもよい。変形例として、第１の樹脂３０を、半導体チップ１０又は半導体チップ１０と基板２０との両方に設けてもよい。
【００１３】
図１に示すように、シート状の（固形の）第１の樹脂３０を設けてもよい。これによれば、例えば、第１の樹脂３０を基板２０に載せるだけで済むので、樹脂の取り扱い及び半導体装置の生産性に優れている。あるいは、ペースト状の（液状又はゲル状の）第１の樹脂３０を使用してもよい。
【００１４】
第１の樹脂３０は、半導体チップ１０の平面形状を含む大きさの平面領域を有するように設けてもよい。詳しくは、半導体チップ１０のボンディング後において、半導体チップ１０が第１の樹脂３０の平面領域の内側に配置されるように（図２参照）、第１の樹脂３０の使用量などを決定する。こうすることで、第１の樹脂３０における半導体チップ１０の外側にはみ出した部分に、第２の樹脂４０を設けることが可能になる（図３参照）。
【００１５】
第１の樹脂３０は、異方性導電接着剤（ペースト状又はシート状であるかは問わない）であってもよい。異方性導電接着剤は、絶縁性接着剤（バインダ）に導電粒子３２が分散されたもので、分散剤（例えば絶縁性粒子（シリカ系粒子など））が添加される場合がある。絶縁性接着剤は、熱硬化性樹脂であってもよい。異方性導電接着剤によれば、半導体チップ１０の電極１２と、基板２０の配線パターン２２との間で、導電粒子３２が押し潰されることによって、両者間の電気的な接続が図られる（図５参照）。
【００１６】
図２に示すように、半導体チップ１０を基板２０にフェースダウンボンディングする。詳しくは、第１の樹脂３０を介して、フェースダウンボンディングすることによって、半導体チップ１０の電極１２及び基板２０の配線パターン２２を電気的に接続する。本工程は、ボンディングツール（図示しない）によって、半導体チップ１０の裏面１８を加圧することで行う。その間、第１の樹脂３０に所定のエネルギーを加え、半導体チップ１０と基板２０を接着する。第１の樹脂３０は、接着時に流動性が高くなって、半導体チップ１０の外側の方向に流れ出し、その後硬化する。第１の樹脂３０は、半導体チップ１０の表面１４に密着していてもよい。半導体チップ１０の角部１６は、第１の樹脂３０から露出していてもよい。図２に示す例では、第１の樹脂３０は、半導体チップ１０の角部１６に対応する部分（例えば角部１６に接する部分）が他の部分（例えば側面１７に接する部分）よりも薄くなっている。このように、適切な量の第１の樹脂３０が角部１６に流れ込まない場合に、本実施の形態を適用すると効果的である。
【００１７】
図３に示すように、第２の樹脂４０を、半導体チップ１０の裏面１８の少なくとも一部（図３では全部）が露出するように、かつ、半導体チップ１０の角部（図３では角部１６）を覆うように設ける。これによって、半導体チップ１０の角部（図３では角部１６）に加わるダメージを軽減することができ、角部（図３では角部１６）を起点として、半導体チップ１０が割れるのを防止することができる。
【００１８】
第２の樹脂４０を、半導体チップ１０における角部１６付近（例えば図１の２点鎖線で示した範囲）に付着させてもよい。その場合、第２の樹脂４０を、半導体チップ１０の側面１７に付着させないで、角部１６付近（のみ）に付着させてもよい。あるいは、第２の樹脂４０を、半導体チップ１０の側面１７にも付着させて、半導体チップ１０の周囲を囲むように設けてもよい。
【００１９】
本実施の形態では、第２の樹脂４０によって、半導体チップ１０の表面１４側の角部１６を覆っている。図３に示す例では、第２の樹脂４０を、半導体チップ１０の裏面１８までの高さよりも低くなるように設けている。こうして、半導体チップ１０の裏面１８側の角部１６は、第２の樹脂４０から露出していてもよい。これによれば、半導体チップ１０の表面１４（いわゆる能動面）側を、第１及び第２の樹脂３０，４０によって封止することができ、表面１４側の角部１６からの割れを防止することができる。
【００２０】
変形例として、第２の樹脂４０を、半導体チップ１０の裏面１８までの高さと同一又はそれよりも高くなるように設けてもよい。こうして、半導体チップ１０の表面１４側の角部１６だけでなく、裏面１８側の角部も覆ってもよい。ただし、上述したように、半導体チップ１０の裏面１８の少なくとも一部は、第２の樹脂４０から露出させる。
【００２１】
第２の樹脂４０は、接着剤である。第２の樹脂４０は、所定のエネルギー（例えば熱、光）によって、接着力が発現し、その後硬化する性質を有してもよい。第２の樹脂４０は、熱硬化性樹脂（又は光硬化性樹脂）であってもよい。
【００２２】
本実施の形態では、半導体チップ１０のフェースダウンボンディング工程後に、第２の樹脂４０を設ける。第１の樹脂３０の硬化後に、第２の樹脂４０を設けてもよい。これによれば、第２の樹脂４０によって、ボンディング後の半導体チップの角部を確実に覆うことができる。また、第２の樹脂４０がボンディングツールに付着することもない。
【００２３】
変形例として、半導体チップ１０のボンディング工程前に、第２の樹脂４０を設けても構わない。その場合、第２の樹脂４０を、半導体チップ１０の角部１６付近に付着させてもよいし、あるいは、基板２０における半導体チップ１０の角部１６に対応する位置に設けてもよい。
【００２４】
ペースト状の第２の樹脂４０をポッティングしてもよい。これによって、第２の樹脂４０を、半導体チップ１０の角部１６付近に密着して設けることができ、確実に角部１６を覆うことができる。あるいは、シート状の第２の樹脂４０を使用してもよい。
【００２５】
図３に示すように、第２の樹脂４０を第１の樹脂３０上に設けてもよい。詳しくは、第１の樹脂３０における半導体チップ１０の外側にはみ出した部分に、第２の樹脂４０を設けてもよい。第１の樹脂３０における半導体チップ１０の角部１６に対応する部分は薄くなっているので、第２の樹脂４０によって、半導体チップ１０の角部１６を補強することができる。
【００２６】
第２の樹脂４０は、絶縁性接着剤（ペースト状又はシート状であるかは問わない）であってもよい。第２の樹脂４０は、導電粒子を含まない絶縁性接着剤であってもよい。第１及び第２の樹脂３０，４０の材料（例えばバインダの材料）は、同一の樹脂（例えばエポキシ樹脂）を使用してもよい。第１及び第２の樹脂３０，４０は、熱膨張率や弾性率などの物性値が同一又は近似していることが好ましい。こうすることで、半導体装置に生じる内部応力を、吸収又は緩和しやすくすることができ、信頼性の向上を図ることができる。第１の樹脂３０における接着時の流動性は、第２の樹脂４０における接着時の流動性よりも低くてもよい。すなわち、半導体チップ１０の角部１６に適切な量の第１の樹脂３０が流れ込まないときに、流動性の高い第２の樹脂４０を使用すると効果的である。
【００２７】
第２の樹脂４０を硬化させた後に、基板２０の配線パターン２２に電気的に接続する複数の外部端子５０を設けてもよい。外部端子５０は、導電性を有する金属（例えばろう材）で形成され、例えば球状をなすハンダボールであってもよい。
【００２８】
本実施の形態に係る半導体装置の製造方法は、上述のように構成されており、その効果はすでに説明した通りである。
【００２９】
半導体装置１は、半導体チップ１０と、基板２０と、第１の樹脂（異方性導電接着剤）３０と、第２の樹脂（絶縁性接着剤）４０と、を含む。半導体チップ１０は、第１の樹脂３０を介して、基板２０にフェースダウンボンディングされている。第２の樹脂４０は、半導体チップ１０の裏面１８の少なくとも一部が露出するように、半導体チップ１０の角部（図５では角部１６）を覆うように設けられている。半導体チップ１０の角部１６、第１及び第２の樹脂３０，４０については、上述の製造方法で説明した通りである。
【００３０】
図４及び図５に示すように、第２の樹脂４０は、第１の樹脂３０上に、第１の樹脂３０の硬化反応を終えた後に設けられたものであってもよい。こうして製造された半導体装置は、第１及び第２の樹脂３０，４０の各層が分離している。これによれば、第１及び第２の樹脂３０，４０が混合しない又は混合する量が少ないので、第２の樹脂４０（絶縁性接着剤）が半導体チップ１０の電極１２付近に流れ込むのを防止し、電極１２と配線パターン２２との電気的導通が図れなくなることを防止することができる。なお、その他の事項及び効果は、上述の半導体装置において説明した内容から導くことができるので省略する。
【００３１】
図６には、本発明の実施の形態に係る半導体装置１が実装された回路基板１０００が示されている。本発明の実施の形態に係る半導体装置を有する電子機器として、図７にはノート型パーソナルコンピュータ２０００が示され、図８には携帯電話３０００が示されている。
【００３２】
本発明は、上述した実施の形態に限定されるものではなく、種々の変形が可能である。例えば、本発明は、実施の形態で説明した構成と実質的に同一の構成（例えば、機能、方法及び結果が同一の構成、あるいは目的及び結果が同一の構成）を含む。また、本発明は、実施の形態で説明した構成の本質的でない部分を置き換えた構成を含む。また、本発明は、実施の形態で説明した構成と同一の作用効果を奏する構成又は同一の目的を達成することができる構成を含む。また、本発明は、実施の形態で説明した構成に公知技術を付加した構成を含む。
【図面の簡単な説明】
【図１】図１は、本発明の実施の形態に係る半導体装置の製造方法を示す図である。
【図２】図２は、本発明の実施の形態に係る半導体装置の製造方法を示す図である。
【図３】図３は、本発明の実施の形態に係る半導体装置の製造方法を示す図である。
【図４】図４は、本発明の実施の形態に係る半導体装置の製造方法を示す図である。
【図５】図５は、図４のＶ−Ｖ線断面図である。
【図６】図６は、本発明の実施の形態に係る回路基板を示す図である。
【図７】図７は、本発明の実施の形態に係る電子機器を示す図である。
【図８】図８は、本発明の実施の形態に係る電子機器を示す図である。
【符号の説明】
１０…半導体チップ １２…電極 １４…表面 １６…角部 １７…側面
１８…裏面 ２０…基板 ２２…配線パターン ３０…第１の樹脂
３２…導電粒子 ４０…第２の樹脂[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a method for manufacturing the same, a circuit board, and an electronic device.
[0002]
[Prior art]
[0003]
[Patent Document 1]
JP 2001-257232 A
BACKGROUND OF THE INVENTION
2. Description of the Related Art As a structure of a semiconductor device, there is known a structure in which a semiconductor chip is face-down mounted on a substrate on which a wiring pattern is formed using an adhesive made of an anisotropic conductive material. According to the conventional form, the material and amount of the adhesive are determined so that the adhesive flows into the corners of the semiconductor chip. However, even in such a case, the corners of the semiconductor chip are actually processed. (The corner on the side where the electrode is formed) may be exposed from the adhesive, and when an environmental test such as a temperature cycle test is performed, a crack may be generated from the corner of the semiconductor chip.
[0005]
An object of the present invention is to improve the reliability of a semiconductor device.
[0006]
[Means for Solving the Problems]
(1) The method for manufacturing a semiconductor device according to the present invention is characterized in that (a) a semiconductor chip having electrodes on its surface is face-down bonded to a substrate on which a wiring pattern is formed via a first resin. Electrically connecting the electrode and the wiring pattern,
(B) providing a second resin so as to cover a corner of the semiconductor chip so that at least a part of the back surface of the semiconductor chip is exposed;
including. According to the present invention, the second resin is provided so as to cover the corners of the semiconductor chip. Thus, damage to the corner of the semiconductor chip can be reduced, and the semiconductor chip can be prevented from being broken starting from the corner. Therefore, the reliability of the semiconductor device can be improved.
(2) In this method of manufacturing a semiconductor device,
After the step (a), the step (b) may be performed. According to this, since the step of providing the second resin is performed after the semiconductor chip is face-down bonded, the corner portion of the bonded semiconductor chip can be reliably covered with the second resin.
(3) In this method of manufacturing a semiconductor device,
The step (b) may be performed after the first resin is cured. According to this, since the first and second resins are not mixed or the amount mixed is small, it is possible to prevent the second resin from flowing near the electrodes of the semiconductor chip, and to establish electrical continuity between the electrodes and the wiring pattern. It is possible to prevent the situation from being lost.
(4) In this method of manufacturing a semiconductor device,
The step (a) comprises:
(A 1 ) providing the first resin on at least one of the semiconductor chip and the substrate;
(A 2 ) face-down bonding the semiconductor chip to the substrate;
May be included.
(5) In the method of manufacturing a semiconductor device,
In the step (a 1 ), the first resin is provided so as to have a planar area having a size including a planar shape of the semiconductor chip;
In the step (b), the second resin may be provided on the first resin. According to this, the corner portion of the semiconductor chip can be easily covered with the second resin.
(6) In this method of manufacturing a semiconductor device,
In the step (a 1 ), the sheet-like first resin is provided,
In the step (b), the second resin in a paste form may be provided. According to this, the handling of the first resin is excellent, and the second resin can be provided in close contact with the corners of the semiconductor chip.
(7) In this method of manufacturing a semiconductor device,
The semiconductor chip has a plurality of the corner portions having different planar positions, and side surfaces between the adjacent corner portions,
In the step (b), the second resin may be provided so as not to adhere to the side surface but to adhere near the corner.
(8) In this method of manufacturing a semiconductor device,
The corner portion of the semiconductor chip is a vertex portion where the surface of the semiconductor chip on which the electrodes are formed and two side surfaces in contact with the surface intersect,
In the step (b),
The first resin is in close contact with the surface of the semiconductor chip on which the electrodes are formed,
The second resin may be provided so as to cover the corner on the front side of the semiconductor chip. According to this, it is possible to prevent the semiconductor chip from being cracked from the corner on the surface side where the electrode is formed.
(9) In this method of manufacturing a semiconductor device,
At the start of the step (b), the first resin may have a portion corresponding to the corner portion thinner than other portions.
(10) In this method of manufacturing a semiconductor device,
In the step (b), the second resin may be provided to be lower than the height of the semiconductor chip up to the back surface.
(11) In this method of manufacturing a semiconductor device,
The fluidity of the first resin at the time of bonding may be lower than the fluidity of the second resin at the time of bonding.
(12) In this method of manufacturing a semiconductor device,
The first resin may be an anisotropic conductive adhesive containing conductive particles.
(13) In this method of manufacturing a semiconductor device,
The second resin may be an insulating adhesive containing no conductive particles.
(14) A semiconductor device according to the present invention includes: a semiconductor chip having an electrode on a surface;
A substrate on which a wiring pattern is formed and a semiconductor chip is face-down bonded;
Having conductive particles for electrically connecting the electrode and the wiring pattern, anisotropic conductive adhesive provided between the semiconductor chip and the substrate,
An insulating adhesive provided over a corner of the semiconductor chip so that at least a part of the back surface of the semiconductor chip is exposed,
including. According to the present invention, the insulating adhesive is provided so as to cover the corners of the semiconductor chip. Thus, damage to the corner of the semiconductor chip can be reduced, and the semiconductor chip can be prevented from being broken starting from the corner. Therefore, the reliability of the semiconductor device can be improved.
(15) A semiconductor device according to the present invention includes: a semiconductor chip having an electrode on a surface;
A substrate on which a wiring pattern is formed and a semiconductor chip is face-down bonded;
A first resin provided between the semiconductor chip and the substrate;
A second resin provided so as to cover a corner of the semiconductor chip so that at least a part of the back surface of the semiconductor chip is exposed;
including. According to the present invention, the second resin is provided so as to cover the corners of the semiconductor chip. Thus, damage to the corner of the semiconductor chip can be reduced, and the semiconductor chip can be prevented from being broken starting from the corner. Therefore, the reliability of the semiconductor device can be improved.
(16) A semiconductor device according to the present invention includes: a semiconductor chip having an electrode on a surface;
A substrate on which a wiring pattern is formed and the semiconductor chip is face-down bonded;
A first resin that is in close contact with the surface of the semiconductor chip on which the electrodes are formed,
A second surface provided so as to cover a corner where the surface of the semiconductor chip on which the electrode is formed and two side surfaces contacting the surface intersect, and to expose at least a part of the back surface of the semiconductor chip; Resin and
including. According to the present invention, the second resin is provided so as to cover the corners of the semiconductor chip. Thus, damage to the corner of the semiconductor chip can be reduced, and the semiconductor chip can be prevented from being broken starting from the corner. Therefore, the reliability of the semiconductor device can be improved.
(17) In this semiconductor device,
The first resin has a planar area having a size including a planar shape of the semiconductor chip,
The second resin may be provided on the first resin after a curing reaction of the first resin is completed. According to this, since the first and second resins are not mixed or the amount mixed is small, it is possible to prevent the second resin from flowing near the electrodes of the semiconductor chip, and to establish electrical continuity between the electrodes and the wiring pattern. It is possible to prevent the situation from being lost.
(18) In this semiconductor device,
In the first resin, a portion corresponding to the corner may be thinner than other portions.
(19) In this semiconductor device,
The second resin may be provided so as to be lower than the height of the semiconductor chip up to the back surface.
(20) The semiconductor device described above is mounted on a circuit board according to the present invention.
(21) An electronic apparatus according to the present invention includes the above semiconductor device.
[0007]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. 1 to 3 are views showing a method for manufacturing a semiconductor device according to the present embodiment. FIG. 4 is a plan view of the semiconductor device according to the present embodiment, and FIG. 5 is a sectional view taken along line VV of FIG. In the present embodiment, the semiconductor chip 10 is mounted on the substrate 20.
[0008]
The semiconductor chip 10 is an integrated circuit chip. The semiconductor chip 10 has a plurality of electrodes 12 electrically connected to an internal integrated circuit. The electrode 12 is exposed on the surface 14 of the semiconductor chip 10. The surface 14 may be a so-called active surface. The electrode 12 includes a pad. When the semiconductor chip 10 is face-down bonded, the electrode 12 often further includes a bump on a pad. A passivation film (not shown) (for example, a silicon oxide film) may be formed on the surface 14 of the semiconductor chip 10 so as to avoid the electrodes 12.
[0009]
The semiconductor chip 10 has a plurality of corners. The semiconductor chip 10 has a polyhedral shape, and the plurality of corners may be vertices where three or more surfaces (three surfaces in FIG. 1) intersect. When the semiconductor chip 10 has a rectangular parallelepiped shape, the semiconductor chip 10 has eight corners (four corners 16 on the front surface 14 side and four corners on the back surface 18 side). The corner 16 on the surface 14 side of the semiconductor chip 10 indicates a vertex portion where the surface 14 on which the electrode 12 is formed and two side surfaces 17 in contact with the surface 14 intersect. In addition, the corner 16 of the semiconductor chip 10 includes not only a case where the semiconductor chip 10 is sharp, but also a case where the semiconductor chip 10 is rounded or partially missing.
[0010]
The material of the substrate 20 may be either an organic material (for example, a polyimide resin or an epoxy resin) or an inorganic material (for example, ceramic or glass), or may have a composite structure thereof. The substrate 20 may be an interposer for a semiconductor package. A substrate having a build-up multilayer structure formed by laminating an insulating resin and a wiring pattern, or a multilayer substrate in which a plurality of substrates are laminated may be used.
[0011]
A wiring pattern 22 is formed on the substrate 20 (see FIG. 5). The wiring pattern 22 has an electrical connection (for example, a land) with an electronic component (for example, the semiconductor chip 10) and a wiring. The wiring pattern 22 is preferably formed of a conductive material (for example, a metal such as copper), and a plating layer (for example, a gold layer) is preferably formed on the surface. A through hole (not shown) may be formed in the substrate 20 to achieve electrical connection between both surfaces.
[0012]
As shown in FIG. 1, a first resin 30 is provided on a substrate 20. The first resin 30 is an adhesive. The first resin 30 may have a property that an adhesive force is developed by a predetermined energy (for example, heat or light) and then cured. The first resin 30 may be a thermosetting resin (or a photocurable resin). As a modification, the first resin 30 may be provided on the semiconductor chip 10 or on both the semiconductor chip 10 and the substrate 20.
[0013]
As shown in FIG. 1, a sheet-like (solid) first resin 30 may be provided. According to this, for example, since only the first resin 30 needs to be mounted on the substrate 20, the handling of the resin and the productivity of the semiconductor device are excellent. Alternatively, a paste-like (liquid or gel-like) first resin 30 may be used.
[0014]
The first resin 30 may be provided so as to have a planar region having a size including the planar shape of the semiconductor chip 10. Specifically, the usage amount of the first resin 30 and the like are determined so that the semiconductor chip 10 is arranged inside the planar region of the first resin 30 after the bonding of the semiconductor chip 10 (see FIG. 2). By doing so, it becomes possible to provide the second resin 40 in a portion of the first resin 30 protruding outside the semiconductor chip 10 (see FIG. 3).
[0015]
The first resin 30 may be an anisotropic conductive adhesive (regardless of paste or sheet). The anisotropic conductive adhesive is obtained by dispersing conductive particles 32 in an insulating adhesive (binder), and may include a dispersant (for example, insulating particles (silica-based particles, etc.)). The insulating adhesive may be a thermosetting resin. According to the anisotropic conductive adhesive, the conductive particles 32 are crushed between the electrode 12 of the semiconductor chip 10 and the wiring pattern 22 of the substrate 20, so that an electrical connection therebetween is achieved ( (See FIG. 5).
[0016]
As shown in FIG. 2, the semiconductor chip 10 is face-down bonded to the substrate 20. More specifically, the electrodes 12 of the semiconductor chip 10 and the wiring patterns 22 of the substrate 20 are electrically connected by face-down bonding via the first resin 30. This step is performed by pressing the back surface 18 of the semiconductor chip 10 with a bonding tool (not shown). During this time, predetermined energy is applied to the first resin 30 to bond the semiconductor chip 10 and the substrate 20 together. The first resin 30 has a high fluidity at the time of bonding, flows out of the semiconductor chip 10, and then hardens. The first resin 30 may be in close contact with the surface 14 of the semiconductor chip 10. The corner 16 of the semiconductor chip 10 may be exposed from the first resin 30. In the example shown in FIG. 2, the first resin 30 has a portion corresponding to the corner 16 of the semiconductor chip 10 (for example, a portion in contact with the corner 16) thinner than another portion (for example, a portion in contact with the side surface 17). ing. As described above, it is effective to apply the present embodiment when an appropriate amount of the first resin 30 does not flow into the corner portion 16.
[0017]
As shown in FIG. 3, the second resin 40 is applied so that at least a part (all in FIG. 3) of the back surface 18 of the semiconductor chip 10 is exposed, and a corner of the semiconductor chip 10 (a corner in FIG. 3). 16). Thereby, damage to the corner (corner 16 in FIG. 3) of the semiconductor chip 10 can be reduced, and the semiconductor chip 10 is prevented from being broken starting from the corner (corner 16 in FIG. 3). be able to.
[0018]
The second resin 40 may be attached to the vicinity of the corner 16 of the semiconductor chip 10 (for example, a range indicated by a two-dot chain line in FIG. 1). In that case, the second resin 40 may be attached to the vicinity of the corner 16 (only) without being attached to the side surface 17 of the semiconductor chip 10. Alternatively, the second resin 40 may be attached to the side surface 17 of the semiconductor chip 10 so as to surround the semiconductor chip 10.
[0019]
In the present embodiment, the corner 16 on the surface 14 side of the semiconductor chip 10 is covered with the second resin 40. In the example shown in FIG. 3, the second resin 40 is provided so as to be lower than the height up to the back surface 18 of the semiconductor chip 10. Thus, the corner 16 on the back surface 18 side of the semiconductor chip 10 may be exposed from the second resin 40. According to this, the surface 14 (so-called active surface) side of the semiconductor chip 10 can be sealed with the first and second resins 30 and 40, and the crack from the corner 16 on the surface 14 side is prevented. be able to.
[0020]
As a modification, the second resin 40 may be provided so as to be the same as or higher than the height up to the back surface 18 of the semiconductor chip 10. In this way, not only the corner 16 on the front surface 14 side of the semiconductor chip 10 but also the corner on the back surface 18 side may be covered. However, as described above, at least a portion of the back surface 18 of the semiconductor chip 10 is exposed from the second resin 40.
[0021]
The second resin 40 is an adhesive. The second resin 40 may have a property that an adhesive force is developed by a predetermined energy (for example, heat or light) and then cured. The second resin 40 may be a thermosetting resin (or a photocurable resin).
[0022]
In the present embodiment, the second resin 40 is provided after the face-down bonding step of the semiconductor chip 10. After the first resin 30 is cured, the second resin 40 may be provided. According to this, the corners of the semiconductor chip after bonding can be reliably covered with the second resin 40. Further, the second resin 40 does not adhere to the bonding tool.
[0023]
As a modification, the second resin 40 may be provided before the bonding step of the semiconductor chip 10. In this case, the second resin 40 may be attached near the corner 16 of the semiconductor chip 10, or may be provided at a position on the substrate 20 corresponding to the corner 16 of the semiconductor chip 10.
[0024]
The paste-like second resin 40 may be potted. Thus, the second resin 40 can be provided in close contact with the vicinity of the corner 16 of the semiconductor chip 10, and the corner 16 can be reliably covered. Alternatively, a sheet-shaped second resin 40 may be used.
[0025]
As shown in FIG. 3, the second resin 40 may be provided on the first resin 30. Specifically, the second resin 40 may be provided in a portion of the first resin 30 protruding outside the semiconductor chip 10. Since the portion of the first resin 30 corresponding to the corner 16 of the semiconductor chip 10 is thin, the corner 16 of the semiconductor chip 10 can be reinforced by the second resin 40.
[0026]
The second resin 40 may be an insulating adhesive (regardless of whether it is in the form of a paste or a sheet). The second resin 40 may be an insulating adhesive containing no conductive particles. The same resin (eg, epoxy resin) may be used as the material (eg, binder material) of the first and second resins 30 and 40. It is preferable that the first and second resins 30 and 40 have the same or approximate physical properties such as a coefficient of thermal expansion and an elastic modulus. By doing so, the internal stress generated in the semiconductor device can be easily absorbed or reduced, and the reliability can be improved. The fluidity of the first resin 30 at the time of bonding may be lower than the fluidity of the second resin 40 at the time of bonding. That is, when an appropriate amount of the first resin 30 does not flow into the corners 16 of the semiconductor chip 10, it is effective to use the second resin 40 having high fluidity.
[0027]
After the second resin 40 is cured, a plurality of external terminals 50 that are electrically connected to the wiring pattern 22 of the substrate 20 may be provided. The external terminal 50 is formed of a conductive metal (for example, brazing material), and may be, for example, a spherical solder ball.
[0028]
The method for manufacturing a semiconductor device according to the present embodiment is configured as described above, and the effects thereof are as already described.
[0029]
The semiconductor device 1 includes a semiconductor chip 10, a substrate 20, a first resin (anisotropic conductive adhesive) 30, and a second resin (insulating adhesive) 40. The semiconductor chip 10 is face-down bonded to the substrate 20 via the first resin 30. The second resin 40 is provided so as to cover a corner (the corner 16 in FIG. 5) of the semiconductor chip 10 so that at least a part of the back surface 18 of the semiconductor chip 10 is exposed. The corner portions 16 of the semiconductor chip 10 and the first and second resins 30 and 40 are as described in the above-described manufacturing method.
[0030]
As shown in FIGS. 4 and 5, the second resin 40 may be provided on the first resin 30 after the curing reaction of the first resin 30 is completed. In the semiconductor device manufactured in this manner, each layer of the first and second resins 30 and 40 is separated. According to this, since the first and second resins 30 and 40 are not mixed or the amount to be mixed is small, it is possible to prevent the second resin 40 (insulating adhesive) from flowing near the electrode 12 of the semiconductor chip 10. However, it is possible to prevent the electrical continuity between the electrode 12 and the wiring pattern 22 from being lost. Note that other matters and effects can be derived from the contents described in the above semiconductor device, and thus description thereof is omitted.
[0031]
FIG. 6 shows a circuit board 1000 on which the semiconductor device 1 according to the embodiment of the present invention is mounted. As an electronic device having a semiconductor device according to an embodiment of the present invention, a notebook personal computer 2000 is shown in FIG. 7, and a mobile phone 3000 is shown in FIG.
[0032]
The present invention is not limited to the embodiments described above, and various modifications are possible. For example, the invention includes configurations substantially the same as the configurations described in the embodiments (for example, a configuration having the same function, method, and result, or a configuration having the same object and result). Further, the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. Further, the invention includes a configuration having the same operation and effect as the configuration described in the embodiment, or a configuration capable of achieving the same object. Further, the invention includes a configuration in which a known technique is added to the configuration described in the embodiment.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 2 is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 3 is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 4 is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 5 is a sectional view taken along line VV of FIG. 4;
FIG. 6 is a diagram showing a circuit board according to an embodiment of the present invention.
FIG. 7 is a diagram showing an electronic apparatus according to the embodiment of the present invention.
FIG. 8 is a diagram showing an electronic device according to the embodiment of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 ... Semiconductor chip 12 ... Electrode 14 ... Surface 16 ... Corner 17 ... Side surface 18 ... Back surface 20 ... Substrate 22 ... Wiring pattern 30 ... First resin 32 ... Conductive particles 40 ... Second resin

Claims (21)

（ａ）表面に電極を有する半導体チップを、第１の樹脂を介して、配線パターンが形成された基板にフェースダウンボンディングすることによって、前記電極と前記配線パターンとを電気的に接続すること、
（ｂ）第２の樹脂を、前記半導体チップの裏面の少なくとも一部が露出するように、前記半導体チップの角部を覆って設けること、
を含む半導体装置の製造方法。(A) electrically connecting the electrode and the wiring pattern by face-down bonding a semiconductor chip having an electrode on a surface to a substrate on which a wiring pattern is formed via a first resin;
(B) providing a second resin so as to cover a corner of the semiconductor chip so that at least a part of the back surface of the semiconductor chip is exposed;
A method for manufacturing a semiconductor device including: 請求項１記載の半導体装置の製造方法において、
前記（ａ）工程後に、前記（ｂ）工程を行う半導体装置の製造方法。The method for manufacturing a semiconductor device according to claim 1,
A method of manufacturing a semiconductor device, wherein the step (b) is performed after the step (a). 請求項１又は請求項２記載の半導体装置の製造方法において、
前記（ｂ）工程を、前記第１の樹脂の硬化後に行う半導体装置の製造方法。The method for manufacturing a semiconductor device according to claim 1 or 2,
A method for manufacturing a semiconductor device, wherein the step (b) is performed after the first resin is cured. 請求項１から請求項３のいずれかに記載の半導体装置の製造方法において、
前記（ａ）工程は、
（ａ１）前記半導体チップ及び前記基板の少なくともいずれか一方に前記第１の樹脂を設けること、
（ａ２）前記半導体チップを前記基板にフェースダウンボンディングすること、
を含む半導体装置の製造方法。The method for manufacturing a semiconductor device according to claim 1, wherein
The step (a) comprises:
(A 1 ) providing the first resin on at least one of the semiconductor chip and the substrate;
(A 2 ) face-down bonding the semiconductor chip to the substrate;
A method for manufacturing a semiconductor device including: 請求項４記載の半導体装置の製造方法において、
前記（ａ１）工程で、前記第１の樹脂を、前記半導体チップの平面形状を含む大きさの平面領域を有するように設け、
前記（ｂ）工程で、前記第２の樹脂を、前記第１の樹脂上に設ける半導体装置の製造方法。The method for manufacturing a semiconductor device according to claim 4,
In the step (a 1 ), the first resin is provided so as to have a planar area having a size including a planar shape of the semiconductor chip;
A method of manufacturing a semiconductor device, wherein in the step (b), the second resin is provided on the first resin. 請求項４又は請求項５記載の半導体装置の製造方法において、
前記（ａ１）工程で、シート状の前記第１の樹脂を設け、
前記（ｂ）工程で、ペースト状の前記第２の樹脂を設ける半導体装置の製造方法。The method for manufacturing a semiconductor device according to claim 4 or 5,
In the step (a 1 ), the sheet-like first resin is provided,
A method for manufacturing a semiconductor device, wherein the paste-like second resin is provided in the step (b). 請求項１から請求項６のいずれかに記載の半導体装置の製造方法において、
前記半導体チップは、平面位置の異なる複数の前記角部と、隣り合う前記角部同士の間の側面と、を有し、
前記（ｂ）工程で、前記第２の樹脂を、前記側面に付着させないで、前記角部付近に付着させて設ける半導体装置の製造方法。The method for manufacturing a semiconductor device according to claim 1, wherein
The semiconductor chip has a plurality of the corner portions having different planar positions, and side surfaces between the adjacent corner portions,
In the method for manufacturing a semiconductor device, in the step (b), the second resin is provided not to adhere to the side surface but to adhere near the corner. 請求項１から請求項７のいずれかに記載の半導体装置の製造方法において、
前記半導体チップの前記角部は、前記半導体チップの前記電極が形成された前記表面と、前記表面に接する２つの側面と、が交わる頂点の部分であり、
前記（ｂ）工程で、
前記第１の樹脂は、前記半導体チップの前記電極が形成された前記表面に密着しており、
前記第２の樹脂を、前記半導体チップの前記表面側の前記角部を覆うように設ける半導体装置の製造方法。The method for manufacturing a semiconductor device according to claim 1, wherein
The corner portion of the semiconductor chip is a vertex portion where the surface of the semiconductor chip on which the electrodes are formed and two side surfaces in contact with the surface intersect,
In the step (b),
The first resin is in close contact with the surface of the semiconductor chip on which the electrodes are formed,
A method of manufacturing a semiconductor device, wherein the second resin is provided so as to cover the corner on the front surface side of the semiconductor chip. 請求項１から請求項８のいずれかに記載の半導体装置の製造方法において、
前記（ｂ）工程開始時に、前記第１の樹脂は、前記角部に対応する部分が他の部分よりも薄くなっている半導体装置の製造方法。9. The method for manufacturing a semiconductor device according to claim 1, wherein:
At the start of the step (b), a method of manufacturing a semiconductor device in which a portion corresponding to the corner portion of the first resin is thinner than other portions. 請求項１から請求項９のいずれかに記載の半導体装置の製造方法において、
前記（ｂ）工程で、前記第２の樹脂を、前記半導体チップの前記裏面までの高さよりも低くなるように設ける半導体装置の製造方法。The method for manufacturing a semiconductor device according to claim 1, wherein
A method for manufacturing a semiconductor device, wherein in the step (b), the second resin is provided to be lower than the height of the semiconductor chip up to the back surface. 請求項１から請求項１０のいずれかに記載の半導体装置の製造方法において、
前記第１の樹脂における接着時の流動性は、前記第２の樹脂における接着時の流動性よりも低い半導体装置の製造方法。The method for manufacturing a semiconductor device according to claim 1, wherein
A method of manufacturing a semiconductor device, wherein the fluidity of the first resin during bonding is lower than the fluidity of the second resin during bonding. 請求項１から請求項１１のいずれかに記載の半導体装置の製造方法において、
前記第１の樹脂は、導電粒子を含む異方性導電接着剤である半導体装置の製造方法。The method of manufacturing a semiconductor device according to claim 1, wherein
The method for manufacturing a semiconductor device, wherein the first resin is an anisotropic conductive adhesive containing conductive particles. 請求項１から請求項１２のいずれかに記載の半導体装置の製造方法において、
前記第２の樹脂は、導電粒子を含まない絶縁性接着剤である半導体装置の製造方法。The method for manufacturing a semiconductor device according to claim 1, wherein
The method of manufacturing a semiconductor device, wherein the second resin is an insulating adhesive containing no conductive particles. 表面に電極を有する半導体チップと、
配線パターンが形成され、半導体チップがフェースダウンボンディングされた基板と、
前記電極と前記配線パターンを電気的に接続する導電粒子を有し、前記半導体チップと前記基板との間に設けられた異方性導電接着剤と、
前記半導体チップの裏面の少なくとも一部が露出するように、前記半導体チップの角部を覆って設けられた絶縁性接着剤と、
を含む半導体装置。A semiconductor chip having electrodes on the surface,
A substrate on which a wiring pattern is formed and a semiconductor chip is face-down bonded;
Having conductive particles for electrically connecting the electrode and the wiring pattern, anisotropic conductive adhesive provided between the semiconductor chip and the substrate,
An insulating adhesive provided over a corner of the semiconductor chip so that at least a part of the back surface of the semiconductor chip is exposed,
Semiconductor device including: 表面に電極を有する半導体チップと、
配線パターンが形成され、半導体チップがフェースダウンボンディングされた基板と、
前記半導体チップと前記基板との間に設けられた第１の樹脂と、
前記半導体チップの裏面の少なくとも一部が露出するように、前記半導体チップの角部を覆って設けられた第２の樹脂と、
を含む半導体装置。A semiconductor chip having electrodes on the surface,
A substrate on which a wiring pattern is formed and a semiconductor chip is face-down bonded;
A first resin provided between the semiconductor chip and the substrate;
A second resin provided so as to cover a corner of the semiconductor chip so that at least a part of the back surface of the semiconductor chip is exposed;
Semiconductor device including: 表面に電極を有する半導体チップと、
配線パターンが形成され、前記半導体チップがフェースダウンボンディングされた基板と、
前記半導体チップの前記電極が形成された前記表面に密着してなる第１の樹脂と、
前記半導体チップの前記電極が形成された前記表面と、前記表面に接する２つの側面と、が交わる角部を覆うとともに、前記半導体チップの裏面の少なくとも一部が露出するように設けられた第２の樹脂と、
を含む半導体装置。A semiconductor chip having electrodes on the surface,
A substrate on which a wiring pattern is formed and the semiconductor chip is face-down bonded;
A first resin that is in close contact with the surface of the semiconductor chip on which the electrodes are formed,
A second surface provided so as to cover a corner where the surface of the semiconductor chip on which the electrode is formed and two side surfaces contacting the surface intersect, and to expose at least a part of the back surface of the semiconductor chip; Resin and
Semiconductor device including: 請求項１５又は請求項１６記載の半導体装置において、
前記第１の樹脂は、前記半導体チップの平面形状を含む大きさの平面領域を有し、
前記第２の樹脂は、前記第１の樹脂上に、前記第１の樹脂の硬化反応を終えた後に設けられてなる半導体装置。The semiconductor device according to claim 15 or 16,
The first resin has a planar area having a size including a planar shape of the semiconductor chip,
A semiconductor device, wherein the second resin is provided on the first resin after a curing reaction of the first resin is completed. 請求項１５から請求項１７のいずれかに記載の半導体装置において、
前記第１の樹脂は、前記角部に対応する部分が他の部分よりも薄くなっている半導体装置。The semiconductor device according to any one of claims 15 to 17,
A semiconductor device in which the first resin has a portion corresponding to the corner portion thinner than other portions. 請求項１５から請求項１８のいずれかに記載の半導体装置において、
前記第２の樹脂は、前記半導体チップの前記裏面までの高さよりも低くなるように設けられてなる半導体装置。The semiconductor device according to any one of claims 15 to 18, wherein
The semiconductor device, wherein the second resin is provided to be lower than a height of the semiconductor chip up to the back surface. 請求項１４から請求項１９のいずれかに記載の半導体装置が実装されてなる回路基板。A circuit board on which the semiconductor device according to claim 14 is mounted. 請求項１４から請求項１９のいずれかに記載の半導体装置を有する電子機器。An electronic apparatus comprising the semiconductor device according to claim 14.
JP2003073928A 2003-03-18 2003-03-18 Semiconductor device, manufacturing method thereof, circuit board, and electronic appliance Withdrawn JP2004281899A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010003879A (en) * 2008-06-20 2010-01-07 Fujitsu Ltd Semiconductor device and its method of manufacturing
US8207618B2 (en) 2009-01-29 2012-06-26 Panasonic Corporation Semiconductor device and method of manufacturing the same
JP2013197564A (en) * 2012-03-23 2013-09-30 Murata Mfg Co Ltd Composite module and manufacturing method of the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010003879A (en) * 2008-06-20 2010-01-07 Fujitsu Ltd Semiconductor device and its method of manufacturing
US8207618B2 (en) 2009-01-29 2012-06-26 Panasonic Corporation Semiconductor device and method of manufacturing the same
JP2013197564A (en) * 2012-03-23 2013-09-30 Murata Mfg Co Ltd Composite module and manufacturing method of the same

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