JP5313211B2 - Focus ring and plasma processing apparatus - Google Patents

Abstract

A focus ring and a plasma processing apparatus capable of improving an in-surface uniformity of a surface and reducing occurrences of deposition on a backside surface of a peripheral portion of a semiconductor wafer compared to a conventional case are provided. Installed in a vacuum chamber is a susceptor for mounting the semiconductor wafer thereon and a focus ring is installed to surround the semiconductor wafer mounted on the susceptor. The focus ring includes an annular lower member made of a dielectric, and an annular upper member made of a conductive material and mounted on the lower member. The upper member includes a flat portion which is an outer peripheral portion having a top surface positioned higher than a surface to be processed of the semiconductor wafer W, and an inclined portion which is an inner peripheral portion inclined inwardly.

Description

  The present invention relates to a focus ring and a plasma processing apparatus disposed in a processing chamber for performing a predetermined plasma process such as an etching process on a substrate such as a semiconductor wafer.

  2. Description of the Related Art Conventionally, plasma processing apparatuses such as etching processing apparatuses are widely used in, for example, manufacturing processes of fine electric circuits of semiconductor devices.

  In such a plasma processing apparatus, a substrate to be processed such as a semiconductor wafer is disposed in a processing chamber configured to be hermetically sealed inside, and plasma is generated in the processing chamber. In this way, plasma processing such as etching is performed.

  In addition, there is a plasma processing apparatus in which a ring-shaped member called a focus ring is arranged so as to surround a semiconductor wafer that is a substrate to be processed. This focus ring confines the plasma and alleviates discontinuities due to the edge effect of the bias potential in the semiconductor wafer surface, and evenly and well treats the peripheral edge as well as the central portion of the semiconductor wafer. It is provided for the purpose of making it possible.

  As described above, the focus ring surrounds the semiconductor wafer and the dielectric is placed in contact with the plasma, thereby displacing the plasma in the upper axial direction and moving the plasma away from the lower electrode, thereby reducing the reactive species in the plasma at the bottom. It is known not to focus on the periphery of the electrode and to reduce the process speed at the periphery of the semiconductor wafer (see, for example, Patent Document 1).

  In addition, as described above, the focus ring is intended to alleviate the discontinuity of the bias potential. Therefore, the surface (upper surface) of the focus ring is substantially the same as the processing surface of the semiconductor wafer to be processed. Making the same surface, that is, making the surface (upper surface) of the focus ring and the processing surface of the semiconductor wafer substantially the same height is performed. Further, attempts have been made to alleviate the discontinuity of the bias potential by making the surface (upper surface) of the focus ring higher than the processing surface of the semiconductor wafer or selecting the material thereof (for example, , See Patent Document 2).

JP-T-2001-516948 (page 13-41, FIG. 1-7) Japanese translation of PCT publication No. 2003-503841 (pages 12-22 and 2-6)

  As described above, conventionally, in a plasma processing apparatus, a focus ring has been used. By using such a focus ring, the uniformity of processing is improved.

  FIG. 15 shows an example of a conventional focus ring. As shown in FIG. 15, on the mounting table 100 that also serves as a lower electrode, a semiconductor wafer W as a substrate to be processed is surrounded by, for example, A focus ring 101 formed in a ring shape from a conductive material such as silicon is disposed.

  In the example shown in FIG. 15, the height of the upper surface of the focus ring 101 is substantially the same height as the processing surface (front surface) of the semiconductor wafer W. As a result, the electric field above the focus ring 101 is changed to the semiconductor wafer W. And the discontinuity due to the edge effect of the bias potential is alleviated. As indicated by the dotted line in the figure, the height is substantially the same above the surface of the semiconductor wafer W and above the focus ring 101. The plasma sheath is formed. With such a plasma sheath, as indicated by an arrow in the figure, ions are also incident on the edge of the semiconductor wafer W perpendicularly to the surface of the semiconductor wafer W.

  However, when the focus ring 101 having the above-described configuration is used, so-called deposition may occur in which an undesired deposit made of a CF-based polymer or the like adheres to the back side of the peripheral edge (edge portion) of the semiconductor wafer W. .

  As a result of detailed investigation of the cause of such deposition, when the focus ring 101 having the above-described configuration is used, the semiconductor wafer W and the focus ring 101 have substantially the same potential. An electric field is formed between the peripheral edge portion (edge portion) of the semiconductor wafer W and the inner peripheral portion of the focus ring 101 as indicated by the dotted lines in the figure. For this reason, as shown by the solid line arrow in the figure, the plasma easily enters the back side of the semiconductor wafer W from the intermediate portion between the peripheral portion (edge portion) of the semiconductor wafer W and the inner peripheral portion of the focus ring 101. Thus, it was estimated that deposition occurred on the back surface side of the peripheral edge portion (edge portion) of the semiconductor wafer W due to the plasma entering the back surface side of the semiconductor wafer W.

  The present invention has been made in response to such a conventional situation, and it is possible to perform good and uniform processing at the peripheral portion of a semiconductor wafer in the same manner as the central portion of the semiconductor wafer. It is intended to provide a focus ring and a plasma processing apparatus that can reduce the occurrence of deposition on the rear surface side of the peripheral edge of a semiconductor wafer as compared with the prior art.

One aspect of the focus ring of the present invention is a method in which a substrate to be processed is accommodated on a lower electrode on which the substrate to be processed is placed in a processing chamber for storing a substrate to be processed and subjected to predetermined plasma processing. An annular focus ring arranged so as to surround the periphery, comprising: a lower member made of a dielectric; and an upper member made of a conductive material arranged on the upper side of the lower member. A high-frequency grounding member capable of propagating high-frequency power through the surface layer as a surface wave, comprising a conductive member whose surface is coated with an insulating layer, preventing direct current from flowing through the insulating layer. Te is connected to the ground potential, the high frequency grounding member, the lower side of the upper member and the outer peripheral portion of the lower member, so as to contact at least a portion of the lower surface of the upper member Characterized in that it is arranged.

One aspect of the plasma processing apparatus of the present invention includes a processing chamber for accommodating a substrate to be processed and performing a predetermined plasma processing, a lower electrode provided in the processing chamber, on which the substrate to be processed is placed, An upper electrode provided in the processing chamber and facing the lower electrode; a high-frequency power source for supplying high-frequency power between the lower electrode and the upper electrode to convert the gas in the processing chamber into plasma; An annular member disposed on the lower electrode and surrounding the periphery of the substrate to be processed, the lower member made of a dielectric, and the conductive member disposed on the lower member. The upper member is made of a conductive member whose surface is coated with an insulating layer, prevents direct current from flowing through the insulating layer, and represents as a surface wave. High frequency power by the high frequency grounding member which can propagate a layer for high-frequency power is connected to a ground potential, the high frequency grounding member, the lower and outer periphery of the lower member of the upper member It is arrange | positioned at a part so that at least one part of the lower surface of the said upper side member may be contacted .

  According to the present invention, it is possible to perform good and uniform processing at the peripheral portion of the semiconductor wafer as in the central portion of the semiconductor wafer, improve the in-plane uniformity of processing, and improve the uniformity of the semiconductor wafer. The occurrence of deposition on the rear surface side of the peripheral edge can be reduced as compared with the conventional case.

The figure which shows schematic structure of the plasma processing apparatus of the reference example of this invention. The figure which expands and shows the principal part of the focus ring of the plasma processing apparatus of FIG. The figure for demonstrating the measurement site | part of deposition. The figure which shows the measurement result of the deposition in the measurement site | part of FIG. The figure which shows the angle of the electric field in each position on a wafer. The figure for demonstrating the evaluation method of the displacement amount of the incident angle of ion. The figure which shows the relationship between the displacement amount of the incident angle of ion, and the height of a focus ring. The figure which shows the relationship between the displacement amount of the incident angle of ion, and the height of a focus ring. The figure which shows the relationship between a taper cut depth and the consumption amount tolerance | permissible_range of a focus ring. The figure for demonstrating the adjustment method of an impedance. The figure which shows the structure of the focus ring which concerns on embodiment of this invention. The figure which shows the mode of the period fluctuation | variation of the potential of each part. The figure which shows the result of having measured the adhesion amount of the polymer with respect to the bevel part of a wafer. The figure which shows the structure of the focus ring which concerns on other embodiment. The figure which shows the structure of the conventional focus ring. The figure for demonstrating the state of the electric field in the focus ring of FIG. The figure which shows the state of the electric field and plasma sheath in the focus ring using a dielectric material.

  The details of the present invention will be described below with reference to the drawings.

  FIG. 1 schematically shows a schematic configuration of an entire plasma processing apparatus (etching apparatus) according to a reference example of the present invention. In FIG. 1, reference numeral 1 is made of, for example, aluminum, and the inside is airtight. A cylindrical processing chamber (vacuum chamber) that is configured to be closed and that constitutes a processing chamber is shown.

  Inside the vacuum chamber 1, a mounting table 2 is provided which is formed in a block shape from a conductive material such as aluminum and serves also as a lower electrode.

  The mounting table 2 is supported in the vacuum chamber 1 via an insulating plate 3 such as ceramic, and a static wafer (not shown) for adsorbing and holding the semiconductor wafer W on the semiconductor wafer W mounting surface of the mounting table 2. An electric chuck is provided.

  Further, inside the mounting table 2, a heat medium flow path 4 for circulating an insulating fluid as a heat medium for temperature control and a temperature control gas such as helium gas are provided on the back surface of the semiconductor wafer W. A gas flow path 5 for supply is provided.

  Then, by circulating an insulating fluid controlled to a predetermined temperature in the heat medium flow path 4, the mounting table 2 is controlled to a predetermined temperature, and between the mounting table 2 and the back surface of the semiconductor wafer W. Gas for temperature control is supplied through the gas flow path 5 to promote heat exchange between them, and the semiconductor wafer W can be accurately and efficiently controlled to a predetermined temperature.

  Further, a high frequency power source (RF power source) 7 is connected to the mounting table 2 via a matching unit 6, and high frequency power of a predetermined frequency is supplied from the high frequency power source 7.

  Further, a focus ring 8 is provided on the upper peripheral edge of the mounting table 2. The focus ring 8 is disposed on a ring-shaped lower member 9 made of a dielectric material (for example, ceramics such as quartz and alumina, resin such as Vespel (registered trademark)), and an upper portion of the lower member 9. The ring-shaped upper member 10 is made of a conductive material (for example, silicon, carbon, SiC, etc.), and is placed so as to surround the periphery of the semiconductor wafer W that is the substrate to be processed.

  As shown in FIG. 2, the upper member 10 has a flat surface 10 a whose outer peripheral side is higher than the surface to be processed of the semiconductor wafer W, and the inner peripheral portion of the flat portion 10 a is the inner peripheral side. It is set as the inclination part 10b which inclines so that it may become higher. Further, the upper member 10 is arranged between the upper member 10 and the peripheral edge of the semiconductor wafer W so that a gap C1 is formed. In FIG. 2, P indicates plasma, and in the portion of the focus ring 8, the mounting table (lower electrode) 2 receives high frequency power from the high frequency power source 7 via the lower member 9. By being coupled (RF coupling) and interposing the lower member 9 (dielectric material), the impedance to this high frequency increases.

  Here, the reason why the focus ring 8 is configured as described above will be described. As described above, in the focus ring 101 as shown in FIGS. 15 and 16, since the semiconductor wafer W and the focus ring 101 have substantially the same potential, plasma is generated from the semiconductor wafer due to the shape of the electric field. It is easy to wrap around the back side of the end of W.

  Therefore, as shown in FIG. 17, a focus ring 110 having a configuration in which a conductive ring 112 is placed on top of a dielectric ring 111 is used, and a potential difference is provided between the semiconductor wafer W and the conductive ring 112. As indicated by a dotted arrow, an electric field in which electric lines of force are directed from the end of the semiconductor wafer W to the conductive ring 112 is formed. Then, it turned out that this electric field can suppress the wraparound of the plasma to the edge part back surface side of the semiconductor wafer W.

  However, when the focus ring 110 having the above configuration is used, the thickness of the plasma sheath formed above the semiconductor wafer W and the thickness of the plasma sheath formed on the focus ring 110 are different as shown by the dotted line in FIG. The electric field is inclined at the peripheral edge of the semiconductor wafer W, and the angle of entry of ions that collide with the surface of the semiconductor wafer W from above is inclined, so that the etching proceeds obliquely and the uniformity of the etching process is reduced. .

  For this reason, by adopting the focus ring 8 having the above-described configuration, an etching process is performed while suppressing the wraparound of the plasma toward the back surface side of the end of the semiconductor wafer W and suppressing the inclination of the electric field at the peripheral edge of the semiconductor wafer W. It also suppresses a decrease in the uniformity of the.

  Further, an exhaust ring 11 having an annular shape and formed with a large number of exhaust holes is provided outside the focus ring 8 described above, and the exhaust connected to the exhaust port 12 through the exhaust ring 11. The processing space in the vacuum chamber 1 is evacuated by a vacuum pump of the system 13 or the like.

  On the other hand, a shower head 14 is provided on the top wall portion of the vacuum chamber 1 above the mounting table 2 so as to face the mounting table 2 in parallel, and the mounting table 2 and the shower head 14 are paired with each other. It functions as an electrode (upper electrode and lower electrode). In addition, a high frequency power supply 16 is connected to the shower head 14 via a matching unit 15.

  The shower head 14 is provided with a number of gas discharge holes 17 on the lower surface thereof, and has a gas introduction portion 18 on the upper portion thereof. A gas diffusion space 19 is formed inside. A gas supply pipe 20 is connected to the gas introduction unit 18, and a gas supply system 21 is connected to the other end of the gas supply pipe 20. The gas supply system 21 includes a mass flow controller (MFC) 22 for controlling a gas flow rate, for example, a processing gas supply source 23 for supplying a processing gas for etching and the like.

  Next, an etching process procedure performed by the etching apparatus configured as described above will be described.

  First, a gate valve (not shown) provided in the vacuum chamber 1 is opened, and a semiconductor wafer W is transferred by a transfer mechanism (not shown) through a load lock chamber (not shown) arranged adjacent to the gate valve. Is loaded into the vacuum chamber 1 and placed on the mounting table 2. Then, after the transfer mechanism is retracted out of the vacuum chamber 1, the gate valve is closed.

  Thereafter, a predetermined processing gas is supplied into the vacuum chamber 1 from the processing gas supply source 23 while the vacuum chamber 1 is exhausted to a predetermined degree of vacuum through the exhaust port 12 by a vacuum pump of the exhaust system 13.

  In this state, a predetermined high frequency power having a relatively low frequency is supplied from the high frequency power source 7 and a predetermined high frequency power having a relatively high frequency is supplied from the high frequency power source 16 to generate plasma, and etching of the semiconductor wafer W by the plasma. Do.

  Then, when a predetermined etching process is executed, the etching process is stopped by stopping the supply of high-frequency power from the high-frequency power sources 7 and 16, and the semiconductor wafer W is evacuated by a procedure opposite to the above-described procedure. It is carried out of the chamber 1.

  In the above-described plasma etching process, in the focus ring 8 in the reference example, the lower member 9 made of a dielectric is placed on the mounting table 2 as described above, and the upper member is placed on the lower member 9. 10 is disposed, the impedance of the portion of the upper member 10 (impedance with respect to the high-frequency power applied to the mounting table 2) is higher than that of the semiconductor wafer W. As a result, the potential is lowered and the semiconductor wafer is reduced. A potential difference is generated between W and the upper member 10. By the action of the electric field formed by this potential difference, the plasma is prevented from flowing to the back surface side of the peripheral portion of the semiconductor wafer W, and the deposition of CF-based polymer or the like is suppressed on the back surface side of the peripheral portion of the semiconductor wafer W. be able to.

  As shown in FIG. 3, the edge (0.0 mm) of the horizontal part on the rear surface side of the peripheral edge of the semiconductor wafer W, the part 1.0 mm inside, 0.5 mm inside, 30 ° and 45 ° of the end face. FIG. 4 shows the result of measuring the amount of deposition in the portion. 4A, the comparative example shows the result when the focus ring 101 having the configuration shown in FIGS. 15 and 16 is used, and the reference examples 1 and 2 have the above-described configuration shown in FIGS. The case where the focus ring 8 is used is shown. Reference Example 1 shows no ashing and Reference Example 2 shows ashing. In the graph of FIG. 4B, the vertical axis indicates the deposition amount, and the horizontal axis indicates the position on the semiconductor wafer W. The solid line A is the comparative example, the dotted line B is the reference example 1, and the alternate long and short dash line C is the reference. Example 2 is shown. As shown in FIG. 4, when the focus ring 8 is used, the amount of deposition can be greatly reduced as compared with the case where the focus ring 101 is used.

  In this reference example, since the lower member 9 made of a dielectric is interposed as described above, a potential difference is generated between the semiconductor wafer W and the upper member 10. Is formed with an inclined portion 10b inclined so that the outer peripheral side is higher than the inner peripheral side, and a flat portion 10a higher than the surface to be processed of the semiconductor wafer W is formed on the outer peripheral side of the inclined portion 10b. In this manner, since the upper surface of the focus ring 8 is higher than the surface to be processed of the semiconductor wafer W, the height of the boundary portion of the plasma sheath formed above the focus ring 8 is set to the height of the semiconductor wafer W. The height can be raised to substantially the same height as above, and the gradient of the electric field at the peripheral edge of the semiconductor wafer W can be suppressed.

  In the focus ring 8 described above, the flat portion 10a of the upper member 10 formed so as to be higher than the processing surface of the semiconductor wafer W acts to increase the height of the plasma sheath. Therefore, the presence of the inclined portion 10b can alleviate a sudden change in the electric field at the boundary between the semiconductor wafer W and the focus ring 8. For example, the electric field is opposite to that shown in FIG. Inclination in the direction can also be suppressed.

As a result of the electric field simulation, the height h of the inclined portion 10b shown in FIG. 2 from the surface to be processed of the semiconductor wafer W is preferably in the range of 0 <h ≦ 6 mm, and more preferably 2 mm ≦ h ≦. 4 mm. Similarly, the horizontal length l of the inclined portion 10b shown in FIG. 2 is preferably in the range of 0.5 mm ≦ l ≦ 9 mm, and more preferably 1 mm ≦ l ≦ 6 mm. The horizontal length l of the inclined portion 10b can be set to l = 0 depending on the distance C1 between the end portion of the semiconductor wafer W and the focus ring 8. That is, in this case the inclined portion 10b is no shape, it is possible to suppress the rapid change in the electric field at this portion by adjusting the distance C ₁ between the semiconductor wafer W ends and the focus ring 8. Note that the height d of the lower end portion of the inclined portion 10b shown in FIG. 2 is preferably about 0 ≦ d ≦ 1 mm.

Further, since a potential difference is generated between the semiconductor wafer W and the focus ring 8, there is a possibility that arcing occurs in the semiconductor wafer W when the semiconductor wafer W and the focus ring 8 are too close to each other. On the other hand, if the semiconductor wafer W and the focus ring 8 are separated too much, the effect of preventing the plasma from entering the back side of the semiconductor wafer W due to the electric field described above will be reduced. Therefore, the distance C ₁ between the end portion of the semiconductor wafer W and the focus ring 8 shown in FIG. 2 is preferably in the range of 0.3 mm ≦ C ₁ ≦ 1.5 mm, and 1.0 mm ≦ C ₁ ≦ 1. More preferably, it is 5 mm. 2 is preferably set to 0.3 mm ≦ C _{2 in} order to prevent similar abnormal discharge from occurring, with respect to the distance C ₂ between the rear surface of the end portion of the semiconductor wafer W and the focus ring 8 shown in FIG. , with the interval _{C 3} shown in FIG. 2 for the same reason, it is preferable that the 0.4 mm ≦ _{C 3.}

  FIG. 5 shows the result of examining the gradient of the electric field at the peripheral edge of the semiconductor wafer W. In the graph of FIG. 5A, the vertical axis is the electric field angle (angle θ shown in FIG. 2), and the horizontal axis is the wafer. The upper position (the position of the inner periphery of the semiconductor wafer W with the end portion being 10 mm as shown in FIG. 2) is shown.

  In the same figure, a curve A indicated by a square symbol is a triangular shape of the focus ring shown in FIG. 15, and a curve B indicated by a circular symbol is a triangular shape of the focus ring shown in FIG. A curve C indicated by a symbol and a curve D indicated by an inverted triangle symbol indicate the case of a focus ring having a configuration according to a reference example. The triangle symbol indicates that the length of l shown in FIG. 2 is 1 mm and the length of h is 3.6 mm. The inverted triangle symbol indicates that the length of l shown in FIG. 2 is 2 mm and h. The case where the length is 3.6 mm is shown.

  As shown in FIGS. 5A and 5B, when the focus ring having the configuration shown in FIG. 17 is used, the gradient of the electric field at the peripheral edge of the semiconductor wafer W becomes large, and θ is about 82 degrees at the maximum. An inward tilt will occur about 8 degrees. On the other hand, in the reference example, as shown in FIGS. 5A and 5C, θ can be suppressed to about 88 degrees at the maximum, that is, the inward inclination can be suppressed to about 2 degrees at the maximum.

  Note that holes were actually formed in the semiconductor wafer W by etching, and the inclination of the holes from the vertical was measured, and the result also substantially coincided with the result of the inclination of the electric field.

  As described above, according to the reference example, it is possible to reduce the occurrence of deposition with respect to the back surface side of the peripheral edge of the semiconductor wafer as compared with the conventional case, and to suppress the inclination of the electric field at the peripheral edge of the semiconductor wafer. Even in the peripheral portion of the wafer, it is possible to perform substantially vertical etching, and the in-plane uniformity of processing can be improved.

  Incidentally, as described above, the focus ring 8 has a structure having the inclined portion 10b and the flat portion 10a, whereby the life of the focus ring 8 can be extended. That is, by adopting the above configuration, it is possible to suppress a decrease in the height of the plasma sheath above the focus ring 8 when the focus ring 8 (upper member 10) is consumed, and the focus ring 8 is consumed to some extent. Even in this case, the incident angle of ions at the edge of the semiconductor wafer W can be kept in the vertical vicinity.

  Hereinafter, the results of investigating the influence on the plasma sheath due to the consumption of the focus ring and the influence on the incident angle of ions on the surface of the semiconductor wafer W will be described.

  First, as shown in FIG. 6, for the focus ring 101 having a flat upper surface, the relationship between the height of the upper surface and the incident angle of ions at the edge of the semiconductor wafer W (indicated by a dotted arrow in the figure) was investigated.

The specific process targeted for the above investigation is a process of forming contact holes, vias, etc., with a pressure of about 2 to 11 Pa, a high frequency RF power density of 3 to 5 W, and a low frequency RF. The power density is 3 to 5 W, the temperature of the semiconductor wafer W is 80 to 120 ° C., the distance between the electrodes is 25 to 70 mm, the gas system is C ₄ F ₆ or C ₅ F ₈ / Cx Hy Fz (C ₂ F ₆ ) / Ar / O ₂ : Process such as 30 to 50/10 to 30/500 to 1500/30 to 50 sccm.

  Since the thickness of the plasma sheath formed above the semiconductor wafer W (diameter: 200 to 300 mm) in the above process is about 3 mm, the incident angle of ions is from the upper end of the plasma sheath having a thickness of 3 mm to the semiconductor. Argon ions incident at a position of 1 mm from the edge of the wafer W were evaluated based on the incident position on the surface of the semiconductor wafer W, that is, the amount of displacement in the radial direction from the origin, where the incident was perpendicular. In FIG. 6, the displacement in the left direction in the figure is negative, and the displacement in the right direction is positive.

  In the above case, the height of the top surface of the focus ring (the height of the processing surface (surface) of the semiconductor wafer W is the origin, the upward direction is the positive direction, and the downward direction is the negative direction) is +0.3 mm, and ions are incident The displacement amount of the position was +0.03 mm, the height of the top surface of the focus ring was −0.4 mm, and the displacement amount of the ion incident position was −0.05 mm.

  For this reason, the comparison was performed on the assumption that the displacement amount of the ion incident position is +0.03 mm to -0.05 mm as the lifetime of the focus ring.

  As described above, in the focus ring 101 having a flat upper surface, the displacement amount of the ion incident position is +0.03 mm to −0.05 mm because the height of the upper surface of the focus ring is +0.3 mm to −0 mm. Since it is in the range of 4 mm, when the height of the focus ring 101 is set to +0.3 mm in the initial state, the focus ring 101 is replaced when the amount of wear on the upper surface of the focus ring becomes 0.7 mm.

  Next, for a focus ring having the same shape as the focus ring 8 described above, that is, the focus ring having a flat portion and an inclined portion, l and h shown in FIG. 2 are changed, and the top surface of the focus ring (the surface of the flat portion) ) And the processing surface of the semiconductor wafer W and the result of investigating the relationship between the displacement amount of the ion incident position will be described. It was assumed that the focus ring was consumed in a similar shape from the initial state.

  FIG. 7 shows that l is 3 mm (same as plasma sheath thickness) and h is 0.5 mm (curve A), 1.0 mm (curve B), 1.5 mm (curve C), 2.0 mm (curve D). ), 2.5 mm (curve E), and 3.0 mm (curve F), the results of investigating the relationship between the height t and the amount of displacement are shown. In FIG. The horizontal axis indicates the height t (mm) of the upper surface of the focus ring. For comparison, the case of the focus ring 101 having a flat upper surface is indicated by a dotted line in the drawing.

  As shown in the figure, as h becomes deeper, the slope of the curve becomes gentler, and the change in the amount of displacement of ions when the height of the upper surface of the focus ring changes decreases. Therefore, in the above range, the longer the h, the longer the life of the focus ring and the longer the replacement cycle. In addition, when the result shown in FIG.

  When h = 0.5, allowable range of height t: -0.3 to +0.55 mm (0.85 mm)

  When h = 1.0 Allowable range of height t: -0.1 to +0.8 mm (0.9 mm)

  When h = 1.5, allowable range of height t: 0 to +1.0 mm (1.0 mm)

  When h = 2.0, allowable range of height t: 0 to +1.1 mm (1.1 mm)

  When h = 2.5, allowable range of height t: 0 to +1.1 mm (1.1 mm)

When h = 3.0 Allowable range of height t: 0 to +1.2 mm (1.2 mm)
It is.

  As described above, when l is 3 mm, which is the same as the plasma sheath thickness, even if h is 0.5 mm, the allowable range of height t is 0.85 mm, and the focus ring has a flat upper surface (high A clear effect is seen in comparison with a tolerance range of 0.7 mm. Further, by setting h to 3.0 mm, the allowable range of height t is 1.2 mm, and the allowable range of height t can be enlarged by about 1.7 times compared to a focus ring with a flat upper surface. .

  When h is 3.0 mm, the initial focus ring height t = + 1.2 mm. Accordingly, the initial height of the lowest height portion (inner peripheral side end portion) of the inclined portion is 1.2 mm−3.0 mm = −1 when the height of the processing surface of the semiconductor wafer W is used as a reference. It is at a height of .8 mm and is lower than the height of the processing surface of the semiconductor wafer W.

  FIG. 8 shows that h is 0.5 mm (curve A), 1.0 mm (curve B), 1.5 mm (curve C), 2.0 mm when l is 6 mm (twice the plasma sheath thickness). (Curve D), 2.5 mm (Curve E), 3.0 mm (Curve F) shows the results of investigating the relationship between the height t and the amount of displacement. The amount of displacement of the incident position (mm), and the horizontal axis indicates the height t (mm) of the focus ring top surface. For comparison, the case of the focus ring 101 having a flat upper surface is indicated by a dotted line in the drawing.

  As shown in the figure, when l is set to 6 mm, as in the case where l is set to 3 mm, as h becomes deeper, the slope of the curve becomes gentler, and the ion at the time when the height of the focus ring upper surface changes is changed. Less change in displacement.

  In addition, when the result shown in FIG.

  When h = 0.5, allowable range of height t: -0.3 to +0.65 mm (0.95 mm)

  When h = 1.0 Allowable range of height t: 0 to +1.0 mm (1.0 mm)

  When h = 1.5, allowable range of height t: +0.2 to +1.3 mm (1.1 mm)

  When h = 2.0, allowable range of height t: +0.3 to +1.6 mm (1.3 mm)

  When h = 2.5 Allowable range of height t: +0.4 to +2.0 mm (1.6 mm)

When h = 3.0 Allowable range of height t: +0.5 to +2.1 mm (1.6 mm)
It is.

  As described above, when l is 6 mm, which is twice the plasma sheath thickness, even if h is 0.5 mm, the allowable range of height t is 0.95 mm, and the focus ring has a flat top surface ( A clear effect is seen in comparison with the allowable range of height t being 0.7 mm. Further, by setting h to 2.5 to 3.0 mm, the allowable range of height t is 1.6 mm, and the allowable range of height t is more than double that of a focus ring with a flat upper surface. Can be expanded.

  Conventionally, for example, the processing time integration is about 400 hours, and the focus ring is replaced. Therefore, the exchange period of such a focus ring can be extended to about 800 hours or more.

  FIG. 9 shows a case where the vertical axis is the allowable consumption range Δ (mm) of the focus ring (F / R), the horizontal axis is h (taper cut depth) (mm), and the above-mentioned l is 3 mm (in the figure, the square shape). ) And 6 mm (indicated by a circular mark in the figure), and when the taper cut position l estimated from these is 9 mm (indicated by a dotted line in the figure) It is.

  As shown in the figure, when h is deeper to some extent, the allowable consumption range Δ of the focus ring becomes larger, but tends to be saturated at about 2.5 to 3.0 mm.

  In addition, the longer l has a tendency that the allowable consumption range Δ of the focus ring tends to be larger, and is preferably at least as large as the thickness of the plasma sheath (3 mm) or more, and further, the thickness of the plasma sheath. Is preferably about twice (6 mm) or more.

  As described above, by adopting a focus ring having a shape having an inclined portion and a flat portion, the consumption tolerance range Δ of the focus ring can be increased. As a result, the focus ring replacement cycle can be prolonged as compared with the conventional case, and the running cost can be reduced and the apparatus operating rate can be improved. Further, from the viewpoint of extending the life of the focus ring, it is preferable to use CVD-SiC as the material, and in particular, CVD-SiC having a resistivity equivalent to that of Si (1 to 30Ω) is manufactured. Therefore, it is preferable to use CVD-SiC having such a resistivity. If a focus ring is configured using such CVD-SiC, the same electrical characteristics as when Si is used can be obtained, and the life is 2-3 times longer than when Si is used. be able to.

  By the way, in the focus ring 8 having the above-described configuration, there is an optimum range for the impedance of the portion of the focus ring 8, and it is preferable to adjust the impedance value to this optimum range. In the focus ring 8, the impedance can be adjusted by selecting the material of the lower member 9 made of a dielectric and changing its dielectric constant or changing its thickness. That is, the impedance Z can be adjusted by changing the value of the capacitance C formed by sandwiching the lower member 9. Therefore, for example, as in the focus ring 8 shown in FIG. 10, the lower member 9 having a reduced thickness d is used, and the conductive member 30 is provided below the lower member 9, whereby the capacitance C is changed and the impedance Z is changed. It can be adjusted to the desired value. Further, by interposing the conductive member 30 between the lower member 9 and the mounting table 2 in this way, the thermal conductivity between the lower member 9 and the mounting table 2 can be improved, The side member 9 can be controlled to a predetermined temperature to prevent the process from being overheated and adversely affecting the process. In this case, as the conductive member 30, it is preferable to select a material having good thermal conductivity, such as silicon or silicon rubber.

Here, an insulating member or the like (thickness, for example, 0.6 mm) for actually forming an electrostatic chuck is also provided on the lower portion of the semiconductor wafer W, and the above-described effect is caused by the influence of the insulating member. The same impedance is generated. The impedance of this semiconductor wafer W is Z0,
(Z / Z0) = 60
In order to adjust the value of the impedance Z so as to be about, assuming that the area of the upper surface (or lower surface) of the lower member 9 is S, the thickness is d, the relative dielectric constant is ε, and the vacuum dielectric constant is ε0,
Z = ε0 · ε (S / d)
Therefore, when the material of the lower member 9 is quartz (quartz), the inner diameter is about 300 mm, and the outer diameter is about 360 mm, the thickness is preferably about 5 to 10 mm, preferably 7 to 9 mm. Is more preferable.

  Next, an embodiment of the present invention will be described. FIG. 11 schematically shows a cross-sectional configuration of the focus ring of this embodiment. As described above, the mounting table 2 on which the semiconductor wafer W is mounted is supported by the insulating plate 3, and the high-frequency power source 7 is connected to the mounting table 2.

  Further, a focus ring 50 is provided on the upper peripheral edge of the mounting table 2. The focus ring 50 is disposed on a ring-shaped lower member 51 made of a dielectric (for example, ceramics such as quartz and alumina, resin such as Vespel (registered trademark)), and an upper portion of the lower member 51. It is composed of a ring-shaped upper member 52 made of a conductive material (for example, silicon, carbon, SiC, etc.), and is placed so as to surround the periphery of the semiconductor wafer W which is a substrate to be processed.

The upper member 52 is made of, for example, a conductive material such as aluminum, and has an insulating surface such as a ceramic sprayed film (for example, FCC (fine ceramic coat) such as Al / Al ₂ O ₃ and Y ₂ O ₃ ). The high-frequency power is connected to the ground potential via a high-frequency grounding member 53 coated with a layer (insulating film). This insulating layer is formed for the purpose of protecting the high-frequency grounding member 53 from plasma and preventing a direct current from flowing. That is, the insulating layer has a sufficient thickness not to pass a direct current, and the direct current is blocked by the insulating layer and does not propagate. On the other hand, the high frequency (RF) capable of propagating on the solid surface as a surface wave can propagate through the surface layer of the high frequency grounding member 53, and the high frequency grounding member 53 acts as a high frequency ground path. Further, between the high frequency grounding member 53 and the ground, a frequency cut filter such as a high-pass filter or a low-pass filter, depending on the frequency of the high-frequency power applied for plasma generation in order to inhibit high-frequency return, An attenuation filter or the like may be interposed. It is also possible to provide a switch means between the high frequency grounding member 53 and the ground, and control whether or not to drop the high frequency to the ground at a predetermined timing in conjunction with the process recipe. Between the high-frequency grounding member 53 and the mounting table 2 and on the outer peripheral side of the upper member 52 (above the high-frequency grounding member 53), a ring-shaped dielectric (for example, ceramics such as quartz and alumina, vespel, etc.) Insulating members 54 and 55 made of resin such as (registered trademark) are disposed. Among these, the insulating member 54 is for preventing a DC voltage component from leaking outside from the mounting table 2. Further, the insulating member 55 has an effect of preventing the plasma from spreading too much in the outer peripheral direction, and prevents the plasma from spreading too much and leaking from the exhaust baffle (not shown) to the exhaust side. Regulate the electric field.

  The graph of FIG. 12, with the vertical axis representing voltage and the horizontal axis representing time period, shows a temporal change in the potential (voltage) of the semiconductor wafer W, the focus ring 50 and the plasma. As indicated by a curve A in the figure, the potential of the semiconductor wafer W changes according to a high frequency (for example, 2 MHz) applied from the high frequency power supply 7.

  On the other hand, since the upper member 52 of the focus ring 50 is at the ground potential with respect to the high-frequency power, the potential is constant as shown by the straight line B. Therefore, the potential difference between the semiconductor wafer W and the upper member 52 can be made large as indicated by the arrows in the figure, whether the high frequency cycle is on the plus side or the minus side.

  In the figure, curve C represents the change in plasma potential, and curve D represents the change in potential of the upper member 10 of the focus ring 8 shown in FIG. As shown by the curve D, in the case of the focus ring 8 shown in FIG. 2, when the high frequency cycle is on the plus side, the potential difference between the semiconductor wafer W and the upper member 10 becomes small. Such variation in potential difference due to high-frequency vibration can be suppressed by setting the upper member 52 to the ground potential with respect to the high-frequency power as described above.

  The graph of FIG. 13A, where the vertical axis represents the polymer thickness and the horizontal axis represents the bevel position, shows the adhesion of the polymer at 0, 30, 45, and 90 degrees on the bevel portion of the semiconductor wafer shown in FIG. The result of measuring the quantity is shown. In FIG. 13A, the solid line E is the case where the conventional focus ring 101 shown in FIG. 15 is used, the solid line F is the case where the focus ring 8 shown in FIG. 2 is used, and the solid line G is the focus shown in FIG. The case where the ring 50 is used is shown. As shown in this graph, when the focus ring 50 is used, the electric field strength between the semiconductor wafer and the focus ring can be increased, thereby preventing the wraparound of the plasma and reducing the amount of radicals during this period. Therefore, the amount of polymer deposition at the wafer bevel portion can be further reduced than when the focus ring 8 is used.

  In the above embodiment, the case where the upper member 52 is connected to the ground potential with respect to the high-frequency power by the high-frequency grounding member 53 has been described, but the high-frequency grounding member 53 having such a structure is not used. The upper member 52 may be connected to the ground potential with respect to the high-frequency power by this method.

  FIG. 14A schematically shows a cross-sectional configuration of a focus ring 60 according to another embodiment. As described above, the mounting table 2 on which the semiconductor wafer W is mounted is supported by the insulating plate 3, and the high-frequency power source 7 is connected to the mounting table 2.

  Further, a focus ring 60 is provided on the upper peripheral edge of the mounting table 2. The focus ring 60 is disposed on a ring-shaped lower member 61 made of a dielectric (for example, ceramics such as quartz and alumina, resin such as Vespel (registered trademark)), and an upper portion of the lower member 61. It is composed of a ring-shaped upper member 62 made of a conductive material (for example, silicon, carbon, SiC, etc.) and is placed so as to surround the periphery of the semiconductor wafer W which is a substrate to be processed.

The upper member 62 is made of, for example, a conductive material such as aluminum, and the surface thereof is a ceramic sprayed film (for example, FCC (fine ceramic coat (FCC) such as Al ₂ / Al ₂ O ₃ , Y ₂ O ₃ )). The high frequency power is connected to the ground potential via a high frequency grounding member 63 coated with an insulating layer (insulating film). This insulating layer is formed for the purpose of protecting the high frequency grounding member 63 from plasma and preventing a direct current from flowing. That is, the insulating layer has a sufficient thickness not to pass a direct current, and the direct current is blocked by the insulating layer and does not propagate. On the other hand, a high frequency (RF) capable of propagating as a surface wave on the solid surface can propagate through the surface layer of the high frequency grounding member 63, and the high frequency grounding member 63 acts as a high frequency ground path. Between the high-frequency grounding member 63 and the mounting table 2 and on the outer peripheral side of the upper member 62 (above the high-frequency grounding member 63), a ring-shaped dielectric (for example, ceramics such as quartz and alumina, vespel, etc.) Insulating members 64 and 65 made of a resin such as (registered trademark) are disposed. Among these, the insulating member 64 is for preventing a DC voltage component from leaking out from the mounting table 2. Further, the insulating member 65 has an effect of preventing the plasma from spreading too much toward the outer peripheral direction, and prevents the plasma from spreading too much and leaking from the exhaust baffle (not shown) to the exhaust side. Regulate the electric field.

  Further, in the present embodiment, a predetermined distance D is provided between the lower member 61 and the upper member 62, and the predetermined distance D is approximately 0.5 mm. Moreover, the length L in the radial direction of the portion where the lower member 61 and the upper member 62 face each other with the gap D is set to 5 to 10 mm. The lower end of the upper member 62 is configured to be higher by 1.5 to 2.5 mm (H in the figure) than the upper surface of the semiconductor wafer W. The reason for this configuration is as follows.

  That is, the polymer of the bevel part (90 °, 45 °, 30 ° part of FIG. 13B) and the back surface of the semiconductor wafer end part (0 ° part of FIG. 13B) as described above. In order to reduce the amount of adhesion, it is desirable to keep the temperature of the lower member 61 at a relatively low temperature during the plasma treatment, for example, to keep it lower than 100 ° C., and preferably 70 ° C. or lower. On the other hand, the upper member 62 is desirably maintained at a relatively high temperature, for example, 250 ° C. or higher during the plasma processing. The reason is that by setting the temperature of the upper member 62 to 250 ° C. or more, the bonding between fluorine radicals and Si can be promoted and the amount of fluorine radicals can be reduced, thereby causing a chemical reaction such as photoresist or SiN. This is because it is possible to suppress the phenomenon that the etching rate in a highly etching application increases at the peripheral edge of the semiconductor wafer. Thus, in order to maintain the temperature of the lower member 61 and the temperature of the upper member 62 at different temperatures, a predetermined distance D is provided between the lower member 61 and the upper member 62. Further, in order to raise the temperature of the upper member 62, a high frequency (frequency is 2 MHz, for example) flowing from the mounting table 2 through the path of the lower member 61, the upper member 62, and the high frequency grounding member 63 as indicated by an arrow in the figure. It is necessary to increase the applied voltage and heat the upper member 62 by Joule heat. For this reason, it is necessary to reduce the impedance of the path. In order to satisfy such conditions, the interval D is preferably about 0.5 mm.

In other words, in order to satisfy such a condition, the interval D is preferably set to about 0.5 mm in order to heat the upper member 62 to a predetermined temperature, that is, 250 ° C. or higher when a high frequency power of 2 MHz is applied. Has been found that an impedance of at least 3 to 10 times the plasma impedance Zp is necessary. Therefore, since the high frequency is alternating current, it is necessary to consider not only the resistance but also the capacitance (capacitor) and inductance (coil), and considering the combined impedance (current resistance component against alternating current) as the load effect. This can be explained as follows. The impedance of the junction between the upper member 62 and the high-frequency grounding member 63 and Z _1, and the distance D between the impedance Z _2, Z ₂ becomes a high resistance and there are at least 10 times the impedance Z _1, control of efficiency From the viewpoint of
Z ₂ >> Z ₁ , Z ₂ ≧ 10 × Z ₁
Then, as shown in FIG.
Z ₁ + Z ₂ > Zp
To control so that
Impedance [Ω]: Z = ε0 S / D
(Ε0 = dielectric constant of vacuum, S = area [m ² ], D = interval [m])
It can be obtained from the following formula.

  Since the surface area of the lower member 61 is different between the 200 mm wafer and the 300 mm wafer, if the desired surface area of the lower member 61 is introduced into the above equation, the distance D can be uniquely determined. That is, the present invention can be applied not only to a semiconductor wafer but also to a lower member of a substrate processing apparatus that performs plasma processing on an LCD substrate having a larger area. Accordingly, since the upper member 62 and the lower member 61 are not in contact with each other, it is possible to adopt a structure in which heat is not transferred, and the high frequency, which is a surface wave generated from the high frequency power source 7, is passed through the capacitance (distance D) by the electrostatic induction principle. It is transmitted to the member 62. In addition, when a heat insulating material is sandwiched at the space D, the dielectric constant of the portion is limited by the dielectric constant of the material of the heat insulating material. However, when the vacuum capacitance is configured as in this case, the degree of vacuum in the processing chamber is controlled. Thus, the dielectric constant ε can be variably controlled, which is excellent in terms of controllability.

  In order to reduce heat conduction and prevent heat from escaping, an interval may be provided between the upper member 62 and the high frequency grounding member 63. Other configurations may be adopted as long as the lower member 61 and the upper member 62 can be controlled to the above temperature.

  Further, in order to control the electric field at the peripheral edge of the semiconductor wafer and perform the etching substantially vertically as described above, the lower end of the upper member 62 is 1.5-2. 5 mm (H in the figure) is configured to be higher.

According to the present embodiment having the above-described configuration, the amount of polymer deposition in the wafer bevel portion can be reduced, and the phenomenon that the etching rate of the photoresist increases at the peripheral portion of the semiconductor wafer can be suppressed, and Also, substantially vertical etching can be performed at the peripheral edge of the semiconductor wafer, and the in-plane uniformity of processing can be improved.

  W: Semiconductor wafer, 1 ... Vacuum chamber, 2 ... Mounting table, 8 ... Focus ring, 9 ... Lower member, 10 ... Upper member, 10a ... Flat part, 10b ... Inclined part, 14 ……shower head.

Claims (10)

An annular ring disposed on a lower electrode on which the substrate to be processed is placed in a processing chamber for accommodating the substrate to be processed and performing a predetermined plasma process, and surrounding the substrate to be processed. A focus ring,
A lower member made of a dielectric, and an upper member made of a conductive material disposed on the lower member;
The upper member is made of a conductive member whose surface is coated with an insulating layer, prevents direct current from flowing through the insulating layer, and a high frequency grounding member capable of propagating high frequency power through the surface layer as a surface wave, For high frequency power, it is connected to ground potential ,
The high-frequency grounding member is disposed on the lower side of the upper member and on the outer periphery of the lower member so as to contact at least part of the lower surface of the upper member. . The focus ring according to claim 1.
A focus ring, wherein an insulating member is disposed between the lower electrode and the high-frequency grounding member. The focus ring according to claim 1 or 2,
A focus ring, wherein an annular insulating member is disposed on an outer peripheral side of the upper member. In the focus ring according to any one of claims 1 to 3,
A focus ring, wherein a predetermined interval is provided between the upper member and the lower member. The focus ring according to claim 4, wherein
A focus ring, wherein a predetermined distance between the upper member and the lower member is 0.5 mm. The focus ring according to claim 5, wherein
The focus ring, wherein a length in a radial direction of a portion where the upper member and the lower member are opposed to each other with the predetermined interval is 5 to 10 mm. In the focus ring according to any one of claims 1 to 6,
The focus ring, wherein the upper member is arranged so that a lower end of the upper member is 1.5 to 2.5 mm higher than an upper surface of the substrate to be processed. The focus ring according to any one of claims 1 to 7,
A focus ring, wherein the temperature of the upper member is configured to be 250 ° C. or higher during plasma processing. The focus ring according to any one of claims 1 to 8,
A focus ring, wherein the temperature of the lower member is configured to be 100 ° C. or lower during plasma processing. A processing chamber for accommodating a substrate to be processed and performing a predetermined plasma processing;
A lower electrode provided in the processing chamber and on which the substrate to be processed is placed;
An upper electrode provided in the processing chamber and facing the lower electrode;
A high-frequency power source for supplying high-frequency power between the lower electrode and the upper electrode to turn the gas in the processing chamber into plasma,
An annular member disposed on the lower electrode and surrounding the substrate to be processed, and a lower member made of a dielectric;
An annular upper member made of a conductive material, disposed on the lower member;
Comprising
The upper member is made of a conductive member whose surface is coated with an insulating layer, prevents direct current from flowing through the insulating layer, and a high frequency grounding member capable of propagating high frequency power through the surface layer as a surface wave, For high frequency power, it is connected to ground potential ,
The high frequency grounding member is disposed on the lower side of the upper member and on the outer peripheral portion of the lower member so as to be in contact with at least part of the lower surface of the upper member. apparatus.

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