JP2007250967A - Plasma treating apparatus and method, and focus ring - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the occurrence of deposition on the lower surface of a peripheral section when performing the plasma treatment of a substrate to be treated, such as a semiconductor wafer. <P>SOLUTION: When the substrate W to be treated is placed on a placement table 11 arranged in a treatment chamber 10, and plasma is generated in the treatment chamber 10 by giving high-frequency voltages for treating the substrate W to be treated, an electric field for accelerating ions generated by plasma toward the lower surface of the periphery of the substrate W to be treated is formed at the lower section of the periphery of the substrate W to be treated placed on the placement table 11, thus reducing the generation of deposition by allowing the ions to collide with the lower surface of the periphery of the substrate W to be treated. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a plasma processing apparatus and a plasma processing method for performing plasma processing such as etching processing on a substrate to be processed such as a semiconductor wafer, and further relates to a focus ring and a focus ring component used in the plasma processing apparatus.

  2. Description of the Related Art Conventionally, plasma processing apparatuses that perform plasma processing such as etching using plasma generated by applying a high-frequency voltage have been widely used in, for example, manufacturing processes of fine electric circuits in semiconductor devices. In such a plasma processing apparatus, a semiconductor wafer is placed in a processing chamber hermetically sealed inside, a plasma is generated in the processing chamber by applying a high frequency voltage, and this plasma is applied to the semiconductor wafer to perform etching. Etc. are subjected to plasma treatment.

  Among such plasma processing apparatuses, there is one in which a ring-shaped member called a focus ring is arranged so as to surround the periphery of a semiconductor wafer. This focus ring is made of a conductive material such as silicon in the case of etching an insulating film, for example, and confines the plasma and alleviates the discontinuity due to the edge effect of the bias potential in the semiconductor wafer surface. The semiconductor wafer is provided for the purpose of enabling uniform and good processing at the peripheral portion as well as the central portion of the semiconductor wafer.

  In addition, in order to improve the processing uniformity at the peripheral edge of the semiconductor wafer by this focus ring, the present inventors have made the upper surface of the focus ring continuous with the inclined surface portion surrounding the semiconductor wafer and the outside of the inclined surface portion. The thing formed in the horizontal plane part formed by this is disclosed (refer patent document 1).

Japanese Patent Laying-Open No. 2005-277369 (for example, FIGS. 1 and 2)

  In the invention of the above-mentioned Patent Document 1, by devising the shape of the upper surface of the focus ring, the inclination of the electric field at the peripheral portion of the semiconductor wafer is suppressed, and the uniformity of the etching process is achieved. By forming a potential difference between the inner peripheral surface and the inner peripheral surface, the wraparound of the plasma below the peripheral portion of the semiconductor wafer is suppressed.

  However, even if the wraparound of the plasma is suppressed by the potential difference between the peripheral edge of the semiconductor wafer and the inner peripheral surface of the focus ring in this way, so-called deposition occurs in which CF polymer or the like adheres to the lower surface of the peripheral edge of the semiconductor wafer. There was a case.

  An object of the present invention is to reduce deposition adhesion to the lower surface of the peripheral portion when plasma processing is performed on a substrate to be processed such as a semiconductor wafer.

  As described above, the present inventors have studied various factors of deposition occurring on the lower surface of the peripheral edge of the substrate to be processed. As a result, when a potential difference between the peripheral edge of the semiconductor wafer and the inner peripheral surface of the focus ring is applied as in Patent Document 1, ions in the plasma are caused by a gap between the peripheral edge of the semiconductor wafer and the inner peripheral surface of the focus ring. When passing through the substrate, it is drawn toward either the peripheral edge of the semiconductor wafer or the inner peripheral surface of the focus ring due to the potential difference between the two. The plasma product having no electric charge passes through the gap between the peripheral edge of the semiconductor wafer and the inner peripheral surface of the focus ring as it is, and reaches the lower part of the peripheral edge of the substrate to be processed, which is a cause of deposition. I understand. On the other hand, in order to suppress the deposition generated on the lower surface of the peripheral edge of the substrate to be processed as described above, ions in the plasma are made to reach below the peripheral edge of the substrate to be processed, and the ions are allowed to reach the peripheral edge of the substrate to be processed. The knowledge that it was effective to make it collide with the lower surface of the part was obtained.

  The present invention has been created based on the above findings. That is, according to the present invention, a plasma for processing a substrate to be processed by placing the substrate to be processed on a mounting table disposed in the processing chamber and generating a plasma in the processing chamber by applying a high frequency voltage. A processing apparatus, comprising: a focus ring arranged so as to surround a substrate to be processed placed on the mounting table, wherein the focus ring is formed of a substrate to be processed placed on the mounting table. An outer ring portion made of a conductive material arranged on the outer periphery and an inner ring portion made of a conductive material arranged at a predetermined interval below the peripheral edge portion of the substrate to be processed placed on the mounting table. There is provided a plasma processing apparatus, wherein the inner ring portion and the mounting table are electrically insulated.

  In this plasma processing apparatus, for example, the outer ring portion and the inner ring portion are electrically connected, and the outer ring portion and the mounting table are insulated from each other. In that case, an insulating member may be disposed between the outer ring portion and the inner ring portion and the mounting table. The outer ring portion and the inner ring portion may be integrally formed. In addition, the distance between the outer peripheral surface of the substrate to be processed placed on the mounting table and the inner peripheral surface of the focus ring facing the substrate is set so that the upper surface of the inner ring portion and the substrate mounted on the mounting table are placed on the mounting table. It may be wider than the distance from the lower surface of the peripheral edge of the processing substrate.

  In the plasma processing apparatus, the outer ring portion and the inner ring portion may be electrically insulated from the ground. In that case, the capacitance between the outer ring portion and the inner ring portion and the ground may be variable. A variable DC power supply may be electrically connected to the outer ring portion and the inner ring portion.

  In the plasma processing apparatus, for example, the outer ring portion and the inner ring portion are electrically insulated. In that case, the outer ring portion may be electrically connected to the mounting table.

  The upper surface of the outer ring portion is continuously formed on the outer periphery of the inclined surface portion, which is arranged around the substrate to be processed placed on the mounting table and gradually increases toward the outer side. You may have the horizontal surface part made. Further, the conductive material constituting the outer ring portion and the inner ring portion may be, for example, any one of Si, C, and SiC.

  According to the present invention, in a plasma processing apparatus for processing a substrate to be processed by generating a plasma in the processing chamber by applying a high-frequency voltage, the substrate to be processed on a mounting table disposed in the processing chamber. A focus ring arranged so as to surround the periphery, an outer ring portion made of a conductive material arranged on the outer periphery of the substrate to be processed placed on the mounting table, and placed on the mounting table An inner ring portion made of a conductive material disposed at a predetermined interval below the peripheral edge portion of the processed substrate, wherein the inner ring portion and the mounting table are electrically insulated. A featured focus ring is provided.

  In this focus ring, for example, the outer ring portion and the inner ring portion are electrically connected, and include an insulating member for insulating the outer ring portion and the inner ring portion from the mounting table. ing. In that case, the outer ring portion and the inner ring portion may be integrally formed. Moreover, the recessed part may be formed in the internal peripheral surface facing the outer peripheral surface of the to-be-processed substrate mounted on the mounting base.

  The focus ring may further include a capacitance changing means for changing the capacitance between the outer ring portion and the inner ring portion and the ground. Further, a variable DC power supply electrically connected to the outer ring portion and the inner ring portion may be provided.

  In addition, the focus ring includes an insulating member that electrically insulates the outer ring portion and the inner ring portion, for example. In that case, the outer ring portion may be electrically connected to the mounting table.

  In this focus ring, the upper surface of the outer ring portion is disposed around the substrate to be processed placed on the mounting table, and has an inclined surface portion that gradually increases toward the outside, and an outer side of the inclined surface portion. It may have a horizontal plane portion formed continuously. Further, the conductive material constituting the outer ring portion and the inner ring portion may be, for example, any one of Si, C, and SiC.

  According to the present invention, the focus ring includes the focus ring and a support member that arranges the focus ring so as to surround the substrate to be processed on the mounting table in the processing chamber. A ring component is provided.

  According to the present invention, a plasma processing is performed in which a substrate to be processed is mounted on a mounting table disposed in the processing chamber, and plasma is generated in the processing chamber by applying a high frequency voltage to process the substrate to be processed. In the method, an electric field for accelerating ions generated by the plasma toward the lower surface of the peripheral portion of the substrate to be processed is formed below the peripheral portion of the substrate to be processed placed on the mounting table. A plasma processing method is provided, characterized in that ions collide with the lower surface of the peripheral edge of the substrate to be processed.

  In this plasma processing method, the electric field is generated, for example, by disposing an inner ring portion made of a conductive material at a predetermined interval below the peripheral portion of the substrate to be processed placed on the mounting table. And a potential difference between the inner ring portion and the inner ring portion. Further, the amount of collision of ions with the lower surface of the peripheral edge of the substrate to be processed may be adjusted by changing the strength of the electric field. Furthermore, the equipotential surface in the electric field is rough on the outer side from the outer peripheral surface of the substrate to be processed placed on the mounting table, and below the peripheral portion of the substrate to be processed placed on the mounting table. Then it may be made dense.

  According to the present invention, deposition in the lower surface of the peripheral portion of the substrate to be processed is conventionally caused by causing ions in the plasma to reach the lower portion of the peripheral portion of the substrate to be processed and collide with the lower surface of the peripheral portion of the substrate to be processed. Compared to, it can be reduced.

  Preferred embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is an explanatory diagram showing a schematic configuration of a plasma processing apparatus 1 according to an embodiment of the present invention. FIG. 2 is an enlarged longitudinal sectional view showing the focus ring 25 provided in the plasma processing apparatus 1. In the present specification and drawings, components having substantially the same functional configuration are denoted by the same reference numerals, and redundant description is omitted.

  A mounting table 11 that also serves as a lower electrode for mounting a semiconductor wafer W, which is a substrate to be processed, is disposed inside an airtight cylindrical processing chamber 10. The processing chamber 10 and the mounting table 11 are made of a conductive material such as aluminum. However, the mounting table 11 is supported on the bottom surface of the processing chamber 10 via an insulating plate 12 such as ceramic, and the processing chamber 10 and the mounting table 11 are electrically insulated from each other.

  The mounting table 11 includes an electrostatic chuck (not shown) for attracting and holding the semiconductor wafer W placed on the upper surface. Further, inside the mounting table 11, a heat medium flow path 15 for circulating an insulating fluid as a heat medium for temperature control, and a temperature control gas such as helium gas are provided on the back surface of the semiconductor wafer W. A gas flow path 16 for supply is provided. In this way, by circulating the insulating fluid controlled to a predetermined temperature in the heat medium flow path 15, the mounting table 11 is controlled to a predetermined temperature, and the mounting table 11 and the back surface of the semiconductor wafer W are connected to each other. A temperature control gas is supplied between them through the gas flow path 16 to promote heat exchange between them, and the semiconductor wafer W can be accurately and efficiently controlled to a predetermined temperature.

  A high-frequency power source (RF power source) 21 for bias is connected to the mounting table 11 via a matching unit 20. A high frequency voltage having a predetermined frequency is applied to the mounting table 11 from the high frequency power source 21. On the other hand, the processing chamber 10 is electrically connected to a ground (earth) 22.

  Inside the processing chamber 10, a focus ring 25 is disposed around the upper surface of the mounting table 11 so as to surround the semiconductor wafer W mounted on the mounting table 11. The focus ring 25 includes a ring-shaped insulating member 26 that is directly placed on the mounting table 11, and a ring-shaped conductive member 27 that is disposed above the insulating member 26. The insulating member 26 is made of, for example, an insulating material (dielectric) such as ceramics such as quartz or alumina, or a resin such as Vespel (registered trademark). The conductive member 27 is made of a conductive material such as Si (Si doped with B or the like for providing conductivity), C, SiC, or the like.

  As shown in FIG. 2, the conductive member 27 includes an outer ring portion 30 disposed on the outer periphery of the semiconductor wafer W placed on the placement table 11, and a semiconductor wafer W placed on the placement table 11. A ring-shaped inner ring portion 31 is provided below the periphery of the ring portion with a predetermined interval. In the illustrated example, the outer ring portion 30 and the ring-shaped inner ring portion 31 are integrally formed as a conductive member 27 made of a conductive material. Therefore, the outer ring portion 30 and the inner ring portion 31 are electrically connected to each other. It is in a state of being conducted to. However, since the insulating member 26 is interposed between the ring-shaped conductive member 27 and the mounting table 11 as described above, the outer ring portion 30 and the inner ring portion 31 are electrically connected to the mounting table 11. Is insulated. The boundary between the outer ring portion 30 and the inner ring portion 31 is shown as a dotted line 31 'in FIG. As indicated by the boundary 31 ′, in the integrally formed conductive member 27, the portion disposed on the outer periphery of the semiconductor wafer W placed on the placement table 11 is the outer ring portion 30. A portion disposed at a predetermined interval below the peripheral edge of the semiconductor wafer W is a ring-shaped inner ring portion 31.

  Further, the ring-shaped conductive member 27 thus insulated from the mounting table 11 is not in electrical contact with the inside of the processing chamber 10 other than the insulating member 26. For this reason, the outer ring portion 30 and the inner ring portion 31 are in an electrically floating state with respect to the ground 22.

  The upper surface of the outer ring portion 30 is continuously formed outside the inclined surface portion 30a and the inclined surface portion 30a which is disposed around the semiconductor wafer W mounted on the mounting table 11 and gradually increases toward the outer side. The horizontal surface portion 30b is formed. The horizontal surface portion 30 b is set higher than the upper surface of the semiconductor wafer W placed on the mounting table 11, and the inclined surface portion 30 a is substantially the same as the upper surface of the semiconductor wafer W placed on the mounting table 11. The heights are equal and set so as to gradually increase to the height of the horizontal surface portion 30b toward the outside.

  Further, inside the processing chamber 10, a ring-shaped exhaust ring 35 in which a large number of exhaust holes are formed is provided outside the focus ring 25. The processing space in the vacuum chamber 10 is evacuated through a vacuum pump of an exhaust system 37 connected to the exhaust port 36 via the exhaust ring 35.

  On the other hand, a shower head 40 is provided on the ceiling portion of the vacuum chamber 10 above the mounting table 11 so as to face the mounting table 11 in parallel. The mounting table 11 and the shower head 40 are paired with each other. It functions as an electrode (upper electrode and lower electrode). The shower head 40 is connected to a high-frequency power source 42 for plasma generation via a matching unit 41.

  The shower head 40 is provided with a large number of gas discharge holes 45 on the lower surface thereof. The inside of the shower head 40 is formed in a gas diffusion space 47 and has a gas introduction part 46 in the upper part thereof. A gas supply pipe 50 is connected to the gas introduction part 46, and a gas supply system 51 is connected to the other end of the gas supply pipe 50. The gas supply system 51 includes a mass flow controller (MFC) 52 for controlling the gas flow rate, for example, a processing gas supply source 53 for supplying a processing gas for etching and the like.

Next, the procedure of the plasma processing by the plasma processing 1 configured as described above will be described.
First, a gate valve (not shown) provided in the vacuum chamber 1 is opened, and a semiconductor wafer W is transferred by a transfer mechanism (not shown) through a load lock chamber (not shown) arranged adjacent to the gate valve. Is loaded into the vacuum chamber 10 and mounted on the mounting table 11. Then, after the transport mechanism is withdrawn outside the vacuum chamber 10, the gate valve is closed and the inside of the vacuum chamber 10 is sealed.

  Thereafter, a predetermined processing gas is supplied into the vacuum chamber 10 from the processing gas supply source 53 through the shower head 40 while the vacuum chamber 10 is exhausted to a predetermined degree of vacuum through the exhaust port 36 by the vacuum pump of the exhaust system 37. Supply.

  In this state, a high frequency power for bias having a relatively low frequency is supplied from the high frequency power source 21 and a high frequency power for plasma generation having a relatively high frequency is supplied from the high frequency power source 42, as shown in FIG. As described above, the plasma P is generated in the vacuum chamber 10 above the semiconductor wafer W. In this way, radical molecules and ions in the plasma P generated above the semiconductor wafer W are drawn toward the upper surface of the semiconductor wafer W, and plasma processing of the upper surface of the semiconductor wafer W is performed by their action.

  When the predetermined plasma processing is completed, the plasma processing is stopped by stopping the supply of high-frequency power from the high-frequency power sources 21 and 42, and the semiconductor wafer W is removed from the vacuum chamber 10 by a procedure reverse to the above-described procedure. Take it out.

  When performing such plasma processing, the plasma processing apparatus 1 according to this embodiment employs the focus ring 25 in which the conductive member 27 is disposed on the mounting table 11 via the insulating member 26 as described above. Therefore, as shown in FIG. 3, a potential difference Ve is generated between the semiconductor wafer W (mounting table 11) and the conductive member 27. In this case, if the capacitance between the semiconductor wafer W and the conductive member 27 is Ce, the potential difference Ve is inversely proportional to the capacitance Ce.

  Further, during the plasma processing, the potential difference Ve is generated between the semiconductor wafer W and the conductive member 27 as described above, so that an electric field E as shown in FIG. 4 is formed between the semiconductor wafer W and the conductive member 27. Is done. The equipotential surface e of the electric field E is substantially vertical between the outer peripheral surface of the semiconductor wafer W and the inner peripheral surface 30c of the outer ring portion 30, as shown in FIG. Between the upper surface of the inner ring portion 31, it is substantially horizontal. Due to the action of the electric field E having the equipotential surface e, the plasma P drawn downward toward the surface of the semiconductor wafer W between the outer peripheral surface of the semiconductor wafer W and the inner peripheral surface 30c of the outer ring portion 30. The ions I in the plasma are accelerated in the direction toward the outer peripheral surface of the semiconductor wafer W, and the ions I in the plasma are absorbed between the lower surface of the peripheral edge of the semiconductor wafer W and the upper surface of the inner ring portion 31. It is possible to accelerate in a direction toward the lower surface of the peripheral edge.

  Thus, during plasma processing, the ions I in the plasma collide with the outer peripheral surface and the lower peripheral surface of the semiconductor wafer W by the action of the electric field E formed by the potential difference Ve between the semiconductor wafer W and the conductive member 27. Thus, the occurrence of deposition on both the outer peripheral surface and the peripheral surface of the semiconductor wafer W can be reduced.

In order to reduce the occurrence of deposition on the lower surface of the peripheral edge of the semiconductor wafer W, all the ions I in the plasma are between the outer peripheral surface of the semiconductor wafer W and the inner peripheral surface 30c of the outer ring portion 30. Instead of colliding with the outer peripheral surface of the semiconductor wafer W, at least a part of the ions I in the plasma pass through the space between the outer peripheral surface of the semiconductor wafer W and the inner peripheral surface 30c of the outer ring portion 30 as it is, and the semiconductor It is necessary to pass the ions I to the lower part of the peripheral edge of the wafer W. For this purpose, as shown in FIG. 2, a distance L ₁ between the outer peripheral surface of the semiconductor wafer W placed on the mounting table 11 and the inner peripheral surface 30 c of the outer ring portion 30 facing it is set as an inner ring portion 31. Is formed wider than the distance L ₂ between the upper surface of the semiconductor wafer and the lower surface of the peripheral edge of the semiconductor wafer W.

  With this configuration, the interval between the equipotential surfaces e shown in FIG. 4 is made relatively rough between the outer peripheral surface of the semiconductor wafer W and the inner peripheral surface 30c of the outer ring portion 30, and the semiconductor wafer W It can be made relatively dense between the lower surface of the peripheral edge portion and the upper surface of the inner ring portion 31. As a result, between the outer peripheral surface of the semiconductor wafer W and the inner peripheral surface 30c of the outer ring portion 30, acceleration in the direction toward the outer peripheral surface of the semiconductor wafer W is made relatively small, and ions are formed below the peripheral portion of the semiconductor wafer W. I can be passed. On the other hand, between the lower surface of the peripheral edge of the semiconductor wafer W and the upper surface of the inner ring portion 31, acceleration in the direction toward the lower surface of the peripheral edge of the semiconductor wafer W is relatively large, and ions are generated on the lower surface of the peripheral edge of the semiconductor wafer W. It is possible to reliably reduce the occurrence of deposition on the lower surface of the peripheral edge of the semiconductor wafer W by colliding I.

Incidentally, the outer peripheral surface and the preferred range of distance L ₂ between the lower surface of the peripheral portion of the upper surface and the semiconductor wafer W intervals L ₁ and the inner ring portion 31 and the inner peripheral surface 30c of the outer ring portion 30 of the semiconductor wafer W, the semiconductor Although it varies depending on the magnitude of the potential difference Ve formed between the wafer W and the conductive member 27, the diameter and thickness of the semiconductor wafer W, the height of the inner peripheral surface 30c, etc., it cannot be determined in general. for example, the spacing _{L 1} between the inner circumferential surface 30c of the outer peripheral surface and the outer ring portion 30 of the semiconductor wafer W is 1 to 5 mm, 2 to 2.5 mm is preferable. When the distance L ₁ is too small, it may result in abnormal discharge between the outer peripheral surface and the outer ring portion 30 of the semiconductor wafer W, and an excessively large, the plasma sheath and the outer ring on the semiconductor wafer W to be described later The plasma sheath on the part 30 may be discontinuous.

Further, for example, distance _{L 2} between the lower surface of the peripheral portion of the upper surface and the semiconductor wafer W of the inner ring portion 31 is 0.2 to 1 mm, 0.2 to 0.5 mm is preferable. When the interval L ₂ is too small, it may result in abnormal discharge between the peripheral portion of the upper surface and the semiconductor wafer W of the inner ring portion 31, and an excessively large peripheral lower surface and an inner ring of semiconductor wafer W The gap between the equipotential surfaces e cannot be made close to the upper surface of the portion 31, and the ions I cannot be sufficiently accelerated in the direction toward the lower surface of the peripheral edge of the semiconductor wafer W. The occurrence of deposition on the lower surface of the part cannot be sufficiently reduced. The distance _{L 4} of the facing portion of the lower surface of the peripheral portion of the upper surface and the semiconductor wafer W of the inner ring portion 31 which faces this way at a distance _{L 2} is, 0.05 to 0.5 mm is preferable.

  In the illustrated embodiment, since a potential difference Ve is generated between the semiconductor wafer W and the conductive member 27 during the plasma processing, the plasma sheath formed on the semiconductor wafer W and the outer ring portion of the conductive member 27 are formed. The thickness of the plasma sheath formed on 30 will be different. However, in the focus ring 25 of this embodiment, as described above, the upper surface of the outer ring portion 30 is continuously formed on the outer surface of the inclined surface portion 30a and the inclined surface portion 30a that gradually increases toward the outer side. Since it is formed on the horizontal surface portion 30b higher than the upper surface of the semiconductor wafer W, the fluctuation of the plasma sheath thickness at the boundary on the semiconductor wafer W and the outer ring portion 30 can be reduced. Thereby, the rapid change of the electric field at the peripheral portion of the semiconductor wafer W can be suppressed, and the ions I in the plasma can be drawn almost perpendicularly to the upper surface of the semiconductor wafer W at the peripheral portion of the semiconductor wafer W. The uniformity of plasma processing can be improved. Further, since the upper surface of the outer ring portion 30 is formed by the inclined surface portion 30a and the horizontal surface portion 30b, the life of the focus ring 25 itself can be extended.

The range h in the height direction of the inclined surface portion 30a formed on the upper surface of the outer ring portion 30 is preferably 0 to 6 mm in height from the upper surface of the semiconductor wafer W, more preferably 2 mm to 4 mm. is there. The horizontal length h ′ of the inclined surface portion 30a (the length in the diameter direction of the semiconductor wafer W) is preferably in the range of 0.5 to 9 mm, and more preferably in the range of 1 to 6 mm. Incidentally, the horizontal length h of the inclined surface portion 30a 'is the distance L ₁ between the inner circumferential surface 30c of the outer peripheral surface and the outer ring portion 30 of the semiconductor wafer W is also possible to zero. In such a case, although the inclined surface portion 30a is not shape, it is also possible to suppress the rapid change in the electric field at the peripheral portion of the semiconductor wafer W by adjusting the distance L _1.

Further, during the plasma processing, a potential difference Ve is generated between the mounting table 11 and the conductive member 27. Therefore, if the inner edge of the inner ring portion 31 is too close to the mounting table 11, an abnormal discharge may occur between the two. There is. On the other hand, if the inner edge of the inner ring portion 31 is excessively separated from the mounting table 11, the inner ring portion 31 cannot be sufficiently intruded below the peripheral edge of the semiconductor wafer W, and the ions I in the plasma as described above can be prevented. The collision with the lower surface of the peripheral edge of the semiconductor wafer W is eliminated, and the effect of reducing deposition cannot be obtained sufficiently. Therefore, the interval _{L 3} between the inner edge and the mounting table 11 of the inner ring portion 31 shown in FIG. 2, is preferably in the range of 0.5 to 1 mm.

  It is necessary to determine how much the electrostatic capacity Ce between the semiconductor wafer W and the conductive member 27 should be determined based on actual individual plasma processing apparatuses. Generally, when the electrostatic capacitance Ce is reduced, the potential difference Ve formed between the semiconductor wafer W and the conductive member 27 is increased. Therefore, the force for accelerating the ions I in the plasma in the direction toward the lower surface of the peripheral edge of the semiconductor wafer W between the lower surface of the peripheral edge of the semiconductor wafer W and the upper surface of the inner ring portion 31 is increased. The effect of reducing the occurrence of deposition on the lower surface of the part tends to increase. Conversely, when the capacitance Ce is increased, the potential difference Ve formed between the semiconductor wafer W and the conductive member 27 is decreased. Therefore, the force for accelerating the ions I in the plasma in the direction toward the lower surface of the peripheral edge of the semiconductor wafer W between the lower surface of the peripheral edge of the semiconductor wafer W and the upper surface of the inner ring portion 31 is weakened. The effect of reducing the occurrence of deposition on the lower surface of the part tends to decrease.

  Further, as described above, the plasma sheath formed on the semiconductor wafer W during the plasma processing and the plasma sheath formed on the outer ring portion 30 of the conductive member 27 are different in thickness, so that the peripheral portion of the semiconductor wafer W The incident angle of ions I is affected. Generally, when the capacitance Ce is reduced, the potential difference Ve formed between the semiconductor wafer W and the conductive member 27 is increased, and the thickness of the plasma sheath formed on the outer ring portion 30 is increased. The incident angle of ions I tends to be inclined (incident angle> 90 °) toward the center of the semiconductor wafer W. Conversely, when the capacitance Ce is increased, the potential difference Ve formed between the semiconductor wafer W and the conductive member 27 is decreased, and the thickness of the plasma sheath formed on the outer ring portion 30 is increased. , The incident angle of the ions I tends to be inclined in the direction from the center of the semiconductor wafer W to the outside (incident angle <90 °).

  Here, with respect to the change in the capacitance Ce between the semiconductor wafer W and the conductive member 27, the polymer adhesion amount (right vertical axis) on the lower surface of the peripheral edge of the semiconductor wafer W and the ions I on the upper surface of the peripheral edge of the semiconductor wafer W. The result of simulating the relationship of the incident angle (left vertical axis) is shown in FIG. The above trends were also confirmed in the simulation results of the present inventors.

  Therefore, according to the plasma processing apparatus 1 of this embodiment, the occurrence of deposition on the lower surface side of the peripheral portion of the semiconductor wafer W can be reduced as compared with the conventional case, and the electric field at the peripheral portion of the semiconductor wafer W can be reduced. By suppressing the inclination, it is possible to perform substantially vertical etching at the peripheral portion of the semiconductor wafer W, and to improve the in-plane uniformity of processing.

As mentioned above, although an example of preferable embodiment of this invention was shown, this invention is not limited to the form illustrated here. For example, in order to widen the distance L ₁ between the inner circumferential surface 30c of the outer peripheral surface of the semiconductor wafer W placed on the mounting table 11 and the outer ring portion 30, as the focus ring 25a shown in FIG. 6, A recess 30d may be formed on the inner peripheral surface 30c of the outer ring portion 30 facing the outer peripheral surface of the semiconductor wafer W. By thus forming the recess 30d is sufficiently wide spacing L ₁ between the outer peripheral surface of the semiconductor wafer W, it is possible to more smoothly pass through the ion I to the peripheral edge portion under the semiconductor wafer W . In the case of the focus ring 25 a described with reference to FIG. 6, it is desirable to omit the inclined surface portion 30 a on the upper surface of the outer ring portion 30.

  Further, as in the focus ring 25b shown in FIG. 7, the second conductive member 60 electrically connected to the ground 22 is brought close to the conductive member 27 insulated from the mounting table 11 by the insulating member 26. The second insulating member (dielectric) 61 may be interposed between the conductive member 27 and the conductive member 60. In the example shown in FIG. 7, a cover ring 62 made of an insulating material is provided outside the conductive member 27.

  In the focus ring 25b, during the plasma processing, as shown in FIG. 8, a potential difference Ve is generated between the semiconductor wafer W (mounting table 11) and the conductive member 27, and the conductive member 27 and the ground 22 ( A potential difference Vg is generated with respect to the conductive member 60). In this case, if the capacitance between the semiconductor wafer W and the conductive member 27 is Ce and the capacitance between the conductive member 27 and the ground 22 is Cg, the semiconductor wafer W (mounting table 11) and the conductive material are conductive. The potential difference Ve between the members 27 is inversely proportional to the capacitance Ce, and the potential difference Vg between the conductive member 27 and the ground 22 is inversely proportional to the capacitance Cg. The following formulas (1) to (3) are established among these potential differences Ve and Vg and capacitances Ce and Cg.

Ve + Vg = V _total (1)
Ce × Ve = Cg × Vg (2)
Ve = Cg × V _total / (Cg + Ce) (3)

  From equation (3), the potential difference Ve between the semiconductor wafer W (mounting table 11) and the conductive member 27 can be changed by changing the capacitance Cg between the conductive member 27 and the ground 22. I understand. For example, in the focus ring 25b shown in FIG. 7, the second insulating member (which is interposed between the conductive member 27 and the conductive member 60, which changes the proximity distance between the conductive member 27 and the second conductive member 60). The capacitance between the conductive member 27 and the ground 22 is changed by a method such as changing the dielectric constant of the (dielectric) 61, thereby changing the semiconductor wafer W (mounting table 11) and the conductive member 27. It is possible to change the potential difference Ve.

  This relationship will be described with reference to FIG. In FIG. 9, a curve W ′ indicates a change in the potential of the semiconductor wafer W during the plasma processing, a curve 27 ′ indicates a change in the potential of the conductive member 27 during the plasma processing, and a straight line 22 ′ indicates the ground 22. Is shown. In the figure, the width of the curve W ′ and the curve 27 ′ is the potential difference Ve between the semiconductor wafer W (mounting table 11) and the conductive member 27, and the width of the curve 27 ′ and the straight line 22 ′ is the conductive member 27. And the ground 22 is a potential difference Vg. As shown in FIG. 9, when the potential difference Vg between the conductive member 27 and the ground 22 is increased (in the case of the alternate long and short dash line 27 'in FIG. 9), the semiconductor wafer W (mounting table 11) and the conductive layer The potential difference Ve between the conductive members 27 is reduced. Conversely, when the potential difference Vg between the conductive member 27 and the ground 22 is reduced (in the case of the two-dot chain line 27 ′ in FIG. 9), the gap between the semiconductor wafer W (mounting table 11) and the conductive member 27. The potential difference Ve becomes larger. Thus, by changing the potential difference Vg between the conductive member 27 and the ground 22, the potential difference Ve between the semiconductor wafer W (mounting table 11) and the conductive member 27 can be changed.

Here, in the plasma processing apparatus 1 using the focus ring 27 b shown in FIG. 7, the polymer adhesion on the lower surface of the peripheral edge of the semiconductor wafer W with respect to the change in the potential difference Ve between the semiconductor wafer W (mounting table 11) and the conductive member 27. The result of simulating the relationship between the quantity (right vertical axis) and the incident angle (left vertical axis) of ions I on the peripheral surface of the semiconductor wafer W is shown in FIG. The _total sum (V _total ) of the potential difference Ve between the semiconductor wafer W (mounting table 11) and the conductive member 27 and the potential difference Vg between the conductive member 27 and the ground 22 (conductive member 60) is constant. From Equation (3), the potential difference Ve between the semiconductor wafer W (mounting table 11) and the conductive member 27 is proportional to the capacitance ratio (Cg / (Cg + Ce)). The axis used the capacitance ratio (Cg / (Cg + Ce)) instead of the potential difference Ve.

  According to the simulation results of the present inventors, when the potential difference Ve formed between the semiconductor wafer W and the conductive member 27 is increased (the capacitance ratio (Cg / (Cg + Ce)) is increased), the semiconductor wafer The occurrence of deposition on the lower surface of the peripheral edge of W was reduced, and the incidence angle of ions I inclined toward the center of the semiconductor wafer W (incident angle> 90 °). Conversely, if the potential difference Ve formed between the semiconductor wafer W and the conductive member 27 is reduced (capacitance ratio (Cg / (Cg + Ce)) is reduced), the depletion on the lower surface of the peripheral edge of the semiconductor wafer W is reduced. The occurrence of the position increased, and there was a tendency that the incident angle of the ions I was inclined (incident angle <90 °) in the direction from the center of the semiconductor wafer W to the outside.

  Further, in order to more easily change the potential difference Ve formed between the semiconductor wafer W and the conductive member 27, the insulating member 26 is insulated from the mounting table 11 like a focus ring 25c shown in FIG. The electrically conductive member 27 may be electrically connected to the ground 22 through the variable capacitor 65.

  Even in the focus ring 25c, as in the focus ring 25b described with reference to FIGS. 7 and 8, a potential difference Ve is generated between the semiconductor wafer W (mounting table 11) and the conductive member 27 during plasma processing. A potential difference Vg is generated between the conductive member 27 and the ground 22 (conductive member 60). According to the focus ring 25c, the capacitance Cg between the conductive member 27 and the ground 22 can be changed by operating the variable capacitor 65, and accordingly, the semiconductor wafer W (mounting table 11). And the potential difference Ve between the conductive member 27 and the conductive member 27 can be easily changed. Thus, by changing the potential difference Ve formed between the semiconductor wafer W and the conductive member 27, the collision amount of the ions I against the lower surface of the peripheral edge of the semiconductor wafer W can be easily adjusted.

  Further, in order to change the potential difference Ve formed between the semiconductor wafer W and the conductive member 27, the insulating member 26 is insulated from the mounting table 11 like a focus ring 25d shown in FIG. The variable DC power supply 66 may be electrically connected to the conductive member 27.

  Even in the focus ring 25d, the potential difference Ve is generated between the semiconductor wafer W (mounting table 11) and the conductive member 27 during the plasma processing, similarly to the focus ring 25b described above with reference to FIGS. A potential difference Vg is generated between the conductive member 27 and the ground 22 (conductive member 60). According to the focus ring 25d, when the variable DC power supply 66 is operated, the potential difference Vg between the conductive member 27 and the ground 22 can be shifted up and down in the figure as shown in FIG. When the potential difference Vg is shifted downward in the drawing (in the case of the alternate long and short dash line 27 ′ in FIG. 13), the potential difference Ve between the semiconductor wafer W (mounting table 11) and the conductive member 27 becomes small. . Conversely, when the potential difference Vg is shifted upward in the drawing (in the case of the two-dot chain line 27 ′ in FIG. 13), the potential difference Ve between the semiconductor wafer W (mounting table 11) and the conductive member 27 is growing. In this way, by operating the variable DC power supply 66 connected to the conductive member 27, the potential difference Ve between the semiconductor wafer W (mounting table 11) and the conductive member 27 can be easily changed. .

  The focus rings 27, 27 a, 27 b, 27 c, and 27 d described above are all disposed below the outer ring portion 30 disposed on the outer periphery of the semiconductor wafer W on the mounting table 11 and the periphery of the semiconductor wafer W. Although the inner ring portion 31 thus formed is integrally formed as the conductive member 27, the outer ring portion 30 and the inner ring portion 31 may be configured as separate members. Further, when configured as separate members, the outer ring portion 30 and the inner ring portion 31 may be electrically connected to each other or may be electrically insulated from each other.

  In the focus ring 25e shown in FIG. 14, an outer ring portion 30 disposed on the outer periphery of the semiconductor wafer W on the mounting table 11 and an inner ring portion 31 disposed below the peripheral edge of the semiconductor wafer W are different from each other. It is configured as a member, and the outer ring portion 30 and the inner ring portion 31 are electrically insulated from each other. In the focus ring 25e, the outer ring portion 30 is placed on the mounting table 11 in an electrically conductive state. On the other hand, since the insulating member 26 is interposed between the inner ring portion 31 and the outer ring portion 30 and the mounting table 11, the inner ring portion 31 is electrically connected to the outer ring portion 30 and the mounting table 11. Insulated.

  In the plasma processing 1 having the focus ring 25e shown in FIG. 14, during the plasma processing, the outer ring portion 30 is always at the same potential as the mounting table 11, and there is no gap between the semiconductor wafer W and the outer ring portion 30. Although the potential difference does not occur, since the insulating member 26 is interposed between the inner ring portion 31 and the mounting table 11, the impedance with respect to the high frequency power applied to the mounting table 11 is increased. A potential difference Ve is generated only between the ring portion 31 and the ring portion 31. For this reason, an electric field for accelerating the ions I in the plasma toward the lower surface of the peripheral edge of the semiconductor wafer W is formed between the lower surface of the peripheral edge of the semiconductor wafer W and the upper surface of the inner ring portion 31. It is possible to reduce the occurrence of deposition on the lower surface of the peripheral edge portion. In addition, in the focus ring 25e shown in FIG. 14, since no potential difference is generated between the outer peripheral surface of the semiconductor wafer W and the inner peripheral surface of the outer ring portion 30, the ions I in the plasma are transferred to the semiconductor wafer W. Between the outer peripheral surface of the semiconductor wafer W and the inner peripheral surface 30 c of the outer ring portion 30, and thus the ions I that have passed down to the lower peripheral portion of the semiconductor wafer W collide with the lower surface of the peripheral portion of the semiconductor wafer W. As a result, the occurrence of deposition on the lower surface of the peripheral edge of the semiconductor wafer W can be further reduced.

  Further, FIG. 1 shows an example in which high-frequency power having a relatively high frequency for plasma generation is supplied to the shower head 40 (upper electrode) on the ceiling portion of the vacuum chamber 10, but as shown in FIG. A high-frequency power source 42 and a matching unit 41 that supply high-frequency power with a relatively high frequency for generation and a high-frequency power source 21 and a matching unit 20 that supply high-frequency power with a relatively low frequency for biasing are mounted on the mounting table 11. A connected configuration may be used.

  Further, according to the present invention, an appropriate support member that arranges the focus rings 25, 25 a, 25 b, 25 c, 25 d, and 25 e described above so as to surround the periphery of the semiconductor wafer W on the mounting table 11 in the processing chamber 10. This also applies to a focus ring component including In this case, examples of the support member that supports the focus rings 25, 25a, 25b, 25c, 25d, and 25e include the mounting table 11 and the exhaust ring 35. Moreover, you may utilize the 2nd electroconductive member 60 demonstrated in FIG. 7, and the 2nd insulating member 61 for a support member.

  The present invention can be used in the semiconductor device manufacturing industry.

It is explanatory drawing which shows schematic structure of the plasma processing apparatus which concerns on embodiment of this invention. It is the longitudinal cross-sectional view which expanded and showed the focus ring. It is explanatory drawing of the electric potential difference which arises between a semiconductor wafer (mounting base) and a conductive member. It is explanatory drawing of the electric field formed by the electrical potential difference between a semiconductor wafer and an electroconductive member. Relationship between the amount of polymer adhering to the lower surface of the peripheral edge of the semiconductor wafer (right vertical axis) and the incident angle of ions on the upper surface of the peripheral edge of the semiconductor wafer (left vertical axis) to the change in capacitance between the semiconductor wafer and the conductive member It is a graph which shows the simulation result of. It is the longitudinal cross-sectional view which expanded and showed the focus ring which formed the recessed part in the internal peripheral surface of the outer side ring part facing the outer peripheral surface of a semiconductor wafer. It is the longitudinal cross-sectional view which expanded and showed the focus ring which arrange | positioned the 2nd electroconductive member electrically connected to a ground with the insulating member (dielectric material) with respect to the electroconductive member. FIG. 8 is an explanatory diagram of a potential difference generated between a semiconductor wafer (mounting table) and a conductive member in the focus ring of FIG. 7. FIG. 8 is a graph showing changes in the potential of the semiconductor wafer, the conductive member, and the ground during plasma processing in the focus ring of FIG. 7. In the focus ring of FIG. 7, the polymer adhesion amount (right vertical axis) on the lower surface of the periphery of the semiconductor wafer and the semiconductor with respect to the change in potential difference (capacitance ratio (Cg / (Cg + Ce))) between the semiconductor wafer and the conductive member. It is a graph which shows the simulation result of the relationship of the incident angle (left vertical axis) of the ion in the peripheral part upper surface of a wafer. It is the longitudinal cross-sectional view which expanded and showed the focus ring which electrically connected the electroconductive member to the ground through the variable capacitor. It is the longitudinal cross-sectional view which expanded and showed the focus ring which electrically connected the variable direct-current power supply to the electroconductive member. 13 is a graph showing changes in potentials of a semiconductor wafer, a conductive member, and a ground during plasma processing in the focus ring of FIG. It is the longitudinal cross-sectional view which expanded and showed the focus ring of the structure by which the outer side ring part and the inner side ring part were electrically insulated from each other. It is explanatory drawing which shows schematic structure of the plasma processing apparatus which connected both the high frequency power source for plasma production, and the high frequency power source for bias to the mounting base.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Plasma processing apparatus 10 Processing chamber 11 Mounting stand 12 Insulating plate 15 Heat medium flow path 16 Gas flow path 29 Matching device 21 High frequency power supply 22 Ground (earth)
25 Focus ring 26 Ring-shaped insulating member 27 Conductive member 30 Outer ring portion 31 Inner ring portion 30a Inclined surface portion 30b Horizontal surface portion 35 Exhaust ring 40 Shower head 41 Matching device 42 High frequency power supply 45 Gas discharge hole 47 Gas diffusion gap 46 Gas Introduction unit 50 Gas supply pipe 51 Gas supply system 52 Mass flow controller 53 Process gas supply source

Claims (27)

A plasma processing apparatus for processing a substrate to be processed by placing the substrate to be processed on a mounting table disposed in the processing chamber and generating a plasma in the processing chamber by applying a high frequency voltage.
A focus ring arranged so as to surround the substrate to be processed placed on the mounting table;
The focus ring includes an outer ring portion made of a conductive material arranged on the outer periphery of the substrate to be processed placed on the mounting table, and a lower peripheral portion of the substrate to be processed placed on the mounting table. Provided with an inner ring portion made of a conductive material arranged at a predetermined interval,
The plasma processing apparatus, wherein the inner ring portion and the mounting table are electrically insulated. The plasma processing apparatus according to claim 1, wherein the outer ring part and the inner ring part are electrically connected, and the outer ring part and the mounting table are insulated from each other. The plasma processing apparatus according to claim 2, wherein an insulating member is disposed between the outer ring part and the inner ring part and the mounting table. The plasma processing apparatus according to claim 2, wherein the outer ring portion and the inner ring portion are integrally formed. The distance between the outer peripheral surface of the substrate to be processed placed on the mounting table and the inner peripheral surface of the focus ring facing the substrate is the upper surface of the inner ring portion and the substrate to be processed mounted on the mounting table. The plasma processing apparatus according to claim 4, wherein the plasma processing apparatus is wider than a distance from a lower surface of the peripheral portion of the substrate. The plasma processing apparatus according to claim 2, wherein the outer ring portion and the inner ring portion are electrically insulated from a ground. The plasma processing apparatus according to claim 6, wherein electrostatic capacity between the outer ring part and the inner ring part and the ground is variably configured. 8. The plasma processing apparatus according to claim 6, wherein a variable DC power source is electrically connected to the outer ring portion and the inner ring portion. The plasma processing apparatus according to claim 1, wherein the outer ring portion and the inner ring portion are electrically insulated. The plasma processing apparatus according to claim 9, wherein the outer ring portion is electrically connected to the mounting table. The upper surface of the outer ring portion is formed continuously on the outer side of the inclined surface portion and the inclined surface portion which is arranged around the substrate to be processed placed on the mounting table and gradually increases toward the outside. The plasma processing apparatus according to claim 1, further comprising a horizontal plane part. The plasma processing apparatus according to claim 1, wherein the conductive material constituting the outer ring portion and the inner ring portion is any one of Si, C, and SiC. In a plasma processing apparatus for processing a substrate to be processed by generating a plasma in the processing chamber by applying a high frequency voltage, the plasma processing apparatus is disposed so as to surround the substrate to be processed on a mounting table disposed in the processing chamber. A focus ring,
A predetermined interval is provided below the outer ring portion made of a conductive material disposed on the outer periphery of the substrate to be processed placed on the mounting table, and below the peripheral portion of the substrate to be processed placed on the mounting table. It has an inner ring part made of a conductive material that is placed open,
The focus ring, wherein the inner ring portion and the mounting table are electrically insulated. The outer ring portion and the inner ring portion are electrically connected, and include an insulating member for insulating between the outer ring portion and the inner ring portion and the mounting table. Item 14. The focus ring according to Item 13. The focus ring according to claim 14, wherein the outer ring portion and the inner ring portion are integrally formed. The focus ring according to claim 15, wherein a concave portion is formed on an inner peripheral surface facing an outer peripheral surface of the substrate to be processed placed on the mounting table. The focus ring according to any one of claims 14 to 16, further comprising a capacitance changing means for changing a capacitance between the outer ring portion and the inner ring portion and the ground. The focus ring according to any one of claims 14 to 17, further comprising a variable DC power supply electrically connected to the outer ring portion and the inner ring portion. The focus ring according to claim 13, further comprising an insulating member that electrically insulates the outer ring portion and the inner ring portion. The focus ring according to claim 19, wherein the outer ring part is electrically connected to the mounting table. The upper surface of the outer ring portion is continuously formed on the outer side of the inclined surface portion and the inclined surface portion which is disposed around the substrate to be processed placed on the mounting table and gradually increases toward the outside. The focus ring according to any one of claims 13 to 20, further comprising a horizontal plane portion. The focus ring according to any one of claims 13 to 21, wherein the conductive material constituting the outer ring portion and the inner ring portion is any one of Si, C, and SiC. A focus ring according to any one of claims 13 to 22, and a support member for arranging the focus ring so as to surround the periphery of the substrate to be processed on the mounting table in the processing chamber. , Focus ring parts. A plasma processing method of processing a substrate to be processed by placing the substrate to be processed on a mounting table disposed in the processing chamber and generating a plasma in the processing chamber by applying a high frequency voltage.
By forming an electric field for accelerating the ions generated by the plasma toward the lower surface of the peripheral portion of the substrate to be processed, the ions are generated below the peripheral portion of the substrate to be processed placed on the mounting table. A plasma processing method characterized by causing a collision with the lower surface of the peripheral edge of the substrate. The electric field is formed by placing an inner ring portion made of a conductive material at a predetermined interval below the periphery of the substrate to be processed placed on the mounting table, and placing the inner ring portion between the substrate to be processed and the inner ring portion. The plasma processing method according to claim 24, wherein the plasma processing method is formed by applying a potential difference. 26. The plasma processing method according to claim 24, wherein the amount of collision of ions with the lower surface of the peripheral edge of the substrate to be processed is adjusted by changing the strength of the electric field. The equipotential surface in the electric field is rough outside the outer peripheral surface of the substrate to be processed placed on the mounting table, and densely below the peripheral edge of the substrate to be processed placed on the mounting table. The plasma processing method according to any one of claims 24 to 26, wherein:

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