TWI411034B - A plasma processing apparatus and a method and a focusing ring - Google Patents
A plasma processing apparatus and a method and a focusing ring Download PDFInfo
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Abstract
Description
本發明係有關對例如半導體晶圓等被處理基板，施加蝕刻處理等電漿處理所需的電漿處理裝置與電漿處理方法，更且有關電漿處理裝置所使用之聚焦環和聚焦環零件。The present invention relates to a plasma processing apparatus and a plasma processing method required for applying a plasma treatment such as an etching process to a substrate to be processed, such as a semiconductor wafer, and more to a focus ring and a focus ring part used in the plasma processing apparatus. .
先前以來，使用藉由賦予高頻電壓所產生之電漿，來進行蝕刻等電漿處理的電漿處理裝置，通常使用於例如半導體裝置中細微之電路的製造工程等。該電漿處理裝置，係在內部被氣密性密封的處理室內配置半導體晶圓，藉由賦予高頻電壓來在處理室內產生電漿，將此電漿作用於半導體晶圓，施加蝕刻等電漿處理。Conventionally, a plasma processing apparatus that performs plasma processing such as etching by applying plasma generated by a high-frequency voltage is generally used, for example, in a manufacturing process of a fine circuit in a semiconductor device. In the plasma processing apparatus, a semiconductor wafer is disposed in a processing chamber that is hermetically sealed inside, and a plasma is generated in the processing chamber by applying a high-frequency voltage, and the plasma is applied to the semiconductor wafer to apply etching and the like. Slurry treatment.
此種電漿處理裝置中，係包圍半導體晶圓的周圍，而配置有叫做聚焦環的環狀構件。此聚焦環在例如絕緣膜之蝕刻等情況下，係以矽等導電性材料所構成；其目的為封入電漿，和緩和半導體晶圓面內之偏壓電位之表面效果所造成的不連續性，使得在半導體晶圓之中央與周邊部，同樣可以進行平均且良好的處理。In such a plasma processing apparatus, an annular member called a focus ring is disposed to surround a periphery of a semiconductor wafer. The focus ring is made of a conductive material such as tantalum in the case of etching of an insulating film or the like; the purpose is to encapsulate the plasma and to alleviate the discontinuity caused by the surface effect of the bias potential in the plane of the semiconductor wafer. The properties are such that average and good processing can be performed in the center and peripheral portions of the semiconductor wafer.
又，為了藉由此聚焦環來提高半導體晶圓之周邊部的處理平均性，本發明者等揭示有以包圍半導體晶圓之傾斜面部，和連續於此傾斜面部之外側而形成的水平面部，來構成聚焦環的上面(參考專利文件1)。In order to improve the processing average of the peripheral portion of the semiconductor wafer by the focus ring, the inventors of the present invention have disclosed a horizontal surface formed by surrounding the inclined surface of the semiconductor wafer and extending outside the inclined surface. To form the top of the focus ring (refer to Patent Document 1).
〔專利文件1〕日本特開2005－277369號公報(例如第1圖、第2圖)[Patent Document 1] Japanese Laid-Open Patent Publication No. 2005-277369 (for example, Fig. 1 and Fig. 2)
上述專利文件1之發明，係在聚焦環之上面形狀下工夫，藉此抑制半導體晶圓之周邊部的電場傾斜，謀求蝕刻處理之平均性，同時在半導體晶圓周邊與聚焦環內周面之間形成電位差，藉此抑制電漿對半導體晶圓之周邊部下方的繞入。The invention of the above Patent Document 1 is based on the shape of the upper surface of the focus ring, thereby suppressing the electric field tilt at the peripheral portion of the semiconductor wafer, and achieving the averaging of the etching process while being between the periphery of the semiconductor wafer and the inner peripheral surface of the focus ring. A potential difference is formed, thereby suppressing the plasma from being wound under the peripheral portion of the semiconductor wafer.
然而即使如此藉由半導體晶圓周邊與聚焦環內周面之間的電位差，來抑制電漿繞入，半導體晶圓之周邊部下面也會附著有CF系聚合物，亦即所謂的堆積情況。However, even if the plasma is prevented from being wound by the potential difference between the periphery of the semiconductor wafer and the inner peripheral surface of the focus ring, the CF-based polymer adheres to the lower surface of the peripheral portion of the semiconductor wafer, that is, the so-called deposition.
本發明之目的，係在將半導體晶圓等被處理基板做電漿處理時，減少周邊部下面之堆積的產生。It is an object of the present invention to reduce the occurrence of deposition under the peripheral portion when the substrate to be processed such as a semiconductor wafer is subjected to plasma treatment.
本發明者等，針對上述般在被處理基板之周邊部下面所產生之堆積的主因，進行各種檢討。結果發現如專利文件1般在半導體晶圓周邊與聚焦環內周面之間賦予電位差的情況下，電漿中之離子在通過半導體晶圓周邊與聚焦環內周面之間的空隙時，會藉由兩者之電位差而向著半導體晶圓周邊或聚焦環內周面的任一邊被拉近；故雖然不會到達被處理基板之周邊部下方，但是CF系聚合物等不具有電荷之電漿產生物，會依原樣通過半導體晶圓周邊與聚焦環內周面之間的空隙，而到達被處理基板之周邊部下方，這就成為堆積的主因。又另一方面，為了抑制此種在被處理基板之周邊部下面所產生的堆積，得到要使電漿中之離子到達被處理基板之周邊部下方為止，使該離子衝撞被處理基板之周邊部下面者較為有效的結論。The inventors of the present invention conducted various reviews on the main causes of the deposition occurring on the lower surface of the peripheral portion of the substrate to be processed as described above. As a result, it has been found that, as in Patent Document 1, when a potential difference is applied between the periphery of the semiconductor wafer and the inner peripheral surface of the focus ring, ions in the plasma pass through the gap between the periphery of the semiconductor wafer and the inner peripheral surface of the focus ring. The potential difference between the two is toward the periphery of the semiconductor wafer or the inner peripheral surface of the focus ring. Therefore, although it does not reach below the peripheral portion of the substrate to be processed, it does not have a charge plasma such as a CF polymer. The generated material passes through the gap between the periphery of the semiconductor wafer and the inner peripheral surface of the focus ring as it is, and reaches the lower portion of the peripheral portion of the substrate to be processed, which is the main cause of the deposition. On the other hand, in order to suppress such accumulation on the lower surface of the peripheral portion of the substrate to be processed, it is possible to cause the ions in the plasma to reach the periphery of the peripheral portion of the substrate to be processed, and to cause the ions to collide with the peripheral portion of the substrate to be processed. The following are more effective conclusions.
本發明係依據上述結論而創造者。亦即若依本發明，則提供一種電漿處理裝置，係在配置於處理室內之放置台上放置被處理基板，藉由賦予高頻電波而在處理室內產生電漿，來處理被處理基板；其特徵係具備包圍上述放置於放置台上之被處理基板周圍來配置的聚焦環；上述聚焦環，具備配置於上述放置於放置台上之被處理基板周圍外側而由導電性材料所構成的外側環部，和在上述放置於放置台上之被處理基板周邊部下方隔開特定間隔來配置，且由導電性材料所構成的內側環部；上述內側環部與上述放置台之間，係電氣絕緣。The present invention has been made in light of the above conclusions. That is, according to the present invention, there is provided a plasma processing apparatus for placing a substrate to be processed on a placing table disposed in a processing chamber, and generating a plasma in the processing chamber by applying high-frequency radio waves to process the substrate to be processed; The present invention is characterized in that it includes a focus ring that surrounds the substrate to be processed placed on the placement stage, and the focus ring includes an outer side that is disposed on the outer side of the substrate to be processed placed on the placement table and is made of a conductive material. a ring portion and an inner ring portion which is disposed at a predetermined interval below the peripheral portion of the substrate to be processed placed on the placing table and is made of a conductive material; and the inner ring portion and the placing table are electrically connected insulation.
此電漿處理裝置中，例如上述外側環部與上述內側環部係電氣導通，而上述外側環部與上述放置台之間則絕緣。此種情況下，上述外側環部及上述內側環部，與上述放置台之間亦可配置有絕緣構件。又，上述外側環部與上述內側環部亦可一體形成。又，上述放置於放置台上之被處理基板之外周面，和與其相對之上述聚焦環之內周面的間隔，可以比上述內側環部之上面與上述放置於放置台上之被處理基板之周邊部下面的間隔要寬。In the plasma processing apparatus, for example, the outer ring portion and the inner ring portion are electrically connected, and the outer ring portion and the placing table are insulated from each other. In this case, an insulating member may be disposed between the outer ring portion and the inner ring portion and the placing table. Further, the outer ring portion and the inner ring portion may be integrally formed. Further, the outer circumferential surface of the substrate to be processed placed on the placing table and the inner circumferential surface of the focusing ring opposed thereto may be larger than the upper surface of the inner ring portion and the substrate to be processed placed on the placing table. The spacing below the perimeter is wider.
又，此電漿處理裝置中，上述外側環部及上述內側環部，可對接地成電氣絕緣。此種情況下，上述外側環部及上述內側環部，對接地之間的靜電容量可構成為可變的。又，上述外側環部及上述內側環部，可電氣連接於可變直流電源。Further, in the plasma processing apparatus, the outer ring portion and the inner ring portion may be electrically insulated from the ground. In this case, the electrostatic capacitance between the outer ring portion and the inner ring portion to the ground may be variable. Further, the outer ring portion and the inner ring portion may be electrically connected to a variable DC power source.
又，此電漿處理裝置中，例如可使上述外側環部與上述內側環部成電氣絕緣。此種情況下，上述外側環部與上述放置台可電氣導通。Further, in the plasma processing apparatus, for example, the outer ring portion and the inner ring portion may be electrically insulated from each other. In this case, the outer ring portion and the placement table can be electrically connected.
另外，上述外側環部之上面，可以具有配置在上述放置於放置台上之被處理基板周圍，且向著外側逐漸變高的傾斜面部；和連續於上述傾斜面部之外側而形成的水平面部。又，構成上述外側環部與上述內側環部的導電性材料，可以是矽、碳、碳化矽的任一種。Further, the upper surface of the outer ring portion may have an inclined surface portion that is disposed around the substrate to be processed placed on the placing table and gradually increases toward the outside, and a horizontal surface portion that is formed to extend outside the inclined surface portion. Further, the conductive material constituting the outer ring portion and the inner ring portion may be any of tantalum, carbon, and tantalum carbide.
又若依本發明，則提供一種聚焦環，係在藉由賦予高頻電波在處理室內產生電漿，來處理被處理基板之電漿處理裝置中，包圍配置於上述處理室內之放置台上的被處理基板周圍；其特徵係具備配置於上述放置於放置台上之被處理基板周圍外側而由導電性材料所構成的外側環部，和在上述放置於放置台上之被處理基板周邊部下方隔開特定間隔來配置，且由導電性材料所構成的內側環部；上述內側環部與上述放置台之間，係電氣絕緣。According to the present invention, a focus ring is provided in a plasma processing apparatus that processes a substrate to be processed by applying a high-frequency wave to generate plasma in a processing chamber, and surrounds a placement table disposed in the processing chamber. The periphery of the substrate to be processed is characterized in that it has an outer ring portion which is disposed on the outer side of the substrate to be processed placed on the placing table and is made of a conductive material, and is disposed below the peripheral portion of the substrate to be processed placed on the placing table. An inner ring portion that is disposed at a predetermined interval and is made of a conductive material; and the inner ring portion is electrically insulated from the placing table.
此聚焦環中，例如上述外側環部與上述內側環部係電氣導通；上述外側環部及上述內側環部，與上述放置台之間係配置有絕緣構件。此種情況下，上述外側環部與上述內側環部可一體形成。又，與上述放置於放置台上之被處理基板之外周面相對的內周面，亦可形成有凹部。In the focus ring, for example, the outer ring portion is electrically connected to the inner ring portion, and the outer ring portion and the inner ring portion are disposed with an insulating member between the outer ring portion and the placing portion. In this case, the outer ring portion and the inner ring portion may be integrally formed. Further, a concave portion may be formed on the inner circumferential surface of the outer surface of the substrate to be processed placed on the placing table.
又，此聚焦環中，可以具有靜電容量可變手段，用以使上述外側環部及上述內側環部與接地之間的靜電容量為可變。又，可具備電氣連接於上述外側環部及上述內側環部的可變直流電源。Further, the focus ring may have a capacitance changing means for making the capacitance between the outer ring portion and the inner ring portion and the ground variable variable. Further, a variable DC power source electrically connected to the outer ring portion and the inner ring portion may be provided.
又，此聚焦環中，例如具備將上述外側環部與上述內側環部電氣絕緣的絕緣構件。此種情況下，上述外側環部係設置為電氣導通於上述放置台。Further, the focus ring includes, for example, an insulating member that electrically insulates the outer ring portion from the inner ring portion. In this case, the outer ring portion is provided to be electrically connected to the placement table.
另外，此聚焦環中，上述外側環部之上面，可具有配置在上述放置於放置台上之被處理基板周圍，且向著外側逐漸變高的傾斜面部；和連續於上述傾斜面部之外側而形成的水平面部。又，構成上述外側環部與上述內側環部的導電性材料，可以是矽、碳、碳化矽的任一種。Further, in the focus ring, the upper surface of the outer ring portion may have an inclined surface portion disposed around the substrate to be processed placed on the placing table and gradually increasing toward the outside; and may be formed continuously outside the inclined surface portion Horizontal face. Further, the conductive material constituting the outer ring portion and the inner ring portion may be any of tantalum, carbon, and tantalum carbide.
又若依本發明，則提供一種聚焦環零件，其特徵係由申請專利範圍第13項至第22項之任一項所記載的聚焦環，和在上述處理室中包圍上述放置台上之被處理基板，來配置上述聚焦環的支撐構件所構成。According to the present invention, there is provided a focus ring member characterized by the focus ring of any one of claims 13 to 22, and the circumstance surrounding the placement table in the processing chamber. The substrate is processed to configure the support member of the focus ring.
又若依本發明，則提供一種電漿處理方法，係在配置於處理室內之放置台上放置被處理基板，藉由賦予高頻電波而在處理室內產生電漿，來處理被處理基板；其特徵係在上述配置於處理室內之放置台的周邊部下方，將上述電漿所產生之離子向著被處理基板之周邊部下方加速來形成電場，藉此使離子衝撞被處理基板的周邊部下面。According to the present invention, there is provided a plasma processing method for placing a substrate to be processed on a placing table disposed in a processing chamber, and generating a plasma in the processing chamber by applying high-frequency waves to process the substrate to be processed; The feature is that the ions generated by the plasma are accelerated below the peripheral portion of the substrate to form an electric field below the peripheral portion of the placement table disposed in the processing chamber, thereby causing ions to collide with the lower surface of the peripheral portion of the substrate to be processed.
此電漿處理方法中，上述電場，係例如在在上述放置於放置台上之被處理基板下方，隔開特定間隔來配置由導電性材料所構成的內側環部，然後藉由在被處理基板與內側環部之間賦予電位差來形成。又，可藉由改變上述電場強度，來調整離子對被處理基板之周邊部下面的衝撞量。更且，上述電場中之等電位面，可以從上述放置於放置台上之被處理基板的外周面起算在外側較疏，而在上述放置於放置台上之被處理基板的周邊部下方較密。In the plasma processing method, for example, the inner ring portion made of a conductive material is disposed under a predetermined interval on the substrate to be processed placed on the placing table, and then the substrate is processed on the substrate to be processed. A potential difference is formed between the inner ring portion and the inner ring portion. Further, by changing the electric field intensity, the amount of collision of ions on the lower surface of the peripheral portion of the substrate to be processed can be adjusted. Further, the equipotential surface of the electric field can be made thinner from the outer peripheral surface of the substrate to be processed placed on the placing table, and densely disposed below the peripheral portion of the substrate to be processed placed on the placing table. .
若依本發明，則藉由使電漿中之離子到達被處理基板之周邊部下方為止，來衝撞被處理基板之周邊部下面，可以比先前減少被處理基板之周邊部下面的堆積產生。According to the present invention, by causing ions in the plasma to reach below the peripheral portion of the substrate to be processed and colliding with the lower surface of the peripheral portion of the substrate to be processed, it is possible to reduce the accumulation of the underside of the peripheral portion of the substrate to be processed.
以下參考圖示，說明本發明之理想實施方式。第1圖，係表示本發明之實施方式中電漿處理裝置1之概略構造的說明圖。第2圖，係放大表示此電漿處理裝置1所具備之聚焦環25的縱剖面圖。另外本說明書及圖示中，針對具有實質上相同功能構造的構成要素，係附加相同符號來省略重複說明。The preferred embodiments of the present invention are described below with reference to the drawings. Fig. 1 is an explanatory view showing a schematic structure of a plasma processing apparatus 1 in an embodiment of the present invention. Fig. 2 is an enlarged longitudinal sectional view showing the focus ring 25 included in the plasma processing apparatus 1. In the present specification and the drawings, the same reference numerals are given to components having substantially the same functional configurations, and the overlapping description will be omitted.
氣密性構成之圓筒形狀的處理室10內部，配置有用以放置被處理基板亦即半導體晶圓W，並兼做為下部電極的放置台11。此等處理室10與放置台11，係例如以鋁等導電性材料所構成。只是放置台11係經由陶瓷等絕緣板12來被支撐於處理室10的底面上，而處理室10與放置台11為互相電氣絕緣的狀態。Inside the cylindrical processing chamber 10 having a hermetic structure, a placing table 11 for placing a semiconductor wafer W, which is a substrate to be processed, and also serving as a lower electrode is disposed. These processing chambers 10 and the placing table 11 are made of, for example, a conductive material such as aluminum. Only the placing table 11 is supported on the bottom surface of the processing chamber 10 via the insulating plate 12 such as ceramics, and the processing chamber 10 and the placing table 11 are electrically insulated from each other.
放置台11，具備用以吸附保持放在上面之半導體晶圓W的未圖示靜電吸盤。又，放置台11內部設置有熱媒體流路15，用以使做為溫度控制用熱媒體的絕緣性流體循環；和氣體流路16，用以將氦氣等溫度控制用氣體供給到半導體晶圓W背面。如此一來，藉由使被控制在特定溫度之絕緣性流體循環於熱媒體流路15內，來將放置台11控制為特定溫度；且在此放置台11與半導體晶圓W的背面之間，經由氣體流路16供給溫度控制用氣體來促進此等之間的熱交換，則可將半導體晶圓W以高精確度且有效率地控制在特定溫度。The placing table 11 is provided with an electrostatic chuck (not shown) for sucking and holding the semiconductor wafer W placed thereon. Further, a heat medium flow path 15 is provided inside the placing table 11 for circulating an insulating fluid as a heat medium for temperature control, and a gas flow path 16 for supplying a temperature control gas such as helium gas to the semiconductor crystal. Round W back. In this way, the placement stage 11 is controlled to a specific temperature by circulating an insulating fluid controlled at a specific temperature in the thermal medium flow path 15; and between the placement stage 11 and the back surface of the semiconductor wafer W By supplying the temperature control gas through the gas flow path 16 to promote heat exchange therebetween, the semiconductor wafer W can be controlled to a specific temperature with high accuracy and efficiency.
放置台11，係經由匹配器20連接於偏壓用高頻電源(RF電源)21。從高頻電源21對放置台11賦予特定頻率的高頻電壓。另一方面，處理室10係對接地(Earth)22電氣導通。The placing table 11 is connected to a bias high frequency power source (RF power source) 21 via a matching unit 20. A high frequency voltage of a specific frequency is applied to the placing table 11 from the high frequency power source 21. On the other hand, the processing chamber 10 is electrically connected to the ground 22.
在處理室10之內部，放置台11之上面的周圍，係包圍放置於放置台11上的半導體晶圓W周圍，而配置有聚焦環25。此聚焦環25，係由直接放在放置台11上之環狀絕緣構件26，和配置於此絕緣構件26上方之環狀導電性構件27來構成。絕緣構件26，係由石英、鋁氧等陶瓷、Bespel(註冊商標)樹脂等絕緣材料(介電質)所構成。導電性構件27，係例如由矽(為了產生導電性而摻雜了硼的矽)、碳、碳化矽等導電性材料所構成。Inside the processing chamber 10, the periphery of the upper surface of the placing table 11 surrounds the semiconductor wafer W placed on the placing table 11, and a focus ring 25 is disposed. The focus ring 25 is composed of an annular insulating member 26 placed directly on the placing table 11, and an annular conductive member 27 disposed above the insulating member 26. The insulating member 26 is made of a ceramic such as quartz or aluminum oxide or an insulating material (dielectric) such as Bespel (registered trademark) resin. The conductive member 27 is made of, for example, a conductive material such as ruthenium (a ruthenium doped with boron for conductivity), carbon, or ruthenium carbide.
如第2圖所示，導電性構件27係具備配置在放置於放置台11上之半導體晶圓W周圍外側的外側環部30，和在放置於放置台11上之半導體晶圓W之週邊部下方，隔開特定間隔來配置之環狀的內側環部31。圖示之例子中，外側環部30與環狀之內側環部31，係與導電性材料所構成之導電性構件27一體形成，故外側環部30與內側環部31係電氣導通的狀態。只是因為如上所述，環狀之導電性構件27與放置台11之間介入有絕緣構件26，故外側環部30與內側環部31對放置台11係電氣絕緣。另外將外側環部30與內側環部31之邊界，在第2圖中記載為虛線31’。如此邊界31’所示，一體形成之導電性構件27中，配置於放置在放置台11上之半導體晶圓W之周圍外側的部分，是外側環部30；在半導體晶圓W之週邊部下方隔開特定間隔而配置的部分，係環狀之內側環部31。As shown in Fig. 2, the conductive member 27 includes an outer ring portion 30 disposed outside the periphery of the semiconductor wafer W placed on the placing table 11, and a peripheral portion of the semiconductor wafer W placed on the placing table 11. The annular inner ring portion 31 is disposed at a predetermined interval. In the illustrated example, the outer ring portion 30 and the annular inner ring portion 31 are integrally formed with the conductive member 27 made of a conductive material, so that the outer ring portion 30 and the inner ring portion 31 are electrically connected to each other. However, since the insulating member 26 is interposed between the annular conductive member 27 and the placing table 11 as described above, the outer ring portion 30 and the inner ring portion 31 are electrically insulated from the placing table 11. Further, the boundary between the outer ring portion 30 and the inner ring portion 31 is indicated by a broken line 31' in Fig. 2 . As shown in the boundary 31', the portion of the integrally formed conductive member 27 disposed outside the periphery of the semiconductor wafer W placed on the placing table 11 is the outer ring portion 30; below the peripheral portion of the semiconductor wafer W The portion disposed at a predetermined interval is an annular inner ring portion 31.
又，如此對放置台11絕緣之環狀的導電性構件27，在處理室10內部除了絕緣構件26之外並無電氣接觸。因此外側環部30與內側環部31對接地22，也是成電氣性漂浮狀態。Further, the annular conductive member 27 insulated from the placing table 11 does not have electrical contact with the inside of the processing chamber 10 except for the insulating member 26. Therefore, the outer ring portion 30 and the inner ring portion 31 face the ground 22 and are also electrically floating.
外側環部30上面，係由配置在放置於放置台11上之半導體晶圓W周圍，且向著外側逐漸變高的傾斜面部30a；和連續於此傾斜面部30a之外側而形成的水平面部30b來形成。水平面部30b，係設定為比放置於放置台11上之半導體晶圓W的上面要高；傾斜面部30a，其內緣係與放置於放置台11上之半導體晶圓W的上面幾乎一樣高度，而設定為朝外側逐漸升高到水平面部30b的高度為止。The upper surface of the outer ring portion 30 is provided by an inclined surface portion 30a disposed around the semiconductor wafer W placed on the placing table 11 and gradually increasing toward the outside; and a horizontal surface portion 30b formed continuously outside the inclined surface portion 30a. form. The horizontal surface portion 30b is set to be higher than the upper surface of the semiconductor wafer W placed on the placing table 11; the inclined surface portion 30a has an inner edge which is almost the same height as the upper surface of the semiconductor wafer W placed on the placing table 11, It is set to gradually rise to the outside to the height of the horizontal surface portion 30b.
又，於處理室10內部，在聚焦環25外側，設置有形成了多數排氣孔的環狀排氣環35。構成為藉著經由此排氣環35而連接於排氣埠36之排氣系統37的真空泵等，來進行處理室10內之處理空間的真空排氣。Further, inside the processing chamber 10, an annular exhaust ring 35 in which a plurality of exhaust holes are formed is provided outside the focus ring 25. The vacuum evacuation of the processing space in the processing chamber 10 is performed by a vacuum pump or the like connected to the exhaust system 37 of the exhaust port 36 via the exhaust ring 35.
另一方面，放置台11上方之處理室10的天花板部分，有蓮蓬頭40與放置台11平行相對來設置；此等放置台11及蓮蓬頭40，係工作為一對電極(上部電極與下部電極)。又，此蓮蓬頭40係經由匹配器41連接於電漿產生用之高頻電源42。On the other hand, in the ceiling portion of the processing chamber 10 above the stage 11, the shower head 40 is disposed in parallel with the placing table 11; the placing table 11 and the shower head 40 operate as a pair of electrodes (upper electrode and lower electrode) . Further, the shower head 40 is connected to the high-frequency power source 42 for plasma generation via the matching unit 41.
蓮蓬頭40，係於其下面設置有多數氣體吐出孔45。蓮蓬頭40內部形成有氣體擴散用空隙47，其上部具有氣體導入部46。此氣體導入部46，係連接於氣體供給配管50，而此氣體供給配管50之另一邊則連接於氣體供給系統51。此氣體供給系統51，係由用以控制氣體流量的流量控制器(MFC)52，和用以供給例如蝕刻用氣體等的處理氣體供給源53等所構成。The shower head 40 is provided with a plurality of gas discharge holes 45 underneath. A gas diffusion gap 47 is formed in the shower head 40, and a gas introduction portion 46 is formed in the upper portion thereof. The gas introduction portion 46 is connected to the gas supply pipe 50, and the other side of the gas supply pipe 50 is connected to the gas supply system 51. The gas supply system 51 is composed of a flow rate controller (MFC) 52 for controlling the flow rate of the gas, and a processing gas supply source 53 for supplying, for example, an etching gas or the like.
其次說明如上述所構成之電漿處理裝置1其電漿處理的手續。Next, the procedure of the plasma treatment of the plasma processing apparatus 1 constructed as described above will be described.
首先將設置於處理室10之未圖示閘閥打開，經由鄰接此閘閥而配置之負載固定室(未圖示)，以搬運機構(未圖示)將半導體晶圓W搬入處理室10內，放置於放置台11上。然後使搬運機構迴避到處理室10外之後，關閉閘閥，將處理室10內做為密閉狀態。First, a gate valve (not shown) provided in the processing chamber 10 is opened, and a semiconductor wafer W is carried into the processing chamber 10 by a transport mechanism (not shown) via a load fixing chamber (not shown) disposed adjacent to the gate valve. On the placement table 11. Then, after the transport mechanism is evacuated to the outside of the processing chamber 10, the gate valve is closed, and the inside of the processing chamber 10 is sealed.
之後以排氣系統37之真空泵，透過排氣埠36將處理室10內排氣到特定真空度，並從處理氣體供給源53透過蓮蓬頭40來對處理室10內供給特定處理氣體。Thereafter, the inside of the processing chamber 10 is exhausted to a specific degree of vacuum through the exhaust port 36 by a vacuum pump of the exhaust system 37, and a specific processing gas is supplied into the processing chamber 10 from the processing gas supply source 53 through the shower head 40.
然後在此狀態下，從高頻電源21供給頻率比較低之偏壓用高頻電力，同時從高頻電源42供給頻率比較高之電漿產生用高頻電力，藉此如第2圖所示，在半導體晶圓W上方的處理室10內產生電漿P。如此一來，在半導體晶圓W上方產生之電漿P中的自由基分子或離子，會向著半導體晶圓W上面被拉近，藉由該等之作用來進行半導體晶圓W上面的電漿處理。Then, in this state, high-frequency power for bias voltage having a relatively low frequency is supplied from the high-frequency power source 21, and high-frequency power for plasma generation having a relatively high frequency is supplied from the high-frequency power source 42 as shown in FIG. A plasma P is generated in the processing chamber 10 above the semiconductor wafer W. As a result, the radical molecules or ions in the plasma P generated above the semiconductor wafer W are pulled closer to the semiconductor wafer W, and the plasma on the semiconductor wafer W is performed by the action of the semiconductor wafer W. deal with.
然後當特定之電漿處理結束後，則停止來自高頻電源21、42的高頻電力供給，藉此停止電漿處理，然後以與上述手續相反的手續，將半導體晶圓W搬出處理室10外。Then, after the specific plasma processing is completed, the supply of the high-frequency power from the high-frequency power sources 21 and 42 is stopped, thereby stopping the plasma processing, and then the semiconductor wafer W is carried out of the processing chamber 10 in the reverse procedure to the above procedure. outer.
進行此種電漿處理之際，此實施方式之電漿處理裝置1中，係如上所述，採用對放置台11經由絕緣性構件26配置有導電性構件27的聚焦環25，故如第3圖所示，半導體晶圓W(放置台11)與導電性構件27之間會是產生電位差Ve的狀態。此時若將半導體晶圓W與導電性構件27之間的靜電容量做為Ce，則電位差Ve會與靜電容量Ce成反比。In the plasma processing apparatus 1 of the present embodiment, as described above, the focus ring 25 in which the conductive member 27 is placed on the placing table 11 via the insulating member 26 is used. As shown in the figure, a potential difference Ve is generated between the semiconductor wafer W (the stage 11) and the conductive member 27. At this time, if the electrostatic capacitance between the semiconductor wafer W and the conductive member 27 is Ce, the potential difference Ve is inversely proportional to the electrostatic capacitance Ce.
又此電漿處理中，藉由在半導體晶圓W與導電性構件27之間產生電位差Ve，會在半導體晶圓W與導電性構件27之間，形成如第4圖所示的電場E。此電場E之等電位面e，係如第4圖所示，在半導體晶圓W之外周面與外側環部30之內周面30c之間幾乎為垂直方向，而在半導體晶圓W之週邊部下面與內側環部31上面之間，則幾乎為水平方向。藉由此種具有等電位面e之電場E的作用，在半導體晶圓W之外周面與外側環部30之內周面30c之間，可以將向著半導體晶圓W之表面而往下被拉近之電漿P中的離子I，往向著半導體晶圓W之外周面的方向加速；又在半導體晶圓W之週邊部下面與內側環部31上面之間，可以將電漿P中的離子I，往向著半導體晶圓W之週邊部下面的方向加速。In the plasma processing, by generating a potential difference Ve between the semiconductor wafer W and the conductive member 27, an electric field E as shown in Fig. 4 is formed between the semiconductor wafer W and the conductive member 27. The equipotential surface e of the electric field E is almost perpendicular to the outer peripheral surface of the semiconductor wafer W and the inner peripheral surface 30c of the outer ring portion 30 as shown in Fig. 4, and is surrounded by the semiconductor wafer W. Between the lower portion of the portion and the upper surface of the inner ring portion 31, it is almost horizontal. By the action of the electric field E having the equipotential surface e, the outer peripheral surface of the semiconductor wafer W and the inner peripheral surface 30c of the outer ring portion 30 can be pulled downward toward the surface of the semiconductor wafer W. The ions I in the plasma P are accelerated toward the outer circumferential surface of the semiconductor wafer W; and between the lower surface of the peripheral portion of the semiconductor wafer W and the upper surface of the inner ring portion 31, the ions in the plasma P can be I, accelerating in a direction toward the lower side of the peripheral portion of the semiconductor wafer W.
如此一來，在電漿處理中，藉由在導體晶圓W與導電性構件27之間之電位差Ve所形成的電場E作用，來使電漿中之離子I衝撞半導體晶圓W之外周面與周邊部下面，可藉此降低半導體晶圓W之外周面與周邊部下面的堆積產生。As a result, in the plasma processing, the ion I in the plasma collides with the outer surface of the semiconductor wafer W by the electric field E formed by the potential difference Ve between the conductor wafer W and the conductive member 27. Under the peripheral portion, the accumulation of the outer peripheral surface of the semiconductor wafer W and the underside of the peripheral portion can be reduced.
另外，為了減少半導體晶圓W之週邊部下面的堆積產生，在半導體晶圓W之外周面與外側環部30之內周面30c之間，並不是使電漿中之離子I全部衝撞半導體晶圓W的外周面，而必須使電漿中之離子I中最少一部份在半導體晶圓W之外周面與外側環部30之內周面30c之間依原樣通過下方，讓離子I通過到半導體晶圓W之週邊部下方為止。為了這麼做，要如第2圖所示，將放置於放置台11上之半導體晶圓W之外周面，和與其相對之外側環部30之內周面30c之間的間隔L1 ，形成為比內側環部31之上面與半導體晶圓W之週邊部下面的間隔L2 更寬。Further, in order to reduce the occurrence of deposition under the peripheral portion of the semiconductor wafer W, the ion I in the plasma is not completely collided with the semiconductor crystal between the outer peripheral surface of the semiconductor wafer W and the inner peripheral surface 30c of the outer ring portion 30. The outer peripheral surface of the circle W, and at least a part of the ions I in the plasma must pass under the outer peripheral surface of the semiconductor wafer W and the inner peripheral surface 30c of the outer ring portion 30 as it is, so that the ions I pass to The lower side of the peripheral portion of the semiconductor wafer W. In order to do so, as shown in Fig. 2, the interval L 1 between the outer peripheral surface of the semiconductor wafer W placed on the placing table 11 and the inner peripheral surface 30c of the outer ring portion 30 is formed as It is wider than the upper surface of the inner ring portion 31 and the space L 2 below the peripheral portion of the semiconductor wafer W.
藉由做為該構造，可以使第4圖所示之等電位面e彼此之間隔，在半導體晶圓W之外周面與外側環部30之內周面30c之間相對較疏，而在半導體晶圓W之週邊部下面與內側環部31上面之間相對較密。藉此，半導體晶圓W之外周面與外側環部30之內周面30c之間，可以使向著半導體晶圓W之外周面方向的加速較小，讓離子I通過到半導體晶圓W的周邊部下方為止。又另一方面，半導體晶圓W之週邊部下面與內側環部31上面之間，可以使向著半導體晶圓W之週邊部下面方向的加速較大，讓離子I衝撞半導體晶圓W週邊部下面，而確實降低半導體晶圓W之週邊部下面的堆積產生。With this configuration, the equipotential surfaces e shown in FIG. 4 can be spaced apart from each other, and the outer peripheral surface of the semiconductor wafer W and the inner peripheral surface 30c of the outer ring portion 30 are relatively thin, and the semiconductor is relatively thin. The lower surface of the peripheral portion of the wafer W and the upper surface of the inner ring portion 31 are relatively dense. Thereby, between the outer peripheral surface of the semiconductor wafer W and the inner peripheral surface 30c of the outer ring portion 30, the acceleration toward the outer peripheral surface of the semiconductor wafer W can be made small, and the ions I can pass to the periphery of the semiconductor wafer W. Until the bottom of the department. On the other hand, between the lower surface of the peripheral portion of the semiconductor wafer W and the upper surface of the inner ring portion 31, the acceleration toward the lower surface of the peripheral portion of the semiconductor wafer W can be made larger, and the ions I collide against the periphery of the semiconductor wafer W. However, the accumulation under the peripheral portion of the semiconductor wafer W is actually reduced.
另外，半導體晶圓W之外周面與外側環部30之內周面30c之間的間隔L1 ，以及內側環部31之上面與半導體晶圓W之週邊部下面的間隔L2 ，其理想範圍係依據半導體晶圓W與導電性構件27之間的電位差Ve大小，半導體晶圓W之直徑或厚度，內周面30c之高度等來變動，故無法一概決定之，但是例如半導體晶圓W之外周面與外側環部30之內周面30c之間的間隔L1 為1~5mm，理想為2~2.5mm。此間隔L1 若過小，則半導體晶圓W之外周面與外側環部30之間有時會產生異常放電；反之若過大，則後述半導體晶圓W上之電漿護套與外側環部30上之電漿護套會有不連續的可能性。Further, the peripheral surface 30 of the semiconductor wafer W than the outer peripheral surface of the ring between the interval L 1 between the portion 30c, and the inner upper ring portion 31 of the peripheral portion of the semiconductor wafer W is below that range over the interval L 2 Depending on the potential difference Ve between the semiconductor wafer W and the conductive member 27, the diameter or thickness of the semiconductor wafer W, the height of the inner peripheral surface 30c, and the like vary, and thus cannot be determined in general, but for example, the semiconductor wafer W The interval L 1 between the outer peripheral surface and the inner peripheral surface 30c of the outer ring portion 30 is 1 to 5 mm, preferably 2 to 2.5 mm. If the interval L 1 is too small, abnormal discharge may occur between the outer peripheral surface of the semiconductor wafer W and the outer ring portion 30. On the other hand, if it is too large, the plasma sheath and the outer ring portion 30 on the semiconductor wafer W will be described later. There is a possibility of discontinuity in the plasma jacket.
又，例如內側環部31之上面與半導體晶圓W之週邊部下面的間隔L2 為0.2~1mm，理想為0.2~0.5mm。此間隔L2 若過小，則內側環部31上面與半導體晶圓W的周邊部之間有時會產生異常放電；反之若過大，則半導體晶圓W之周邊部下面與內側環部31上面之間，無法使等電位面e彼此之間隔變密，則離子I無法往向著半導體晶圓W之週邊部下面的方向充分加速，而就無法充分降低半導體晶圓W之週邊部下面的堆積產生。又，隔著此間隔L2 而相對之內側環部31與半導體晶圓W之周邊部重疊的部分，其間隔L4 以0.05~0.5mm為佳。Further, for example, the distance L 2 between the upper surface of the inner ring portion 31 and the lower surface of the peripheral portion of the semiconductor wafer W is 0.2 to 1 mm, preferably 0.2 to 0.5 mm. If the interval L 2 is too small, an abnormal discharge may occur between the upper surface of the inner ring portion 31 and the peripheral portion of the semiconductor wafer W. On the other hand, if the distance L 2 is too large, the lower surface of the peripheral portion of the semiconductor wafer W and the upper portion of the inner ring portion 31 may be formed. When the equipotential surfaces e cannot be spaced apart from each other, the ions I cannot sufficiently accelerate toward the lower surface of the peripheral portion of the semiconductor wafer W, and the accumulation of the underside of the peripheral portion of the semiconductor wafer W cannot be sufficiently reduced. And, 2 and 31 to overlap the peripheral portion of the semiconductor wafer W relative to the inner portion of the ring portion L via this interval, an interval L 4 preferably to 0.05 ~ 0.5mm.
又，圖示之實施方式中，因為在電漿處理中半導體晶圓W與導電性構件27之間會產生電位差Ve，故在半導體晶圓W上形成之電漿護套，和在導電性構件27之外側環部30上所形成的電漿護套，厚度會有不同。然而就此實施方式之聚焦環25來說，係如上述般將外側環部30之上面，由向著外側逐漸變高之傾斜面部30a，和連續於此傾斜面部30a之外側而形成，且比半導體晶圓W之上面要高的水平面部30b來形成；故可緩和半導體晶圓W上與外側環部30上之邊界的電漿護套之厚度變化。藉此，可抑制半導體晶圓W之週邊部中電場的急遽變化，即使在半導體晶圓W之週邊部，也可將離子I對半導體晶圓W上面幾乎垂直拉近，而可提高電漿處理的平均性。又，以傾斜面部30a和水平面部30b來形成外側環部30的上面，可使聚焦環25本身的壽命長期化。Further, in the illustrated embodiment, since the potential difference Ve is generated between the semiconductor wafer W and the conductive member 27 in the plasma processing, the plasma sheath formed on the semiconductor wafer W, and the conductive member The plasma sheath formed on the outer side ring portion 30 has a different thickness. However, in the focus ring 25 of this embodiment, the upper surface of the outer ring portion 30 is formed by the inclined surface portion 30a which gradually becomes higher toward the outer side, and the outer side of the inclined surface portion 30a is formed as described above, and the semiconductor crystal is formed. The upper surface 30b of the upper side of the circle W is formed to be high; therefore, the thickness variation of the plasma sheath on the boundary between the semiconductor wafer W and the outer ring portion 30 can be alleviated. Thereby, the rapid change of the electric field in the peripheral portion of the semiconductor wafer W can be suppressed, and even in the peripheral portion of the semiconductor wafer W, the ion I can be nearly vertically drawn on the upper surface of the semiconductor wafer W, and the plasma treatment can be improved. Average. Further, the upper surface of the outer ring portion 30 is formed by the inclined surface portion 30a and the horizontal surface portion 30b, and the life of the focus ring 25 itself can be prolonged.
另外，形成於外側環部30上面之傾斜面部30a其高度方向的範圍h，係以半導體晶圓W之上面起算高度0~6mm為佳，更理想為2mm~6mm。又，傾斜面部30a之水平方向長度h’(半導體晶圓W之直徑方向長度)，以0.5~9mm之範圍為佳，更理想的範圍是1~6mm。另外傾斜面部30a之水平方向長度h’，依據半導體晶圓W之外周面與外側環部30之內周面30c之間的間隔L1 ，也可以是0。該情況就成為沒有傾斜面部30a之形狀，但是藉由調節間隔L1 也可抑制半導體晶圓W之週邊部中電場的急遽變化。Further, the range h of the inclined surface portion 30a formed on the upper surface of the outer ring portion 30 in the height direction is preferably 0 to 6 mm, more preferably 2 mm to 6 mm, from the upper surface of the semiconductor wafer W. Further, the horizontal length h' of the inclined surface portion 30a (the length in the radial direction of the semiconductor wafer W) is preferably in the range of 0.5 to 9 mm, and more preferably in the range of 1 to 6 mm. Further, the horizontal direction length h' of the inclined surface portion 30a may be 0 depending on the interval L 1 between the outer circumferential surface of the semiconductor wafer W and the inner circumferential surface 30c of the outer ring portion 30. This situation is not a shape of the inclined surface portion 30a, but by adjusting the interval L 1 between the peripheral portion can be suppressed rapid changes of the semiconductor wafer W in the electric field.
又，電漿處理中因為半導體晶圓W與導電性構件27之間產生有電位差Ve，故若內側環部31之內緣太接近放置台11，則兩者之間可能會產生異常放電。另一方面若使內側環部31之內緣太過遠離放置台11，則無法使內側環部31進入到半導體晶圓W之周邊部下方，上述使電漿中之離子I衝撞半導體晶圓W之周邊部下面就不成立，而無法充分得到所謂降低堆積的作用效果。因此第2圖所示之內側環部31之內緣與放置台11的間隔L3 ，係以0.5~1mm的範圍為佳。Further, in the plasma processing, since the potential difference Ve is generated between the semiconductor wafer W and the conductive member 27, if the inner edge of the inner ring portion 31 is too close to the placing table 11, abnormal discharge may occur between the two. On the other hand, if the inner edge of the inner ring portion 31 is too far away from the placing table 11, the inner ring portion 31 cannot be made to enter below the peripheral portion of the semiconductor wafer W, and the ion I in the plasma collides with the semiconductor wafer W. The lower part of the peripheral portion is not established, and the effect of reducing the accumulation is not sufficiently obtained. Therefore, the distance L 3 between the inner edge of the inner ring portion 31 and the placing table 11 shown in Fig. 2 is preferably in the range of 0.5 to 1 mm.
半導體晶圓W與導電性構件27之間的靜電容量Ce要到哪個程度，必須依實際的各個電漿處理裝置來決定。一般來說若靜電容量Ce較小，則形成於半導體晶圓W與導電性構件27之間的電位差Ve會變大。因此半導體晶圓W之周邊部下面與內側環部31上面之間，使電漿中之離子I往向著半導體晶圓W之周邊部下面加速的力量會增強，而有使半導體晶圓W之周邊部下面的堆積降低效果增加的傾向。反之若加大靜電容量Ce，則形成於半導體晶圓W與導電性構件27之間的電位差Ve會變小。因此半導體晶圓W之周邊部下面與內側環部31上面之間，使電漿中之離子I往向著半導體晶圓W之周邊部下面加速的力量會減弱，而有使半導體晶圓W之周邊部下面的堆積降低效果減少的傾向。To what extent the electrostatic capacitance Ce between the semiconductor wafer W and the conductive member 27 is determined must be determined by the actual plasma processing apparatus. In general, when the electrostatic capacitance Ce is small, the potential difference Ve formed between the semiconductor wafer W and the conductive member 27 becomes large. Therefore, between the lower surface of the peripheral portion of the semiconductor wafer W and the upper surface of the inner ring portion 31, the force for accelerating the ions I in the plasma toward the lower portion of the peripheral portion of the semiconductor wafer W is enhanced, and the periphery of the semiconductor wafer W is enhanced. The tendency of the accumulation reduction effect under the section to increase. On the other hand, when the electrostatic capacitance Ce is increased, the potential difference Ve formed between the semiconductor wafer W and the conductive member 27 becomes small. Therefore, between the lower surface of the peripheral portion of the semiconductor wafer W and the upper surface of the inner ring portion 31, the force for accelerating the ions I in the plasma toward the lower portion of the peripheral portion of the semiconductor wafer W is weakened, and the periphery of the semiconductor wafer W is made weak. The tendency of the accumulation reduction effect under the portion is reduced.
又如上所述，在半導體晶圓W上形成之電漿護套，和在導電性構件27之外側環部30上所形成的電漿護套，其厚度不同會使半導體晶圓W之周邊部的離子I入射角受到影響。一般來說若靜電容量Ce較小，則形成於半導體晶圓W與導電性構件27之間的電位差Ve會變大，形成於外側環部30上之電漿護套會變薄，而離子I之入射角有往半導體晶圓W之中心方向傾斜(入射角>90°)的傾向。反之若加大靜電容量Ce，則形成於半導體晶圓W與導電性構件27之間的電位差Ve會變小，形成於外側環部30上之電漿護套會變厚，而離子I之入射角有從半導體晶圓W之中心往外側方向傾斜(入射角<90°)的傾向。Further, as described above, the plasma sheath formed on the semiconductor wafer W and the plasma sheath formed on the outer ring portion 30 of the conductive member 27 have different thicknesses to cause the peripheral portion of the semiconductor wafer W. The ion I incident angle is affected. Generally, when the electrostatic capacitance Ce is small, the potential difference Ve formed between the semiconductor wafer W and the conductive member 27 becomes large, and the plasma sheath formed on the outer ring portion 30 becomes thin, and the ion I The incident angle tends to be inclined toward the center of the semiconductor wafer W (incident angle > 90°). On the other hand, if the electrostatic capacitance Ce is increased, the potential difference Ve formed between the semiconductor wafer W and the conductive member 27 becomes small, and the plasma sheath formed on the outer ring portion 30 becomes thick, and the incident of the ion I is increased. The angle tends to be inclined from the center of the semiconductor wafer W to the outside direction (incident angle <90°).
在此，第5圖表示相對於半導體晶圓W與導電性構件27之間的靜電容量Ce變化，模擬半導體晶圓W周邊部下面之聚合物附著量(右縱軸)，及半導體晶圓W上面之離子I入射角(左縱軸)的關係。在本發明者等之模擬結果中，分別確認了上述傾向。Here, FIG. 5 shows the amount of polymer adhesion (right vertical axis) under the peripheral portion of the semiconductor wafer W with respect to the change in electrostatic capacitance Ce between the semiconductor wafer W and the conductive member 27, and the semiconductor wafer W. The relationship of the ion I incident angle (left vertical axis) above. In the simulation results of the inventors and the like, the above tendency was confirmed.
於是若依此實施方式之電漿處理裝置1，則比起先前可更降低對半導體晶圓W之下面側的堆積發生，同時藉由抑制半導體晶圓W之周邊部的電場傾斜，在半導體晶圓W之周邊部也可進行略垂直的蝕刻，而可提高處理的面內平均性。Therefore, according to the plasma processing apparatus 1 of this embodiment, the deposition on the lower surface side of the semiconductor wafer W can be reduced more than before, and the electric field tilt of the peripheral portion of the semiconductor wafer W can be suppressed by the semiconductor crystal. The peripheral portion of the circle W can also be slightly etched vertically, and the in-plane average of the treatment can be improved.
以上，表示本發明之理想實施方式的一例，但是本發明並不限定於此例舉方式。例如為了加寬放置於放置台11上之半導體晶圓W的外周面，和外側環部30之內周面30c之間的間隔L1 ，係如第6圖所示之聚焦環25c一般，在與半導體晶圓W之外周面相對的外側環部30之內周面30c，形成凹部30d即可。如此形成凹部30d來充分加寬與半導體晶圓W之外周面的間隔L1 ，可藉此使離子I更平滑地通過到半導體晶圓W的周邊部下方為止。另外此第6圖所說明之聚焦環25a的情況，在外側環部30之上面係省略傾斜面部30a為佳。The above shows an example of a preferred embodiment of the present invention, but the present invention is not limited to the exemplary embodiments. For example, in order to widen the outer peripheral surface of the semiconductor wafer W placed on the placing table 11 and the interval L 1 between the inner peripheral surface 30c of the outer ring portion 30, the focus ring 25c shown in Fig. 6 is generally The concave portion 30d may be formed on the inner circumferential surface 30c of the outer ring portion 30 that faces the outer circumferential surface of the semiconductor wafer W. Thus forming a spacer for L 1 30d sufficiently widened recess and the outside circumferential surface of the semiconductor wafer W, whereby the ions can be more smoothly I up through to the lower peripheral portion of the semiconductor wafer W. Further, in the case of the focus ring 25a described in Fig. 6, it is preferable that the inclined surface portion 30a is omitted on the upper surface of the outer ring portion 30.
又，可如第7圖所示之聚焦環25c一般，在對放置台11以絕緣構件26來絕緣的導電性構件27，靠近配置有電氣連接於接地22之第2導電性構件60，然後在此等導電性構件27與導電性構件60之間介入有第2絕緣構件(介電質)61。另外此第7圖所示之例子，係在導電性構件27外側設置有絕緣材料所構成的蓋環62。Further, as the focus ring 25c shown in Fig. 7, the conductive member 27 insulated by the insulating member 26 to the placing table 11 is disposed adjacent to the second conductive member 60 electrically connected to the ground 22, and then A second insulating member (dielectric) 61 is interposed between the conductive member 27 and the conductive member 60. Further, in the example shown in Fig. 7, a cover ring 62 made of an insulating material is provided outside the conductive member 27.
針對此聚焦環25b，在電漿處理中係如第8圖所示，成為在半導體晶圓W(放置台11)與導電性構件27之間產生電位差Ve，同時在導電性構件27與接地22(導電性構件60)之間產生電位差Vg的狀態。此時若將半導體晶圓W與導電性構件27之間的靜電容量做為Ce，將導電性構件27與接地22之間的靜電容量做為Cg，則半導體晶圓W(放置台11)與導電性構件27之間的電位差Ve會與靜電容量Ce成反比，導電性構件27與接地22之間的電位差Vg會與靜電容量Cg成反比。然後此等電位差Ve、Vg，靜電容量Ce、Cg之間會成立以下算式(1)~(3)的關係。With respect to this focus ring 25b, as shown in Fig. 8, in the plasma processing, a potential difference Ve is generated between the semiconductor wafer W (placement table 11) and the conductive member 27, and at the same time, the conductive member 27 and the ground 22 are formed. A state in which a potential difference Vg is generated between the (conductive members 60). At this time, if the electrostatic capacitance between the semiconductor wafer W and the conductive member 27 is Ce, and the electrostatic capacitance between the conductive member 27 and the ground 22 is Cg, the semiconductor wafer W (placement table 11) and The potential difference Ve between the conductive members 27 is inversely proportional to the electrostatic capacitance Ce, and the potential difference Vg between the conductive member 27 and the ground 22 is inversely proportional to the electrostatic capacitance Cg. Then, the relationship between the potential differences Ve and Vg and the electrostatic capacitances Ce and Cg follows the following equations (1) to (3).
Ve＋Vg＝Vtotal (1) Ce×Ve＝Cg×Vg (2) Ve＝Cg×Vtotal /(Cg＋Ce) (3)Ve+Vg=V total (1) Ce×Ve=Cg×Vg (2) Ve=Cg×V total /(Cg+Ce) (3)
從算式(3)，得知藉由改變導電性構件27與接地22之間的靜電容量Cg，可以改變半導體晶圓W(放置台11)與導電性構件27之間的電位差Ve。在例如第7圖所示之聚焦環25b中，藉由改變導電性構件27與第2導電性構件60的接近距離，或是改變介入於導電性構件27與導電性構件60之間之第2絕緣構件(介電質)61的介電率等方法，可以改變導電性構件27與接地22之間的靜電容量Cg，藉此則可改變半導體晶圓W(放置台11)與導電性構件27之間的電位差Ve。From the formula (3), it is understood that the potential difference Ve between the semiconductor wafer W (the stage 11) and the conductive member 27 can be changed by changing the electrostatic capacitance Cg between the conductive member 27 and the ground 22. For example, in the focus ring 25b shown in Fig. 7, the distance between the conductive member 27 and the second conductive member 60 is changed, or the second portion interposed between the conductive member 27 and the conductive member 60 is changed. The dielectric constant of the insulating member (dielectric) 61 can change the electrostatic capacitance Cg between the conductive member 27 and the ground 22, whereby the semiconductor wafer W (placement table 11) and the conductive member 27 can be changed. The potential difference between Ve.
參考第9圖說明此關係。第9圖中，曲線W’表示在電漿處理中半導體晶圓W的電位變化，曲線27’表示在電漿處理中導電性構件27的電位變化，直線22’表示接地22的電位。圖中曲線W’與曲線27’的寬度，係半導體晶圓W(放置台11)與導電性構件27之間的電位差Ve；曲線27’與直線22’的寬度，係導電性構件27與接地22之間的電位差Vg。如此第9圖所示，加大導電性構件27與接地22之間的電位差Vg時(第9圖之單點破折線27’之情況)，半導體晶圓W(放置台11)與導電性構件27之間的電位差Ve會變大。如此一來，藉由改變導電性構件27與接地22之間的電位差Vg，就可改變半導體晶圓W(放置台11)與導電性構件27之間的電位差Ve。Refer to Figure 9 to illustrate this relationship. In Fig. 9, the curve W' indicates the potential change of the semiconductor wafer W in the plasma processing, the curve 27' indicates the potential change of the conductive member 27 in the plasma processing, and the straight line 22' indicates the potential of the ground 22. The widths of the curve W' and the curve 27' in the figure are the potential difference Ve between the semiconductor wafer W (the stage 11) and the conductive member 27; the width of the curve 27' and the line 22', which is the conductive member 27 and the ground. The potential difference Vg between 22. As shown in FIG. 9, when the potential difference Vg between the conductive member 27 and the ground 22 is increased (in the case of the single-point broken line 27' in FIG. 9), the semiconductor wafer W (the placing table 11) and the conductive member 27 are provided. The potential difference Ve between them becomes large. As a result, by changing the potential difference Vg between the conductive member 27 and the ground 22, the potential difference Ve between the semiconductor wafer W (the stage 11) and the conductive member 27 can be changed.
在此，第10圖表示針對使用第7圖所示之聚焦環25b的電漿處理裝置1，相對於半導體晶圓W(放置台11)與導電性構件27之間的電位差Ve之變化，半導體晶圓W周邊部下面之聚合物附著量(右縱軸)，及半導體晶圓W之周邊部上面之離子I入射角(左縱軸)，其關係的模擬結果。另外半導體晶圓W(放置台11)與導電性構件27之間的電位差Ve與導電性構件27與接地22(導電性構件60)之間的電位差Vg，其總合(Vtotal )為一定值；藉由算式(3)，半導體晶圓W(放置台11)與導電性構件27之間的電位差Ve係等比例於靜電容量比(Cg/(Cg＋Ce))，故第10圖中之橫軸，係取代電位差Ve而使用靜電容量比(Cg/(Cg＋Ce))。Here, FIG. 10 shows a change in the potential difference Ve between the semiconductor wafer W (the stage 11) and the conductive member 27 with respect to the plasma processing apparatus 1 using the focus ring 25b shown in FIG. The simulation result of the relationship between the amount of polymer adhesion (right vertical axis) under the peripheral portion of the wafer W and the incident angle (left vertical axis) of the ion I on the peripheral portion of the semiconductor wafer W. Further, the potential difference Ve between the semiconductor wafer W (the placing table 11) and the conductive member 27 and the potential difference Vg between the conductive member 27 and the ground 22 (the conductive member 60) have a total value (V total ) of a constant value. By the formula (3), the potential difference Ve between the semiconductor wafer W (the stage 11) and the conductive member 27 is proportional to the electrostatic capacitance ratio (Cg/(Cg+Ce)), so the horizontal axis in FIG. 10 In place of the potential difference Ve, a capacitance ratio (Cg/(Cg+Ce)) is used.
若依本發明者等之模擬結果，則當加大半導體晶圓W與導電性構件27之間所形成的電位差Ve(加大靜電容量比(Cg/(Cg＋Ce)))，則半導體晶圓W之周邊部下面的堆積產生會減少，離子I之入射角有往半導體晶圓W之中心方向傾斜(入射角>90°)的傾向。又，反之當減少半導體晶圓W與導電性構件27之間所形成的電位差Ve(減少靜電容量比(Cg/(Cg＋Ce)))，則半導體晶圓W之周邊部下面的堆積產生會增加，離子I之入射角有從半導體晶圓W之中心往外側方向傾斜(入射角<90°)的傾向。According to the simulation result of the inventors of the present invention, when the potential difference Ve (increased capacitance ratio (Cg/(Cg+Ce)))) between the semiconductor wafer W and the conductive member 27 is increased, the semiconductor wafer W The accumulation of the lower portion of the peripheral portion is reduced, and the incident angle of the ion I tends to be inclined toward the center of the semiconductor wafer W (incident angle > 90°). On the other hand, when the potential difference Ve (reduced capacitance ratio (Cg/(Cg+Ce)))) between the semiconductor wafer W and the conductive member 27 is reduced, the deposition under the peripheral portion of the semiconductor wafer W increases. The incident angle of the ion I tends to be inclined outward from the center of the semiconductor wafer W (incident angle <90°).
又，為了容易改變半導體晶圓W與導電性構件27之間所形成的電位差Ve，可以如第11圖所示之聚焦環25c一般，將對放置台11以絕緣性構件26絕緣的導電性構件27，經由可變容量電容器65電氣連接於接地22。Further, in order to easily change the potential difference Ve formed between the semiconductor wafer W and the conductive member 27, the conductive member which insulates the placing table 11 with the insulating member 26 as in the focus ring 25c shown in Fig. 11 can be used. 27 is electrically connected to the ground 22 via a variable capacitor 65.
就此聚焦環25c來說，也與先前第7圖、第8圖所說明的聚焦環25b一樣，成為電漿處理中係在半導體晶圓W(放置台11)與導電性構件27之間產生電位差Ve，在導電性構件27與接地22(導電性構件60)之間產生電位差Vg的狀態。然後若依此聚焦環25c，則藉由操作可變容量電容器65就可改變導電性構件27與接地22之間的靜電容量Cg，因此可輕易改變半導體晶圓W(放置台11)與導電性構件27之間的電位差Ve。藉由如此改變半導體晶圓W與導電性構件27之間所形成的電位差Ve，可以輕易調整離子I對半導體晶圓W之周邊部下面的衝撞量。The focus ring 25c also has a potential difference between the semiconductor wafer W (the stage 11) and the conductive member 27 in the plasma processing as in the focus ring 25b described in the previous FIGS. 7 and 8. Ve is in a state in which a potential difference Vg is generated between the conductive member 27 and the ground 22 (the conductive member 60). Then, if the ring 25c is focused, the capacitance Cg between the conductive member 27 and the ground 22 can be changed by operating the variable capacitor 65, so that the semiconductor wafer W (placement 11) and conductivity can be easily changed. The potential difference Ve between the members 27. By changing the potential difference Ve formed between the semiconductor wafer W and the conductive member 27 in this manner, the amount of collision of the ions I under the peripheral portion of the semiconductor wafer W can be easily adjusted.
又，為了改變半導體晶圓W與導電性構件27之間所形成的電位差Ve，可以如第12圖所示之聚焦環25d一般，在對放置台11以絕緣構件26絕緣的導電性構件27，電氣連接可變直流電源66。Further, in order to change the potential difference Ve formed between the semiconductor wafer W and the conductive member 27, the conductive member 27 insulated from the placing table 11 by the insulating member 26 may be used as the focus ring 25d shown in Fig. 12, The variable DC power source 66 is electrically connected.
就此聚焦環25d來說，也與先前第7圖、第8圖所說明的聚焦環25b一樣，成為電漿處理中係在半導體晶圓W(放置台11)與導電性構件27之間產生電位差Ve，在導電性構件27與接地22(導電性構件60)之間產生電位差Vg的狀態。若依此聚焦環25d，當操作可電直流電源66時則如第13圖所示，可使導電性構件27與接地22之間的電位差Vg在圖中往上下偏移。然後，使電位差Vg往圖中下方偏移時(第13圖中單點破折線27’的情況)，半導體晶圓W(放置台11)與導電性構件27之間的電位差Ve會變小。反之使電位差Vg往圖中上方偏移時(第13圖中兩點破折線27’的情況)，半導體晶圓W(放置台11)與導電性構件27之間的電位差Ve會變大。如此一來，藉由操作連接於導電性構件27之可變直流電源66，則可輕易改變半導體晶圓W(放置台11)與導電性構件27之間的電位差Ve。The focus ring 25d also has a potential difference between the semiconductor wafer W (the stage 11) and the conductive member 27 in the plasma processing as in the focus ring 25b described in the previous FIGS. 7 and 8. Ve is in a state in which a potential difference Vg is generated between the conductive member 27 and the ground 22 (the conductive member 60). According to the focus ring 25d, when the electric DC power supply 66 is operated, as shown in Fig. 13, the potential difference Vg between the conductive member 27 and the ground 22 can be shifted upward and downward in the drawing. Then, when the potential difference Vg is shifted downward in the drawing (in the case of the single-dot broken line 27' in Fig. 13), the potential difference Ve between the semiconductor wafer W (the stage 11) and the conductive member 27 becomes small. On the other hand, when the potential difference Vg is shifted upward in the figure (in the case of the two-point broken line 27' in Fig. 13), the potential difference Ve between the semiconductor wafer W (the stage 11) and the conductive member 27 becomes large. As a result, by operating the variable DC power source 66 connected to the conductive member 27, the potential difference Ve between the semiconductor wafer W (the stage 11) and the conductive member 27 can be easily changed.
又，以上所說明之聚焦環25、25a、25b、25c、25d，任一個都圖示為將配置在放置台11上之半導體晶圓W周圍外側的外側環部30，和配置於半導體晶圓W之周邊部下方的內側環部31，做為導電性構件27來一體形成的型態；但是外側環部30與內側環部31也可互相構成為不同構件。又，當如此互相構成為不同構件的情況下，外側環部30與內側環部31可以互相電氣導通，也可互相電氣絕緣。Further, any of the focus rings 25, 25a, 25b, 25c, and 25d described above is illustrated as an outer ring portion 30 disposed on the outer side of the semiconductor wafer W disposed on the placing table 11, and disposed on the semiconductor wafer. The inner ring portion 31 below the peripheral portion of the W is integrally formed as the conductive member 27; however, the outer ring portion 30 and the inner ring portion 31 may be configured as different members from each other. Further, when the members are configured as different members in this manner, the outer ring portion 30 and the inner ring portion 31 can be electrically connected to each other or electrically insulated from each other.
第14圖所示之聚焦環25e，係將配置在放置台11上之半導體晶圓W周圍外側的外側環部30，和配置於半導體晶圓W之周邊部下方的內側環部31，互相構成為不同構件，且此等外側環部30與內側環部31為互相電氣絕緣的狀態。另一方面，外側環部30與內側環部31及放置台11之間，係介入有絕緣構件26，故內側環部31對於外側環部30及放置台11係電氣絕緣。The focus ring 25e shown in Fig. 14 is formed by interconnecting the outer ring portion 30 disposed on the outer side of the semiconductor wafer W on the placing table 11 and the inner ring portion 31 disposed below the peripheral portion of the semiconductor wafer W. These are different members, and the outer ring portion 30 and the inner ring portion 31 are electrically insulated from each other. On the other hand, since the insulating member 26 is interposed between the outer ring portion 30 and the inner ring portion 31 and the placing table 11, the inner ring portion 31 is electrically insulated from the outer ring portion 30 and the placing table 11.
就具備此第14圖所示之聚焦環25e的電漿處理裝置1來說，在電漿處理中，外側環部30經常與放置台1為相同電位，在半導體晶圓W與外側環部30之間不會產生電位差；但是因為內側環部31與放置台11之間介入有絕緣構件26，故對於施加在放置台11的高頻電力來說阻抗會變高，因此成為只有在半導體晶圓W與內側環部31之間產生電位差Ve的狀態。因此在半導體晶圓W之周邊部下面與內側環部31之上面之間，形成有使電漿中之離子I往向著半導體晶圓W之周邊部下面之方向加速的電場，而可降低半導體晶圓W之周邊部下面的堆積產生。此外，此第14圖所示之聚焦環25e，因為在半導體晶圓W之外周面與外側環部30之內周面之間沒有產生電位差，故電漿中之離子I可平滑通過半導體晶圓W之外周面與外側環部30之內周面30c之間；如此一來通過到半導體晶圓W之周邊部下面為止的離子I，會衝撞半導體晶圓W之周邊部下面，藉此可更加降低半導體晶圓W之周邊部下面的堆積產生。In the plasma processing apparatus 1 including the focus ring 25e shown in Fig. 14, in the plasma processing, the outer ring portion 30 is often at the same potential as the placing table 1, and the semiconductor wafer W and the outer ring portion 30 are A potential difference does not occur between them; however, since the insulating member 26 is interposed between the inner ring portion 31 and the placing table 11, the impedance becomes high for the high-frequency power applied to the placing table 11, and thus becomes only in the semiconductor wafer. A state in which a potential difference Ve is generated between W and the inner ring portion 31. Therefore, between the lower surface of the peripheral portion of the semiconductor wafer W and the upper surface of the inner ring portion 31, an electric field for accelerating the ions I in the plasma toward the lower surface of the peripheral portion of the semiconductor wafer W is formed, thereby reducing the semiconductor crystal. The accumulation under the peripheral portion of the circle W is generated. Further, in the focus ring 25e shown in FIG. 14, since no potential difference is generated between the outer peripheral surface of the semiconductor wafer W and the inner peripheral surface of the outer ring portion 30, the ions I in the plasma can smoothly pass through the semiconductor wafer. The outer peripheral surface of W and the inner peripheral surface 30c of the outer ring portion 30; in this way, the ions I passing under the peripheral portion of the semiconductor wafer W collide with the lower surface of the peripheral portion of the semiconductor wafer W, thereby further The deposition under the peripheral portion of the semiconductor wafer W is reduced.
又，第1圖中例舉了將電漿產生用之較高頻率的高頻電力，供給到處理室10之天花板部分的蓮蓬頭40(上部電極)；但也可以做為如第15圖所示，將供給電漿產生用之較高頻率高頻電力的高頻電源42及匹配器41，和供給偏壓用之較低頻率高頻電力的高頻電源21及匹配器20，雙方都連接於放置台11的構造。Further, in the first drawing, the high-frequency electric power of the higher frequency for plasma generation is supplied to the shower head 40 (upper electrode) of the ceiling portion of the processing chamber 10; however, as shown in Fig. 15, A high-frequency power source 42 and a matching unit 41 for supplying a higher-frequency high-frequency power for plasma generation, and a high-frequency power source 21 and a matching unit 20 for supplying a lower-frequency high-frequency power for biasing are connected to each other. The configuration of the stage 11 is placed.
又，本發明也可將以上所說明之聚焦環25、25a、25b、25c、25d、25e，適用於在處理室10內包圍放置台11上之半導體晶圓W來配置，且包含適當支撐構件的聚焦環零件。此時做為支撐聚焦環25、25a、25b、25c、25d、25e的支撐構件，可舉出例如放置台11、排氣環35等。又，也可將第7圖所說明之第2導電構件60或第2絕緣構件61利用為支撐構件。Furthermore, the present invention can also be applied to the above-described focus rings 25, 25a, 25b, 25c, 25d, 25e for arranging the semiconductor wafer W on the placement table 11 in the processing chamber 10, and including appropriate support members. Focus ring parts. In this case, as the supporting members that support the focus rings 25, 25a, 25b, 25c, 25d, and 25e, for example, the placing table 11, the exhaust ring 35, and the like can be cited. Further, the second conductive member 60 or the second insulating member 61 described in FIG. 7 may be used as a supporting member.
本發明可利用於半導體裝置的製造產業。The present invention can be utilized in the manufacturing industry of semiconductor devices.
1．．．電漿處理裝置1. . . Plasma processing device
10．．．處理室10. . . Processing room
11．．．放置台11. . . Placement table
12．．．絕緣板12. . . Insulation board
15．．．熱媒體流路15. . . Hot media flow
16．．．氣體流路16. . . Gas flow path
20．．．匹配器20. . . Matcher
21．．．高頻電源twenty one. . . High frequency power supply
22．．．接地(Earth)twenty two. . . Earth
25．．．聚焦環25. . . Focus ring
26．．．環狀之絕緣構件26. . . Ring-shaped insulating member
27．．．導電性構件27. . . Conductive member
30．．．外側環部30. . . Outer ring
31．．．內側環部31. . . Inner ring
30a．．．傾斜面部30a. . . Inclined face
30b．．．水平面部30b. . . Horizontal face
35．．．排氣環35. . . Exhaust ring
40．．．蓮蓬頭40. . . Shower head
41．．．匹配器41. . . Matcher
42．．．高頻電源42. . . High frequency power supply
45．．．氣體吐出孔45. . . Gas discharge hole
47．．．氣體擴散用空隙47. . . Gas diffusion gap
46．．．氣體導入部46. . . Gas introduction
50．．．氣體供給配管50. . . Gas supply piping
51．．．氣體供給系統51. . . Gas supply system
52．．．流量控制器52. . . Flow controller
53．．．處理氣體供給源53. . . Process gas supply
〔第1圖〕表示本發明之實施方式中電漿處理裝置之概略構造的說明圖。[Fig. 1] is an explanatory view showing a schematic structure of a plasma processing apparatus in an embodiment of the present invention.
〔第2圖〕放大表示聚焦環的縱剖面圖。[Fig. 2] is an enlarged longitudinal sectional view showing the focus ring.
〔第3圖〕半導體晶圓(放置台)與導電性構件之間所產生之電位差的說明圖。[Fig. 3] An explanatory diagram of a potential difference generated between a semiconductor wafer (placement stage) and a conductive member.
〔第4圖〕半導體晶圓與導電性構件之間之電位差所形成之電場的說明圖。[Fig. 4] An explanatory diagram of an electric field formed by a potential difference between a semiconductor wafer and a conductive member.
〔第5圓〕相對於半導體晶圓與導電性構件之間之靜電容量變化，表示半導體晶圓周邊部下面之聚合物附著量(右縱軸)，及半導體晶圓之周邊部上面之離子入射角(左縱軸)，其關係之模擬結果的圖表。[Circle 5] indicates the amount of polymer adhesion (right vertical axis) under the semiconductor wafer peripheral portion and ion incidence on the peripheral portion of the semiconductor wafer with respect to the change in electrostatic capacitance between the semiconductor wafer and the conductive member. The angle (left vertical axis), a graph of the simulation results of its relationship.
〔第6圖〕將在與半導體晶圓之外周面相對之外側環部內周面上形成有凹部的聚焦環，加以放大表示的縱剖面圖。[Fig. 6] A longitudinal cross-sectional view showing a focus ring in which a concave portion is formed on the inner circumferential surface of the side ring portion opposite to the outer circumferential surface of the semiconductor wafer.
〔第7圖〕將對於導電性構件，經由絕緣構件(介電質)而靠近導通於接地之第2導電性構件來配置的聚焦環，加以放大表示的縱剖面圖。[Fig. 7] A longitudinal cross-sectional view showing an enlarged view of a focus ring in which a conductive member is placed close to a second conductive member that is grounded via an insulating member (dielectric).
〔第8圖〕第7圖之聚焦環中，半導體晶圓(放置台)與導電性構件之間所產生之電位差的說明圖。[Fig. 8] An explanatory diagram of a potential difference generated between a semiconductor wafer (placement stage) and a conductive member in the focus ring of Fig. 7.
〔第9圖〕第7圖之聚焦環中，表示電漿處理中之半導體晶圓與導電性構件與接地等三者之電位變化的圖表。[Fig. 9] A focus ring of Fig. 7 is a graph showing changes in potential of a semiconductor wafer, a conductive member, and a ground in plasma processing.
〔第10圖〕第7圖之聚焦環中，相對於半導體晶圓與導電性構件之間之電位差(靜電容量比(Cg/(Cg＋Ce)))的變化，表示半導體晶圓周邊部下面之聚合物附著量(右縱軸)，及半導體晶圓之周邊部上面之離子入射角(左縱軸)，其關係之模擬結果的圖表。[Fig. 10] In the focus ring of Fig. 7, the change in potential difference (electrostatic capacity ratio (Cg/(Cg+Ce)))) between the semiconductor wafer and the conductive member indicates polymerization under the peripheral portion of the semiconductor wafer. A graph of the simulation results of the relationship between the amount of object adhesion (right vertical axis) and the incident angle of ions on the peripheral portion of the semiconductor wafer (left vertical axis).
〔第11圖〕將使導電性構件經由可變容量電容而電氣連接於接地之聚焦環，加以放大表示的縱剖面圖。[Fig. 11] A longitudinal cross-sectional view showing an electrically conductive member electrically connected to a grounded focus ring via a variable capacitance.
〔第12圖〕將對導電性構件電氣連接可變直流電源之聚焦環，加以放大表示的縱剖面圖。[Fig. 12] A longitudinal sectional view in which a focus ring of a variable DC power supply is electrically connected to a conductive member and enlarged.
〔第13圖〕第12圖之聚焦環中，表示電漿處理中之半導體晶圓與導電性構件與接地等三者之電位變化的圖表。[Fig. 13] The focus ring of Fig. 12 shows a graph showing the change in potential of the semiconductor wafer, the conductive member, and the ground in the plasma processing.
〔第14圖〕將外側環部與內側環部互相電氣絕緣之構造之聚焦環，加以放大表示的縱剖面圖。[Fig. 14] A longitudinal cross-sectional view showing an enlarged focus of a focus ring in which the outer ring portion and the inner ring portion are electrically insulated from each other.
〔第15圖〕將電漿產生用之高頻電源與偏壓用高頻電源雙方連接於放置台的電漿處理裝置，表示其概略構造的說明圖。[Fig. 15] A schematic diagram showing a schematic structure of a plasma processing apparatus in which a high-frequency power source for generating plasma and a high-frequency power source for biasing are connected to a stage.
1．．．電漿處理裝置1. . . Plasma processing device
10．．．處理室10. . . Processing room
11．．．放置台11. . . Placement table
12．．．絕緣板12. . . Insulation board
15．．．熱媒體流路15. . . Hot media flow
16．．．氣體流路16. . . Gas flow path
20．．．匹配器20. . . Matcher
21．．．高頻電源twenty one. . . High frequency power supply
22．．．接地(Earth)twenty two. . . Earth
25．．．聚焦環25. . . Focus ring
26．．．環狀之絕緣構件26. . . Ring-shaped insulating member
27．．．導電性構件27. . . Conductive member
35．．．排氣環35. . . Exhaust ring
36．．．排氣埠36. . . Exhaust gas
37．．．排氣系統37. . . Exhaust system
40．．．蓮蓬頭40. . . Shower head
41．．．匹配器41. . . Matcher
42．．．高頻電源42. . . High frequency power supply
45．．．氣體吐出孔45. . . Gas discharge hole
46．．．氣體導入部46. . . Gas introduction
47．．．氣體擴散用空隙47. . . Gas diffusion gap
50．．．氣體供給配管50. . . Gas supply piping
51．．．氣體供給系統51. . . Gas supply system
52．．．流量控制器52. . . Flow controller
53．．．處理氣體供給源53. . . Process gas supply
W．．．被處理基板W. . . Substrate to be processed
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| JP2006074372A JP2007250967A (en) | 2006-03-17 | 2006-03-17 | Plasma treating apparatus and method, and focus ring |
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| KR20090026321A (en) | 2009-03-12 |
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| KR20070094522A (en) | 2007-09-20 |
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