TWI488236B - Focusing ring and plasma processing device - Google Patents

Description

Focus ring and plasma processing device

The present invention relates to a focus ring and a plasma processing apparatus which are disposed in a processing chamber for performing predetermined plasma processing such as etching treatment on a substrate such as a semiconductor substrate.

Conventionally, a plasma processing apparatus such as an etching processing apparatus is often used in, for example, a process of a microcircuit of a semiconductor device.

In such a plasma processing apparatus, a substrate to be processed such as a semiconductor wafer is placed in a processing chamber configured to hermetically seal the inside thereof, and plasma is generated in the processing chamber to cause the plasma to be processed. On the substrate, plasma treatment such as etching can be performed.

Further, in such a plasma processing apparatus, an annular member called a focus ring that surrounds the periphery of the semiconductor wafer, which is a substrate to be processed, is disposed. The purpose of the focus ring is to close the plasma and to alleviate the discontinuity caused by the creeping effect of the bias in the surface of the semiconductor wafer, so that the peripheral portion of the semiconductor wafer can be uniformly formed in the same manner as the central portion. And good handling.

The above-mentioned focus ring is known to be arranged such that it can enclose the semiconductor wafer and bring the dielectric close to the plasma, and the plasma is displaced in the upper axial direction, and the plasma is moved away from the lower electrode to cause the reaction in the plasma. The type of the semiconductor wafer is not concentrated on the periphery of the lower electrode to reduce the processing speed of the peripheral portion of the semiconductor wafer (see, for example, Patent Document 1).

Further, as described above, since one of the purposes of the focus ring is to alleviate the discontinuity of the bias voltage, the surface (top surface) of the focus ring and the processing surface of the semiconductor wafer to be processed are substantially the same plane. That is, the surface (top surface) of the focus ring and the processing surface of the semiconductor wafer are approximately the same height. Further, a test has been known in which the surface (top surface) of the focus ring is made higher than the processing surface of the semiconductor wafer, or the material is used to reduce the discontinuity of the bias voltage (see, for example, Patent Document 2).

[Patent Document 1] Japanese Patent Publication No. 2001-516948 (pages 13-41, 1-7)

[Patent Document 2] Japanese Patent Publication No. 2003-503841 (pages 12-22, 2-6)

As described above, in the conventional plasma processing apparatus, the focus ring is used, and by using such a focus ring, the uniformity of processing is improved.

Fig. 15 is a view showing an example of a conventional focus ring. As shown in the figure, in the mounting table 100 which also serves as a lower electrode, for example, it is possible to surround the periphery of the semiconductor wafer W as a substrate to be processed. The conductive material of the same is formed into a ring-shaped focus ring 101.

Further, in the example shown in Fig. 15, the height of the top surface of the focus ring 101 is set to be approximately the same as the height of the processing surface (surface) of the semiconductor wafer W; as a result, the electric field above the focus ring 101, It becomes substantially the same as the electric field above the surface of the semiconductor wafer W, and the discontinuity due to the creeping effect of the bias is moderated, as indicated by the broken line in the figure, above the semiconductor wafer W and above the focus ring 101. A plasma sheath of approximately the same height is formed. With such a plasma sheath, ions are incident perpendicularly to the surface of the semiconductor wafer W even at the edge portion of the semiconductor wafer W as indicated by the arrow in the figure.

However, in the case of using the focus ring 101 configured as described above, so-called deposition of adhering substances composed of a CF-based polymer or the like occurs on the back side of the peripheral portion (edge portion) of the semiconductor wafer W.

When the cause of such deposition is examined in detail, in the case of using the focus ring 101 configured as described above, since the semiconductor wafer W and the focus ring 101 have approximately the same potential, the enlarged view of FIG. 16 is on the peripheral portion of the semiconductor wafer W. An electric field between the (edge portion) and the inner peripheral portion of the focus ring 101, which is indicated by a broken line in the figure, is formed. Therefore, as indicated by the solid arrows in the figure, the plasma becomes easy to intrude into the semiconductor wafer W from the intermediate portion between the peripheral portion (edge portion) of the semiconductor wafer W and the inner peripheral portion of the focus ring 101. In the state of the back side, the deposition of the plasma on the back side of the semiconductor wafer W on the back side of the peripheral portion (edge portion) of the semiconductor wafer W is also estimated.

The present invention has been developed in order to deal with such conventional problems, and an object of the invention is to provide a focus ring and a plasma processing apparatus capable of performing the same as a central portion of a semiconductor wafer even in a peripheral portion of a semiconductor wafer. Performing a good and uniform treatment not only improves the in-plane uniformity of the treatment, but also reduces the occurrence of deposition on the back side of the peripheral portion of the semiconductor wafer as compared with the prior art.

That is, the invention of claim 1 is a focus ring for a lower electrode on which the substrate to be processed is placed in a processing chamber for accommodating a substrate to be processed and subjected to a predetermined plasma treatment And an annular focus ring that surrounds the periphery of the substrate to be processed, and includes: a lower member formed of a dielectric; and an upper portion disposed on the lower member, made of a conductive material The upper member is formed such that the top surface thereof is formed with an inclined portion whose outer peripheral side is higher than the inner peripheral side, and the outer peripheral side end portion of the inclined portion is configured to be at least positioned to be processed than the substrate to be processed. a higher position of the surface is disposed at a predetermined interval from a peripheral portion of the substrate to be processed; and a height h of the outer peripheral side of the inclined portion with respect to the surface to be processed of the substrate to be processed is configured to be 0. In the range of <h≦6 mm, a conductive member is provided between the lower electrode and the lower member.

The invention of claim 2 is the focus ring according to the first aspect of the invention, wherein the conductive member is made of tantalum or niobium rubber.

The invention of claim 3, wherein the outer peripheral side of the inclined portion is formed to be flatter than the processed surface of the substrate to be processed, in the focus ring according to the first or second aspect of the invention. unit.

Moreover, the invention of claim 4 of the patent scope is directed to the patent application The focus ring of item 1 or 2, wherein the conductive material is tantalum, carbon or SiC.

The invention of claim 5, wherein the focus ring according to claim 1 or 2, wherein the height h of the outer peripheral side of the inclined portion with respect to the surface to be processed of the substrate to be processed is It is formed in the range of 2≦h≦4mm.

The invention of claim 6 is the focus ring according to claim 1 or 2, wherein the length l of the inclined portion in the longitudinal section of the upper member is formed at 0.5. Mm≦l≦9mm range.

The invention of claim 7 is the focus ring according to claim 1 or 2, wherein the predetermined interval C1 between the upper member and the peripheral portion of the substrate to be processed is configured 0.3mm ≦ C1 ≦ 1.5mm range.

Further, the invention of claim 8 is directed to the focus ring of claim 1 or 2, wherein the lower member is a high frequency combination of the plasma and the lower electrode, and is applied to The high frequency on the lower electrode increases the impedance.

Further, the invention of claim 9 is a plasma processing apparatus characterized by comprising: a processing chamber for accommodating a substrate to be processed and performing a predetermined plasma treatment; a lower electrode, the lower portion An electrode system is disposed in the processing chamber, and the substrate to be processed is placed; a lower member formed of a dielectric, being an annular member, disposed on the lower electrode, and surrounding the periphery of the substrate to be processed; and an upper member disposed on the upper member In the upper portion of the lower member, the annular member formed of the conductive material has an inclined portion whose outer peripheral side is higher than the inner peripheral side on the top surface thereof, and the outer peripheral side end portion of the inclined portion is configured to be at least Located at a position higher than a surface to be processed of the substrate to be processed, and disposed at a predetermined interval from a peripheral portion of the substrate to be processed; and an outer peripheral side of the inclined portion with respect to a surface to be processed of the substrate to be processed The height h is formed in a range of 0 < h ≦ 6 mm, and a conductive member is provided between the lower electrode and the lower member.

The invention is directed to the plasma processing apparatus according to claim 9, wherein the conductive member is made of tantalum or niobium rubber.

The invention is directed to the plasma processing apparatus according to the ninth or tenth aspect, wherein the outer peripheral side of the inclined portion of the upper member is formed to be larger than the substrate to be processed. A flat portion with a higher surface.

Further, the invention of claim 12 is the plasma processing apparatus according to claim 9 or claim 10, wherein the conductive material is tantalum, carbon or SiC.

Moreover, the invention of claim 13 is for patent application The plasma processing apparatus according to the ninth or tenth aspect, wherein the height h of the outer peripheral side of the inclined portion with respect to the surface to be processed of the substrate to be processed is within a range of 2 ≦ h ≦ 4 mm.

The invention is directed to the plasma processing apparatus according to claim 9 or claim 10, wherein the length l of the inclined portion in the longitudinal section of the upper member is formed in the horizontal direction. In the range of 0.5 mm ≦ l ≦ 9 mm.

The invention is directed to the plasma processing apparatus according to claim 9 or claim 10, wherein the predetermined interval C1 between the upper member and the peripheral portion of the substrate to be processed is The composition is in the range of 0.3 mm ≦ C1 ≦ 1.5 mm.

Further, the invention of claim 16 is directed to the plasma processing apparatus of claim 9 or claim 10, wherein the lower side member is configured to combine the plasma and the lower electrode at a high frequency, and The high frequency applied to the lower electrode increases the impedance.

(Best form for carrying out the invention)

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

Fig. 1 is a schematic view showing a schematic configuration of a whole plasma processing apparatus (etching apparatus) according to an embodiment of the present invention; in this figure, reference numeral 1 denotes a cylindrical processing chamber (vacuum chamber); The material is formed, for example, of aluminum or the like, and is configured to be airtightly closed to form a processing chamber.

Inside the vacuum chamber 1, a mounting table 2 is provided. The mounting table 2 is formed of a conductive material such as aluminum, and also serves as a lower electrode.

The mounting table 2 is supported in the vacuum chamber 1 via an insulating plate 3 such as ceramics. On the semiconductor wafer W mounting surface of the mounting table 2, static electricity (not shown) for absorbing and holding the semiconductor wafer W is provided. Chuck.

Further, inside the mounting table 2, a heat medium flow path 4 for circulating an insulating fluid as a temperature-controlled heat medium, and a gas flow path 5 for sputum are provided. A temperature control gas such as gas is supplied to the back surface of the semiconductor wafer W.

In the heat medium flow path 4, the insulating fluid controlled at a predetermined temperature is circulated, the mounting table 2 is controlled to a predetermined temperature, and the gas for temperature control is supplied to the mounting table via the gas flow path 5. Between the back surface of the semiconductor wafer W and the back surface of the semiconductor wafer W, the semiconductor wafer W can be controlled to a predetermined temperature with high precision and efficiency.

Further, the high-frequency power source (RF power source) 7 is connected to the mounting table 2 via the matching unit 6, and the high-frequency power of a predetermined frequency can be supplied from the high-frequency power source 7.

Further, a focus ring 8 is provided on the upper peripheral portion of the mounting table 2. The focus ring 8 is an annular lower member 9 formed of a dielectric material (for example, a ceramic such as quartz or alumina or a resin such as VESPEL (registered trademark); and a lower member 9 disposed thereon. Upper portion, and an annular upper member 10 formed of a conductive material (for example, tantalum, carbon, SiC, etc.) And configured to be placed around the semiconductor wafer W that can surround the substrate to be processed.

As shown in Fig. 2, the upper member 10 has a flat portion 10a which is higher than the surface to be processed of the semiconductor wafer W, and the inner peripheral portion of the flat portion 10a is formed. The inclined portion 10b whose outer peripheral side is higher than the inner peripheral side and inclined. Further, the upper member 10 is disposed between the upper member 10 and the peripheral portion of the semiconductor wafer W such that the interval C1 is formed. Further, in Fig. 2, P denotes plasma; and in the portion of the focus ring 8, the mounting table (lower electrode) 2, the high-frequency power applied from the high-frequency power source, through the lower member 9 is combined by high frequency, and by the lower member 9 (dielectric) interposed therebetween, the impedance increases for this high frequency.

Here, the reason why the focus ring 8 is formed as described above will be described. As described above, as shown in FIGS. 15 and 16, the focus ring 101, since the semiconductor wafer W and the focus ring 101 have approximately the same potential, the plasma becomes easily entangled into the semiconductor wafer due to the state of the electric field. The back side of the end of W.

Therefore, as shown in Fig. 17, a focus ring 110 having a structure in which the conductive ring 112 is placed on the upper portion of the dielectric ring 111 is used, and a potential difference is provided between the semiconductor wafer W and the conductive ring 112, as shown in the figure. The electric field of the power line from the end of the semiconductor wafer W toward the conductive ring 112 is formed as indicated by the dashed arrow. Therefore, it is known from the electric field that the plasma can be prevented from being wound around the back side of the end portion of the semiconductor wafer W.

However, in the case of using the focus ring 110 constructed as described above, as shown by the broken line in FIG. 17, the electricity generated above the semiconductor wafer W is generated. Since the thickness of the plasma sheath and the plasma sheath formed on the focus ring 110 are different, the electric field is inclined at the peripheral portion of the semiconductor wafer W, and thus the ions colliding from the upper surface toward the surface of the semiconductor wafer W When the entrance angle is inclined, the etching progresses obliquely, and the uniformity of the etching process is lowered.

Therefore, in the present embodiment, the focus ring 8 having the above-described configuration is used to suppress the electric field from tilting in the peripheral portion of the semiconductor wafer W while suppressing the plasma from being wound around the end portion of the end surface of the semiconductor wafer W. The case where the uniformity of the etching treatment is suppressed is suppressed.

Further, an exhaust ring 11 formed in a ring shape and having a plurality of exhaust ports is formed outside the focus ring 8, and the exhaust ring 11 is connected to the exhaust system 13 via the exhaust port 11 A vacuum pump or the like constitutes a vacuum exhaust that can perform a processing space in the vacuum chamber 1.

On the other hand, in the ceiling portion of the vacuum chamber 1 above the mounting table 2, the shower head 14 is disposed opposite to the mounting table 2, and the mounting table 2 and the air jet head 14 function as a pair of electrodes (upper electrode). And the function of the lower electrode). Further, the high frequency power source 16 is connected to the air jet head 14 via the matching unit 15.

The air jet head 14 is provided with a plurality of gas discharge ports 17 on its bottom surface and a gas introduction portion 18 at its upper portion. Further, a gas diffusion gap 19 is formed in the inside. The gas supply pipe 20 is connected to the gas introduction portion 18, and the gas supply system 21 is connected to the other end of the gas supply pipe 20. The gas supply system 21 is composed of a mass flow controller (MFC) 22 for controlling a gas flow rate, a processing gas supply source 23 for supplying a processing gas such as etching, and the like.

Next, the procedure of the etching process performed by the etching apparatus configured as described above will be described.

First, a gate valve (not shown) provided in the vacuum chamber 1 is opened, and a semiconductor wafer is transferred by a transfer mechanism (not shown) via a load lock vacuum chamber (not shown) disposed adjacent to the gate valve. W is carried into the vacuum chamber 1 and placed on the mounting table 2. Then, after the transport mechanism is retracted to the outside of the vacuum chamber 1, the gate valve is closed.

Thereafter, the inside of the vacuum chamber 1 is exhausted to a predetermined degree of vacuum through the exhaust port 12 by the vacuum pump of the exhaust system 13, and a predetermined processing gas is supplied from the processing gas supply source 23 into the vacuum chamber 1.

In this state, a predetermined high-frequency power having a low frequency is supplied from the high-frequency power source 7 and a high-frequency power having a high frequency is supplied from the high-frequency power source 16 to generate a plasma to perform a semiconductor by plasma. Etching of wafer W.

When a predetermined etching process is performed, the supply of the high-frequency power from the high-frequency power sources 7 and 16 is stopped, the etching process is stopped, and the semiconductor wafer W is carried out of the vacuum chamber 1 in the reverse order of the above-described order. .

When the etching process is performed by the above-described plasma, the focus ring 8 in the present embodiment is placed on the mounting table 2 as described above, and the upper member 10 is placed on the mounting table 2 as described above. Since it is disposed on the lower member 9, the impedance of the portion of the upper member 10 (the impedance against the high-frequency power applied to the mounting table 2) becomes higher than that of the semiconductor wafer W, and as a result, the potential is lowered. A potential difference is generated between the semiconductor wafer W and the upper member 10. By the action of the electric field formed by the potential difference, the plasma is prevented from being wound around the back surface side of the peripheral portion of the semiconductor wafer W, and deposition of CF-based polymer or the like on the back surface side of the peripheral portion of the semiconductor wafer W can be suppressed.

The end portion (0.0 mm) of the horizontal portion on the back side of the peripheral portion of the semiconductor wafer W shown in Fig. 3, the portion inside the 1.0 mm from the inside, the portion inside the 0.5 mm, and the 30° of the end surface were measured. The amount of deposition of the 45° portion, and the results are shown in Fig. 4. In Table 1, the comparative example shows the results of the case where the focus ring 101 of the configuration shown in Figs. 15 and 16 is used; and the examples 1 and 2 show the focus ring of the above configuration shown in Figs. The case of 8; and Examples 1 and 2 show the case of ashing and ashing, respectively. Further, in the graph of Fig. 4, the vertical axis indicates the deposition amount, and the horizontal axis indicates the position on the semiconductor wafer W. The solid line A indicates a comparative example, the broken line B indicates the first embodiment, and the chain line C indicates the second embodiment. As shown in Fig. 4, in the case of using the focus ring 8, the amount of deposition can be significantly reduced as compared with the case where the focus ring 101 is applied.

(Table 1)

Further, in the present embodiment, a potential difference is generated between the semiconductor wafer W and the upper member 10 by interposing the lower member 9 formed of the dielectric therebetween, and a peripheral portion is formed on the top surface of the upper member 10. The inclined portion 10b whose side is higher than the inner peripheral side is inclined, and a flat portion 10a higher than the processed surface of the semiconductor wafer W is formed on the outer peripheral side of the inclined portion 10b. As described above, by having a portion higher than the surface to be processed of the semiconductor wafer W on the top surface of the focus ring 8, the boundary portion of the plasma formed above the focus ring 8 can be raised to the semiconductor wafer W. The boundary portion of the upper plasma is about the same height, and the tilt of the electric field in the peripheral portion of the semiconductor wafer W can be suppressed.

Further, the focus ring 8 is formed at a position higher than the surface to be processed of the semiconductor wafer W, and the flat portion 10a of the side member 10 is raised to increase the height of the plasma sheath, and the height of the plasma sheath is changed. It is relieved by the presence of the inclined portion 10b; thereby, it is possible to suppress a sharp electric field change in the boundary portion between the semiconductor wafer W and the focus ring 8, and for example, it is also possible to suppress the electric field to be shown in FIG. The situation is reversed in the opposite direction.

As a result of the electric field simulation, the height h from the surface to be processed of the semiconductor wafer W of the inclined portion 10b shown in Fig. 2 is desirably set in a range of 0 < h ≦ 6 mm, and more preferably 2 mm ≦ h. ≦ 4mm. Further, similarly, the length l of the inclined portion 10b shown in Fig. 2 in the horizontal direction is preferably set to a range of 0.5 mm ≦ l ≦ 9 mm, and more preferably 1 mm ≦ l ≦ 6 mm. The length l of the inclined portion 10b in the horizontal direction may be set to l=0 depending on the interval C1 between the semiconductor wafer W and the focus ring 8. That is, although this case has a shape without the inclined portion 10b, by adjusting the interval C1 between the end portion of the semiconductor wafer W and the focus ring 8, it is possible to suppress a sudden change in the electric field in this portion. Further, the height d of the lower end portion of the inclined portion 10b shown in Fig. 2 is desirably set to about 0 ≦ d ≦ 1 mm.

Further, since a potential difference is generated between the semiconductor wafer W and the focus ring 8, if the semiconductor wafer W and the focus ring 8 are too close, an arc may be generated on the semiconductor wafer W. On the other hand, if the semiconductor wafer W and the focus ring 8 are too apart, the effect of preventing the invasion of the plasma on the back side of the semiconductor wafer W by the electric field is lowered. Therefore, the interval C1 between the end portion of the semiconductor wafer W and the focus ring 8 shown in Fig. 2 is desirably set to a range of 0.3 mm ≦ C1 ≦ 1.5 mm, and more preferably set to 1.0 mm ≦ C1 ≦ 1.5 mm. The scope. In addition, the interval C2 between the end surface of the semiconductor wafer W and the focus ring 8 shown in FIG. 2 is similarly set to 0.3 mm ≦ C2 in order to prevent abnormal discharge, and the same is true. The reason is that the interval C3 shown in Fig. 2 is desirably set to 0.4 mm ≦ C3.

Fig. 5 is a view showing the result of investigating the inclination of the electric field in the peripheral portion of the semiconductor wafer W. The vertical axis in the graph of Fig. 5(a) indicates the angle of the electric field (the angle θ shown in Fig. 2), The horizontal axis indicates the position on the wafer (as shown in Fig. 2, the end portion of the semiconductor wafer W is set to a position of the inner peripheral portion of 10 mm).

In addition, in the fifth drawing, the curve A indicated by the square symbol indicates the case of the focus ring shown in Fig. 15, and the curve B indicated by the circular symbol indicates the configuration shown in Fig. 17. The case of the focus ring, the curve C indicated by the symbol of the triangle, and the symbol of the inverted triangle indicate the case of the focus ring of the configuration of the present embodiment. Further, the triangular symbol indicates that the length of l shown in Fig. 2 is 1 mm, and the length of h is 3.6 mm; the symbol of the inverted triangle indicates that the length of l shown in Fig. 2 is 2 mm, and the length of h is 3.6mm case.

As shown in Fig. 5 (a) and (b), when the focus ring shown in Fig. 7 is used, the inclination of the electric field in the peripheral portion of the semiconductor wafer W becomes large; at the maximum, θ is 82. Degree is about; that is, it is inclined to the inside by about 8 degrees. On the other hand, in the present embodiment, as shown in Figs. 5(a) and 5(c), θ is about 88 degrees even in the largest case; that is, the inclination toward the inside can be suppressed to the maximum. It is about 2 degrees.

Further, in practice, a hole is formed in the semiconductor wafer W by etching, and the inclination of the hole from the vertical is measured, and as a result, the result is approximately the same as the result of the tilt of the electric field.

As described above, according to the present embodiment, it is possible to reduce the occurrence of deposition on the back surface side of the peripheral portion of the semiconductor wafer, and to suppress the tilt of the electric field in the peripheral portion of the semiconductor wafer, even if it is conventionally In the peripheral portion of the semiconductor wafer, approximately vertical etching can be performed, and the in-plane uniformity of the processing can be improved.

Further, by configuring the focus ring 8 to have the inclined portion 10b and the flat portion 10a as described above, the life of the focus ring 8 can be increased. That is, by adopting the above configuration, when the focus ring 8 (upper member 10) is consumed, it is possible to suppress a decrease in the height of the plasma sheath above the focus ring 8, even when the focus ring 8 has consumed a certain degree. The incident angle of ions at the peripheral portion of the semiconductor wafer W can be maintained in the vicinity of the vertical.

Hereinafter, the influence of the consumption of the focus ring on the plasma sheath and the influence of the incidence angle of ions on the surface of the semiconductor wafer W will be described.

First, as shown in FIG. 6, regarding the focus ring 101 whose top surface is flat, the height of the top surface and the incident angle of ions in the peripheral portion of the semiconductor wafer W are investigated (indicated by broken arrows in the figure) The relationship between.

Further, the specific process to be investigated is a process of forming contact holes, through holes, and the like; the pressure is about 2 to 11 Pa, the RF power density on the high frequency side is 3 to 5 W, and the RF power density on the low frequency side is 3. ~5W, the temperature of the semiconductor wafer W is 80 to 120 ° C, the distance between the electrodes is 25 to 70 mm, and the gas system is C ₄ F ₆ or C ₅ F ₈ /C _x H _y F _z (C ₂ F ₆ )/Ar /O ₂ : A process such as 30 to 50/10 to 30/500 to 1500/30 to 50 sccm.

The thickness of the plasma sheath formed above the semiconductor wafer W (200-300 mm in diameter) formed in the above process is about 3 mm, so the incident angle of ions is about the upper end of the plasma sheath from the thickness of 3 mm. The argon ions incident at a position of 1 mm around the circumference of the circle W are based on the incident position on the surface of the semiconductor wafer W, that is, the case of being vertically incident, and the diametrical direction from the origin. The amount of displacement is evaluated. In addition, in Fig. 6, the displacement in the left direction is set to negative in the drawing, and the displacement in the right direction is set to positive.

In the above case, the height of the top surface of the focus ring (the processing surface (surface) of the semiconductor wafer W is the origin, the forward direction indicates the positive direction, and the downward direction indicates the negative direction) is +0.3 mm. The amount of displacement at the incident position is +0.03 mm; and when the height of the top surface of the focus ring is -0.4 mm, the amount of displacement of the incident position of the ions is -0.05 mm.

Therefore, the amount of displacement of the incident position of the ions is in the range of +0.03 mm to -0.05 mm, and the life of the focus ring is assumed to be compared.

Furthermore, as described above, the top surface is a flat focus ring 101, and the displacement amount of the incident position of the ions is in the range of +0.03 to -0.05 mm, since the height of the top surface of the focus ring is +0.3. In the range of mm to -0.4 mm, in the initial state, when the height of the focus ring 101 is set to +0.3 mm, the consumption of the top surface of the focus ring should be exchanged at 0.7 mm.

Next, the same shape as the focus ring 8 described above, that is, a focus ring having a flat portion and an inclined portion on the top surface thereof, and 1 and h shown in Fig. 2 are changed, and the top surface of the focus ring (the surface of the flat portion) is explained. The result of the relationship between the height t between the processing surface of the semiconductor wafer W and the amount of displacement of the incident position of the ions. Furthermore, the focus ring system assumes that a similar shape is consumed from the initial state.

Fig. 7 shows that in the case where the above l is 3 mm (the thickness of the plasma sheath is the same), it is investigated that h is set to 0.5 mm (curve A), 1.0 mm (curve B), 1.5 mm (curve C), 2.0 mm ( A graph showing the relationship between the height t and the displacement amount in the case of curve D), 2.5 mm (curve E), 3.0 mm (curve F); in the figure, the vertical axis indicates the incident position of the ions The displacement amount (mm) and the horizontal axis indicate the height t (mm) of the top surface of the focus ring. Further, for comparison, a case where the top surface of the focus ring 101 is flat is indicated by a broken line in the drawing.

As shown in the figure, the deeper the h is, the slower the inclination of the curve is, and the change in the amount of displacement of the ions when the height of the top surface of the focus ring changes is small. Therefore, in the above range, the deeper h is, the longer the life of the focus ring becomes, and the longer the exchange period can be. Furthermore, if the result shown in Fig. 7 is represented by a numerical value, then

In the case of h=0.5, the allowable range of height t: -0.3 to +0.55 mm (0.85 mm)

In the case of h=1.0, the allowable range of height t: -0.1 to +0.8 mm (0.9 mm) h = 1.5, the allowable range of height t: 0 to +1.0 mm (1.0 mm)

In the case of h=2.0, the allowable range of height t: 0 to +1.1 mm (1.1 mm)

In the case of h=2.5, the allowable range of height t: 0 to +1.1 mm (1.1 mm)

In the case of h=3.0, the allowable range of height t: 0 to +1.2 mm (1.2 mm)

As described above, when l is set to 3 mm which is the same as the thickness of the plasma sheath, even if h is 0.5 mm, the allowable range of the height t is 0.85 mm; and the case where the top surface is a flat focus ring (allowing of the height t) Compared with the range of 0.7mm), it is obvious that there is a significant effect. Moreover, by setting h to 3.0 mm, the allowable range of the height t becomes 1.2 mm, and the allowable range of the height t can be expanded to about 1.7 times as compared with the case where the top surface is a flat focus ring.

Further, when the above h is 3.0 mm, the height of the initial focus ring top surface is t = +1.2 mm. Therefore, the initial height of the portion (the inner peripheral end portion) having the lowest height among the inclined portions is at a height of 1.2 mm - 3.0 mm = -1.8 mm when the height of the processed surface of the semiconductor wafer W is used as a reference. And at a position lower than the height of the processing surface of the semiconductor wafer W.

Fig. 8 shows the case where h is set to 6 mm (two times the thickness of the plasma sheath), and h is set to 0.5 mm (curve A), 1.0 mm (curve B), 1.5 mm (curve C), and 2.0. A graph showing the relationship between the height t and the displacement amount in the case of mm (curve D), 2.5 mm (curve E), and 3.0 mm (curve F); in the figure, the vertical axis indicates the incidence of ions The displacement amount (mm) of the position and the horizontal axis indicate the height t (mm) of the top surface of the focus ring. Further, for comparison, a case where the top surface of the focus ring 101 is flat is indicated by a broken line in the drawing.

As shown in the figure, when l is set to 6 mm, the same as the case where l is set to 3 mm, the deeper the h is, the slower the inclination of the curve is, and the amount of displacement of the ions when the height of the top surface of the focus ring changes is changed. The change is less.

Furthermore, if the result shown in Fig. 8 is represented by a numerical value, then

In the case of h=0.5, the allowable range of height t: -0.3 to +0.65 mm (0.95 mm)

In the case of h=1.0, the allowable range of height t: 0 to +1.0 mm (1.0 mm)

In the case of h=1.5, the allowable range of height t: +0.2 to +1.3 mm (1.1 mm)

In the case of h=2.0, the allowable range of height t: +0.3 to +1.6 mm (1.3 mm)

In the case of h=2.5, the allowable range of height t: +0.4 to +2.0 mm (1.6 mm)

In the case of h=3.0, the allowable range of height t: +0.5 to +2.1 mm (1.6 mm)

As described above, when l is set to be twice the thickness of the plasma sheath, that is, 6 mm, even if h is 0.5 mm, the allowable range of the height t is 0.95 mm; the case where the top surface is a flat focus ring (height) Compared with the allowable range of t (0.7 mm), it is obvious that there is a significant effect. Moreover, by setting h to 2.5 to 3.0 mm, the allowable range of the height t becomes 1.6 mm, and the allowable range of the height t can be expanded to twice or more as compared with the case where the top surface is a flat focus ring.

Further, in the related art, for example, the integration (accumulation) time of the processing time is about 400 hours, and the focus ring is exchanged. Therefore, the exchange time of such a focus ring can be extended to the extent of 800 hours or more.

Fig. 9 is a view showing a case where the vertical axis is the consumption allowable range Δ (mm) of the focus ring (F/R), and the vertical axis is h (pushing depth) (mm), and the above l is 3 mm ( In the figure, it is represented by a square symbol) and 6 mm (indicated by a circular symbol in the figure), and the case where the push-out cutting position l estimated based on these data is 9 mm (indicated by a broken line in the figure) The relationship between.

As shown in the figure, h is within a certain depth range, and the deeper the allowable range Δ of the focus ring is larger, but when h is about 2.5 to 3.0 mm, the saturation tends to be saturated.

Further, the longer the l is, the more the consumption allowable range Δ of the focus ring tends to be larger, and it is preferable to set it at least to the same extent as the thickness of the plasma sheath (3 mm) or more, and more preferably to the thickness of the plasma sheath. 2 times (6mm) or more.

As described above, by forming the focus ring having the shape of the inclined portion and the flat portion, it is possible to increase the allowable range Δ of the focus ring. As a result, the exchange cycle of the focus ring can be made longer than in the related art, and the operation cost can be reduced and the device operation rate can be improved. Further, from the viewpoint of the long-term life of the focus ring, it is preferable to use CVD-SiC as the material thereof; in particular, it is possible to manufacture CVD-SiC having a resistivity equivalent to that of Si (1 to 30 Ω). It is desirable to use CVD-SiC having such a resistivity. When such a CVD-SiC is used to form the focus ring, electrical characteristics similar to those in the case of using Si can be obtained, and it is possible to have a life of 2 to 3 times as compared with the case of using Si.

Further, in the focus ring 8 configured as described above, the impedance of the portion of the focus ring 8 has an optimum range, and it is desirable to adjust the value of the impedance within the optimum range. Further, the focus ring 8 can be selected from the material of the lower member 9 formed of a dielectric to change its (electric) dielectric constant; or the impedance can be adjusted by changing its thickness. That is, the impedance Z can be adjusted by changing the value of the capacitance C formed by sandwiching the lower member 9. Therefore, for example, the focus ring 8 shown in Fig. 10 can be adjusted to the desired impedance by changing the capacitance C by using the lower member 9 having a reduced thickness d and providing the conductive member 30 thereunder. value. Further, by causing the conductive member 30 to be interposed between the lower member 9 and the mounting table 2, the thermal conductivity between the lower member 9 and the mounting table 2 can be improved, and the lower member 9 can be controlled to a predetermined temperature. It can prevent adverse effects on the process due to overheating. In this case, as the conductive member 30, a material having good thermal conductivity, for example, a material such as tantalum or niobium rubber is preferably used.

Here, in the lower portion of the semiconductor wafer W, an insulating member (thickness, for example, 0.6 mm) for constituting the electrostatic chuck is actually provided; and the same impedance as described above is generated by the influence of the insulating member. The impedance of the portion of the semiconductor wafer W is Z0, and if the value of the impedance Z is adjusted to (Z/Z0)=60, the area of the top surface (or the bottom surface) of the lower member 9 is set to S, the thickness is d, the dielectric constant is ε, and the dielectric constant of the vacuum is ε0. Since Z=ε0‧ε(S/d), the material of the lower member 9 is quartz (quartz), and the inner diameter is approximately In the case of 300 mm and an outer diameter of about 360 mm, the thickness is desirably set to about 5 to 10 mm, and more preferably set to 7 to 9 mm.

Next, other embodiments will be described. Fig. 11 is a view schematically showing the cross-sectional configuration of the focus ring of this embodiment. As described above, the mounting table 2 on which the semiconductor wafer W is placed is supported by the insulating plate 3, and the high-frequency power source 7 is connected to the mounting table 2.

Further, a focus ring 50 is provided on the upper peripheral portion of the mounting table 2. The focus ring 50 is an annular lower member 51 formed of a dielectric material (for example, a ceramic such as quartz or alumina or a resin such as VESPEL (registered trademark); and a lower member 51 disposed thereon. The upper portion is composed of a ring-shaped upper member 52 formed of a conductive material (for example, tantalum, carbon, SiC, or the like), and is placed so as to surround the periphery of the semiconductor wafer W, which is a substrate to be processed.

The upper member 52 is formed, for example, by a high-frequency grounding member 53 made of a conductive material such as aluminum, and is formed of a ceramic spray film (for example, Al/Al ₂ O ₃ , An insulating layer (insulating film) such as FCC (fine ceramic coating film) such as Y ₂ O ₃ is coated on the surface thereof, and is connected to a ground potential for high-frequency power. This insulating layer is formed to protect the high-frequency grounding member 53 from the influence of plasma and to prevent a direct current from flowing. That is, the insulating layer has a sufficient thickness that the direct current cannot pass, and the direct current is blocked in the insulating layer and cannot propagate. On the other hand, a high frequency (RF) that can propagate through a solid surface as a surface wave can propagate on the surface layer of the high-frequency grounding member 53. The high-frequency grounding member 53 serves as a grounding path for high-frequency grounding. . Further, a high-pass filter or a low-pass filter corresponding to a frequency for generating high-frequency power applied by the plasma may be interposed between the high-frequency grounding member 53 and the ground line in order to block the high-frequency circuit. Frequency cutoff filter, frequency attenuation filter, etc. Further, a switching means is provided between the high-frequency grounding member 53 and the ground line to move with the process method, and the high-frequency control can be controlled to be grounded or not grounded at a predetermined timing. Between the high-frequency grounding member 53 and the mounting table 2 and the outer peripheral side of the upper member 52 (upper side of the high-frequency grounding member 53), a dielectric material (for example, ceramics such as quartz or alumina) is disposed. Insulating members 54, 55 formed of a resin such as VESPEL (registered trademark). Such an insulating member 54 is for preventing the DC voltage component from leaking to the outside from the mounting table 2. Further, the insulating member 55 functions so that the plasma does not excessively expand in the outer circumferential direction, and the electric field is restricted to prevent the plasma from excessively expanding and leaking from the exhaust damper (not shown) to the exhaust side.

A graph showing a graph in which the vertical axis is a voltage and the horizontal axis is a time period is a diagram showing a state in which the semiconductor wafer W and the focus ring 50 and the potential (voltage) of the plasma change. As shown by the curve A in the figure, the potential of the semiconductor wafer W changes in accordance with the frequency (for example, 2 MHz) of the high frequency applied from the high-frequency power source 7.

On the other hand, since the upper member 52 of the focus ring 50 is grounded with respect to the high-frequency power system, its potential is constant as indicated by the straight line B. Therefore, the high frequency cycle can increase the potential difference between the semiconductor wafer W and the upper member 52 as indicated by the arrows in the figure on the positive side or on the negative side.

In the figure, the curve C indicates the change in the plasma potential, and the curve D indicates the change in the potential of the upper member 10 of the focus ring 8 shown in Fig. 2 . As shown by the curve D, in the case of the focus ring 8 shown in FIG. 2, when the high frequency cycle becomes the positive side, the potential difference between the semiconductor wafer W and the upper member 10 becomes small. By setting the upper member 52 to the ground potential with respect to the high-frequency power as described above, it is possible to suppress the fluctuation of the potential difference accompanying the high-frequency vibration.

The figure of Fig. 13(A) in which the vertical axis is the polymer thickness and the horizontal axis is the bevel position is shown as 0, 30, and 45 of the slope portion of the semiconductor wafer shown in Fig. 13(B). The result of measuring the amount of adhesion of the polymer at a position of 90 degrees. In the case of Fig. 13 (A), the solid line E is the case where the conventional focus ring 101 shown in Fig. 15 is used, the solid line F is the case where the focus ring 8 shown in Fig. 2 is used, and the solid line G is used. The case of using the focus ring 50 shown in Fig. 11 is shown. As shown in the figure, in the case where the focus ring 50 is used, the electric field intensity between the semiconductor wafer and the focus ring can be increased, thereby preventing the plasma from being wound, and since the amount of radicals therebetween can be reduced, it is better than using the focus. In the case of the ring 8, the amount of deposition of the polymer on the bevel of the wafer is more reduced.

Furthermore, in the above-described embodiment, the case where the upper member 52 is connected to the ground potential with respect to the high-frequency power by the high-frequency grounding member 53 has been described. However, the high-frequency grounding of the structure may not be used. The member 53 is connected to the ground potential by the other method with respect to the high frequency power.

Fig. 14(a) schematically shows the cross-sectional configuration of the focus ring 60 according to another embodiment. As described above, the mounting table 2 on which the semiconductor wafer W is placed is supported by the insulating plate 3, and the high-frequency power source 7 is connected to the mounting table 2.

Further, a focus ring 60 is provided on the upper peripheral portion of the mounting table 2. The focus ring 60 is an annular lower member 61 formed of a dielectric material (for example, a ceramic such as quartz or alumina or a resin such as VESPEL (registered trademark); and a lower member 61 disposed thereon. The upper portion is composed of a ring-shaped upper member 62 formed of a conductive material (for example, tantalum, carbon, SiC, etc.), and is placed so as to surround the periphery of the semiconductor wafer W, which is a substrate to be processed.

The upper member 62 is formed, for example, by a high-frequency grounding member 63 made of a conductive material such as aluminum, and is formed of a ceramic melt film (for example, Al/Al ₂ O ₃ , An insulating layer (insulating film) such as FCC (fine ceramic coating film) such as Y ₂ O ₃ is coated on the surface thereof, and is connected to a ground potential for high-frequency power. This insulating layer is formed to protect the high-frequency grounding member 63 from the influence of the plasma and to prevent the direct current from flowing. That is, the insulating layer has a sufficient thickness that the direct current cannot pass, and the direct current is blocked in the insulating layer and cannot propagate. On the other hand, a high frequency (RF) that can propagate through a solid surface as a surface wave can propagate on the surface layer of the high-frequency grounding member 63. The high-frequency grounding member 63 serves as a grounding path for high-frequency grounding. . Between the high-frequency grounding member 63 and the mounting table 2 and the outer peripheral side of the upper member 62 (upper side of the high-frequency grounding member 63), a dielectric material (for example, ceramics such as quartz or alumina) is disposed. Insulating members 64 and 65 formed of a resin such as VESPEL (registered trademark). Such an insulating member 64 is used to prevent the DC voltage component from leaking to the outside from the mounting table 2. Further, the insulating member 65 functions so that the plasma does not excessively expand in the outer circumferential direction, and the electric field is restricted to prevent the plasma from excessively expanding and leaking from the exhaust damper (not shown) to the exhaust side.

Further, in the present embodiment, a predetermined interval D is provided between the lower member 61 and the upper member 62; the predetermined interval D is approximately 0.5 mm. Moreover, the length L in the radial direction of the portion in which the lower side member 61 and the upper side member 62 face each other across the gap D is 5 to 10 mm. Further, the lower end of the upper member 62 is located at a position 1.5 to 2.5 mm (H in the drawing) higher than the top surface of the semiconductor wafer W. The reason for such a configuration is as follows.

That is, in order to reduce the slope portion of the semiconductor wafer (90°, 45°, 30° in FIG. 13(B)) and the back surface of the semiconductor wafer (0° in FIG. 13(B)) In the plasma treatment, it is desirable to maintain the temperature of the lower member 61 at a relatively low temperature, for example, a temperature lower than 100 ° C, and more preferably at a temperature lower than 70 ° C. On the other hand, the upper member 62 is desirably maintained at a relatively high temperature, for example, 250 ° C or higher in the plasma treatment. The reason for this is that the temperature of the upper member 62 is set to 250° C. or more to promote the bonding of the fluorine radical and Si, and the amount of the fluorine radical can be reduced, whereby the chemical reactivity such as photoresist or SiN is strong. In the etching application, it is possible to suppress the phenomenon that the etching rate rises in the peripheral portion of the semiconductor wafer. In this manner, in order to maintain the temperature of the lower member 61 and the temperature of the upper member 62 at different temperatures, a predetermined interval D is provided between the lower member 61 and the upper member 62. In order to increase the temperature of the upper member 62, it is necessary to increase the frequency (for example, the frequency of the lower side member 61, the upper member 62, and the high-frequency grounding member 63 from the mounting table 2 as shown by the arrow in the figure. A voltage is applied to 2 MHz), and the upper member 62 is heated by Joule heat. Therefore, it is necessary to reduce the impedance of the above path. In order to satisfy such a condition, the interval D is desirably set to about 0.5 mm.

In other words, in order to satisfy this condition, the interval D is set to about 0.5 mm, based on the application of high-frequency power of 2 MHz, in order to heat the upper member 62 to a predetermined temperature, that is, 250 ° C or more, relative to the plasma impedance Zp. At least 3 to 10 times the impedance is required. Therefore, since the high frequency is AC, the load effect is not only the resistance, but also the electrostatic capacity (capacitance) or inductance (coil), and if the impedance of these factors is integrated (for the alternating current against the component), it can be as follows Explain in general. The impedance of the joint portion between the upper member 62 and the high-frequency grounding member 63 is Z1, the impedance of the interval D is Z2, and Z2 has a high resistance of at least 10 times the impedance of Z1, from the viewpoint of self-control. The consideration is ideal, so if Z2>>Z1, Z2≧10×Z1 is set, as shown in Fig. 14(b), in order to control the formula of Z1+Z2>ZP, the impedance [Ω] can be established. It is obtained from the formula of Z=ε0S/D. (ε0 = dielectric constant of vacuum, S = area [m ² ], D = interval [m])

The surface area of the lower member 61 is different for each of the 200 mm wafer and the 300 mm wafer. Therefore, if the desired surface area of the lower member 61 is brought into the above formula, the interval D can be fundamentally determined. That is to say, not only a semiconductor wafer but also a lower member of a substrate processing apparatus that performs plasma processing on a larger-area LCD panel or the like can be applied. Thereby, the upper member 62 and the lower member 61 can be configured to have no heat transfer due to the non-contact, and the surface wave generated from the high-frequency power source 7 is a high frequency, and the capacitance is passed through the electrostatic induction principle (interval D). It is transmitted to the upper member 62. Further, when the heat insulating material is interposed between the spaces D, the dielectric constant at that place is limited according to the dielectric constant of the heat insulating material, and if the vacuum capacitor is configured as in the present embodiment, the degree of vacuum in the control chamber is controlled. Since the medium constant ε can be variably controlled, the controllability is excellent.

Further, in order to reduce heat conduction and prevent heat loss, a space may be provided between the upper member 62 and the high-frequency grounding member 63. Further, other methods may be employed as long as the lower member 61 and the upper member 62 can be controlled to the above temperature.

Further, in order to control the electric field of the peripheral portion of the semiconductor wafer to perform an approximately vertical etching as described above, as described above, the lower end structure of the upper member 62 is located 1.5 to 2.5 higher than the top surface of the semiconductor wafer W. The position of mm (H in the figure).

According to the embodiment of the above configuration, in addition to reducing the deposition amount of the polymer on the wafer slope portion, the etching rate of the photoresist can be suppressed from rising in the peripheral portion of the semiconductor wafer, and even in the semiconductor wafer The peripheral portion can also be etched approximately vertically, and the in-plane uniformity of the treatment can be improved.

(industrial use possibility)

The focus ring and the plasma processing apparatus of the present invention can be utilized in the manufacturing industry of semiconductor devices. Therefore, it has industrial applicability.

(Effect of the invention)

According to the present invention, even in the peripheral portion of the semiconductor wafer, it is possible to perform good and uniform processing in the same manner as the central portion of the semiconductor wafer, and it is possible to improve the in-plane uniformity of the processing, and it is possible to improve the in-plane uniformity of the processing. The occurrence of deposition on the back side of the peripheral portion of the semiconductor wafer is reduced.

W. . . Semiconductor wafer

1. . . Vacuum chamber

2. . . Mounting table

8. . . Focus ring

9. . . Lower member

10. . . Upper member

10a. . . Flat part

10b. . . Inclined portion

14. . . Jet head

Fig. 1 is a view showing a schematic configuration of a plasma processing apparatus according to an embodiment of the present invention.

Fig. 2 is an enlarged view showing an important part of a focus ring of the plasma processing apparatus of Fig. 1.

Figure 3 is a diagram for explaining the measurement site of deposition.

Fig. 4 shows the measurement results of the deposition in the measurement site of Fig. 3.

Figure 5 is a graph showing the angle of the electric field at various locations on the wafer.

Fig. 6 is a view for explaining a method of evaluating the amount of displacement of an incident angle of ions.

Fig. 7 is a graph showing the relationship between the amount of displacement of the incident angle of ions and the height of the focus ring.

Fig. 8 is a graph showing the relationship between the amount of displacement of the incident angle of ions and the height of the focus ring.

Fig. 9 is a view showing the relationship between the push depth and the allowable range of the consumption of the focus ring.

Fig. 10 is a view for explaining a method of adjusting the impedance.

Fig. 11 is a view showing the configuration of a focus ring according to another embodiment.

Fig. 12 is a view showing a periodic dynamic sample of potentials of respective portions.

Fig. 13 is a view showing the result of measuring the amount of adhesion to the polymer of the inclined surface of the wafer.

Fig. 14 is a view showing the configuration of a focus ring according to another embodiment.

Fig. 15 is a view showing the configuration of a conventional focus ring.

Fig. 16 is a view for explaining the state of the electric field in the focus ring of Fig. 15.

Fig. 17 is a view showing the state of an electric field and a plasma sheath in a focus ring using a dielectric.

W. . . Semiconductor wafer

2. . . Mounting table

8. . . Focus ring

9. . . Lower member

10. . . Upper member

30. . . Conductive member

Claims (16)

A focus ring is disposed on a lower electrode on which a substrate to be processed is placed in a processing chamber for accommodating a substrate to be processed and subjected to predetermined plasma treatment, and may surround the periphery of the substrate to be processed The annular focus ring of the aspect is characterized by comprising: a lower member formed of a dielectric; an upper member formed of an electrically conductive material disposed on an upper portion of the lower member; and a top surface of the upper member An inclined portion whose outer peripheral side is higher than the inner peripheral side is formed, and an outer peripheral end portion of the inclined portion is formed at least at a position higher than a processed surface of the substrate to be processed, and is disposed in the foregoing The peripheral portion of the substrate to be processed is spaced apart by a predetermined interval; and the height h of the outer peripheral side of the inclined portion of the surface to be processed of the substrate to be processed is set to be in a range of 0 < h ≦ 6 mm, and the lower electrode is An electrically conductive member is provided between the lower member and the lower member. The focus ring according to claim 1, wherein the conductive member is made of tantalum or niobium rubber. The focus ring according to the first or second aspect of the invention, wherein the outer peripheral side of the inclined portion is formed to be a flat portion higher than a surface to be processed of the substrate to be processed. The focus ring of claim 1 or 2, wherein the conductive material is tantalum, carbon or SiC. The focus ring according to claim 1 or 2, wherein an outer peripheral side of the inclined portion with respect to a surface to be processed of the substrate to be processed The height h is formed in the range of 2≦h≦4mm. The focus ring according to the first or second aspect of the invention, wherein the length l of the inclined portion in the longitudinal section of the upper member is in the range of 0.5 mm ≦ 9 9 mm. The focus ring according to claim 1 or 2, wherein the predetermined interval C1 between the upper member and the peripheral portion of the substrate to be processed is set to be within a range of 0.3 mm ≦ C1 ≦ 1.5 mm. The focus ring according to claim 1 or 2, wherein the lower member is a high frequency combination of the plasma and the lower electrode, and the impedance is increased for a high frequency applied to the lower electrode. A plasma processing apparatus, characterized in that: a processing chamber for accommodating a substrate to be processed and performing a predetermined plasma treatment; and a lower electrode, the lower electrode is disposed in the processing chamber, and a substrate to be processed; a lower member formed of a dielectric, being an annular member, disposed on the lower electrode, and surrounding the periphery of the substrate to be processed; and an upper member; The upper member is disposed at an upper portion of the lower member, and the annular member formed of a conductive material has an inclined portion whose outer peripheral side is higher than the inner peripheral side on the top surface thereof, and an outer peripheral side of the inclined portion. The end portion is configured to be located at least higher than the processed surface of the substrate to be processed, and is disposed to be spaced apart from the peripheral portion of the substrate to be processed by a predetermined interval; The height h of the outer peripheral side of the inclined portion of the surface to be processed of the substrate to be processed is set to be in a range of 0 < h ≦ 6 mm, and a conductive member is provided between the lower electrode and the lower member. . The plasma processing apparatus according to claim 9, wherein the conductive member is made of tantalum or niobium rubber. The plasma processing apparatus according to claim 9 or 10, wherein an outer peripheral side of the inclined portion of the upper member is a flat portion higher than a surface to be processed of the substrate to be processed. The plasma processing apparatus according to claim 9 or 10, wherein the conductive material is tantalum, carbon or SiC. The plasma processing apparatus according to claim 9 or 10, wherein the height h of the outer peripheral side of the inclined portion with respect to the surface to be processed of the substrate to be processed is set to be in the range of 2 ≦ h ≦ 4 mm. Inside. The plasma processing apparatus according to the ninth or tenth aspect, wherein the length l of the inclined portion in the longitudinal direction of the upper member is in a range of 0.5 mm ≦ 9 9 mm. The plasma processing apparatus according to claim 9 or 10, wherein the predetermined interval C1 between the upper member and the peripheral portion of the substrate to be processed is set to be within a range of 0.3 mm ≦ C1 ≦ 1.5 mm. . The plasma processing apparatus according to claim 9 or 10, wherein the lower side member causes the plasma and the lower electrode to be combined at a high frequency, and the impedance is increased for a high frequency applied to the lower electrode. .