JP5309472B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
- Publication number
- JP5309472B2 JP5309472B2 JP2007143908A JP2007143908A JP5309472B2 JP 5309472 B2 JP5309472 B2 JP 5309472B2 JP 2007143908 A JP2007143908 A JP 2007143908A JP 2007143908 A JP2007143908 A JP 2007143908A JP 5309472 B2 JP5309472 B2 JP 5309472B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- displacement meter
- bonding head
- wiring board
- heat spreader
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Description
22 半導体チップ
31 放熱樹脂
32 ヒートスプレッダー
51 テーブル
52 ボンディングヘッド
54 エアーシリンダー(負荷制限手段)
55 本体部材
57 第1の変位計
58 第2の変位計
59 第3の変位計
61 フィラー
Claims (2)
- 配線基板上に半導体チップをフリップチップボンドする工程と、
前記半導体チップをフリップチップボンドした前記配線基板をテーブル上に搭載し、ヒートスプレッダーをボンディングヘッドで支持する工程と、
前記テーブルに対して高さが一定の第1の変位計により、前記第1の変位計と前記ヒートスプレッダーとの高さの差aを計測する工程と、
前記ボンディングヘッドに対して高さが一定の第2の変位計により、前記第2の変位計と前記半導体チップの裏面との高さの差bを計測する工程と、
前記半導体チップの裏面に放熱樹脂を塗布する工程と、
前記第1の変位計と前記第2の変位計との高さの差をc、目標とする前記放熱樹脂の厚みをdとして、前記ボンディングヘッドをa+b−c−dだけ下降させて、前記半導体チップの裏面に前記放熱樹脂を介して前記ヒートスプレッダーを接着する工程とを有し、
前記ボンディングヘッドに一定以上の負荷がかかった場合に縮んで負荷を緩和する負荷制限手段により前記ボンディングヘッドを保持し、
前記ヒートスプレッダーを接着する工程において、前記負荷制限手段を固定した本体部材を下降させることにより前記ボンディングヘッドを下降させ、
前記本体部材に対して高さが一定の第3の変位計により、前記第3の変位計と前記ボンディングヘッドとの高さの差を計測し、この差が所定値よりも縮んだ場合に前記本体部材の下降を中止することを特徴とする半導体装置の製造方法。 - 前記ヒートスプレッダーを接着する工程において、前記ボンディングヘッドに一定以上の負荷がかかった場合に前記ボンディングヘッドの下降を中止することを特徴とする請求項1に記載の半導体装置の製造方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007143908A JP5309472B2 (ja) | 2007-05-30 | 2007-05-30 | 半導体装置の製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007143908A JP5309472B2 (ja) | 2007-05-30 | 2007-05-30 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008300561A JP2008300561A (ja) | 2008-12-11 |
JP5309472B2 true JP5309472B2 (ja) | 2013-10-09 |
Family
ID=40173797
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2007143908A Expired - Fee Related JP5309472B2 (ja) | 2007-05-30 | 2007-05-30 | 半導体装置の製造方法 |
Country Status (1)
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JP (1) | JP5309472B2 (ja) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011049311A (ja) * | 2009-08-26 | 2011-03-10 | Shinko Electric Ind Co Ltd | 半導体パッケージ及び製造方法 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3116509B2 (ja) * | 1992-01-29 | 2000-12-11 | 松下電器産業株式会社 | ヒートシンクのボンディング装置およびボンディング方法 |
JPH07221138A (ja) * | 1994-02-07 | 1995-08-18 | Fujitsu Ltd | ボンディング装置及びボンディング方法 |
JP3973340B2 (ja) * | 1999-10-05 | 2007-09-12 | Necエレクトロニクス株式会社 | 半導体装置、配線基板、及び、それらの製造方法 |
JP2006049732A (ja) * | 2004-08-09 | 2006-02-16 | Sony Corp | 半導体パッケージの製造方法および半導体パッケージの製造装置 |
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2007
- 2007-05-30 JP JP2007143908A patent/JP5309472B2/ja not_active Expired - Fee Related
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Publication number | Publication date |
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JP2008300561A (ja) | 2008-12-11 |
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