JP5303330B2 - Dicing tape and semiconductor chip manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a dicing tape with which a semiconductor wafer can be diced precisely to obtain a semiconductor chip with a desired shape, so that pickup efficiency is improved. <P>SOLUTION: The dicing tape 1 includes an intermediate layer 4, a release layer 2 disposed on the side of one surface 4a of the intermediate layer 4, and a dicing layer 5 overlaid on the other surface 4b of the intermediate layer 4. The intermediate layer 4 has an adhesive portion 4B having adhesion at least in a partial region of the intermediate layer 4, and the release layer 2 and the adhesive portion 4B of the intermediate layer 4 are pasted together. The dicing layer 5 shows a heating shrinkage of &le;3.4% at 60&deg;C, and the dicing layer 5 shows a rigidness of &ge;17.5 N/25 mm at 23&deg;C. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

  The present invention relates to a dicing tape used for dicing a semiconductor wafer to obtain a semiconductor chip, and a method for manufacturing a semiconductor chip using the dicing tape.

  Conventionally, a dicing tape is used to cut a semiconductor chip from a semiconductor wafer to obtain a semiconductor chip. A dicing tape having an adhesive layer as a die bonding layer is used for die-bonding a semiconductor chip to a substrate or the like. The dicing tape having this adhesive layer is sometimes referred to as a dicing-die bonding tape.

  The following Patent Document 1 discloses an example of the dicing die bonding tape. As shown in FIG. 16, the dicing die bonding tape 101 described in Patent Document 1 includes a base sheet 102, a die attach film 103, a light release film 104, and a dicing film 105 laminated in this order. It is configured. The dicing film 105 has a base material layer 105a and an adhesive layer 105b.

  The base sheet 102 and the dicing film 105 have a region projecting laterally from the outer peripheral side surfaces of the die attach film 103 and the light release film 104. The dicing film 105 is stuck on the base material sheet 102 from the pressure-sensitive adhesive layer 105b side in a region projecting laterally from the outer peripheral side surfaces of the die attach film 103 and the light release film 104.

JP 2007-149748 A

  When dicing a semiconductor wafer using the conventional dicing-die bonding tape 101, the base sheet 102 is peeled off, and the adhesive layer 105b in the above-described overhanging region of the dicing film 105, the die attach film 103, To expose. A semiconductor wafer is attached to the exposed die attach film 103, and a dicing ring is attached to the adhesive layer 105b of the exposed dicing film 105. At the time of this pasting, a tensile stress is applied to the dicing film 105 from the center to the end so that wrinkles do not occur in the dicing film 105 and the like. For this reason, a shrinkage force is acting on the dicing film 105 after pasting. Accordingly, a shrinkage force acts on the dicing film 105 also when dicing the semiconductor wafer.

  As shown in a plan view of the semiconductor wafer in FIG. 17, the dicing line 112 may be curved after dicing even if an attempt is made to dice the semiconductor wafer 111 in a straight line due to contraction force acting on the dicing film 105. there were. Therefore, the semiconductor wafer cannot be cut with high accuracy, and a semiconductor chip having a desired shape may not be obtained.

  An object of the present invention is a dicing tape used for dicing a semiconductor wafer to obtain a semiconductor chip. The dicing tape can be diced with high accuracy, so that a semiconductor chip having a desired shape can be obtained, and the efficiency of pick-up can be obtained. It is to provide a dicing tape capable of increasing the resistance and a method for manufacturing a semiconductor chip using the dicing tape.

  According to a wide aspect of the present invention, a dicing tape used for dicing a semiconductor wafer to obtain a semiconductor chip, an intermediate layer, a release layer disposed on one surface side of the intermediate layer, A dicing layer laminated on the other surface of the intermediate layer, and the intermediate layer has an adhesive portion having adhesiveness in at least a part of the intermediate layer, and the release layer and the intermediate layer The adhesive portion of the layer is affixed, the heat shrinkage rate of the dicing layer at 60 ° C. is 3.4% or less, and the rigidity of the dicing layer at 23 ° C. is 17.5 N / 25 mm. A dicing tape as described above is provided.

  In a specific aspect of the dicing tape according to the present invention, the intermediate layer includes a non-adhesive portion having non-adhesiveness in a central region of the intermediate layer, and an outer portion of the intermediate layer surrounding the non-adhesive portion. It has the said adhesion part which has adhesiveness in an area | region.

  On the other specific situation of the dicing tape which concerns on this invention, the said intermediate | middle layer is an adhesive layer which has adhesiveness.

  In still another specific aspect of the dicing tape according to the present invention, the dicing tape further includes an adhesive layer disposed between the release layer and the intermediate layer, the release layer, the intermediate layer, and the dicing. The layer has a region that projects laterally from the outer peripheral side surface of the adhesive layer, the intermediate layer has the adhesive portion in the projecting region, and the adhesive layer In the region projecting laterally from the outer peripheral side surface, the release layer and the adhesive portion of the intermediate layer are affixed, and the adhesive layer is formed by the release layer and the intermediate layer. Covered.

  The adhesive layer is a part used as a die bonding layer. That is, the adhesive layer is a portion taken out together with the semiconductor chip when the semiconductor chip is picked up.

  In another specific aspect of the dicing tape according to the present invention, the dicing tape further includes a base material layer and an adhesive layer disposed between the release layer and the intermediate layer, and the base material layer is non-tacky. The base material layer is disposed on the intermediate layer side, and the adhesive layer is disposed on the release layer side, and the release layer, the intermediate layer, and the dicing layer are The base layer and the adhesive layer have a region projecting laterally from the outer peripheral side surface, the intermediate layer has the adhesive portion in the projecting region, the base layer and the In the region projecting laterally from the outer peripheral side surface of the adhesive layer, the release layer and the adhesive portion of the intermediate layer are attached, and the release layer and the intermediate layer The base material layer and the adhesive layer are covered.

  In still another specific aspect of the dicing tape according to the present invention, the dicing tape further includes a non-adhesive base material layer disposed between the release layer and the intermediate layer, the release layer, The intermediate layer and the dicing layer have a region projecting laterally from the outer peripheral side surface of the base material layer, the intermediate layer has the adhesive portion in the projecting region, and the base material In the region projecting laterally from the outer peripheral side surface of the layer, the release layer and the adhesive portion of the intermediate layer are attached, and the base material layer is formed by the release layer and the intermediate layer. Covered.

  The method for manufacturing a semiconductor chip according to the present invention includes a step of peeling the release layer of a dicing tape configured according to the present invention to expose the intermediate layer, and a step of peeling the release layer or the release layer. After the mold layer is peeled off, a step of laminating a semiconductor wafer on the exposed intermediate layer and attaching a dicing ring to the adhesive portion of the intermediate layer, and dicing the semiconductor wafer and dividing it into individual semiconductor chips And a step of peeling and removing the semiconductor chip after dicing.

  Further, another method for manufacturing a semiconductor chip according to the present invention includes peeling the release layer of a dicing tape configured according to the present invention, and the protruding region of the intermediate layer and the adhesive layer. And, after peeling the release layer or after peeling the release layer, laminating a semiconductor wafer on the exposed adhesive layer, and on the adhesive portion of the intermediate layer A step of attaching a dicing ring; a step of dicing the semiconductor wafer together with the adhesive layer; and dividing the semiconductor wafer into individual semiconductor chips; and the adhesive layer to which the semiconductor chip is attached after dicing. And removing the semiconductor chip together with the adhesive layer.

  Furthermore, another method for manufacturing a semiconductor chip according to the present invention includes separating the release layer of the dicing tape configured according to the present invention, and combining the protruding region of the intermediate layer and the base material layer. A step of exposing and laminating the release layer, or after peeling off the release layer, laminating a semiconductor wafer on the exposed base material layer, and attaching a dicing ring to the adhesive portion of the intermediate layer A step of attaching, a step of dicing the semiconductor wafer and dividing the semiconductor wafer into individual semiconductor chips, and a step of separating and taking out the divided semiconductor chips after dicing.

  The dicing tape according to the present invention includes a release layer, an intermediate layer, and a dicing layer, and the release layer and the adhesive portion of the intermediate layer are attached to each other, and the heat shrinkage rate of the dicing layer at 60 ° C. is 3 .4% or less and the rigidity of the dicing layer at 23 ° C. is 17.5 N / 25 mm or more, so that the semiconductor wafer can be diced with high accuracy, and thus a semiconductor chip having a desired shape can be obtained. And the pickup efficiency can be increased. Further, for example, the semiconductor wafer can be diced linearly, and the dicing line can be prevented from being curved.

  In the method for manufacturing a semiconductor chip according to the present invention, a semiconductor wafer can be diced with high accuracy, so that a semiconductor chip having a desired shape can be obtained and the efficiency of pick-up can be increased.

1A and 1B are a partially cutaway front sectional view and a partially cutaway plan view showing a dicing tape according to a first embodiment of the present invention. FIG. 2 is a plan view showing a semiconductor wafer used for manufacturing semiconductor chips. FIG. 3 is a view for explaining an example of a method of manufacturing a semiconductor chip using the dicing tape according to the first embodiment of the present invention, and is a front cross-sectional view showing a state in which the semiconductor wafer is placed on the stage FIG. FIG. 4 is a front sectional view showing a state when the release layer of the dicing tape according to the first embodiment of the present invention is peeled from the adhesive portion of the intermediate layer. FIG. 5 is a front sectional view showing a state after the release layer of the dicing tape according to the first embodiment of the present invention is peeled from the intermediate layer and the adhesive layer. FIG. 6 is a front cross-sectional view showing a state in which a semiconductor wafer is attached to an adhesive layer using the dicing tape according to the first embodiment of the present invention. FIG. 7 is a front cross-sectional view showing a state in which a semiconductor wafer attached to an adhesive layer is diced using the dicing tape according to the first embodiment of the present invention and divided into individual semiconductor chips. is there. FIG. 8 is a partially cutaway front sectional view showing a dicing tape according to a second embodiment of the present invention. FIG. 9 is a partially cutaway front sectional view showing a dicing tape according to a third embodiment of the present invention. FIG. 10 is a partially cutaway front sectional view showing a dicing tape according to a fourth embodiment of the present invention. FIG. 11 is a front sectional view showing a state in which a semiconductor wafer is divided into semiconductor chips using a dicing tape according to a fourth embodiment of the present invention. FIG. 12 is a partially cutaway front sectional view showing a dicing tape according to a fifth embodiment of the present invention. FIG. 13: is front sectional drawing which shows the state which divided | segmented the semiconductor wafer into the semiconductor chip using the dicing tape which concerns on the 5th Embodiment of this invention. FIG. 14 is a partially cutaway front sectional view showing a dicing tape according to a sixth embodiment of the present invention. FIG. 15 is a front sectional view showing a state in which a semiconductor wafer is divided into semiconductor chips using a dicing tape according to a sixth embodiment of the present invention. FIG. 16 is a partially cutaway front cross-sectional view showing a state when a release layer of a conventional dicing die bonding tape is peeled off. FIG. 17 is a plan view showing a semiconductor wafer that has been diced using a conventional dicing-die bonding tape.

  Hereinafter, the present invention will be clarified by describing specific embodiments and examples of the present invention with reference to the drawings.

(First embodiment)
The dicing tape which concerns on FIG. 1 (a) and (b) at the 1st Embodiment of this invention is shown with a partial notch front sectional drawing and a partial notch top view.

  As shown in FIGS. 1A and 1B, the dicing tape 1 includes a release layer 2, an adhesive layer 3, an intermediate layer 4, and a dicing layer 5. The adhesive layer 3 is laminated on one surface 4a of the intermediate layer 4, and the dicing layer 5 is laminated on the other surface 4b opposite to the one surface 4a of the intermediate layer 4. The release layer 2 is disposed on the one surface 4 a side of the intermediate layer 4.

  The release layer 2 is laminated and affixed on the surface 3a opposite to the surface of the adhesive layer 3 on which the intermediate layer 4 is affixed. The adhesive layer 3 is a layer used for die bonding of a semiconductor chip. The surface 3a to which the release layer 2 of the adhesive layer 3 is attached is a surface to which the semiconductor wafer is attached. Since the dicing tape 1 includes the adhesive layer 3, it is a dicing-die bonding tape. In this specification, not only a dicing tape that does not include an adhesive layer but also a dicing-die bonding tape that includes an adhesive layer is referred to as a dicing tape.

  The planar shapes of the adhesive layer 3, the intermediate layer 4, and the dicing layer 5 are circular. The outer peripheral side surface of the intermediate layer 4 is not covered with the adhesive layer 3. In the plan view, the adhesive layer 3 is smaller than the release layer 2, the intermediate layer 4, and the dicing layer 5. In plan view, the size of the dicing layer 5 is substantially equal to the size of the intermediate layer 4.

  The shape of the release layer 2 is long. In a plan view, the release layer 2 is larger than the intermediate layer 4 and the dicing layer 5. The release layer 2 has a region projecting laterally from the outer peripheral side surfaces of the intermediate layer 4 and the dicing layer 5.

  Since the adhesive layer 3 is smaller than the release layer 2 and the intermediate layer 4, the adhesive layer 3 is disposed in a partial region between the release layer 2 and the intermediate layer 4. Therefore, the release layer 2 has a portion indirectly laminated on the intermediate layer 4. The intermediate layer 4 has a non-adhesive portion 4 </ b> A having non-adhesiveness in a central region of the intermediate layer 4. The adhesive layer 3 is laminated on the non-adhesive portion 4 </ b> A of the intermediate layer 4. The non-adhesive part 4A of the intermediate layer 4 is a part corresponding to the position where the semiconductor wafer of the adhesive layer 3 is attached.

  “Non-tacky” includes not only the case where the surface is not sticky but also the case where the surface is sticky enough not to stick when touched with a finger. Specifically, “non-adhesive” means that the non-adhesive portion 4A of the intermediate layer 4 is attached to a stainless steel plate, and the non-adhesive portion 4A is peeled from the stainless steel plate at a peeling rate of 23 ° C. and 300 mm / min. Furthermore, it means that the adhesive strength is 5 g / 25 mm width or less.

  The release layer 2, the intermediate layer 4, and the dicing layer 5 have a region that protrudes laterally from the outer peripheral side surface 3 b of the adhesive layer 3. The overhanging region is a region of the outer portion of the intermediate layer 4 that surrounds the central region of the intermediate layer 4. In the region of the outer portion of the intermediate layer 4, the intermediate layer 4 has an adhesive part 4B having adhesiveness. The release layer 2 and the pressure-sensitive adhesive portion 4B of the intermediate layer 4 are attached to each other in a region protruding laterally from the outer peripheral side surface 3b of the adhesive layer 3. Therefore, the release layer 2 has a portion directly laminated on the intermediate layer 4. The adhesive layer 3 is covered with the release layer 2 and the intermediate layer 4.

  It is not always necessary that all the regions of the intermediate layer 4 projecting laterally from the outer peripheral side surface 3b of the adhesive layer 3 are adhesive portions 4B having adhesiveness. The intermediate | middle layer should just have the adhesion part which has adhesiveness in the at least one part area | region of an intermediate | middle layer. For example, in order to be able to affix a dicing ring, the intermediate layer is formed in at least a part of the region of the outer portion of the intermediate layer projecting laterally from the outer peripheral side surface 3b of the adhesive layer 3. What is necessary is just to have the adhesion part which has adhesiveness.

  Thus, by having the adhesive part 4B in which the intermediate layer 4 has adhesiveness in at least a part of the region of the intermediate layer 4 projecting laterally from the outer peripheral side surface 3b of the adhesive layer 3. During dicing, a dicing ring can be easily attached to the adhesive portion 4B of the intermediate layer 4.

  The heat shrinkage rate at 60 ° C. of the dicing layer 5 is 3.4% or less. Further, the rigidity of the dicing layer at 23 ° C. is 17.5 N / 25 mm or more.

  When dicing a semiconductor wafer using the dicing tape 1, the semiconductor wafer is attached to the adhesive layer 3 and a dicing ring is attached to the adhesive portion 4 b of the intermediate layer 4. At the time of this pasting, tensile stress is applied to the dicing layer 5 from the center to the end so that wrinkles do not occur in the dicing layer 5 and the like. Therefore, the dicing layer 5 needs to have an appropriate tensile stress. Further, by applying a tensile stress to the dicing layer 5, a shrinkage force tends to act on the dicing layer 5 after being attached. That is, when the semiconductor wafer is diced, a shrinkage force tends to act on the dicing layer 5.

  The inventors of the present application have a large relationship with the dicing properties of the semiconductor wafer, the heating shrinkage rate and the rigidity rate of the dicing layer 5, and for dicing the semiconductor wafer with high accuracy, It has been found that it is extremely important that the rigidity ratios satisfy the above ranges. That is, the main feature of the present embodiment is that the heat shrinkage rate and the rigidity rate of the dicing layer 5 satisfy the above ranges, respectively. When the heat shrinkage rate and the rigidity factor of the dicing layer 5 satisfy the above ranges, the dicing layer 5 can be appropriately stretched during bonding, and the end of the dicing of the semiconductor wafer can be reduced. Since the shrinkage force from the center portion to the center portion hardly acts on the dicing layer 5, the semiconductor wafer can be diced with high accuracy. Therefore, a semiconductor chip having a desired shape can be obtained. For example, the semiconductor wafer can be diced linearly, and the dicing line can be prevented from being curved during dicing.

  A preferable upper limit of the heat shrinkage rate at 60 ° C. of the dicing layer 5 is 3.0%. A preferable lower limit of the rigidity of the dicing layer 5 at 23 ° C. is 20.0 N / 25 mm. When the upper limit or lower limit of the heat shrinkage rate and the rigidity factor are the above values, the semiconductor wafer can be diced with higher accuracy.

  The heat shrinkage rate at 60 ° C. of the dicing layer 5 can be measured as follows.

  A dicing layer having a size of 210 mm × 297 mm is sampled so that one side is parallel to the longitudinal direction (MD) of the dicing layer. Further, the dicing layer is cut into a size of 150 mm in length and 150 mm in width. After that, 150 mm long marks are drawn on the dicing layer 5 in the vertical direction (MD) and the horizontal direction (TD), respectively. Next, after leaving still in a 60 degreeC dryer for 24 hours, the length of a marked line is measured and a heat shrinkage rate is calculated | required by the formula shown below. Further, the heat shrinkage rate in the vertical direction (MD) and the horizontal direction (TD) of the dicing layer 5 is measured, and the heat shrinkage rate in the direction with a large shrinkage rate is defined as the heat shrinkage rate of the dicing layer.

Heat shrinkage rate (%) = {(150−marked line length after heating) / 150} × 100
The rigidity of the dicing layer 5 at 23 ° C. can be measured as follows.

  The dicing layer was cut into a length (longitudinal direction (MD)) of 150 mm and a width of 25 mm, and RTC-1310A manufactured by Orientec Co., Ltd. was used at a breaking speed of the dicing layer 5 under the condition of a tensile speed of 300 mm / min. The load is measured as the rigidity.

  The non-adhesive part 4A and the adhesive part 4B of the intermediate layer 4 are integrally formed. The intermediate layer 4 can be formed using, for example, an active energy ray-curable or thermosetting adhesive composition. In the case of an active energy ray-curable composition, the adhesiveness of the intermediate layer 4 can be partially varied by partially adjusting the irradiation amount of the active energy ray with respect to the composition. The composition will be described later.

  The central region of the intermediate layer 4, that is, the non-adhesive part 4A may be an adhesive part having adhesiveness. In this case, the adhesive strength of the central region of the intermediate layer may be the same as or different from the adhesive strength of the adhesive portion 4B. However, since the semiconductor chip with the adhesive layer 3 can be more easily separated from the intermediate layer 4, the intermediate layer 4 preferably has a non-adhesive portion 4 </ b> A in the central region of the intermediate layer 4.

  As shown in FIG. 1B, a plurality of laminated bodies having an adhesive layer 3, an intermediate layer 4, and a dicing layer 5 are arranged at equal intervals on the upper surface 2a of the long release layer 2. Yes. Further, protective sheets 6 and 7 are provided on the upper surface 2 a of the release layer 2. Note that the protective sheets 6 and 7 may not be provided. Moreover, the thickness and shape of the release layer 2, the adhesive layer 3, the intermediate layer 4, and the dicing layer 5 are not particularly limited.

(Semiconductor chip manufacturing method using the dicing tape according to the first embodiment)
Next, an example of a method for manufacturing a semiconductor chip when the dicing tape 1 according to the first embodiment of the present invention described above is used will be described below with reference to FIGS.

  First, the dicing tape 1 and the semiconductor wafer 21 are prepared.

  As shown in FIG. 2, the planar shape of the semiconductor wafer 21 is circular. On the surface 21 a of the semiconductor wafer 21, circuits for forming individual semiconductor chips are formed in each region partitioned in a matrix by streets.

  The thickness of the semiconductor wafer 21 is preferably 30 μm or more. If the thickness of the semiconductor wafer 21 is thin, cracks or the like may occur during grinding or handling, and the semiconductor chip may be damaged.

  As shown in FIG. 3, the semiconductor wafer 21 is turned over, and the semiconductor wafer 21 turned over is placed on the stage 22. That is, the semiconductor wafer 21 is placed on the stage 22 from the surface 21a side. An annular dicing ring 23 is provided on the stage 22 at a position spaced apart from the outer peripheral side surface 21 c of the semiconductor wafer 21.

  Moreover, as shown in FIG. 4, the release layer 2 of the dicing tape 1 is peeled off. When the release layer 2 is peeled off, the release layer 2 is generally peeled off from the outer peripheral edge 4 c portion of the intermediate layer 4. For example, the outer peripheral edge 4c of the intermediate layer 4 is bent from the side opposite to the surface on which the intermediate layer 4 of the release layer 2 is laminated by bending the release layer 2 in the outer peripheral edge 4c portion of the intermediate layer 4. The release layer 2 can be peeled by pushing up. As shown in FIG. 5, when the release layer 2 is peeled off, the surface 3a of the adhesive layer 3 and the region of the outer portion where the intermediate layer 4 projects, that is, the adhesive portion 4B, are exposed.

  Next, as shown in FIG. 6, while peeling the release layer 2 of the dicing tape 1 or after peeling the release layer 2, the exposed surface 3 a of the adhesive layer 3 is applied to the semiconductor wafer 21. Affixed to the back surface 21b. The intermediate layer 4 has an adhesive portion 4B having adhesiveness in a region that protrudes laterally from the outer peripheral side surface 3b of the adhesive layer 3. While peeling the release layer 2 of the dicing tape 1 or after peeling the release layer 2, the exposed adhesive portion 4 </ b> B of the intermediate layer 4 is attached to the dicing ring 23.

  In plan view, the semiconductor wafer 21 is preferably smaller than the adhesive layer 3. When the size of the semiconductor wafer 21 and the adhesive layer 3 satisfies the above preferable relationship, the bonding of the semiconductor wafer 21 is facilitated, and workability can be further enhanced.

  In plan view, the adhesive layer 3 is preferably smaller than the non-adhesive portion 4A. If the magnitude | size of the adhesive layer 3 and the non-adhesion part 4A satisfy | fills the said preferable relationship, the cutting blade used for dicing will not touch the adhesion part 4B. For this reason, the adhesion part 4B adheres to a dicing blade, and a dicing blade is not contaminated. Therefore, the working efficiency of dicing and pickup can be further enhanced.

  Next, the semiconductor wafer 21 with the adhesive layer 3 attached is taken out of the stage 22 and turned over. At this time, the dicing ring 23 is taken out in a state of being attached to the adhesive portion 4B of the intermediate layer 4.

  As shown in FIG. 7, the taken-out semiconductor wafer 21 is turned over so that the surface 21 a faces upward, and is placed on another stage 24. Next, as shown by an arrow X in FIG. 7, the semiconductor wafer 21 is diced together with the adhesive layer 3 and divided into individual semiconductor chips. The semiconductor wafer 21 and the adhesive layer 3 are each cut so as to penetrate both surfaces. After cutting, a cut surface 31 is formed in the adhesive layer 3 and the intermediate layer 4.

  In the present embodiment, since the heating shrinkage rate and the rigidity factor of the dicing layer 5 are within the above ranges, the semiconductor wafer can be diced with high accuracy. For example, the semiconductor wafer 21 can be diced linearly. Specifically, as shown in FIG. 2, the semiconductor wafer 21 can be divided with high accuracy for each region partitioned in a matrix by streets.

  Dicing is not particularly limited as long as it is performed so as to penetrate the semiconductor wafer 21 and the adhesive layer 3. For example, a dicing blade may be inserted so as to reach a position deeper than the interface between the adhesive layer 3 and the intermediate layer 4 to form a cut in the intermediate layer 4.

  Examples of the method for dicing the semiconductor wafer 21 include a method using a dicing blade, a method of laser dicing, and the like.

  When the non-adhesive part 4A of the intermediate layer 4 is cured, for example, the non-adhesive part 4A is difficult to react by irradiation with laser light. For this reason, it is difficult for the intermediate layer 4 to be fused to the adhesive layer 3. Therefore, even when dicing using laser light is performed, the semiconductor chip can be picked up without difficulty.

  After the semiconductor wafer is diced and divided into individual semiconductor chips, the dicing layer 5 is extended to extend the distance between the divided individual semiconductor chips. Thereafter, the adhesive layer 3 with the semiconductor chip attached is peeled off from the intermediate layer 4 and taken out. In this way, a semiconductor chip with the adhesive layer 3 can be obtained.

  The intermediate layer 4 is preferably formed of a composition containing an acrylic polymer. The composition preferably has adhesiveness. The composition is preferably a pressure-sensitive adhesive composition. Examples of the composition include a thermosetting or active energy ray curable composition. Since the adhesive force of the intermediate layer 4 can be more easily controlled, the composition is preferably an active energy ray-curable composition.

(Details of the intermediate layer 4)
The intermediate layer 4 is preferably formed of a crosslinked body obtained by crosslinking a composition containing an acrylic polymer. In this case, the machinability during dicing can be further enhanced.

  The content of the acrylic polymer is preferably 50% by weight or more in a total of 100% by weight of the resin content in the composition. The intermediate layer formed of the composition containing the acrylic polymer is softer than the layer formed of the polyolefin resin. For this reason, the machinability at the time of dicing can be made still higher.

  The acrylic polymer is not particularly limited. The acrylic polymer is preferably a (meth) acrylic acid alkyl ester polymer. As the (meth) acrylic acid alkyl ester polymer, a (meth) acrylic acid alkyl ester polymer having an alkyl group having 1 to 18 carbon atoms is suitably used. By using a (meth) acrylic acid alkyl ester polymer having an alkyl group having 1 to 18 carbon atoms, the polarity of the intermediate layer 4 can be sufficiently reduced, the surface energy of the intermediate layer 4 can be reduced, and The peelability of the adhesive layer 3 from the intermediate layer 4 can be increased. When the carbon number of the alkyl group exceeds 18, it may be difficult to produce the intermediate layer 4. The alkyl group preferably has 6 or more carbon atoms. In this case, the polarity of the intermediate layer 4 can be further reduced. The “(meth) acrylic acid” means methacrylic acid or acrylic acid.

  The acrylic polymer is preferably a polymer obtained using a (meth) acrylic acid alkyl ester monomer having an alkyl group having 1 to 18 carbon atoms as a main monomer. The acrylic polymer is a (meth) acryl obtained by copolymerizing the main monomer, a functional group-containing monomer, and, if necessary, another modifying monomer that can be copolymerized therewith by a conventional method. More preferably, it is an acid alkyl ester polymer. The number of carbon atoms in the alkyl group of the (meth) acrylic acid alkyl ester polymer is preferably 2 or more, and particularly preferably 6 or more. The acrylic polymer has a weight average molecular weight of about 200,000 to 2,000,000.

  The other modifying monomers are not particularly limited. The other modifying monomer is preferably not a monomer having a carboxyl group. When a monomer having a carboxyl group is used, the polarity of the intermediate layer 4 is increased. As a result, the pickup property may be deteriorated.

  The (meth) acrylic acid alkyl ester monomer is not particularly limited. The (meth) acrylic acid alkyl ester monomer is an alkyl (meth) acrylate obtained by an esterification reaction between a primary or secondary alkyl alcohol having a C 1-18 alkyl group and (meth) acrylic acid. An ester monomer is preferred.

  Specific examples of the (meth) acrylic acid alkyl ester monomer include methyl (meth) acrylate, ethyl (meth) acrylate, propyl (meth) acrylate, isopropyl (meth) acrylate, and (meth) acrylic acid. Examples include n-butyl, t-butyl (meth) acrylate, 2-ethylhexyl (meth) acrylate, octyl (meth) acrylate, or lauryl (meth) acrylate. As for the said (meth) acrylic-acid alkylester monomer, only 1 type may be used and 2 or more types may be used together.

  Examples of the functional group-containing monomer include 2-hydroxyethyl (meth) acrylate, 2-hydroxypropyl (meth) acrylate, 4-hydroxybutyl (meth) acrylate, 6-hydroxyhexyl (meth) acrylate, (meth And hydroxyl group-containing monomers such as 8-hydroxyoctyl acrylate, 10-hydroxydecyl (meth) acrylate, 12-hydroxylauryl (meth) acrylate or (4-hydroxymethylcyclohexyl) methyl (meth) acrylate.

  The acrylic polymer is preferably a curable acrylic polymer having a reactive double bond. In this case, the crosslinking density of the crosslinked body obtained by crosslinking the composition containing the curable acrylic polymer can be increased. Examples of the curable acrylic polymer include a curable acrylic polymer having a reactive double bond in the side chain, main chain, or main chain terminal.

  The method for introducing a reactive double bond into the acrylic polymer is not particularly limited. Since the molecular design is easy, the reactive double bond is preferably introduced into the side chain. For example, after preparing a functional group-containing acrylic polymer obtained by copolymerizing an acrylic polymer with a functional group-containing monomer, a functional group (hereinafter referred to as functional group B) that can react with this functional group (hereinafter also referred to as functional group A). And a compound having both a reactive double bond (hereinafter, also referred to as compound C) to the functional group-containing acrylic polymer by condensation reaction or addition reaction so that the reactive double bond remains. The method to introduce is mentioned.

  Examples of the combination of the functional group A and the functional group B include a combination of a carboxyl group and an epoxy group, a carboxyl group and an aziridyl group, or a hydroxyl group and an isocyanate group. Among these combinations of functional groups, a combination of a hydroxyl group and an isocyanate group is preferable because the reaction can be easily controlled. In the combination of these functional groups, any functional group may be contained in the functional group-containing acrylic polymer, and any functional group may be contained in the compound C. A combination of a functional group-containing acrylic polymer having a hydroxyl group and the above compound having an isocyanate group is preferred.

  Examples of the isocyanate compound having an isocyanate group and a reactive double bond include methacryloyl isocyanate, 2-methacryloyloxyethyl isocyanate, 1,1-bis (acryloyloxymethyl) ethyl isocyanate, or m-isopropenyl-α, α. -Dimethyl benzyl isocyanate etc. are mentioned.

  The composition may further include an oligomer having a double bond capable of reacting with an acrylic group and having a weight average molecular weight in the range of 500 to 50,000.

  The composition may contain an ultraviolet absorber. Moreover, it is preferable that a composition contains at least one of an active energy ray reaction initiator and a thermal reaction initiator, and it is more preferable that an active energy ray reaction initiator is included. The active energy ray reaction initiator is preferably a photoreaction initiator.

  The active energy rays include ultraviolet rays, electron rays, α rays, β rays, γ rays, X rays, infrared rays and visible rays. Among these active energy rays, ultraviolet rays or electron beams are preferable because they are excellent in curability and hardened products are hardly deteriorated.

  The photoinitiator is not particularly limited. As the photoreaction initiator, for example, a photo radical generator or a photo cation generator can be used. The thermal reaction initiator is not particularly limited. Examples of the thermal reaction initiator include a thermal radical generator.

  The photo radical generator is not particularly limited. Examples of commercially available photo radical generators include Irgacure 184, Irgacure 2959, Irgacure 907, Irgacure 819, Irgacure 651, Irgacure 369, and Irgacure 379 (all of which are manufactured by Ciba Specialty Chemicals), benzoin methyl ether. Benzoin ethyl ether, benzoin isopropyl ether, and lucillin TPO (manufactured by BASF Japan).

  As the photocation generator, onium salts or organometallic complexes can be used. Examples of the onium salts include aromatic diazonium salts, aromatic halonium salts, and aromatic sulfonium salts. Examples of the organometallic complexes include iron-allene complexes, titanocene complexes, and arylsilanol-aluminum complexes.

  Examples of the thermal radical generator include organic peroxides or azo compounds. Examples of the organic peroxide include cumene hydroperoxide, diisopropylbenzene peroxide, di-t-butyl peroxide, lauryl peroxide, benzoyl peroxide, t-butylperoxyisopropyl carbonate, and t-butylperoxy-2- Examples thereof include ethyl hexanoate and t-amyl peroxy-2-ethyl hexanoate. Examples of the azo compound include 2,2′-azobis (isobutyronitrile), 1,1′-azobis (cyclohexanecarbonitrile), 2,2′-azobis (2,4-dimethylvaleronitrile), dimethyl 2, And 2'-azobis (2-methylpropionate).

  An isocyanate-based crosslinking agent may be added to the composition in order to control the adhesive force. The isocyanate-based crosslinking agent is not particularly limited. Isocyanate-based crosslinking agents include tolylene diisocyanate, diphenylmethane diisocyanate, 1,5-naphthalene diisocyanate, hexamethylene diisocyanate, isophorone diisocyanate, xylylene diisocyanate, hydrogenated xylylene diisocyanate, hydrogenated diphenylmethane diisocyanate, paraphenylene diisocyanate, tetramethylxylylene. Examples thereof include isocyanate monomers such as range isocyanate, dicyclohexylmethane diisocyanate, isophorone diisocyanate, lysine isocyanate, isopropylidenebiscyclohexyl diisocyanate, and tolidine diisocyanate. Dimers, trimers and adducts of these isocyanate monomers may be used. Examples of commercially available products of the adduct include Coronate L, Coronate HL, Coronate 2030, and Millionate MR (all of which are manufactured by Nippon Polyurethane Industry Co., Ltd.).

  The thickness of the intermediate layer 4 is not particularly limited. The thickness of the intermediate layer 4 is preferably in the range of 1 to 100 μm. A more preferable lower limit of the thickness of the intermediate layer 4 is 5 μm, and a more preferable upper limit is 60 μm. If the intermediate layer 4 is too thin, the expandability may be insufficient. If the thickness of the intermediate layer 4 is too thick, the thickness becomes non-uniform and dicing may not be performed properly.

  The intermediate layer 4 is obtained as follows using, for example, the above composition.

  For example, an adhesive composition layer for forming the intermediate layer 4 is formed on the release layer. Next, partially, at least one of irradiation of active energy rays and application of heat is performed. Alternatively, the irradiation amount or heat amount of the active energy ray is partially changed. The composition layer is cured (crosslinked) by active energy ray curing or thermal curing, or by active energy ray curing and thermal curing.

  In the central region of the intermediate layer 4 attached to the adhesive layer 3 by irradiation with active energy rays or application of heat, the non-adhesive part 4A having non-adhesiveness and the adhesive layer 3 The intermediate layer 4 having the adhesive portion 4A having adhesiveness can be obtained in the region of the intermediate layer 4 projecting laterally from the outer peripheral side surface 3a.

  It is preferable to use active energy ray curing, and it is particularly preferable to use photocuring. In the case of active energy ray curing, the non-adhesive portion 4A can be more easily formed at a desired position.

  The crosslink density of the non-adhesive part 4A is preferably higher than the crosslink density of the adhesive part 4B. When the intermediate layer 4 is formed, for example, the crosslinking density can be increased by increasing the irradiation amount of the active energy ray to the active energy ray-curable composition.

(Details of the dicing layer 5)
The dicing layer 5 is not particularly limited. As the material constituting the dicing layer 5, polyester resins such as polyethylene terephthalate resin, polytetrafluoroethylene resins, polyethylene resins, polypropylene resins, polymethylpentene resins, polyolefin resins such as polyvinyl acetate resins, polyvinyl chloride resins, Examples thereof include plastic resins such as polyimide resins.

  The thickness of the dicing layer 5 is not particularly limited. The thickness of the dicing layer 5 is preferably in the range of 10 to 200 μm. A more preferable lower limit of the thickness of the dicing layer 5 is 60 μm, and a more preferable upper limit is 150 μm. When the thickness of the dicing layer 5 is within the above range, the peelability of the release layer 2 and the expandability of the dicing layer 5 can be further enhanced.

(Details of release layer 2)
The material constituting the release layer 2 includes polyester resins such as polyethylene terephthalate resin, polytetrafluoroethylene resins, polyethylene resins, polypropylene resins, polymethylpentene resins, polyolefin resins such as polyvinyl acetate resins, and polyvinyl chloride resins. And plastic resins such as polyimide resins.

  The thickness of the release layer 2 is not particularly limited. The thickness of the release layer 2 is preferably in the range of 10 to 100 μm. A more preferable lower limit of the thickness of the release layer 2 is 25 μm, and a more preferable upper limit is 50 μm. When the thickness of the release layer 2 is within the above range, the handleability or peelability of the release layer 2 can be further enhanced.

(Details of the adhesive layer 3)
The adhesive layer 3 is used for bonding a semiconductor chip to a substrate or another semiconductor chip. The adhesive layer 3 is cut along with the semiconductor wafer during dicing.

  The adhesive layer 3 is formed of, for example, a curable resin composition containing an appropriate curable resin, a thermoplastic resin, or the like. Since the curable resin composition before curing is soft, it is easily deformed by an external force. After obtaining the semiconductor chip with the adhesive layer 3, the obtained semiconductor chip with the adhesive layer 3 is laminated on an adherend such as a substrate from the adhesive layer 3 side. Thereafter, the semiconductor chip can be firmly bonded to the adherend via the adhesive layer 3 by applying heat or light energy to cure the adhesive layer 3. A thermoplastic resin may be used instead of the curable resin.

  The curable resin is not particularly limited. Examples of the curable resin include a thermosetting resin and a photocurable resin.

  The thermosetting resin is not particularly limited. As said thermosetting resin, an epoxy resin or a polyurethane resin etc. are mentioned, for example. The said photocurable resin is not specifically limited. Examples of the photocurable resin include an epoxy resin that is polymerized by a photocationic catalyst such as a photosensitive onium salt, or an acrylic resin having a photosensitive vinyl group. As the curable resin, an epoxy resin, a polyester resin, methyl methacrylate, or a hot-melt adhesive resin is preferably used. Examples of the hot-melt adhesive resin include poly (meth) acrylate resins having butyl acrylate as a main monomer unit. As for the said curable resin, only 1 type may be used and 2 or more types may be used together.

  The epoxy resin is not particularly limited. The epoxy resin is preferably an epoxy resin having a polycyclic hydrocarbon skeleton in the main chain. The epoxy resin which has the said polycyclic hydrocarbon skeleton in a principal chain is not specifically limited. Examples of the epoxy resin having a polycyclic hydrocarbon skeleton in the main chain include dicyclopentadiene dioxide, dicyclopentadiene type epoxy resin, naphthalene type epoxy resin, tetrahydroxyphenylethane type epoxy resin, tetrakis (glycidyloxyphenyl). ) Ethane, or 3,4-epoxy-6-methylcyclohexylmethyl-3,4-epoxy-6-methylcyclohexane carbonate.

  A high molecular polymer having a functional group that reacts with the epoxy group may be used together with the curable resin. Examples of the polymer polymer having an epoxy group include an epoxy group-containing acrylic rubber, an epoxy group-containing butadiene rubber, a bisphenol type high molecular weight epoxy resin, an epoxy group-containing phenoxy resin, an epoxy group-containing acrylic resin, an epoxy group-containing urethane resin, or Examples thereof include an epoxy group-containing polyester resin. As for the high molecular polymer which has the said epoxy group, only 1 type may be used and 2 or more types may be used together.

  A curing agent is used for curing the curable resin composition. The curing agent is not particularly limited. Examples of the curing agent include heat curing acid anhydride curing agents such as trialkyltetrahydrophthalic anhydride, latent curing agents such as phenol curing agents, amine curing agents and dicyandiamide, or cationic catalyst curing. Agents and the like. As for the said hardening | curing agent, only 1 type may be used and 2 or more types may be used together. Moreover, in order to adjust the curing rate or the physical properties of the cured product, the curing agent and a curing accelerator may be used in combination.

  The thickness of the adhesive layer 3 is not particularly limited. The thickness of the adhesive layer 3 is preferably in the range of 1 to 100 μm. A more preferable lower limit of the thickness of the adhesive layer 3 is 3 μm, and a more preferable upper limit is 60 μm. When the thickness of the adhesive layer 3 is within the above range, the semiconductor chip can be more easily attached to the substrate via the adhesive layer 3, or the semiconductor device can be made thinner.

(Second Embodiment)
In FIG. 8, the dicing tape which concerns on the 2nd Embodiment of this invention is shown with a partial notch front sectional drawing. The dicing tape 51 shown in FIG. 8 is configured in the same manner as the dicing tape 1 except that the intermediate layer is different. The dicing tape 51 is a dicing-die bonding tape. The same components as those of the dicing tape 1 are denoted by the same reference numerals and description thereof is omitted.

  The dicing tape 51 includes an intermediate layer 52. In the central region of the intermediate layer 52 attached to the adhesive layer 3, the intermediate layer 52 has a non-adhesive portion 52A having non-adhesiveness. The intermediate layer 52 has a region projecting laterally from the outer peripheral side surface 3 b of the adhesive layer 3. The intermediate layer 52 has an adhesive portion 52B having adhesiveness in the region of the inner portion of the intermediate layer 52 in the overhanging region. The intermediate layer 52 has a non-adhesive portion 52C having non-adhesiveness in the region of the outer portion of the intermediate layer 52 in the overhanging region. That is, the intermediate layer 52 has a non-adhesive portion 52C in the region of the outer peripheral edge of the intermediate layer 52. The release layer 2 and the adhesive portion 52 </ b> B of the intermediate layer 52 are attached to each other in a region projecting laterally from the outer peripheral side surface 3 b of the adhesive layer 3. The adhesive layer 3 is covered with the release layer 2 and the intermediate layer 52. In plan view, the intermediate layer 52 has a non-adhesive part 52A, an adhesive part 52B, and a non-adhesive part 52C from the center to the end.

  The intermediate layer 52 can be formed of a material constituting the intermediate layer 4. For example, in order to form the non-adhesive parts 52A and 52C and the adhesive part 52B using an active energy ray-curable or thermosetting type composition, the irradiation amount or heat amount of the active energy ray applied to the composition is partially You can make them different.

(Third embodiment)
In FIG. 9, the dicing tape which concerns on the 3rd Embodiment of this invention is shown with a partial notch front sectional drawing. The dicing tape 61 shown in FIG. 9 is configured in the same manner as the dicing tape 1 except that the intermediate layer is different. The dicing tape 61 is a dicing die bonding tape.

  The dicing tape 61 includes an intermediate layer 62. The intermediate layer 62 is an adhesive part having adhesiveness. That is, the intermediate layer 62 is an adhesive layer having adhesiveness. The intermediate layer 62 has a region projecting laterally from the outer peripheral side surface 3 b of the adhesive layer 3. The release layer 2 and the adhesive intermediate layer 62 are pasted in a region projecting laterally from the outer peripheral side surface 3 b of the adhesive layer 3. The adhesive layer 3 is covered with the release layer 2 and the intermediate layer 62.

  The intermediate layer 62 can be formed of a material constituting the intermediate layer 4. For example, in order to form the intermediate layer 62 using an active energy ray curable composition or a thermosetting composition, no active energy rays or heat is applied to the composition, or active energy rays applied to the composition. What is necessary is just to reduce irradiation amount or heat amount.

  Furthermore, other specific examples of the material constituting the intermediate layer 62 include an acrylic adhesive, a special synthetic rubber adhesive, a synthetic resin adhesive, or a rubber adhesive. Of these, a pressure-sensitive acrylic pressure-sensitive adhesive is preferable. By using a pressure-sensitive acrylic pressure-sensitive adhesive, the dicing ring can be peeled off from the intermediate layer 62 more easily. Furthermore, the cost of the intermediate layer 62 can be reduced.

(Fourth embodiment)
In FIG. 10, the dicing tape which concerns on the 4th Embodiment of this invention is shown with a partial notch front sectional drawing. The dicing tape 71 shown in FIG. 10 is configured in the same manner as the dicing tape 61 except that it further includes a base material layer. The dicing tape 71 is a dicing-die bonding tape.

  The dicing tape 71 includes a base material layer 72. The base material layer 72 is disposed on the intermediate layer 62 side, and the adhesive layer 3 is disposed on the release layer 2 side. The adhesive layer 3 is smaller than the base material layer 72 in plan view. In plan view, the base material layer 72 is smaller than the intermediate layer 62, the dicing layer 5 and the release layer 2. In plan view, the adhesive layer 3 is preferably smaller than the base material layer 72.

  The base material layer 72 has non-adhesiveness. Since the adhesive layer 3 and the base material layer 72 are smaller than the release layer 2 and the intermediate layer 62, the adhesive layer 3 and the base material layer 72 are located between the release layer 2 and the intermediate layer 62. Arranged in some areas.

  The release layer 2, the intermediate layer 62, and the dicing layer 5 have regions that protrude laterally from the outer peripheral side surfaces 72 a and 3 b of the base material layer 72 and the adhesive layer 3. Since the intermediate layer 62 is entirely an adhesive portion, the intermediate layer 62 has an adhesive portion in the protruding area. In the region of the base material layer 72 and the adhesive layer 3 that protrudes laterally from the outer peripheral side surfaces 72a and 3b, the release layer 2 and the adhesive intermediate layer 62 are attached. The base material layer 72 and the adhesive layer 3 are covered with the release layer 2 and the intermediate layer 62.

  The base material layer 72 can be formed of the material constituting the intermediate layer 4 described above. For example, the base material layer 72 can be formed by using an active energy ray-curable or thermosetting composition, increasing the irradiation amount or heat amount of active energy rays, and sufficiently curing (crosslinking) the composition. .

  A preferable range of the thickness of the intermediate layer 62 in the case of including the base material layer 72 is the same as the thickness of the intermediate layer 4. Further, the thickness of the base material layer 72 is not particularly limited. The thickness of the base material layer 72 is preferably in the range of 1 to 100 μm. The minimum with more preferable thickness of the base material layer 72 is 5 micrometers, and a more preferable upper limit is 60 micrometers. If the thickness of the base material layer 72 is too thin, the expandability may be insufficient. If the thickness of the base material layer 72 is too thick, the thickness may be non-uniform. If the thickness is not uniform, dicing may not be performed properly.

  When manufacturing a semiconductor chip using the dicing tape 71, first, the release layer 2 of the dicing tape 71 is peeled off, and the region where the intermediate layer 62 that is an adhesive portion is overhanging, the adhesive layer 3, To expose. As shown in FIG. 11, while peeling the release layer 2 or after peeling the release layer 2, a semiconductor wafer is laminated on the exposed adhesive layer 3, and the intermediate layer 62 that is an adhesive portion is formed. A dicing ring 23 is attached. Next, the semiconductor wafer is diced and divided into individual semiconductor chips. After dicing, the divided semiconductor chip is peeled off and taken out.

  After dicing, the adhesive layer 3 to which the semiconductor chip is attached is laminated on a non-tacky substrate layer 72. For this reason, the semiconductor chip with the adhesive layer 3 can be easily peeled off from the base material layer 72 and taken out.

(Fifth embodiment)
In FIG. 12, the dicing tape which concerns on the 5th Embodiment of this invention is shown with a partial notch front sectional drawing. The dicing tape 81 shown in FIG. 12 is configured in the same manner as the dicing tape 71 except that it does not include an adhesive layer.

  The dicing tape 81 does not include the adhesive layer 3. Since the base material layer 72 is smaller than the release layer 2 and the intermediate layer 62, the base material layer 72 is disposed in a partial region between the release layer 2 and the intermediate layer 62.

  The release layer 2, the intermediate layer 62, and the dicing layer 5 have a region that protrudes laterally from the outer peripheral side surface 72 a of the base material layer 72. Since the intermediate layer 62 is entirely an adhesive portion, the intermediate layer 62 has an adhesive portion in the protruding area. In a region projecting laterally from the outer peripheral side surface 72a of the base material layer 72, the release layer 2 and the adhesive intermediate layer 62 are attached. The base material layer 72 is covered with the release layer 2 and the intermediate layer 62.

  When manufacturing a semiconductor chip using the dicing tape 81, first, the release layer 2 of the dicing tape 81 is peeled off to expose the region in which the intermediate layer 62 that is an adhesive portion projects and the base material layer 72. Let As shown in FIG. 13, while peeling the release layer 2 or after peeling the release layer 2, a semiconductor wafer is laminated on the exposed base material layer 72, and a dicing ring is applied to the intermediate layer 62 which is an adhesive portion. 23 is pasted. Next, the semiconductor wafer is diced and divided into individual semiconductor chips. After dicing, the divided semiconductor chip is peeled off and taken out.

(Sixth embodiment)
In FIG. 14, the dicing tape which concerns on the 6th Embodiment of this invention is shown with a partial notch front sectional drawing. A dicing tape 91 shown in FIG. 14 is configured in the same manner as the dicing tape 1 except that it does not include an adhesive layer.

  The dicing tape 91 does not include the adhesive layer 3. The release layer 2 and the adhesive portion 4B of the adhesive intermediate layer 4 are attached. Instead of the intermediate layer 4, an intermediate layer 52 or an intermediate layer 62 may be used.

  When manufacturing a semiconductor chip using the dicing tape 91, first, the release layer 2 of the dicing tape 91 is peeled to expose the intermediate layer 4. As shown in FIG. 15, a semiconductor wafer is laminated on the exposed intermediate layer 4 while peeling the release layer 2 or after peeling the release layer 2, and a dicing ring 23 is formed on the adhesive portion 4 </ b> B of the intermediate layer 4. Paste. Next, the semiconductor wafer is diced and divided into individual semiconductor chips. After dicing, the divided semiconductor chip is peeled off and taken out.

  Hereinafter, the present invention will be specifically described by giving examples and comparative examples. The present invention is not limited to the following examples.

Example 1
95 parts by weight of 2-ethylhexyl acrylate, 5 parts by weight of 2-hydroxyethyl acrylate, 0.2 parts by weight of Irgacure 651 (manufactured by Ciba Geigy, 50% ethyl acetate solution) as a photo radical generator, and 0.01 parts by weight of lauryl mercaptan Was dissolved in ethyl acetate to obtain a solution. Polymerization was performed by irradiating this solution with ultraviolet rays to obtain an ethyl acetate solution of the polymer. Furthermore, with respect to 100 parts by weight of the solid content of this solution, 3.5 parts by weight of 2-methacryloyloxyethyl isocyanate (manufactured by Showa Denko Co., Ltd., Karenz MOI) was reacted to produce a copolymer of (meth) acrylic resin crosslinked. Coalescence was obtained. The acrylic copolymer had a weight average molecular weight of 700,000 and an acid value of 0.86 (mgKOH / g).

  100 parts by weight of the obtained acrylic copolymer, 2 parts by weight of U-324A (manufactured by Shin-Nakamura Chemical Co., Ltd., urethane acrylic oligomer), 1 part by weight of Irgacure 651 (manufactured by Ciba Geigy) as a photo radical generator, and Coronate L 0.5 part by weight (manufactured by Nippon Polyurethane Industry Co., Ltd., isocyanate crosslinking agent) was blended and dissolved in ethyl acetate to obtain a composition. This composition was applied onto a release PET film using an applicator and heat-dried at 110 ° C. for 3 minutes to form a film-shaped composition layer having a thickness of 20 μm. A dicing layer was bonded to this composition layer and stored at 40 ° C. for 24 hours to obtain a laminate. The dicing layer was manufactured to a thickness of 60 μm (DC1) by a T-die method using LDPE (manufactured by Prime Polymer, M12) as a raw material. The surface of the dicing layer on which the intermediate layer was bonded was subjected to corona treatment.

  Further, G-2050M (Nippon Yushi Co., Ltd., epoxy group-containing acrylic polymer, weight average molecular weight Mw 200,000) 15 parts by weight, EXA-7200HH (Dainippon Ink Co., Ltd., dicyclopentadiene type epoxy resin) 80 wt. Parts, HP-4032D (manufactured by Dainippon Ink, Naphthalene-type epoxy resin), 35 parts by weight YH-309 (Japan Epoxy Resin, acid anhydride curing agent), 2MAOK-PW (Shikoku) 8 parts by weight of Kasei Co., Ltd. (imidazole) and 2 parts by weight of S320 (manufactured by Chisso Corporation, aminosilane) were blended to obtain a blend. This blend was applied onto PET38CS manufactured by Lintec so as to have a thickness of 40 μm with an applicator, and dried by heating at 110 ° C. for 3 minutes to obtain an adhesive layer.

  The release PET film of the obtained laminate was peeled off, and the exposed composition layer was bonded to the adhesive layer on PET38CS to obtain a laminate. Next, an intermediate layer was formed by irradiating the central region of the composition layer with ultraviolet light of 365 nm at 2000 mJ under a high-pressure mercury lamp. The ultraviolet irradiation part was made larger than the adhesive layer. In a region projecting laterally from the outer peripheral side surface of the adhesive layer, an ultraviolet non-irradiated portion as an adhesive portion was bonded onto PET 38CS, and an ultraviolet irradiated portion was laminated on PET 38CS. A dicing tape was thus obtained.

(Example 2)
A dicing tape was obtained in the same manner as in Example 1 except that the thickness of the dicing layer was changed to 50 μm (DC2).

(Example 3)
A dicing tape was obtained in the same manner as in Example 1, except that the raw material for the dicing layer was changed to HDLE (3300F manufactured by Prime Polymer Co., Ltd.) and the thickness of the dicing layer was changed to 50 μm (DC3).

(Comparative Example 1)
A dicing tape was obtained in the same manner as in Example 1 except that the thickness of the dicing layer was changed to 40 μm (DC4).

(Comparative Example 2)
A dicing tape was obtained in the same manner as in Example 1 except that the dicing layer was changed to PE tape (6318B) manufactured by Sekisui Chemical Co., Ltd. and the thickness of the dicing layer was changed to 60 μm (DC5).

(Evaluation of heat shrinkage)
A dicing layer having a size of 210 mm × 297 mm was sampled so that one side was parallel to the longitudinal direction (MD) of the dicing layer. Further, the dicing layer was cut into a size of 150 mm in length and 150 mm in width. Next, a marked line having a length of 150 mm was drawn in the vertical direction (MD) and the horizontal direction (TD) on the dicing layer. Next, after leaving still in a 60 degreeC dryer for 24 hours, the length of the marked line was measured and the heat shrinkage rate was calculated | required by the formula shown below. Further, the heat shrinkage rate in the vertical direction (MD) and the horizontal direction (TD) of the dicing layer was measured, and the heat shrinkage in the direction with a large shrinkage rate was defined as the heat shrinkage rate of the dicing layer.

Heat shrinkage rate (%) = {(150−marked line length after heating) / 150} × 100
(Evaluation of rigidity)
The dicing layer was cut into a length (longitudinal direction (MD)) of 150 mm and a width of 25 mm, and the load at the breaking point of the dicing layer under the condition of a tensile speed of 300 mm / min using RTC-1310A manufactured by Orientec Co., Ltd. Was measured as the rigidity.

(Calfline shift evaluation)
Whether or not the groove (dicing line) at the time of dicing is curved was evaluated based on the movement amount of the semiconductor chip divided by dicing (shift amount of the kerf line).

  Using the obtained dicing tape, the release PET film was peeled off with a die sheet bonding machine DAM-812MS manufactured by Takatori, and the exposed adhesive layer was 8 inches in diameter and 80 μm in thickness at a feed rate of 45 mm / second. An evaluation sample was prepared by laminating on one surface of the silicon wafer at a temperature of 60 ° C. Further, a dicing ring was bonded to the intermediate layer so that the evaluation sample could be diced.

  Dicing was performed using a dicing apparatus DFD651 (manufactured by Disco Corporation) at a feed rate of 50 mm / sec to a chip size of an evaluation sample of 10 mm × 10 mm. Dicing was performed parallel and perpendicular to the longitudinal direction of the dicing layer.

  The amount of shift of the kerf line of the evaluation sample with the dicing ring after dicing was measured for all the dicing lines, and the one with the largest movement amount was defined as the amount of shift of the kerf line of the evaluation sample.

  The kerf line shift amount is preferably 0 mm. If the kerf line shift amount is within 0.080 mm, it can be picked up without any problem. Moreover, if the shift amount of the kerf line is larger than 0.080 mm, the pickup efficiency is lowered.

(Evaluation of pickup)
After dicing, using a die bonder best D-02 (manufactured by Canon Machinery Co., Ltd.), the divided semiconductor chips were continuously picked up under the conditions of a collet size of 8 mm square, a push-up speed of 5 mm / second, and an expand of 4 mm. Of the 100 semiconductor chips, the number of semiconductor chips that could not be picked up was counted.

  The results are shown in Table 1 below.

DESCRIPTION OF SYMBOLS 1 ... Dicing tape 2 ... Release layer 2a ... Upper surface 3 ... Adhesive agent layer 3a ... Surface 3b ... Outer peripheral side surface 4 ... Intermediate | middle layer 4a ... One side 4b ... Other side 4c ... Outer periphery 4A ... Non-adhesive part 4B ... Adhesive part 5 ... Dicing layer 6,7 ... Protective sheet 21 ... Semiconductor wafer 21a ... Front side 21b ... Back side 21c ... Outer peripheral side 22 ... Stage 23 ... Dicing ring 24 ... Stage 31 ... Cut surface 51 ... Dicing tape 52 ... Intermediate layer 52A ... 1st non-adhesive part 52B ... Adhesive part 52C ... 2nd non-adhesive part 61 ... Dicing tape 62 ... Intermediate layer 71 ... Dicing tape 72 ... Base material layer 72a ... Outer peripheral side surface 81 ... Dicing tape 91 ... Dicing tape

Claims (9)

A dicing tape used for dicing a semiconductor wafer to obtain a semiconductor chip,
The middle layer,
A release layer disposed on one side of the intermediate layer;
A dicing layer laminated on the other surface of the intermediate layer,
The intermediate layer has an adhesive portion having adhesiveness in at least a part of the intermediate layer, and the release layer and the adhesive portion of the intermediate layer are attached,
A dicing tape in which the heat shrinkage rate at 60 ° C. of the dicing layer is 3.4% or less, and the rigidity rate at 23 ° C. of the dicing layer is 17.5 N / 25 mm or more.   The intermediate layer includes a non-adhesive portion having non-adhesiveness in a central region of the intermediate layer, and the adhesive portion having adhesive properties in a region of an outer portion of the intermediate layer surrounding the non-adhesive portion. The dicing tape according to claim 1.   The dicing tape according to claim 1 or 2, wherein the intermediate layer is an adhesive layer having adhesiveness. Further comprising an adhesive layer disposed between the release layer and the intermediate layer,
The release layer, the intermediate layer, and the dicing layer have a region projecting laterally from the outer peripheral side surface of the adhesive layer,
The intermediate layer has the adhesive portion in the protruding area,
In the region projecting laterally from the outer peripheral side surface of the adhesive layer, the release layer and the adhesive portion of the intermediate layer are pasted, and the release layer and the intermediate layer The dicing tape according to claim 1, wherein the adhesive layer is covered. Further comprising a base material layer and an adhesive layer disposed between the release layer and the intermediate layer,
The substrate layer has non-adhesiveness,
The base material layer is disposed on the intermediate layer side, and the adhesive layer is disposed on the release layer side;
The release layer, the intermediate layer, and the dicing layer have a region projecting laterally from the outer peripheral side surface of the base material layer and the adhesive layer,
The intermediate layer has the adhesive portion in the protruding area,
The release layer and the adhesive portion of the intermediate layer are affixed in a region projecting laterally from the outer peripheral side surfaces of the base material layer and the adhesive layer, and the release layer and The dicing tape according to claim 1, wherein the base layer and the adhesive layer are covered with the intermediate layer. A base layer disposed between the release layer and the intermediate layer and having non-adhesiveness;
The release layer, the intermediate layer, and the dicing layer have a region projecting laterally from the outer peripheral side surface of the base material layer,
The intermediate layer has the adhesive portion in the protruding area,
The release layer and the adhesive portion of the intermediate layer are attached to each other in a region projecting laterally from the outer peripheral side surface of the base material layer, and the base layer is formed by the release layer and the intermediate layer. The dicing tape according to claim 1, wherein the material layer is covered. Peeling the release layer of the dicing tape according to claim 1 to expose the intermediate layer;
Laminating a semiconductor wafer on the exposed intermediate layer while peeling the release layer or after peeling the release layer, and attaching a dicing ring to the adhesive portion of the intermediate layer;
Dicing the semiconductor wafer and dividing it into individual semiconductor chips;
A method of manufacturing a semiconductor chip, comprising: a step of peeling and removing the semiconductor chip after dicing. Peeling the release layer of the dicing tape according to claim 4 or 5 to expose the protruding region of the intermediate layer and the adhesive layer;
A step of laminating a semiconductor wafer on the exposed adhesive layer while peeling off the release layer or after peeling off the release layer, and attaching a dicing ring to the adhesive portion of the intermediate layer; ,
Dicing the semiconductor wafer together with the adhesive layer, and dividing into individual semiconductor chips,
A method of manufacturing a semiconductor chip, comprising: after dicing, peeling off the adhesive layer to which the semiconductor chip is attached and taking out the semiconductor chip together with the adhesive layer. Peeling the release layer of the dicing tape according to claim 6 to expose the protruding region of the intermediate layer and the base material layer;
A step of laminating a semiconductor wafer on the exposed base layer while peeling the release layer or after peeling the release layer, and attaching a dicing ring to the adhesive portion of the intermediate layer;
Dicing the semiconductor wafer and dividing it into individual semiconductor chips;
A method of manufacturing a semiconductor chip, comprising: a step of peeling and removing the divided semiconductor chip after dicing.

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