JP5282431B2 - Circuit board and manufacturing method thereof - Google Patents

Circuit board and manufacturing method thereof Download PDF

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JP5282431B2
JP5282431B2 JP2008089522A JP2008089522A JP5282431B2 JP 5282431 B2 JP5282431 B2 JP 5282431B2 JP 2008089522 A JP2008089522 A JP 2008089522A JP 2008089522 A JP2008089522 A JP 2008089522A JP 5282431 B2 JP5282431 B2 JP 5282431B2
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electrode
conductive
insulating resin
semiconductor element
particles
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JP2009246078A (en
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圭史郎 岡本
剛 石塚
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Fujitsu Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Conductive Materials (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a means for enhancing the reliability of connections between a semiconductor element and a wiring substrate by avoiding poor electrical connections between an electrode of the semiconductor element and an electrode of the wiring substrate and shortage between the adjacent electrodes, in flip chip implementation. <P>SOLUTION: A circuit substrate includes: a wiring substrate 13 which includes a first electrode 14; a semiconductor device 17 which includes a second electrode 16 in a surface thereof and is arranged on the wiring substrate so that the second electrode is opposed to the first electrode; and a conductive adhesive which is arranged between the wiring substrate and the semiconductor element. The conductive adhesive consists of: a first insulating resin 12; and conductive particles 11 which are dispersed within the first insulating resin and cover a surface of a core particle 1 with a conductive film 2 and a second insulating resin 3, in sequence. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

本発明は半導体素子が配線基板へのフリップチップ実装に関する。 The present invention relates to flip chip mounting of a semiconductor element on a wiring board.

近年、半導体素子の電極端子は、半導体素子の回路規模に応じて、数個から数千個形成される。このような状況の中で、半導体素子の電極端子を高密度に実装する要求が高まっており、即ち端子間隔は小さくなる方向へ推移している。このため、ワイヤ・ボンディング実装に代わって、フリップチップ実装方式が注目されている。   In recent years, several to several thousand electrode terminals of a semiconductor element are formed depending on the circuit scale of the semiconductor element. Under such circumstances, there is an increasing demand for mounting the electrode terminals of the semiconductor element at a high density, that is, the terminal interval is decreasing. For this reason, a flip chip mounting method has attracted attention in place of wire bonding mounting.

フリップチップ実装方式とは、半導体素子をフェイスダウン(半導体素子の回路面を下向き)にした状態で、半導体素子を配線基板に実装する方式である。このフリップ実装方式では、一般に、バンプと呼ばれる突起状の端子によって、半導体素子と配線基板とが電気的に接続される。このような接続方法としては、はんだバンプによる接続、金バンプ圧着、或いは、導電性接着剤による接続等が既に実施されている。   The flip chip mounting method is a method of mounting a semiconductor element on a wiring board in a state where the semiconductor element is face-down (the circuit surface of the semiconductor element faces downward). In this flip mounting method, generally, a semiconductor element and a wiring board are electrically connected by protruding terminals called bumps. As such a connection method, a connection using a solder bump, a gold bump pressure bonding, a connection using a conductive adhesive, or the like has already been performed.

また、対向端子間の電気的接続後、隣接端子間の隙間から液状樹脂(アンダーフィル)を流入させることにより、外部環境からの保護及び接続信頼性の向上に寄与させている。   Further, after the electrical connection between the opposing terminals, a liquid resin (underfill) is caused to flow from the gap between the adjacent terminals, thereby contributing to protection from the external environment and improvement in connection reliability.

しかしながら、対向部品の間隙及び隣接端子間隙が小さくなることにより、当該アンダーフィル材を流入させることが難しくなってきている。そのため、アンダーフィルの流入は必要としない実装方法が提案されている。   However, as the gap between the opposing parts and the gap between adjacent terminals become smaller, it becomes difficult to allow the underfill material to flow in. Therefore, a mounting method that does not require inflow of underfill has been proposed.

この方法では、予め半導体素子を搭載する配線基板領域に導電性接着剤を塗布し、半導体素子の電極と配線基板の電極との位置を合わせた後、熱圧着により接合する。
特開平11−203938号公報 特開平11−251368号公報 特開平11−12494号公報
In this method, a conductive adhesive is applied in advance to a wiring board region on which a semiconductor element is mounted, the positions of the electrodes of the semiconductor element and the wiring board are aligned, and then bonded by thermocompression bonding.
Japanese Patent Laid-Open No. 11-203938 Japanese Patent Laid-Open No. 11-251368 Japanese Patent Laid-Open No. 11-12494

このような導電性接着剤においては、熱膨張率を調節するために、無機フィラーを所定の量で混合することが必要であるが、無機フィラーを多数混合すると、半導体素子の電極や配線基板の電極と導電粒子間に無機フィラーが挟まりやすくなり、接続抵抗値の上昇や断線の原因となる。このような問題を回避するために、無機フィラーの混合量を制限すると、熱膨張率の低減が不十分となり、接続信頼性が低下する。   In such a conductive adhesive, in order to adjust the coefficient of thermal expansion, it is necessary to mix an inorganic filler in a predetermined amount. However, when a large number of inorganic fillers are mixed, an electrode of a semiconductor element or a wiring board is mixed. Inorganic fillers are likely to be sandwiched between the electrode and the conductive particles, which causes an increase in connection resistance and disconnection. In order to avoid such a problem, if the mixing amount of the inorganic filler is limited, the thermal expansion coefficient is not sufficiently reduced, and the connection reliability is lowered.

従って、半導体素子の電極と配線基板の電極の電気接続性および隣接電極間の絶縁性に優れ、接続信頼性にも優れたフリップチップ実装構造が望まれている。   Therefore, a flip-chip mounting structure that is excellent in electrical connection between the electrode of the semiconductor element and the electrode of the wiring board, insulation between adjacent electrodes, and excellent in connection reliability is desired.

上記問題を解決するために、本発明の一観点によれば、本発明の回路基板は、第1の電極を備える配線基板と、表面に第2の電極を備え、前記第2の電極が前記第1の電極と対向するように、前記配線基板上に配置された半導体素子と、前記配線基板と前記半導体素子との間に配置される導電性接着剤とを有し、前記導電性接着剤は、第1の絶縁性樹脂と、
前記第1の絶縁性樹脂の内部に分散して存在し、コア粒子の表面に導電膜と第2の絶縁性樹脂とを順に被覆した導電粒子とを含む。
In order to solve the above problem, according to one aspect of the present invention, a circuit board according to the present invention includes a wiring board including a first electrode, a second electrode on a surface, and the second electrode includes the second electrode. A semiconductor element disposed on the wiring board so as to face the first electrode; and a conductive adhesive disposed between the wiring board and the semiconductor element, the conductive adhesive Is a first insulating resin;
Conductive particles that are dispersed inside the first insulating resin and have the surface of the core particles coated with a conductive film and a second insulating resin in order.

また、本発明の他の観点によれば、本発明の導電性接着剤は、第1の絶縁性樹脂と、前記第1の絶縁性樹脂の内部に分散して存在し、コア粒子の表面に導電膜と第2の絶縁性樹脂とを順に被覆した導電粒子とを含む。   According to another aspect of the present invention, the conductive adhesive of the present invention is present in a dispersed manner in the first insulating resin and the first insulating resin, and on the surface of the core particle. The conductive particle which coat | covered the electrically conductive film and 2nd insulating resin in order is included.

更に、本発明の他の観点によれば、本発明の回路基板の製造方法は、第1の絶縁樹脂と、コア粒子の表面に導電膜と第2の絶縁性樹脂とが順に被覆された導電粒子とを混合し、導電性接着剤を形成する工程と、表面に第1の電極を備えた配線基板を形成する工程と、表面に第2の電極を備えた半導体素子を形成する工程と、前記導電性接着剤を、前記配線基板の表面或いは前記半導体素子の表面に塗布する工程と、前記第1の電極と前記第2の電極とを位置合わせした状態で加熱及び押圧し、前記第1の電極と前記第2の電極との間を前記導電性接着剤を介して電気的に接合する工程とを備える。   Furthermore, according to another aspect of the present invention, the circuit board manufacturing method of the present invention includes a first insulating resin, and a conductive material in which a conductive film and a second insulating resin are sequentially coated on the surface of the core particles. Mixing a particle to form a conductive adhesive; forming a wiring substrate having a first electrode on a surface; forming a semiconductor element having a second electrode on a surface; The step of applying the conductive adhesive to the surface of the wiring substrate or the surface of the semiconductor element, and heating and pressing in a state where the first electrode and the second electrode are aligned, Electrically connecting the second electrode and the second electrode via the conductive adhesive.

本発明によれば、半導体素子の電極と配線基板の電極との電気接続不良および隣接電極間の短絡を避けることができるとともに、半導体素子と配線基板の接続信頼性を高めることができる。更に、配線基板の熱膨張率の低減も同時にできるようになる。   ADVANTAGE OF THE INVENTION According to this invention, while being able to avoid the electrical connection failure of the electrode of a semiconductor element and the electrode of a wiring board and the short circuit between adjacent electrodes, the connection reliability of a semiconductor element and a wiring board can be improved. Furthermore, the thermal expansion coefficient of the wiring board can be reduced at the same time.

以下は、本発明の実施形態について、添付の図面を参照して具体的に説明する。   Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

図1(a)は本発明の実施例に係る回路基板を示す平面図であり、図1(b)は図1(a)のX−X’により切断した断面を示す図である。また、図1(c)は図1(a)中の導電粒子の拡大図である。   FIG. 1A is a plan view showing a circuit board according to an embodiment of the present invention, and FIG. 1B is a view showing a cross section taken along line X-X ′ of FIG. Moreover, FIG.1 (c) is an enlarged view of the electrically-conductive particle in Fig.1 (a).

図1(b)に示すように、本実施例の回路基板10は、例えばBTレジン配線基板13上に半導体素子17が実装された構造を有している。半導体素子17は、基板15に形成された回路面17cを当該配線基板13側に向けた状態で、即ち、フェイスダウン状態で配線基板13に実装されている。回路面17cには、電極パッド16が形成されている。     As shown in FIG. 1B, the circuit board 10 of this embodiment has a structure in which a semiconductor element 17 is mounted on, for example, a BT resin wiring board 13. The semiconductor element 17 is mounted on the wiring substrate 13 with the circuit surface 17c formed on the substrate 15 facing the wiring substrate 13 side, that is, in a face-down state. Electrode pads 16 are formed on the circuit surface 17c.

また、半導体素子17が実装される配線基板13の一方の主面には、電極パッド14が形成されている。なお、配線基板13の面積は、例えば、40mm×40mmの大きさを有している。   An electrode pad 14 is formed on one main surface of the wiring board 13 on which the semiconductor element 17 is mounted. In addition, the area of the wiring board 13 has a size of 40 mm × 40 mm, for example.

配線基板13と半導体素子17との隙間には、第1の絶縁性樹脂12が充填されている。第1の絶縁性樹脂12に、導電粒子11が分散され、配線基板13側の電極パッド14と半導体素子17側の電極パッド16とが導電粒子11を介して接続されている。   A gap between the wiring substrate 13 and the semiconductor element 17 is filled with the first insulating resin 12. Conductive particles 11 are dispersed in the first insulating resin 12, and the electrode pads 14 on the wiring board 13 side and the electrode pads 16 on the semiconductor element 17 side are connected via the conductive particles 11.

図1(c)に示すように、導電粒子11は、無機粒子1をコアとして、導電膜2、第2絶縁性樹脂3の順に被覆された形態を有している。   As shown in FIG. 1C, the conductive particles 11 have a form in which the conductive particles 2 and the second insulating resin 3 are coated in this order with the inorganic particles 1 as the core.

なお、本実施例では、第1の絶縁性樹脂12及び導電粒子11を含むものを、導電性接着剤と呼ぶ。   In the present embodiment, a material including the first insulating resin 12 and the conductive particles 11 is referred to as a conductive adhesive.

導電粒子11は、その外表面が第2の絶縁性樹脂3によって被覆されているので、圧力を掛けない状態では、絶縁性を示している。しかし、後の部分で述べるように、実装工程を施すと、縦方向に繋がっている導電粒子11により、配線基板13側の電極パッド14と半導体素子側の電極パッド16とが電気的に接続される。   Since the outer surface of the conductive particle 11 is covered with the second insulating resin 3, the conductive particle 11 exhibits insulating properties when no pressure is applied. However, as will be described later, when the mounting process is performed, the electrode pads 14 on the wiring board 13 side and the electrode pads 16 on the semiconductor element side are electrically connected by the conductive particles 11 connected in the vertical direction. The

一方、横方向には圧力が存在しないため、横方向に繋がっている導電粒子11の第2絶縁性樹脂3が溶けることがない。即ち、横方向に並んでいる導電粒子同士11が、お互いに接触しても、横方向で絶縁性を保つことが可能となる。   On the other hand, since there is no pressure in the lateral direction, the second insulating resin 3 of the conductive particles 11 connected in the lateral direction does not melt. That is, even if the conductive particles 11 arranged in the horizontal direction are in contact with each other, it is possible to maintain the insulation in the horizontal direction.

更に、無機粒子1は導電粒子のコアとなっているので、無機粒子1が半導体素子17の電極パッド16や配線基板13の電極パッド14と直接接触することがない。従って、接続抵抗値の上昇を避けることができる。それと同時に、無機粒子1の存在は、配線基板13の熱膨張率を下げる効果があるので、導電粒子の他に無機フィラーを入れる必要がなくなる。   Furthermore, since the inorganic particles 1 are the core of the conductive particles, the inorganic particles 1 do not directly contact the electrode pads 16 of the semiconductor element 17 or the electrode pads 14 of the wiring board 13. Therefore, an increase in connection resistance value can be avoided. At the same time, the presence of the inorganic particles 1 has the effect of lowering the coefficient of thermal expansion of the wiring board 13, so that it is not necessary to add an inorganic filler in addition to the conductive particles.

以下、本発明の回路基板を製造する方法について、添付の図面を参照して具体的に説明する。   Hereinafter, a method for manufacturing a circuit board according to the present invention will be specifically described with reference to the accompanying drawings.

図2(a)乃至図2(c)は実施例1に係る回路基板を製造する方法の工程順に示す断面図である。   FIG. 2A to FIG. 2C are cross-sectional views shown in the order of steps of the method of manufacturing the circuit board according to the first embodiment.

まず最初に、導電粒子11を作成する。   First, conductive particles 11 are created.

導電粒子11のコア粒子1としては、例えば、シリカ(SiO2)、アルミナ(Al23)等の非導電性無機粒子を用いる。更に、このようなシリカやアルミナ粒子の他に、ガラス粒子、その他種々のセラミックス粒子、FRP(繊維強化プラスチック)粒子等も使用可能である。 As the core particles 1 of the conductive particles 11, for example, non-conductive inorganic particles such as silica (SiO 2 ) and alumina (Al 2 O 3 ) are used. In addition to such silica and alumina particles, glass particles, other various ceramic particles, FRP (fiber reinforced plastic) particles, and the like can also be used.

コア粒子1の形状は特に制限されない。真球状、粒状、塊状、破砕状、多孔質状、凝集状、フレーク状、スパイク状、フィラメント状、ファイバー状、ウイスカー状など、用途に応じて各種形状の粒子が使用できる。一般的には、使用する際の電気伝導度のバラツキを小さくする上で、できるだけ粒径の揃った真球状の粉末を使用するのが望ましい。   The shape of the core particle 1 is not particularly limited. Various shapes of particles can be used depending on the application, such as true spherical shape, granular shape, massive shape, crushed shape, porous shape, aggregated shape, flake shape, spike shape, filament shape, fiber shape, whisker shape and the like. In general, it is desirable to use a true spherical powder having as uniform a particle size as possible in order to reduce the variation in electrical conductivity during use.

また、コア粒子1の直径としては、例えば、1〜20umの範囲で、平均としては、10um程度が望ましい。   In addition, the diameter of the core particle 1 is, for example, in the range of 1 to 20 μm, and preferably about 10 μm on average.

コア粒子の表面に導電膜2をコートするには、金属を無電解めっき、スパッタリング、蒸着などの公知の方法が使用できる。金属の種類としては、Ag、Au、Ni、Cu、Pt、Pd、Snなどが挙げられるが、導電性とコスト面よりAgが最も好ましい。なお、これらは1種を単独で、又は2種以上を組み合わせて用いることもできる。   In order to coat the conductive film 2 on the surface of the core particles, a known method such as electroless plating, sputtering, or vapor deposition of a metal can be used. Examples of the metal include Ag, Au, Ni, Cu, Pt, Pd, and Sn. Ag is most preferable from the viewpoint of conductivity and cost. In addition, these can also be used individually by 1 type or in combination of 2 or more types.

導電膜の外側に絶縁被覆を形成する方法としては、次のような公知の手法を使用することができる。例えば、有機溶媒や分散剤による化学変化を利用した湿式方式、機械エネルギーによる物理化学的変化を利用した乾式方式(具体的に、噴霧法、高速撹拌法、スプレードライヤー法)などが挙げられる。   As a method of forming an insulating coating on the outside of the conductive film, the following known methods can be used. For example, a wet method using a chemical change by an organic solvent or a dispersant, a dry method using a physicochemical change by mechanical energy (specifically, a spray method, a high-speed stirring method, a spray dryer method) and the like can be mentioned.

なお、被覆される絶縁性樹脂3は、チオール基、ジスルフィド基、シラノール基、アミノ基、水酸基、カルボキシル基などのうちいずれかの官能基のうち、少なくとも一つを含む化合物であればよい。   The insulating resin 3 to be coated may be a compound containing at least one of functional groups among any of thiol groups, disulfide groups, silanol groups, amino groups, hydroxyl groups, carboxyl groups and the like.

また、絶縁性樹脂3は、熱可塑性あるいは熱硬化性のものでよい。絶縁性樹脂3に使用可能な樹脂としては、例えば、ポリエチレン、アクリロニトリル、スチレン、ポリブタジエン、エチルセルロース、ポリエステル、ポリアミド、ポリウレタン、天然ゴム、シリコン系ゴム、ポリクロロプレンなどの合成ゴム類、ポリビニルエーテルなどが挙げられる。   The insulating resin 3 may be thermoplastic or thermosetting. Examples of resins that can be used for the insulating resin 3 include polyethylene, acrylonitrile, styrene, polybutadiene, ethyl cellulose, polyester, polyamide, polyurethane, natural rubber, silicone rubber, synthetic rubber such as polychloroprene, and polyvinyl ether. It is done.

更に、絶縁性樹脂3は、絶縁性樹脂12に混ぜやすくするため、絶縁性樹脂12と同様に親水性あるいは疎水性を有することが望ましい。   Further, the insulating resin 3 is desirably hydrophilic or hydrophobic like the insulating resin 12 so as to be easily mixed with the insulating resin 12.

次に、半導体素子と配線基板を封止する絶縁性樹脂12を作製する。   Next, an insulating resin 12 for sealing the semiconductor element and the wiring board is produced.

半導体素子と配線基板を封止する絶縁性樹脂12は、例えば、マイクロカプセル型のエポキシとイミダゾール系からなる硬化剤(イミダゾール変性体を核とし、その表面をポリウレタンで被覆してなるマイクロカプセル型硬化剤を、ビスフェノールF型エポキシ樹脂中に分散してなる硬化剤)、及びメルカプタン系硬化剤を含む。   The insulating resin 12 for sealing the semiconductor element and the wiring board is, for example, a microcapsule type epoxy and imidazole-based curing agent (microcapsule type curing having an imidazole modified as a core and a surface coated with polyurethane. A curing agent formed by dispersing the agent in a bisphenol F-type epoxy resin), and a mercaptan curing agent.

具体的には、硬化剤は、例えば、大日本インキ化学工業社製のナフタレン型エポキシ“HP−4032D” (商品名)40重量部、大日本インキ化学工業社製のビスフェノールF型エポキシ“EXA−830LVP” (商品名)30重量部、ADEKA社製のビスフェノールF型エポキシ“EP−3020” (商品名)30重量部、旭化成ケミカルズ社製のマイクロカプセル型イミダゾール系硬化剤“LSA−H0206”(商品名)25重量部、及び、ジャパンエポキシレジン社製のメルカプタン系硬化剤“QX−40”(商品名)50重量部の各材料を混合したものである。   Specifically, the curing agent is, for example, 40 parts by weight of naphthalene type epoxy “HP-4032D” (trade name) manufactured by Dainippon Ink & Chemicals, Inc., bisphenol F type epoxy “EXA-” manufactured by Dainippon Ink & Chemicals, Inc. "830LVP" (trade name) 30 parts by weight, ADEKA bisphenol F type epoxy "EP-3020" (trade name) 30 parts by weight, microcapsule type imidazole curing agent "LSA-H0206" (product) Name) 25 parts by weight and 50 parts by weight of a mercaptan-based curing agent “QX-40” (trade name) manufactured by Japan Epoxy Resin Co., Ltd. are mixed.

次いで、導電性接着フィルムを作製する。   Next, a conductive adhesive film is produced.

上記作製された絶縁性樹脂12と65重量部の導電粒子11とを混合、撹拌し、導電性接着剤を作製した。この導電性接着剤をシート状に作製し、導電性接着フィルム20を作製した。   The insulating resin 12 produced above and 65 parts by weight of the conductive particles 11 were mixed and stirred to produce a conductive adhesive. This conductive adhesive was produced in a sheet shape, and a conductive adhesive film 20 was produced.

導電性接着剤の接着界面の接着性改質や、耐熱性、耐湿性を向上するために、カップリング剤を適量添加してもよい。カップリング剤は、シランカップリング剤、チタンカップリング剤、ジルコニウムカップリング剤、またはアルミニウムカップリング剤などを使用することができる。   An appropriate amount of a coupling agent may be added in order to improve adhesion at the bonding interface of the conductive adhesive, heat resistance, and moisture resistance. As the coupling agent, a silane coupling agent, a titanium coupling agent, a zirconium coupling agent, an aluminum coupling agent, or the like can be used.

シランカップリング剤としては、有機官能基が、例えばビニル基、エポキシ基、ニトロ基、メタクリル基、アミノ基、メルカプト基、イソシアナト基、カルボキシル基、水酸基のうち少なくとも一つを含み、また、加水分解性基が、例えばクロル基、アルコキシ基、アセトキシ基、イソプロペノキシ基、アミノ基のうち少なくとも一つを含む化合物を用いることができる。   As the silane coupling agent, the organic functional group contains, for example, at least one of a vinyl group, an epoxy group, a nitro group, a methacryl group, an amino group, a mercapto group, an isocyanato group, a carboxyl group, and a hydroxyl group. For example, a compound in which the functional group contains at least one of a chloro group, an alkoxy group, an acetoxy group, an isopropenoxy group, and an amino group can be used.

即ち、シランカップリング剤としては、3−メルカプトプロピルトリメトキシシラン以外にも、例えばビニルトリクロルシラン、ビニルメトキシシラン、ビニルトリス(2メトキシエトキシ)シラン、ビニルトリエトキシシラン、ビニルトリメトキシシラン、3−(メタクリロキシプロピル)トリメトキシシラン、2−(3、4エポキシシクロヘキシル)3−グリシドキシプロピル3メチルジエトキシシラン、N−2(アミノエチル)3−アミノプロピルトリメトキシシラン、N−2(アミノエチル)3−アミノプロピルメチルジメトキシシラン、3−アミノプロピルトリメトキシシラン、3−アミノプロピルトリエトキシシラン、N−フェニル−3−アミノプロピルトリメトキシシラン、3−クロロプロピルトリメトキシシラン等のうち少なくとも一つを用いてもよい。   That is, as the silane coupling agent, in addition to 3-mercaptopropyltrimethoxysilane, for example, vinyltrichlorosilane, vinylmethoxysilane, vinyltris (2methoxyethoxy) silane, vinyltriethoxysilane, vinyltrimethoxysilane, 3- ( Methacryloxypropyl) trimethoxysilane, 2- (3,4-epoxycyclohexyl) 3-glycidoxypropyl 3-methyldiethoxysilane, N-2 (aminoethyl) 3-aminopropyltrimethoxysilane, N-2 (aminoethyl) ) Less than 3-aminopropylmethyldimethoxysilane, 3-aminopropyltrimethoxysilane, 3-aminopropyltriethoxysilane, N-phenyl-3-aminopropyltrimethoxysilane, 3-chloropropyltrimethoxysilane, etc. It may be used one also.

次に、サイズが8.5×8.5mm2で周辺に約120個の金電極パッド16を設置した半導体素子17を準備し、更に、半導体素子17の金電極パッド16と同じ配置の電極パッドを有する40×40mm2のBTレジン配線基板13を準備した。 Next, a semiconductor element 17 having a size of 8.5 × 8.5 mm 2 and having about 120 gold electrode pads 16 disposed in the periphery is prepared. Further, the electrode pads having the same arrangement as the gold electrode pads 16 of the semiconductor element 17 are prepared. A 40 × 40 mm 2 BT resin wiring board 13 having the following structure was prepared.

次いで、図2(a)に示すように、配線基板13の電極パッド14が設置されている領域に上記の導電性接着フィルム20をラミネートして貼り付けた。ラミネートする際の圧力、温度、及び時間は、それぞれ1MPa、60−80℃、30秒に設定した。   Next, as shown in FIG. 2A, the conductive adhesive film 20 was laminated and attached to the region where the electrode pads 14 of the wiring substrate 13 were installed. The pressure, temperature, and time for laminating were set to 1 MPa, 60-80 ° C., and 30 seconds, respectively.

その後、図2(b)に示すように、フェイスダウンの半導体素子17の金電極パッド16と配線基板13の電極パッド14との位置合わせを行った。   Thereafter, as shown in FIG. 2B, the gold electrode pad 16 of the face-down semiconductor element 17 and the electrode pad 14 of the wiring board 13 were aligned.

続いて、図2(c)に示すように、半導体素子17を配線基板13に圧接した。圧接時の圧力は、例えば、3MPaであった。同時に、ボンダ装置のチップ加熱ツールに半導体素子を保持し、150℃で約10秒にて導電性接着フィルムを硬化させた。   Subsequently, as shown in FIG. 2C, the semiconductor element 17 was pressed against the wiring board 13. The pressure at the time of press contact was 3 MPa, for example. At the same time, the semiconductor element was held on the chip heating tool of the bonder apparatus, and the conductive adhesive film was cured at 150 ° C. for about 10 seconds.

このような加熱、加圧工程により、縦方向に繋がっている導電粒子11の第2絶縁性樹脂3(具体的には、電極パッド16と導電粒子11との間の第2の絶縁性樹脂3、導電粒子11と導電粒子11との間の第2の絶縁性樹脂3、及び配線基板電極パッド14と導電粒子11との間の第2の絶縁性樹脂3)が溶けることにより、導電粒子の導電膜2を介して、配線基板13側の電極パッド14と半導体素子側の電極16とが電気的に接続される。   By such heating and pressurizing processes, the second insulating resin 3 of the conductive particles 11 connected in the vertical direction (specifically, the second insulating resin 3 between the electrode pad 16 and the conductive particles 11). The second insulating resin 3 between the conductive particles 11 and the conductive particles 11 and the second insulating resin 3) between the wiring board electrode pad 14 and the conductive particles 11 are melted, so that the conductive particles Via the conductive film 2, the electrode pad 14 on the wiring substrate 13 side and the electrode 16 on the semiconductor element side are electrically connected.

以上の工程により、本実施例に係るフリップチップ型回路基板を作製した。   The flip chip type circuit board according to this example was manufactured through the above steps.

上記回路基板の配線基板13側の引き出し配線を用いて接合部の導通を試験した結果、全ての接合部について導通していることが確認できた。さらに、−25℃〜125℃の温度サイクル試験において、−25℃、30min〜+125℃、30minを1サイクルとし、これを 1000サイクル繰り返す熱サイクル試験を行った。その結果、本実施例に係る回路基板では接続抵抗変化率が+5%以下であった。   As a result of testing the continuity of the joint using the lead wiring on the wiring board 13 side of the circuit board, it was confirmed that all the joints were conducting. Furthermore, in the temperature cycle test of -25 ° C to 125 ° C, a cycle of -25 ° C, 30min to + 125 ° C, 30min was set as one cycle, and a thermal cycle test was repeated for 1000 cycles. As a result, in the circuit board according to this example, the connection resistance change rate was + 5% or less.

なお、出来るだけ封止用絶縁性樹脂の熱膨張率を配線基板や半導体素子の熱膨張率に近づけ、配線基板や半導体素子への応力を減らすために、熱膨張率が異なるコアを持つ二種類以上の導電粒子を用いてもよい。熱膨張率が比較的に大きいコア粒子を内包する高熱膨張率導電粒子を配線基板の近くのフィルム部分に配置し、熱膨張率が比較的に小さいコア粒子を内包する低熱膨張率導電粒子を半導体素子の近くのフィルム部分に配置すればよい。   In order to make the thermal expansion coefficient of the insulating resin for sealing as close as possible to the thermal expansion coefficient of the wiring board or semiconductor element, and to reduce the stress on the wiring board or semiconductor element, there are two types with cores with different thermal expansion coefficients. The above conductive particles may be used. High thermal expansion conductive particles that contain core particles with a relatively high coefficient of thermal expansion are placed in the film portion near the wiring board, and low thermal expansion coefficient conductive particles that contain core particles with a relatively low thermal expansion coefficient are used as semiconductors. What is necessary is just to arrange | position to the film part near an element.

また、本実施例では、電極パッドを半導体素子の周辺に配置する場合を示したが、半導体素子の中心部に配置してもよい。
(比較例1)
導電性接着剤において、導電粒子として、Ni粉末5重量部の材料を用いた。更に、フィラーとして、アルミナ粉末60重量部を用いた。これらのものを混合、攪拌し、導電性接着剤を作製した。
In this embodiment, the electrode pad is arranged around the semiconductor element. However, the electrode pad may be arranged at the center of the semiconductor element.
(Comparative Example 1)
In the conductive adhesive, 5 parts by weight of Ni powder was used as the conductive particles. Furthermore, 60 parts by weight of alumina powder was used as a filler. These were mixed and stirred to prepare a conductive adhesive.

実施例1と同様のフリップチップ型回路基板を作製してから、実施例1と同様にして、導通を測定した。その結果、導通のない接合部が存在した。導通のない接合部は、FE−SEM観察の結果、半導体素子の電極パッドとNi粉末の間にアルミナ粉末が挟まっていることが確認された。   A flip-chip circuit board similar to that in Example 1 was produced, and then continuity was measured in the same manner as in Example 1. As a result, there was a non-conductive junction. As a result of FE-SEM observation, it was confirmed that alumina powder was sandwiched between the electrode pad of the semiconductor element and the Ni powder in the non-conductive joint.

次に、本実施例について説明する。実施例2では、導電性接着剤に使用する材料及び作製する方法などが実施例1と相違している。   Next, this embodiment will be described. In Example 2, the material used for the conductive adhesive, the manufacturing method, and the like are different from those in Example 1.

本実施例に係る回路基板を製造する方法の工程は図2(a)乃至図2(c)と同じであるため、先に説明した部分に対応する部分には同一の参照符号を付し、説明を省略する。   Since the steps of the method of manufacturing the circuit board according to the present embodiment are the same as those shown in FIGS. 2A to 2C, the same reference numerals are given to the portions corresponding to the portions described above, Description is omitted.

実施例2に使用される導電性接着剤は、下記の方法で作製することができる。   The conductive adhesive used in Example 2 can be produced by the following method.

大日本インキ化学工業社製のビスフェノールF型エポキシ“EXA830CRP”(商品名)100重量部、アミノメチルフェノールのトリグリシジルエーテル15重量部、四国化成社製のアジンアダクトされたイミダゾール系硬化剤“キュアゾールC11Z−A” (商品名)7.5重量部、及び旭化成社製のマイクロカプセル型イミダゾール系硬化剤“ノバキュアHX3721” (商品名)7.5重量部の各材料を混合してから、実施例1で作製された導電粒子65重量部を混合、撹拌して、導電性接着剤を作製した。   100 parts by weight of bisphenol F type epoxy “EXA830CRP” (trade name) manufactured by Dainippon Ink & Chemicals, Inc., 15 parts by weight of triglycidyl ether of aminomethylphenol, azine adducted imidazole-based curing agent “Curazole C11Z-” manufactured by Shikoku Kasei Co., Ltd. In Example 1, 7.5 parts by weight of A ″ (trade name) and 7.5 parts by weight of microcapsule type imidazole curing agent “Novacure HX3721” (trade name) manufactured by Asahi Kasei Co., Ltd. were mixed. 65 parts by weight of the produced conductive particles were mixed and stirred to produce a conductive adhesive.

次に、上記方法で作製された導電性接着剤12を実施例1と同様の配線基板13に塗布し、配線基板13を60℃に設定したボンダ装置の基板ステージに設置した。約10分間放置した後、フェイスダウンの半導体素子17の金電極パッド16と配線基板13の電極パッド14との位置合わせを行った。   Next, the conductive adhesive 12 produced by the above method was applied to the same wiring substrate 13 as in Example 1, and the wiring substrate 13 was placed on the substrate stage of the bonder apparatus set at 60 ° C. After leaving for about 10 minutes, the gold electrode pad 16 of the face-down semiconductor element 17 and the electrode pad 14 of the wiring board 13 were aligned.

その後、30℃、0.15秒間の条件で、半導体素子17の電極パッド16を配線基板13の電極パッド14に超音波接合する。その後、ボンダ装置のチップ加熱ツールに半導体素子を保持し、180℃で約3秒にて導電性接着剤を硬化させた後、本実施例に係るフリップチップ型回路基板を作製した。   Thereafter, the electrode pad 16 of the semiconductor element 17 is ultrasonically bonded to the electrode pad 14 of the wiring board 13 under the conditions of 30 ° C. and 0.15 seconds. Thereafter, the semiconductor element was held on the chip heating tool of the bonder apparatus, and the conductive adhesive was cured at 180 ° C. for about 3 seconds, and then the flip chip type circuit board according to this example was manufactured.

次に、実施例1と同様にして、接合部の導通を試験した結果、全ての接合部について導通していることが確認できた。さらに、−25℃〜125℃の温度サイクル試験において、−25℃、30min〜+125℃、30minを1サイクルとし、これを 1000サイクル繰り返す熱サイクル試験を行った。その結果、本発明の回路基板では接続抵抗変化率が+5%以下であった。   Next, in the same manner as in Example 1, as a result of testing the continuity of the joint, it was confirmed that all the joints were conductive. Furthermore, in the temperature cycle test of -25 ° C to 125 ° C, a cycle of -25 ° C, 30min to + 125 ° C, 30min was set as one cycle, and a thermal cycle test was repeated for 1000 cycles. As a result, in the circuit board of the present invention, the connection resistance change rate was + 5% or less.

以上のように作成した導電性接着剤又は導電性接着フィルムは、半導体素子17の電極パッド16と配線基板13の電極パッド14の間に導電性が現れるが、他の方向では導電性が現れない。従って、このような導電性接着剤又は導電性接着フィルムは、異方導電性接着剤又は導電性接着フィルムとも呼ぶ。
(比較例2)
導電性接着剤において、導電粒子として、Au粉末を5重量部の材料を用いた。更に、フィラーとして、アルミナ粉末を60重量部を用いた。これらのものを混合、攪拌し、導電性接着剤を作製した。
The conductive adhesive or conductive adhesive film prepared as described above exhibits conductivity between the electrode pad 16 of the semiconductor element 17 and the electrode pad 14 of the wiring substrate 13, but does not exhibit conductivity in other directions. . Therefore, such a conductive adhesive or a conductive adhesive film is also called an anisotropic conductive adhesive or a conductive adhesive film.
(Comparative Example 2)
In the conductive adhesive, 5 parts by weight of Au powder was used as the conductive particles. Furthermore, 60 parts by weight of alumina powder was used as a filler. These were mixed and stirred to prepare a conductive adhesive.

実施例2と同様のフリップチップ型回路基板を作製してから、実施例2と同様にして、導通を測定した。その結果、接続抵抗値は実施例2の5倍であった。さらに、−25℃〜125℃の温度サイクル試験において、−25℃、30min〜+125℃、30minを1サイクルとし、これを 1000サイクル繰り返す熱サイクル試験を行った結果、本発明の回路基板では接続抵抗変化率が+10%であった。   A flip-chip circuit board similar to that of Example 2 was produced, and then continuity was measured in the same manner as in Example 2. As a result, the connection resistance value was five times that of Example 2. Furthermore, in the temperature cycle test of -25 ° C to 125 ° C, a cycle of -25 ° C, 30min to + 125 ° C, 30min was set as one cycle. The rate of change was + 10%.

以上、実施例に沿って本発明を説明したが、本発明はこれらの実施例に限られるものではない。例えば、種々の置換、変更、改良、組み合わせなどが可能であることは当然である。   As mentioned above, although this invention was demonstrated along the Example, this invention is not limited to these Examples. For example, various substitutions, changes, improvements, combinations, and the like are naturally possible.

本発明の実施例に係る回路基板の構造を示す図である。It is a figure which shows the structure of the circuit board based on the Example of this invention. 本発明の実施例に係る回路基板を製造する方法を示す断面図である。It is sectional drawing which shows the method of manufacturing the circuit board based on the Example of this invention.

符号の説明Explanation of symbols

1 コア粒子
2 導電膜
3 第2絶縁性樹脂
10 回路基板
11 導電粒子
12 第1絶縁性樹脂
13 配線基板
14 電極パッド
15 基板
16 電極パッド
17c 回路面
17 半導体素子
20 導電性接着フィルム
DESCRIPTION OF SYMBOLS 1 Core particle 2 Conductive film 3 2nd insulating resin 10 Circuit board 11 Conductive particle 12 1st insulating resin 13 Wiring board 14 Electrode pad 15 Substrate 16 Electrode pad 17c Circuit surface 17 Semiconductor element 20 Conductive adhesive film

Claims (3)

第1の電極を備える配線基板と、
表面に第2の電極を備え、前記第2の電極が前記第1の電極と対向するように、前記配線基板上に配置された半導体素子と、
前記配線基板と前記半導体素子との間に配置される導電性接着剤と
を有し、
前記導電性接着剤は、
第1の絶縁性樹脂と、
前記第1の絶縁性樹脂の内部に分散して存在し、無機材からなるコア粒子の表面に導電膜と前記導電膜の全面に熱硬化性の第2の絶縁性樹脂とを順に被覆して形成された、前記第1及び第2の電極間の距離より小径の導電粒子とを含み、
前記第1および第2の電極は、前記導電性接着剤中の複数の前記導電粒子を介して電気的に接続され、
前記導電粒子は、互いに異なる熱膨張率を有する前記コア粒子をコアとする第1及び第2の導電粒子を含み、
前記導電性接着剤中の前記第1及び第2の導電粒子の存在比が、前記配線基板と前記半導体素子とが対向する領域で前記第1及び第2の電極が対向する方向に変化する、
ことを特徴とする回路基板。
A wiring board comprising a first electrode;
A semiconductor element provided on a surface of the wiring board so as to have a second electrode and the second electrode facing the first electrode;
A conductive adhesive disposed between the wiring board and the semiconductor element;
The conductive adhesive is
A first insulating resin;
The first present dispersed in the insulating resin, the entire surface thermosetting second insulating resin of the conductive film and the conductive film on the surface of the core particles consisting of inorganic material coated in this order formed, seen including a small diameter of the conductive particles than the distance between said first and second electrodes,
The first and second electrodes are electrically connected via the plurality of conductive particles in the conductive adhesive,
The conductive particles include first and second conductive particles having the core particles having different thermal expansion coefficients as cores,
The abundance ratio of the first and second conductive particles in the conductive adhesive changes in a direction in which the first and second electrodes face each other in a region where the wiring board and the semiconductor element face each other.
A circuit board characterized by that.
前記第1の絶縁性樹脂が、マイクロカプセル型のエポキシとイミダゾール系硬化剤、及びメルカプタン系硬化剤を含む
ことを特徴とする請求項1に記載の回路基板。
The circuit board according to claim 1, wherein the first insulating resin includes a microcapsule type epoxy, an imidazole curing agent, and a mercaptan curing agent .
無機材からなる第1のコア粒子の全表面に導電膜と熱硬化性の第2の絶縁性樹脂とが順に被覆された第1の導電粒子と、前記第1のコア粒子と熱膨張率が異なる無機材からなる第2のコア粒子の全表面に導電膜と熱硬化性の前記第2の絶縁性樹脂とが順に被覆された第2の導電粒子とを第1の絶縁樹脂フィルム中に分散させ、前記第1及び第2の導電粒子の存在比が厚さ方向に変化する第1の絶縁樹脂フィルムからなる導電性接着剤フィルムを形成する工程と、First conductive particles in which a conductive film and a thermosetting second insulating resin are sequentially coated on the entire surface of the first core particles made of an inorganic material, and the first core particles and the coefficient of thermal expansion are Dispersed in the first insulating resin film are second conductive particles in which a conductive film and the thermosetting second insulating resin are sequentially coated on the entire surface of the second core particles made of different inorganic materials. Forming a conductive adhesive film comprising a first insulating resin film in which the abundance ratio of the first and second conductive particles changes in the thickness direction;
表面に第1の電極を備えた配線基板を形成する工程と、Forming a wiring board having a first electrode on the surface;
表面に第2の電極を備えた半導体素子を形成する工程と、Forming a semiconductor element having a second electrode on the surface;
前記導電性接着剤フィルムを、前記配線基板の表面或いは前記半導体素子の表面に配置する工程と、Arranging the conductive adhesive film on the surface of the wiring substrate or the surface of the semiconductor element;
前記第1の電極と前記第2の電極とを前記第1および第2の導電粒子の径より広い間隔を保持して対向させた状態で加熱及び押圧し、前記第1の電極と前記第2の電極との間を前記導電性接着剤フィルム中の複数の前記導電粒子を介して電気的に接合する工程とThe first electrode and the second electrode are heated and pressed in a state where the first electrode and the second electrode are opposed to each other while maintaining an interval wider than the diameters of the first and second conductive particles, and the first electrode and the second electrode A step of electrically bonding a plurality of conductive particles in the conductive adhesive film via the plurality of conductive particles
を有することを特徴とする回路基板の製造方法。A method of manufacturing a circuit board, comprising:
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