JP4045471B2 - Electronic component mounting method - Google Patents

Electronic component mounting method Download PDF

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Publication number
JP4045471B2
JP4045471B2 JP10111097A JP10111097A JP4045471B2 JP 4045471 B2 JP4045471 B2 JP 4045471B2 JP 10111097 A JP10111097 A JP 10111097A JP 10111097 A JP10111097 A JP 10111097A JP 4045471 B2 JP4045471 B2 JP 4045471B2
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Japan
Prior art keywords
substrate
chip
adhesive
electronic component
electrode
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JP10111097A
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JPH10294422A (en
Inventor
功 塚越
宏治 小林
和也 松田
直樹 福島
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Showa Denko Materials Co Ltd
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Hitachi Chemical Co Ltd
Showa Denko Materials Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/28Applying non-metallic protective coatings
    • H05K3/284Applying non-metallic protective coatings for encapsulating mounted components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/321Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product

Description

【0001】
【発明の属する技術分野】
本発明は、チップを実装した基板を、他の電子部品に実装する場合に有効な電子部品実装法に関する。
【0002】
【従来の技術】
半導体チップや電子部品の小型薄型化に伴い、これらに用いる回路や電極は高密度化、高精細化している。このような微細電極の接続は、最近接着剤を用いる方法が多用されるようになってきた。この場合、接着剤中に導電粒子を配合し加圧により接着剤の厚み方向に電気的接続を得るもの(例えば特開昭55−104007号公報)と、導電粒子を用いないで接続時の加圧により電極面の微細凹凸の直接接触により電気的接続を得るもの(例えば特開昭60−262430号公報)がある。
接着剤を用いた接続方法は、比較的低温での接続が可能であり、接続部はフレキシブルなことから信頼性に優れ、加えてフィルム状もしくはテープ状接着剤を用いた場合、一定厚みの長尺状で供給されることから実装ラインの自動化が図れる等から注目されている。
近年、上記方式を発展させて複数以上のチップ類を、比較的小形の基板に高密度に実装するマルチチップモジュール(MCM)が注目されている。この場合、まず接着剤層を基板全面に形成した後、セパレータのある場合にはこれを剥離し、次いで基板電極とチップ電極を位置合わせし接着接合することが一般的である。MCMに用いるチップ類としては、半導体チップ、能動素子、受動素子、抵抗、コンデンサなどの多種類(以下チップ類)がある。
【0003】
【発明が解決しようとする課題】
MCMに用いるチップ類は多種類であり、それに応じてチップサイズ(面積、高さ)は多くの種類となる。そのため基板への接着剤を用いた接続の際に、基板との熱圧着法などで従来にない問題点が生じている。例えば、チップ接続時に多層回路基板の回路沈み込みが発生し、残留応力により信頼性が低下する現象がある。これは、多層基板の層間接着剤が一般的に耐熱性が低いことが原因である。例えば、層間接着剤のガラス転移点が130℃以下なのに対し、チップ接続時の温度は150℃以上が必要なことによる。この対策のためにチップ接続時に高価な耐熱性基板を適用せざるを得ないが、耐熱性基板は概して層間接着力が低く多層基板に適用できない矛盾がある。その一方で、MCMは引き出し電極数が多いことから、基板は多層とする必要がある。
またMCMを、他の電子部品としての例えばマザーボードに接続する場合、従来からの手法であるはんだリフロー炉による接続が行われるが、この場合、はんだリフロー炉の温度が200〜300℃と高温であり、MCM接続部の接着剤耐熱性がこの温度に耐えないケースが多く、接続信頼性が不十分となる。
また他の電子部品として、チップ類のケースもある。この場合は、基板の両面に実装するので、表裏でチップ位置が対象状態に設置される場合が少ないことから、圧力むらのない均一加圧が要求される微細電極の接合に適当な加圧する手段もない状態である。
本発明は、上記欠点に鑑みなされたものでチップを実装した基板を、多層回路基板やマザーボード、あるいは高さの異なるチップ等の他の電子部品に実装する場合に、有効な電子部品実装法を提供する。
【0004】
【課題を解決するための手段】
本発明は、チップと基板に第一の接着剤を介在させ電気的な接続を得たチップを実装した基板の裏面と電子部品の間に活性温度が50〜150℃であるマイクロカプセル型硬化剤を含有する第二の接着剤を介在させ、チップを実装した基板のチップ面の上に緩衝層を設け、前記チップを実装した基板の第一の接着剤のガラス転移点よりも低温での加熱加圧により基板裏面の電極と他の電子部品の電極間の直接接触により電極間の電気的な接続を得て、基板と他の電子部品とを接着することを特徴とする電子部品実装法に関する。また、チップと基板に第一の接着剤を介在させ電気的な接続を得たチップを実装した基板の裏面と他の電子部品の間に高分子核材に導電層を形成した導電粒子及び活性温度が50〜150℃であるマイクロカプセル型硬化剤を含有する第二の接着剤を介在させ、チップを実装した基板のチップ面の上に緩衝層を設け、前記チップを実装した基板の第一の接着剤のガラス転移点よりも低温での加熱加圧により基板裏面の電極と他の電子部品の電極間に導電粒子を介在させ電極間の電気的な接続と厚みの保持を得て、基板と他の電子部品とを接着することを特徴とする電子部品実装法に関する。
【0005】
【発明の実施の形態】
本発明を図面を参照しながら、以下説明する。
図1は、基板1上の電極5の形成面と、複数個以上のチップ2、2a、2bの電極4間に、接着剤3を介在させ、相対峙するチップの電極を位置合わせした状態を示す断面模式図である。基板1上の電極5もしくはチップ2上の電極4は、いずれも配線回路をそのまま接続端子としても、あるいはさらに突起状の電極を形成してもよい。電極4および/または5が突起状であると、相対峙する電極間で加圧が集中的に得られるため、電気的な接続が容易なので好ましい。接着剤3は、フィルム状でも、液状やペースト状でもよい。
接続すべきチップの電極4と基板の電極5を位置合わせする方法は、接続すべき基板1の電極5Bとチップ2の電極4Aとを、顕微鏡や、画像記憶装置等を用いて位置合わせする。このとき位置合わせマークの使用や併用も有効である。
位置合わせ後の基板1とチップ2の保持は、接着剤3の有する粘着性や、凝集力を用いて仮接続することで可能である。また、クリップや粘着テープ等の補助手段も単独もしくは併用して適用できる。仮接続は加熱加圧がある程度であれば不均一でもよいので、従来から用いられている熱圧着装置を用いることが可能である。
【0006】
電極の位置合わせを終了したチップの電極と基板の電極加熱加圧することで、基板上にチップの電気的接続を得る。この時、チップ2、2a、2bのように基板1からの高さが異なる場合には、チップ面と加圧型の間にゴム等の緩衝層を形成したり、オートクレー等により静水圧化で加圧したり、クッション性を有するゴムロール間で加圧したり、あるいはチップ毎にヘッドを独立させて加圧するなどにより、チップ付き基板が作製可能である。上記電極の位置合わせ工程や電気的接続工程において、接続すべき電極間で導通検査を行うことも可能である。接着剤は、未硬化あるいは硬化反応の不十分な状態で導通検査が可能なので、接着剤のリペア作業が容易である。同様にしてチップ周囲の、余剰接着剤を除去する工程を付加することも可能である。この方法によれば、導通検査を終了した良好な接続品は、次の工程で接着剤の硬化反応を進めるので、不良品再生が少なく工程のロス時間が短い。
【0007】
図2は、図1のようにして作製したチップ付き基板8と、電子部品9の間に接着剤10を介在させ、両基板を接着することを説明する本発明の実施例を示す断面模式図である。この時の接着温度は、チップ実装材料である接着剤3のガラス転移転よりも、低温であることが、チップの基板に対する接着剤が低下しないことから好ましい。
接着方法としては、前述の緩衝層やゴムロール間および静水圧下による方法を適用できる。さらに両基板の接着時においては、基板にチップが位置合わされ固定されていればよく、各基板に対する接着剤の硬化状態は問わない。
すなわち、基板へのチップ接続は、接着剤が未硬化あるいは硬化反応の不十分な状態で両基板の接着過程で接着剤3および接着剤層10の硬化反応を同時に行っても、あるいは基板へのチップ接続の接着剤が硬化反応が終了したものでもよい。前者の場合、製造工程の時間短縮やリペア作業に有効であり、後者の場合、保存時の基板へのチップ接続状態の変動が少ないので、安定した特性が得られる。
【0008】
図3は、チップ付き基板8と電子部品9の間に接着剤10を介在させ、電子部品9を接着した構造体を説明する本発明の実施例を示す断面模式図である。
チップ2の電極4と基板1の電極5は、接着剤3により電気的および機械的に接続される。なお図2の場合も接続後は同様な構造体が得られるが、図3により説明を代用する。この時の電極4−5および5−6の電気的な接続は、電極4−5および5−6の直接接触でも、電極間に導電粒子11が介在しても、あるいはこれらが混在してもよい。また電極5−6の電気的接続は不要な場合もある。基板8と電子部品9の間の接着剤10は、図3のように基板8の全面もしくはそれ以上に形成しても、基板8の一部であっても強度保持が可能であればよい。前者の場合、接着面積が大きなことから十分な接着力が得られ、また電極5、6を腐食等から保護できる。
チップ付き基板8と、電子部品9の接続は、従来はんだリフローなどの処理によるはんだ接合が一般的であったが、本発明では、接着剤10で接合するのでチップ付き基板8にはんだ溶融迄の高温がかからないので接続信頼性が向上する。
本発明の基板1としては、ポリイミドやポリエステル等のプラスチックフィルム、ガラス繊維/エポキシ等の複合体、シリコン等の半導体、ガラスやセラミック等の無機質等を例示できる。また電子部品9としては、多層回路基板(図2)や、マザーボード(図3)等の電気配線を有するものや、筺体や支持体などの様に、電気的な接続が不要な場合も適用できる。
【0009】
本発明に用いる接着剤3および10は、熱可塑性材料や、熱や光により硬化性を示す材料が広く適用できる。これらは接続後の耐熱性や耐湿性に優れることから、硬化性材料の適用が好ましい。なかでも潜在性硬化剤を含有したエポキシ系接着剤は、短時間硬化が可能で接続作業性がよく、分子構造上接着性に優れるので特に好ましい。潜在性硬化剤は、熱およびまたは圧力による反応開始の活性点が比較的明瞭であり、熱や圧力工程を伴う本発明に好適である。
潜在性硬化剤としては、イミダゾール系、ヒドラジド系、三フッ化ホウ素−アミン錯体、アミンイミド、ポリアミンの塩、オニウム塩、ジシアンジアミドなど、及びこれらの変性物があり、これらは単独または2種類以上の混合体として使用出来る。
これらはアニオン又はカチオン重合型などのいわゆるイオン重合体の触媒型硬化剤であり、速硬化性を得やすくまた化学当量的な考慮が少なくてよいことから好ましい。これの中では、イミダゾール系のものが非金属系であり電食しにくく、また反応性や接続信頼性の点から特に好ましい。硬化剤としてはその他に、ポリアミン類、ポリメルカプタン、ポリフェノール、酸無水物等の適用や前記触媒型硬化剤との併用も可能である。また硬化剤を核としその表面を高分子物質や、無機物で被覆したマイクロカプセル型硬化剤は、長期保存性と速硬化性という特性があることが好ましい。
本発明の硬化剤の活性温度は、40〜200℃が好ましい。40℃未満であると室温との温度差が少なく保存に低温が必要であり、200℃を越すと接続の他の部材に熱影響を与えるためであり、このような理由から50〜150℃がより好ましい。本発明の活性温度は、DSC(示差走査熱量計)を用いて、エポキシ樹脂と硬化剤の配合物を試料として、室温から10℃/分で昇温させた時の発熱ピーク温度を示す。活性温度は、低温側であると反応性に勝るが、保存性が低下する傾向にあるので、これらを考慮して決定する。
本発明において、硬化剤の活性温度以下の熱処理により、仮接続することで接着剤付き基板の保存性が向上し、活性温度以上の熱処理により、信頼性に優れたマルチチップの接続が得られる。
【0010】
これら接着剤3、10には、導電粒子や絶縁粒子を添加することが、接着剤付きチップの製造時の加熱加圧時に、厚み保持材として作用するので好ましい。この場合、導電粒子や絶縁粒子の割合は、0.1〜30体積%程度であり、異方導電性とするには0.5〜15体積%である。接着剤層は、絶縁層と導電層を分離形成した複数層の構成品も適用可能である。この場合、分解能が向上するため高ピッチな電極接続が可能となる。導電粒子としては、Au、Ag、Pt、Ni、Cu、W、Sb、Sn、はんだ等の金属粒子やカーボン、黒鉛等があり、またこれら導電粒子を核材とするか、あるいは非導電性のガラス、セラミックス、プラスチック等の高分子等からなる核材に前記したような材質からなる導電層を被覆形成したものでよい。さらに、導電材料を絶縁層で被覆してなる絶縁被覆粒子や、導電粒子とガラス、セラミックス、プラスチック等の絶縁粒子の併用等も分解能が向上するので、適用可能である。これら導電粒子の中では、プラスチック等の高分子核材に導電層を形成したものや、はんだ等の熱溶融金属が、加熱加圧もしくは加圧により変形性を有し、接続に回路との接触面積が増加し、信頼性が向上するので好ましい。特に高分子類を核とした場合、はんだのように融点を示さないので軟化の状態を接続温度で広く制御でき、電極の厚みや平坦性のばらつきに対応し易いので特に好ましい。また、例えばNiやW等の硬質金属粒子や、表面に多数の突起を有する粒子の場合、導電粒子が電極や配線パターンに突き刺さるので、酸化膜や汚染層の存在する場合にも低い接続抵抗が得られ、信頼性が向上するので好ましい。以上の説明では、フィルム状接着剤を用いた場合について述べたが、液状もしくはペースト状についても、同様に適用可能である。またチップ高さの異なる場合について述べたが、チップ高さが同等の場合も適用可能である。さらに基板へのチップ搭載個数が単体でもよい。
【0011】
本発明の電子部品実装法によれば、チップを実装した基板と電子部品の間に接着剤を介在させ接着一体化するので、基板と電子部品の特性を分離して接続可能である。例えばチップ実装基板は、回路の沈み込みの発生しない耐熱性の基板を用い、他の電子部品として例えば余り耐熱性のない汎用多層基板を用いることにより、コスト削減が可能である。このことは基板種類の組み合わせの多様性に対応可能となる。すなわち片側に高精密なピッチに対応可能な高価な基板を配置し、他の面には安価な一般基板といった特性や価格対応の組み合わせや、ガラス基板と有機基板といった材質の組み合わせなどが広く可能となる。本発明の電子部品実装法によれば、チップを実装した基板と電子部品の間で導電性接続とすることで、従来のはんだ接続が不要になるので、例えばリフロー工程などの高温過程がなくなり、接続信頼性が向上する。また接着剤による面接着であり、加えて接着剤によるフレキシブルな接着なので、タフな接続が得られる。本発明の電子部品実装法によれば、接着剤を介在させて接着するので、接着剤はシート状、液状、プリプレグといった各種の形態が使用でき、必要な特性に応じた接着剤の選択が可能であり、選択の自由度が向上する。さらに接着剤は、適当な厚みとすることで、接続時にクッション材的に作用し、圧力むらのない均一加圧が得られる。また基板接着時の加熱により、チップ実装部の熱硬化反応を後から促進可能であり、チップ実装部のリペアにも有効である。すなわち、基板へのチップ実装部の硬化反応を不十分な状態で導通検査等の特性チェックを行い、特性不良なときにチップを再接続するが、この時接着剤の硬化反応不十分な状態なので剥離が容易である。
【0012】
【実施例】
以下、実施例でさらに詳細に説明するが、本発明はこれに限定されない。
実施例1〜2
(1)接着剤付き基板の作成
フェノキシ樹脂(高分子量エポキシ樹脂)とマイクロカプセル型潜在性硬化剤を含有する液状エポキシ樹脂(エポキシ当量185)の比率を25/75とし、酢酸エチルの30%溶液を得た。この溶液に、粒径3±0.2μmのポリスチレン系粒子に、Ni/Auの厚さ0.2/0.02μmの金属被覆を形成した導電性粒子を2体積%添加し混合分散した。
この分散液をセパレータ(シリコーン処理ポリエチレンテレフタレートフィルム)にロールコータで塗布し、100℃20分乾燥し、厚み40μmのフィルム状接着剤を得た。
5mm×11mmで厚み0.4mmの耐熱性ガラスエポキシ基板の両面回路板(FR−5グレード…Tg180℃)上に、高さ18μmの銅の回路を有し、回路端部が後記するICチップのバンプピッチに対応した接続電極を有する2種の基板の接続領域に、前記フィルム状接着剤を貼り付けて形成し、セパレータを剥離した。この接着層のDSCによる活性温度は120℃であり、200℃10分硬化後のガラス転移点(Tg)は135℃であった。
【0013】
(2)電極の位置合わせと接続
前記の接着剤付き基板に、ICチップ3個(高さ0.3、0.55、1.0mm)を配置し、CCDカメラによる電極の位置合わせを行った。接着剤は室温でも若干の粘着性がある状態であり、室温で接着面に押しつけることで基板に簡単に保持でき、チップの仮付け基板を得た。チップの仮付け基板を、AC−SC450B(日立化成工業(株)製COB接続装置)の定盤上に基板面がくるように載せた。チップ面の上に緩衝層としてTC−80A(信越化学(株)製放熱用シリコンゴム、厚み0.8mm、JISゴム硬度75、熱伝導率3×10-3cal/cm/sec/℃)を基板と同一サイズでチップ接続部を覆ってかぶせた。20kgf/mm2 、10秒間の加熱加圧により接続した。なお温度は、20秒後に接着剤が170℃となるようにした。
(3)多層基板との接着
前記チップ付き基板と汎用材料からなる4層多層基板(FR−4…Tg120℃)を、(1)の接着剤(実施例1)および導電性粒子の添加なし(実施例2)を2種類の基板間に形成し、両基板を貼り合わせ、AC−SC450Bで130℃、20kgf/mm2 、10分間処理後に室温に冷却して取出した。
(4)評価
各チップの電極と多層基板の電極は良好に接続が可能であった。チップ付き基板の断面を観察したが、回路の沈み込みは見られなかった。また接着剤は、チップ近傍のにみに存在しているので、基板表面の不要接着剤は殆どなかった。本実施例では、高さの異なるICチップ3個を多層基板に接続できた。
実施例1の場合、基板が絶縁性のため、チップ接続と全く同一の接着剤の使用が可能であり工程が簡単であった。また、導電粒子が基板間のギャップ調整材となり同一厚みで基板間の接着が可能であった。実施例2の場合は、両基板のICチップ高さにある程度順応した形で接着していた。
【0014】
比較例1
実施例1と同様であるが、FR−4からなる6層多層基板に直接チップを接続した。この場合、各チップの電極と多層基板の電極は接続が不可能であった。基板の断面を観察したところ、回路の沈み込みのある部分と電極の接続不能が混在して多く見られた。これは、チップが高さが異なり、さらに多層回路板なので、場所により金属回路、ガラス繊維、および樹脂のそれぞれの層が混在し凹凸を有するので、接続時に圧力むらが生じたためと考える。
【0015】
実施例3〜4
実施例1〜2と同様であるが、多層基板に代えてFR−4からなるガラスエポキシ基板とした。各チップの電極と多層基板の電極は良好に接続が可能であった。
接続部の断面を観察したところ、実施例3の絶縁性接着剤の場合電極の直接接触で、実施例4の導電性粒子の添加接着剤の場合は、電極間に導電粒子が介在して接続されていた。
実施例3〜4においては、基板同士が接着剤で接続されているので、両基板は強固に接着されていた。
【0016】
比較例2
実施例4と同様であるが、はんだリフロー炉(最高240℃)で電極を接続した。リフロー炉の熱により各チップの電極と多層基板の電極は接続が不可能であった。また電極部のみの、金属接合なので、基板同士の固定が極めて弱く、別途補強が必要であった。
【0017】
【発明の効果】
以上詳述したように本発明によれば、チップを実装した基板を、例えば多層回路基板やマザーボード、あるいは高さの異なるチップ等の電子部品に実装する場合に有効な、電子部品実装法を提供できる。
【図面の簡単な説明】
【図1】本発明の一実施例を説明する、基板上の電極とチップ電極間に接着剤を介在させ位置合わせした状態を説明する断面模式図である。
【図2】本発明の一実施例を説明する、チップ付き基板と電子部品の間に接着剤を介在させ両基板を接着することを説明する断面模式図である。
【図3】本発明の一実施例を説明する、チップ付き基板と電子部品の間に接着剤を介在させ、電子部品を接着した構造体を説明する断面模式図である。
【符号の説明】
1 基板
2 チップ
3 接着剤A
4 電極A
5 電極B
6 電極C
7 内層回路
8 チップ付き基板
9 電子部品
10 接着剤層B
11 導電粒子
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an electronic component mounting method effective when a substrate on which a chip is mounted is mounted on another electronic component.
[0002]
[Prior art]
With the miniaturization and thinning of semiconductor chips and electronic components, the circuits and electrodes used for these have become higher in density and higher in definition. For the connection of such fine electrodes, a method using an adhesive has recently been frequently used. In this case, the conductive particles are blended in the adhesive, and electrical connection is obtained in the thickness direction of the adhesive by pressurization (for example, Japanese Patent Application Laid-Open No. 55-104007). There is one that obtains an electrical connection by direct contact of fine irregularities on the electrode surface by pressure (for example, JP-A-60-262430).
The connection method using an adhesive can be connected at a relatively low temperature, and the connection part is flexible, so it has excellent reliability. In addition, when a film or tape adhesive is used, it has a certain length. Since it is supplied in the form of a scale, it is attracting attention because the mounting line can be automated.
In recent years, a multi-chip module (MCM) that has developed the above-described method and mounts a plurality of chips on a relatively small substrate with high density has attracted attention. In this case, it is common to first form an adhesive layer on the entire surface of the substrate, then peel off the separator, if any, and then align and adhesively bond the substrate electrode and the chip electrode. As chips used for MCM, there are many types (hereinafter referred to as chips) such as a semiconductor chip, an active element, a passive element, a resistor, and a capacitor.
[0003]
[Problems to be solved by the invention]
There are many types of chips used for MCM, and there are many types of chip sizes (area, height) accordingly. For this reason, when connecting to the substrate using an adhesive, unprecedented problems have arisen due to the thermocompression bonding method with the substrate. For example, a circuit sink of a multilayer circuit board occurs at the time of chip connection, and there is a phenomenon that reliability is lowered due to residual stress. This is because the interlayer adhesive of the multilayer substrate generally has low heat resistance. For example, the glass transition point of the interlayer adhesive is 130 ° C. or lower, while the temperature at the time of chip connection needs to be 150 ° C. or higher. For this measure, an expensive heat-resistant substrate must be applied at the time of chip connection, but the heat-resistant substrate generally has a contradiction that cannot be applied to a multilayer substrate because of its low interlayer adhesion. On the other hand, since the MCM has a large number of extraction electrodes, the substrate needs to be multi-layered.
In addition, when connecting the MCM to, for example, a mother board as another electronic component, connection is performed by a solder reflow furnace, which is a conventional technique. In this case, the temperature of the solder reflow furnace is as high as 200 to 300 ° C. In many cases, the adhesive heat resistance of the MCM connection portion cannot withstand this temperature, and the connection reliability is insufficient.
As another electronic component, there is a chip case. In this case, since it is mounted on both sides of the substrate, the chip position is rarely placed in the target state on the front and back sides. Therefore, means for applying pressure suitable for bonding of fine electrodes that require uniform pressure without pressure unevenness. There is no state.
The present invention has been made in view of the above disadvantages, and is an effective electronic component mounting method when a substrate on which a chip is mounted is mounted on another electronic component such as a multilayer circuit board, a motherboard, or a chip having a different height. provide.
[0004]
[Means for Solving the Problems]
The present invention is a microcapsule type curing activity temperature between the first back surface and the electronic components of the board on which a chip to obtain the electrical connection of an adhesive is interposed in the chip and the substrate is 50 to 150 ° C. A buffer layer is provided on the chip surface of the substrate on which the chip is mounted, with a second adhesive containing an agent interposed therebetween, at a temperature lower than the glass transition point of the first adhesive on the substrate on which the chip is mounted. An electronic component mounting method characterized in that an electrical connection between electrodes is obtained by direct contact between an electrode on the back surface of a substrate and an electrode of another electronic component by heating and pressing, and the substrate and the other electronic component are bonded. About. In addition, conductive particles in which a conductive layer is formed on the polymer core material between the back surface of the substrate on which the chip having the electrical connection is obtained by interposing a first adhesive between the chip and the substrate and other electronic components, and the active particles temperature is interposed a second adhesive you containing a microcapsule-type curing agent is 50 to 150 ° C., the buffer layer on the chip surface of the substrate mounted with chips provided, the board mounted with the tip first Conductive particles are interposed between the electrode on the back surface of the substrate and the electrode of the other electronic component by heating and pressing at a temperature lower than the glass transition point of one adhesive to obtain electrical connection between the electrodes and maintenance of the thickness, The present invention relates to an electronic component mounting method characterized by bonding a substrate and another electronic component.
[0005]
DETAILED DESCRIPTION OF THE INVENTION
The present invention will be described below with reference to the drawings.
FIG. 1 shows a state in which an adhesive 3 is interposed between a formation surface of an electrode 5 on a substrate 1 and the electrodes 4 of a plurality of chips 2, 2a, 2b, and the electrodes of the chips facing each other are aligned. It is a cross-sectional schematic diagram shown. The electrode 5 on the substrate 1 or the electrode 4 on the chip 2 may be formed by using a wiring circuit as a connection terminal as it is, or further forming a protruding electrode. It is preferable that the electrodes 4 and / or 5 have a protruding shape because electrical connection is easy because pressure is concentrated between the electrodes facing each other. The adhesive 3 may be a film, a liquid, or a paste.
As a method of aligning the electrode 4 of the chip to be connected and the electrode 5 of the substrate, the electrode 5B of the substrate 1 to be connected and the electrode 4A of the chip 2 are aligned using a microscope, an image storage device or the like. At this time, the use or use of the alignment mark is also effective.
The substrate 1 and the chip 2 after the alignment can be held by temporarily connecting them using the adhesive property of the adhesive 3 and the cohesive force. In addition, auxiliary means such as a clip and an adhesive tape can be applied alone or in combination. Since the temporary connection may be non-uniform as long as the heating and pressurization is performed to some extent, a conventionally used thermocompression bonding apparatus can be used.
[0006]
The chip electrode on which the alignment of the electrodes has been completed and the electrode on the substrate are heated and pressed to obtain electrical connection of the chip on the substrate. At this time, the chip 2, 2a, if the height from the substrate 1 is different as 2b, or form a buffer layer of rubber or the like between the chip surface and the pressure-type, electrostatic by autoclave or the like water pressure A substrate with a chip can be produced by pressurizing by pressing, pressing between rubber rolls having cushioning properties, or by pressing the head independently for each chip. It is also possible to perform a continuity test between the electrodes to be connected in the electrode positioning step and the electrical connection step. Since the adhesive can be inspected for continuity in an uncured state or in a state where the curing reaction is insufficient, the repair work of the adhesive is easy. Similarly, it is possible to add a step of removing excess adhesive around the chip. According to this method, since a good connection product that has completed the continuity test advances the curing reaction of the adhesive in the next step, the defective product is regenerated and the process loss time is short.
[0007]
FIG. 2 is a schematic cross-sectional view showing an embodiment of the present invention for explaining that an adhesive 10 is interposed between an electronic component 9 and a substrate 8 with a chip manufactured as shown in FIG. It is. The bonding temperature at this time is preferably lower than the glass transition of the adhesive 3 as the chip mounting material because the adhesive to the chip substrate does not decrease.
As an adhesion method, the above-described buffer layer, rubber roll, and hydrostatic pressure can be applied. Further, at the time of bonding the two substrates, it is sufficient that the chip is aligned and fixed to the substrates, and the cured state of the adhesive on each substrate is not limited.
That is, the chip connection to the substrate can be performed even if the curing reaction of the adhesive 3 and the adhesive layer 10 is simultaneously performed in the bonding process of both substrates in a state where the adhesive is not cured or the curing reaction is insufficient. The adhesive for chip connection may be one in which the curing reaction has been completed. In the former case, it is effective for shortening the manufacturing process time and repair work, and in the latter case, since the variation of the chip connection state to the substrate during storage is small, stable characteristics can be obtained.
[0008]
FIG. 3 is a schematic cross-sectional view showing an embodiment of the present invention for explaining a structure in which an electronic component 9 is bonded with an adhesive 10 interposed between the chip-attached substrate 8 and the electronic component 9.
The electrode 4 of the chip 2 and the electrode 5 of the substrate 1 are electrically and mechanically connected by the adhesive 3. In the case of FIG. 2 as well, a similar structure can be obtained after connection, but the description will be substituted by FIG. The electrical connection between the electrodes 4-5 and 5-6 at this time may be the direct contact between the electrodes 4-5 and 5-6, the conductive particles 11 interposed between the electrodes, or a mixture of these. Good. Moreover, the electrical connection of the electrode 5-6 may be unnecessary. The adhesive 10 between the substrate 8 and the electronic component 9 may be formed on the entire surface of the substrate 8 or more as shown in FIG. In the former case, since the adhesion area is large, sufficient adhesion can be obtained, and the electrodes 5 and 6 can be protected from corrosion and the like.
Conventionally, the connection between the chip-equipped substrate 8 and the electronic component 9 is generally performed by solder bonding by a process such as solder reflow. Connection reliability is improved because high temperature is not applied.
Examples of the substrate 1 of the present invention include plastic films such as polyimide and polyester, composites such as glass fiber / epoxy, semiconductors such as silicon, and inorganic materials such as glass and ceramics. Also, the electronic component 9 can be applied to a case where electrical connection is not required, such as a multilayer circuit board (FIG. 2), a mother board (FIG. 3) or the like having electrical wiring, a housing or a support. .
[0009]
As the adhesives 3 and 10 used in the present invention, thermoplastic materials and materials exhibiting curability by heat and light can be widely applied. Since these are excellent in heat resistance and moisture resistance after connection, application of a curable material is preferable. Among them, an epoxy adhesive containing a latent curing agent is particularly preferable because it can be cured for a short time, has good connection workability, and is excellent in adhesion due to its molecular structure. The latent curing agent has a relatively clear active site of reaction initiation by heat and / or pressure, and is suitable for the present invention involving heat and pressure processes.
Examples of latent curing agents include imidazole series, hydrazide series, boron trifluoride-amine complex, amine imide, polyamine salt, onium salt, dicyandiamide, and modified products thereof. These may be used alone or in combination of two or more. Can be used as a body.
These are catalyst type curing agents of so-called ionic polymers such as anion or cation polymerization type, and are preferable because they can easily obtain fast curability and require less chemical equivalent consideration. Of these, imidazole-based compounds are non-metallic, are less susceptible to electrolytic corrosion, and are particularly preferable from the viewpoints of reactivity and connection reliability. In addition, polyamines, polymercaptans, polyphenols, acid anhydrides, and the like can be used as the curing agent, and the catalyst-type curing agent can be used in combination. Moreover, it is preferable that the microcapsule type curing agent having a curing agent as a nucleus and the surface thereof coated with a polymer substance or an inorganic substance has characteristics of long-term storage and fast curing.
As for the active temperature of the hardening | curing agent of this invention, 40-200 degreeC is preferable. If the temperature is less than 40 ° C, the temperature difference from room temperature is small and a low temperature is required for storage. If the temperature exceeds 200 ° C, the other members of the connection are affected by heat. More preferred. The active temperature of the present invention indicates an exothermic peak temperature when the temperature is raised from room temperature to 10 ° C./min using a DSC (differential scanning calorimeter) as a sample of a mixture of an epoxy resin and a curing agent. The activation temperature is superior to the reactivity at the low temperature side, but tends to decrease the storage stability, and is determined in consideration of these.
In the present invention, the preserving of the substrate with the adhesive is improved by temporary connection by a heat treatment below the activation temperature of the curing agent, and a multi-chip connection with excellent reliability is obtained by the heat treatment above the activation temperature.
[0010]
It is preferable to add conductive particles or insulating particles to these adhesives 3 and 10 because they act as a thickness-retaining material at the time of heating and pressing at the time of manufacturing a chip with an adhesive. In this case, the ratio of conductive particles or insulating particles is about 0.1 to 30% by volume, and 0.5 to 15% by volume for anisotropic conductivity. As the adhesive layer , a multi-layer component in which an insulating layer and a conductive layer are separately formed is also applicable. In this case, since the resolution is improved, electrode connection with a high pitch is possible. Examples of the conductive particles include metal particles such as Au, Ag, Pt, Ni, Cu, W, Sb, Sn, and solder, carbon, graphite, and the like. These conductive particles are used as a core material or non-conductive. A core material made of a polymer such as glass, ceramics, or plastic may be coated with a conductive layer made of the above-described material. Furthermore, the insulating coating particles formed by coating a conductive material with an insulating layer, or the combined use of conductive particles and insulating particles such as glass, ceramics, and plastics can be applied because the resolution is improved. Among these conductive particles, those in which a conductive layer is formed on a polymer core material such as plastic, and hot-melt metal such as solder are deformable by heating or pressurization, and contact with a circuit for connection This is preferable because the area is increased and the reliability is improved. In particular, when a polymer is used as a nucleus, it does not show a melting point like solder, so that the softening state can be widely controlled by the connection temperature, and it is easy to cope with variations in electrode thickness and flatness, which is particularly preferable. Also, for example, in the case of hard metal particles such as Ni and W, or particles having a large number of protrusions on the surface, the conductive particles pierce the electrode and the wiring pattern, so that even when an oxide film or a contaminated layer exists, a low connection resistance is obtained. It is preferable because it is obtained and reliability is improved. In the above description, the case where a film adhesive is used has been described, but the present invention can be similarly applied to a liquid or paste. Further, the case where the chip heights are different has been described, but the case where the chip heights are equivalent is also applicable. Further, the number of chips mounted on the substrate may be single.
[0011]
According to the electronic component mounting method of the present invention, since the adhesive is interposed between the substrate on which the chip is mounted and the electronic component for bonding and integration, the characteristics of the substrate and the electronic component can be separated and connected. For example, the chip mounting substrate can be reduced in cost by using a heat-resistant substrate that does not cause sinking of the circuit, and using, for example, a general-purpose multilayer substrate that does not have much heat resistance as another electronic component. This can cope with the diversity of combinations of substrate types. In other words, an expensive substrate that can handle a high-precision pitch is placed on one side, and a combination of characteristics such as an inexpensive general substrate or a price-compatible combination, or a combination of materials such as a glass substrate and an organic substrate is possible on the other side. Become. According to the electronic component mounting method of the present invention, by making a conductive connection between the substrate on which the chip is mounted and the electronic component, the conventional solder connection becomes unnecessary, so that a high temperature process such as a reflow process is eliminated, Connection reliability is improved. In addition, it is surface bonding with an adhesive, and in addition, flexible bonding with an adhesive allows tough connection. According to the electronic component mounting method of the present invention, since the adhesive is bonded, the adhesive can be used in various forms such as a sheet, a liquid, and a prepreg, and the adhesive can be selected according to the required characteristics. Therefore, the degree of freedom of selection is improved. Furthermore, by setting the adhesive to an appropriate thickness, the adhesive acts as a cushion material at the time of connection, and uniform pressure without pressure unevenness can be obtained. Further, the heat curing reaction of the chip mounting portion can be accelerated later by heating at the time of bonding the substrate, which is also effective for repairing the chip mounting portion. In other words, a characteristic check such as continuity inspection is performed with insufficient curing reaction of the chip mounting part to the substrate, and the chip is reconnected when the characteristic is poor, but at this time the adhesive curing reaction is insufficient So peeling is easy.
[0012]
【Example】
Hereinafter, although an Example demonstrates in detail, this invention is not limited to this.
Examples 1-2
(1) Preparation of substrate with adhesive 30% solution of ethyl acetate with a ratio of liquid epoxy resin (epoxy equivalent 185) containing phenoxy resin (high molecular weight epoxy resin) and microcapsule type latent curing agent to 25/75 Got. To this solution, 2% by volume of conductive particles having a Ni / Au thickness of 0.2 / 0.02 μm formed on polystyrene particles having a particle diameter of 3 ± 0.2 μm were added and mixed and dispersed.
This dispersion was applied to a separator (silicone-treated polyethylene terephthalate film) with a roll coater and dried at 100 ° C. for 20 minutes to obtain a film adhesive having a thickness of 40 μm.
An IC chip having a circuit of 18 μm in height on a double-sided circuit board (FR-5 grade Tg180 ° C.) of a heat-resistant glass epoxy substrate having a thickness of 5 mm × 11 mm and a thickness of 0.4 mm, and the circuit end portion of which is described later The film adhesive was applied to the connection region of two types of substrates having connection electrodes corresponding to the bump pitch, and the separator was peeled off. The activation temperature by DSC of this adhesive layer was 120 ° C., and the glass transition point (Tg) after curing at 200 ° C. for 10 minutes was 135 ° C.
[0013]
(2) Positioning and connection of electrodes Three IC chips (height 0.3, 0.55, 1.0 mm) were placed on the above-mentioned substrate with adhesive, and the position of the electrodes was adjusted by a CCD camera. . The adhesive was in a state where there was a slight stickiness even at room temperature, and it could be easily held on the substrate by pressing against the adhesive surface at room temperature, and a temporary substrate for chip was obtained. The temporary substrate for the chip was placed on the surface plate of AC-SC450B (COB connection device manufactured by Hitachi Chemical Co., Ltd.) so that the substrate surface would come. TC-80A (Shin-Etsu Chemical Co., Ltd. heat dissipation silicon rubber, thickness 0.8 mm, JIS rubber hardness 75, thermal conductivity 3 × 10 −3 cal / cm / sec / ° C.) as a buffer layer on the chip surface. The chip connection part was covered and covered with the same size as the substrate. The connection was established by heating and pressing at 20 kgf / mm 2 for 10 seconds. The temperature was adjusted to 170 ° C. after 20 seconds.
(3) Adhesion with multilayer substrate The substrate with chips and a four-layer multilayer substrate (FR-4... Tg 120 ° C.) made of a general-purpose material were added without the addition of the adhesive (Example 1) and conductive particles of (1) ( Example 2) was formed between two types of substrates, and both substrates were bonded together and treated with AC-SC450B at 130 ° C., 20 kgf / mm 2 for 10 minutes, and then cooled to room temperature and taken out.
(4) Evaluation The electrode of each chip and the electrode of the multilayer substrate could be connected satisfactorily. Although the cross section of the substrate with the chip was observed, the circuit did not sink. Further, since the adhesive is present only in the vicinity of the chip, there was almost no unnecessary adhesive on the substrate surface. In this example, three IC chips having different heights could be connected to the multilayer substrate.
In the case of Example 1, since the substrate is insulative, it is possible to use the same adhesive as the chip connection, and the process is simple. In addition, the conductive particles became a gap adjusting material between the substrates, and it was possible to bond the substrates with the same thickness. In the case of Example 2, the two substrates were bonded in a form that conformed to the IC chip height to some extent.
[0014]
Comparative Example 1
Similar to Example 1, but the chip was directly connected to a 6-layer multilayer substrate made of FR-4. In this case, the electrodes of each chip and the electrodes of the multilayer substrate cannot be connected. When the cross section of the substrate was observed, there were many cases where the part where the circuit was depressed and the inability to connect the electrodes were mixed. This is thought to be because pressure unevenness occurred at the time of connection because the chip was different in height and was a multilayer circuit board, and each layer of metal circuit, glass fiber, and resin was mixed depending on the location and had irregularities.
[0015]
Examples 3-4
Although it is the same as that of Examples 1-2, it replaced with the multilayer substrate and set it as the glass epoxy board | substrate which consists of FR-4. The electrode of each chip and the electrode of the multilayer substrate could be connected well.
When the cross section of the connecting portion was observed, in the case of the insulating adhesive of Example 3, the electrode was in direct contact, and in the case of the additive of the conductive particle of Example 4, the conductive particles were interposed between the electrodes. It had been.
In Examples 3 to 4, since the substrates are connected to each other with an adhesive, both the substrates are firmly bonded.
[0016]
Comparative Example 2
Similar to Example 4, but the electrodes were connected in a solder reflow oven (up to 240 ° C.). The electrode of each chip and the electrode of the multilayer substrate could not be connected due to the heat of the reflow furnace. In addition, since only the electrode portion is a metal joint, the fixing between the substrates is extremely weak, and a separate reinforcement is required.
[0017]
【The invention's effect】
As described above in detail, according to the present invention, there is provided an electronic component mounting method that is effective when a substrate on which a chip is mounted is mounted on an electronic component such as a multilayer circuit board, a motherboard, or a chip having a different height. it can.
[Brief description of the drawings]
BRIEF DESCRIPTION OF DRAWINGS FIG. 1 is a schematic cross-sectional view illustrating a state where an adhesive is interposed between an electrode on a substrate and a chip electrode and is positioned, explaining an embodiment of the present invention.
FIG. 2 is a schematic cross-sectional view for explaining an embodiment of the present invention and explaining bonding of both substrates by interposing an adhesive between the chip-attached substrate and the electronic component.
FIG. 3 is a schematic cross-sectional view illustrating a structure in which an electronic component is bonded with an adhesive interposed between the chip-attached substrate and the electronic component, according to an embodiment of the present invention.
[Explanation of symbols]
1 Substrate 2 Chip 3 Adhesive A
4 Electrode A
5 Electrode B
6 Electrode C
7 Inner layer circuit 8 Substrate with chip 9 Electronic component 10 Adhesive layer B
11 Conductive particles

Claims (2)

チップと基板に第一の接着剤を介在させ電気的な接続を得たチップを実装した基板の裏面と他の電子部品の間に活性温度が50〜150℃であるマイクロカプセル型硬化剤を含有する第二の接着剤を介在させ、チップを実装した基板のチップ面の上に緩衝層を設け、前記チップを実装した基板の第一の接着剤のガラス転移点よりも低温での加熱加圧により基板裏面の電極と他の電子部品の電極間の直接接触により電極間の電気的な接続を得て、基板と他の電子部品とを接着することを特徴とする電子部品実装法。 The microcapsule-type curing agent activity temperature of 50 to 150 ° C. during the first back surface and other electronic components of the board on which a chip to obtain an electrical connection by interposing an adhesive to the chip and the substrate A buffer layer is provided on the chip surface of the substrate on which the chip is mounted, with the second adhesive contained , and heating at a temperature lower than the glass transition point of the first adhesive on the substrate on which the chip is mounted. An electronic component mounting method characterized in that an electrical connection between electrodes is obtained by direct contact between an electrode on a back surface of a substrate and an electrode of another electronic component by pressure, and the substrate and the other electronic component are bonded. チップと基板に第一の接着剤を介在させ電気的な接続を得たチップを実装した基板の裏面と他の電子部品の間に高分子核材に導電層を形成した導電粒子及び活性温度が50〜150℃であるマイクロカプセル型硬化剤を含有する第二の接着剤を介在させ、チップを実装した基板のチップ面の上に緩衝層を設け、前記チップを実装した基板の第一の接着剤のガラス転移点よりも低温での加熱加圧により基板裏面の電極と他の電子部品の電極間に導電粒子を介在させ電極間の電気的な接続と厚みの保持を得て、基板と他の電子部品とを接着することを特徴とする電子部品実装法。Conductive particles having a conductive layer formed on the polymer core material between the back surface of the substrate on which the first adhesive is interposed between the chip and the substrate to obtain electrical connection, and other electronic components, and the activation temperature are is 50 to 150 ° C. is interposed a second adhesive you containing a microcapsule type curing agent, a buffer layer on the chip surface of the substrate mounted with chips provided, a first substrate mounted with the tip Conductive particles are interposed between the electrode on the backside of the substrate and the electrode of another electronic component by heating and pressing at a temperature lower than the glass transition point of the adhesive to obtain electrical connection between the electrodes and maintenance of the thickness, An electronic component mounting method characterized by bonding another electronic component.
JP10111097A 1997-04-18 1997-04-18 Electronic component mounting method Expired - Fee Related JP4045471B2 (en)

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JP4602150B2 (en) * 2005-04-20 2010-12-22 シャープ株式会社 Connection method of drive circuit board and display panel
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