JP4223581B2

JP4223581B2 - Multi-chip mounting method

Info

Publication number: JP4223581B2
Application number: JP10111197A
Authority: JP
Inventors: 功塚越; 宏治小林; 和也和田; 直樹福島
Original assignee: Hitachi Chemical Co Ltd; Showa Denko Materials Co Ltd
Current assignee: Showa Denko Materials Co Ltd
Priority date: 1997-04-18
Filing date: 1997-04-18
Publication date: 2009-02-12
Anticipated expiration: 2017-04-18
Also published as: JPH10294563A

Description

【０００１】
【発明の属する技術分野】
本発明は、基板面へのマルチチップ実装方法に関する。
【０００２】
【従来の技術】
半導体チップや電子部品の小型薄型化に伴い、これらに用いる回路や電極は高密度化、高精細化している。このような微細電極の接続は、最近接着剤を用いる方法が多用されるようになってきた。この場合、接着剤中に導電粒子を配合し加圧により接着剤の厚み方向に電気的接続を得るもの（例えば特開昭５５−１０４００７号公報）と、導電粒子を用いないで接続時の加圧により電極面の微細凹凸の直接接触により電気的接続を得るもの（例えば特開昭６０−２６２４３０号公報）がある。
接着剤を用いた接続方式は、比較的低温での接続が可能であり、接続部はフレキシブルなことから信頼性に優れ、加えてフィルム状もしくはテープ状接着剤を用いた場合、一定厚みの長尺状で供給されることから実装ラインの自動化が図れる等から注目されている。
近年、上記方式を発展させて複数以上のチップ類を、比較的小形の基板に高密度に実装するマルチチップモジュール（ＭＣＭ）が注目されている。この場合、まず接着剤層を基板全面に形成した後、セパレータのある場合にはこれを剥離し、次いで基板電極とチップ電極を位置あわせし接着接合することが一般的である。ＭＣＭに用いるチップ類としては、半導体チップ、能動素子、受動素子、抵抗、コンデンサなどの多種類（以下チップ類）がある。
【０００３】
【発明が解決しようとする課題】
ＭＣＭに用いるチップ類は多種類であり、それに応じてチップサイズ（面積、高さ）は多くの種類となる。そのため基板への接着剤を用いた接続の際に、基板との熱圧着法などで従来にない問題点が生じている。例えばチップ高さの異なる場合や基板の両面に実装する場合、従来一般的に行われていた平行設置された金型を、油圧や空気圧により圧縮するプレス法や、平行設置されたゴムや金属の加圧ロールにより圧縮するいわゆるロール法などでは、図３に示すように、チップ高さが異なると、加熱加圧が均一に行われない欠点がある。
すなわち、これらのプレス法やロール法では金型やロール間で加圧し、例えば平行された定盤６と加圧型７の間で加圧するために、チップ高さの異なる場合（２、２ａ、２ｂや２’、２ａ’２ｂ’）やチップを基板の両面に実装（２と、２’など）すると、加圧状態が一定とならないため、電極間の接続が不十分となり接続信頼性が得られない。
特に基板の両面（３と３’面）に実装する場合には、表裏でチップ位置が対象状態に設置される場合が少ないことから、圧力むらのない均一加圧が要求される微細電極の接合に適当な加圧する手段もない状態である。同様なことは、片面にチップ類を搭載した基板を、配線や電子部品などにより凹凸を有する他の基板に積層する場合にもいえる。
さらに他の問題点として、チップのリペアがある。これは実装後のチップを交換する際に接着剤が硬化反応が終了した物であると、チップが剥がしにくく接着剤が除去しにくいために、極めて困難視されていた。特にマルチチップ実装の場合、隣接するチップとの間隔が狭く機械的な除去が困難であり、また基板も例えばガラス・エポキシやフィルム等の有機基板の場合、有機溶剤に基板も侵されてしまうなどの制限から不可能視されていた。
本発明は、上記欠点に鑑みなされたもので、高さの異なるチップを基板の両面に実装する場合に有効で、かつリペアに対応可能なマルチチップ実装法を提供する。
【０００４】
【課題を解決するための手段】
本発明は、少なくとも一方が有機基板である２枚の基板の電極表面にそれぞれ高さの異なるＩＣチップを接着剤で実装し電気的接続を得た後、前記基板の裏面間に接着剤を介在させ、チップ実装接着剤のガラス転移点よりも低温で両基板を接着することを特徴とするマルチチップ実装法に関する。また、少なくとも一方が有機基板である２枚の基板の電極表面にそれぞれ高さの異なるＩＣチップを接着剤の硬化が不十分な条件下で実装し、この状態で必要に応じて導通検査を行った後、前記基板の裏面間に接着剤層を介在させてチップ実装接着剤のガラス転移点よりも低温で両基板を接着し、実装部の接着剤の硬化反応を促進することを特徴とするマルチチップ実装法に関する。
【０００５】
【発明の実施の形態】
本発明の図面を参照しながら、以下説明する。
図１は、基板１上の電極５の形成面と、複数個以上のチップ２、２ａ、２ｂの電極４間に、接着剤３を介在させ、相対峙するチップの電極を位置合わせした状態を示す断面模式図である。基板１上の電極Ｂ５もしくはチップ２上の電極Ａ４は、いずれも配線回路をそのまま接続端子としても、あるいはさらに突起状の電極を形成してもよい。電極４および／または５が突起状であると、相対峙する電極間で加圧が集中的に得られるため、電気的な接続が容易なので好ましい。接着剤３は、フィルム状でも、液状やペースト状でもよい。また接着剤層を２分割し接着剤付き基板間に、例えば両面板等の多層基板を配してもよい。
接続すべき接着剤付きチップの電極と基板の電極を位置合わせする方法は、接続すべき基板１の電極５Ｂとチップ２の電極Ａ４とを、顕微鏡や、画像記憶装置を用いて位置合わせする。このとき位置合わせマークの使用や併用も有効である。
位置合わせ後の基板１とチップ２の保持は、接着剤３の有する粘着性や、凝集力を用いて仮接続することで可能である。また、クリップや粘着テープ等の補助手段も単独もしくは併用して適用できる。仮接続は加熱加圧がある程度であれば不均一でもよいので、従来から用いられている熱圧着装置を用いることが可能である。
【０００６】
電極の位置合わせを終了したチップの電極と基板の電極を加熱加圧することで、基板上にチップの電極的接続を得る。この時、チップ２、２ａ、２ｂのように基板１からの高さが異なる場合には、チップ面と加圧型７の間にゴム等の緩衝層を形成したり、オートクレーブ等により静水圧化で加圧したり、クッション性を有するゴムロール間で加圧したり、あるいはチップ毎にヘッドを独立させて加圧するなどにより、チップ付き基板が作製可能である。上記電極の位置合わせ工程や電気的接続工程において、接続すべき電極間で導通検査を行うことも可能である。接着剤は、未硬化あるいは硬化反応の不十分な状態で導通検査が可能なので、接着剤のリペア作業が容易である。同様にしてチップ周囲の、余剰接着剤を除去する工程を付加することも可能である。この方法によれば、導通検査を終了した良好な接続品は、次の工程で接着剤の硬化反応を進めるので、不良品再生が少なく工程のロス時間が短い。
【０００７】
図２は、図１のようにして作製したチップ付き基板８、９の間に接着剤層１０を介在させ、両基板を接着することを説明する、本発明の実施例を示す断面模式図である。この時の接着温度は、チップ実装材料である接着剤３のガラス転移点よりも、低温であることが、チップの基板に対する接着性が低下しないことから好ましい。
接着方法としては、前述の緩衝層やゴムロール間および静水圧下による方法を適用できる。さらに両基板の接着時においては、基板にチップが位置合わされ固定されていればよく、各基板に対する接着剤の硬化状態は問わない。
すなわち、基板へのチップ接続は、接着剤が未硬化あるいは硬化反応の不十分な状態で両基板の接着過程で、接着剤３および接着剤層１０の硬化反応を同時に行っても、あるいは基板へのチップ接続の接着剤が硬化反応が終了したものでもよい。前者の場合、製造工程の時間短縮やリペア作業に有効であり、後者の場合、保存時の基板へのチップ接続状態の変動が少ないので、安定した特性が得られる。
【０００８】
以上で図１や３のような、複数以上の各種形状やサイズのチップ類２（ａ〜ｃ）の電極４を接着剤３を用いて、基板の両面に高密度に実装するマルチチップモジュール（ＭＣＭ）が得られる。本発明の基板１としては、ポリイミドやポリエステル等のプラスチックフィルム、ガラス繊維／エポキシ等の複合体、シリコン等の半導体、ガラスやセラミック等の無機質等を例示できる。
【０００９】
本発明に用いる接着剤３および接着剤層１０は、熱可塑性材料や、熱や光により硬化性を示す材料が広く適用できる。これらは接続後の耐熱性や耐湿性に優れることから、硬化性材料の適用が好ましい。なかでも潜在性硬化剤を含有したエポキシ系接着剤は、短時間硬化が可能で接続作業性がよく、分子構造上接着性に優れるので特に好ましい。潜在性硬化剤は、熱およびまたは圧力による反応開始の活性点が比較的明瞭であり、熱や圧力工程を伴う本発明に好適である。
潜在性硬化剤としては、イミダゾール系、ヒドラジド系、三フッ化ホウ素−アミン錯体、アミンイミド、ポリアミンの塩、オニウム塩、ジシアンジアミドなど、及びこれらの変性物があり、これらは単独または２種類以上の混合体として使用できる。
これらは、アニオン又はカチオン重合型などのいわゆるイオン重合性の触媒型硬化剤であり、速硬化性を得やすく、また化学当量的な考慮が少なくてよいことから好ましい。これらの中では、イミダゾール系のものが非金属系であり電食しにくく、また反応性や接続信頼性の点から特に好ましい。硬化剤としてはその他に、ポリアミン類、ポリメルカプタン、ポリフェノール、酸無水物等の適用や前記触媒型硬化剤との併用も可能である。また硬化剤を核とし、その表面を高分子物質や、無機物で被覆したマイクロカプセル型硬化剤は、長期保存性と速硬化性という矛盾した特性の両立があることが好ましい。
本発明の硬化剤の活性温度は、４０〜２００℃が好ましい。４０℃未満であると室温との温度差が少なく保存に低温が必要であり、２００℃を越すと接続の他の部材に熱影響を与えるためであり、このような理由から５０〜１５０℃がより好ましい。本発明の活性温度は、ＤＳＣ（示差走査熱量計）を用いて、エポキシ樹脂と硬化剤の配合物を試料として、室温から１０℃／分で昇温させた時の発熱ピーク温度を示す。活性温度は、低温側であると反応性に勝るが保存性が低下する傾向にあるので、これらを考慮して決定する。
本発明において、硬化剤の活性温度以下の熱処理により、仮接続することで接着剤付き基板の保存性が向上し、活性温度以上で信頼性に優れたマルチチップの接続が得られる。
【００１０】
これら接着剤３には、導電粒子や絶縁粒子を添加することが、接着剤付きチップの製造時の加熱加圧時に厚み保持材として作用するので好ましい。この場合、導電粒子や絶縁粒子の割合は、０．１〜３０体積％程度であり、異方導電性とするには０．５〜１５体積％である。接着剤層４は、絶縁層と導電層を分離形成した複数層の構成品も適用可能である。この場合、分解能が向上するため高ピッチな電極接続が可能となる。
導電粒子としては、Ａｕ、Ａｇ、Ｐｔ、Ｎｉ、Ｃｕ、Ｗ、Ｓｂ、Ｓｎ、はんだ等の金属粒子やカーボン、黒鉛等があり、またこれら導電粒子を核材とするか、あるいは非道電性のガラス、セラミックス、プラスチック等の高分子等からなる核材に、前記したような材質からなる導電層を被覆形成したものでよい。さらに導電材料を絶縁層で被覆してなる絶縁被覆粒子や、導電粒子とガラス、セラミックス、プラスチック等の絶縁粒子の併用等も、分解能が向上するので適用可能である。
これら導電粒子の中では、プラスチック等の高分子核材に導電層を形成したものや、はんだ等の熱溶融金属が、加熱加圧もしくは加圧により変形性を有し、接続に回路との接触面積が増加し、信頼性が向上するので好ましい。特に高分子類を核とした場合、はんだのように融点を示さないので硬化の状態を接続温度で広く制御でき、電極の厚みや平坦性のばらつきに対応し易いので特に好ましい。また、例えばＮｉやＷ等の硬質金属粒子や、表面に多数の突起を有する粒子の場合、導電粒子が電極や配線パターンに突き刺さるので、酸化膜や汚染層の存在する場合にも低い接続抵抗が得られ、信頼性が向上するので好ましい。
以上の説明では、フィルム状接着剤を用いた場合について述べたが、液状もしくはペースト状についても、同様に適用可能である。またチップ高さの異なる場合について述べたが、チップ高さが同等の場合も適用可能である。さらに基板へのチップ搭載個数が単数でもよく、他の基板面にチップではなく、例えば凹凸の大きな回路などの場合にも同様に適用可能である。
【００１１】
本発明のマルチチップ実装法によれば、２枚の基板表面にそれぞれチップを実装した後、前記基板の裏面間に接着剤層を介在させ両基板を接着するので、接続時の加圧が基板の片側毎に行われ影響が半分に分散され、圧力むらのない均一加圧が得られる。これは基板の両面に実装する場合に、表裏でチップ位置が対象状態に設置される場合が少ないことから、圧力むらのない均一加圧が要求される微細電極の接合に極めて有効である。
本発明のマルチチップ実装法によれば、基板の裏面間に接着剤層を介在させ両基板を接着するので、基板種類の組み合わせの多様性に対応可能となる。すなわち、片側に高精細なピッチに対応可能な高価な基板を配置し、他の面には安価な一般基板といった特性や価格対応の組み合わせや、ガラス基板と有機基板といった材質の組み合わせ等が可能となる。
本発明のマルチチップ実装法によれば、接着剤層を介在させて両基板を接着するので、接着剤はシート状、液状、ペースト状、プリプレグといった各種の形態が使用でき、必要な特性に応じた接着剤の選択が可能であり、選択の自由度が向上する。さらに接着剤は、適当な厚みとすることで、接続時にクッション材的に作用し圧力むらのない均一加圧が得られる。また基板接着時の加熱により、チップ実装部の熱硬化反応を促進可能であり、チップ実装部のリペアにも有効である。すなわち、基板へのチップ実装部の硬化反応を不十分な状態で導通検査等の特性チェックを行い、特性不良なときにチップを再接続するが、この時接着剤の硬化反応が不十分な状態なので剥離が容易である。
本発明の好ましい実施態様によれば、両基板の接着温度をチップ実装材料のガラス転移点より低温とすることで、チップを実装部熱の影響が少なくなり、接続歩留まりが向上する。
以上は、両面のマルチチップ実装法について述べたが、同様なことは片面にチップ類を搭載した基板を、配線や電子部品などにより凹凸を有する他の基板に積層する場合にもいえる。
【００１２】
【実施例】
以下実施例でさらに詳細に説明するが、本発明はこれに限定されない。
実施例１〜２
（１）接着剤付き基板の作製
フェノキシ樹脂（高分子量エポキシ樹脂）とマイクロカプセル型潜在性硬化剤を含有する液状エポキシ樹脂（エポキシ当量１８５）の比率を２５／７５とし、酢酸エチルの３０％溶液を得た。この溶液に、粒径３±０．２μｍのポリスチレン系粒子に、Ｎｉ／Ａｕの厚さ０．２／０．０２μｍの金属被覆を形成した導電性粒子を２体積％添加し混合分散した。
この分散液をセパレータ（シリコーン処理ポリエチレンテレフタレートフィルム）にロールコータで塗布し、１００℃で２０分乾燥し、厚み４０μｍのフィルム状接着剤を得た。
５ｍｍ×１１ｍｍで厚み０．４ｍｍのガラスエポキシ基板（ＦＲ−４グレート）および同サイズのＦＰＣ（厚み５０μｍポリイミド基板）上に、高さ１８μｍの銅の回路を有し、回路端部が後記するＩＣチップのバンプピッチに対応した接続電極を有する２種の基板の接続領域に、前記フィルム状接着剤を貼り付けて形成しセパレータを剥離した。この接着層のＤＳＣによる活性温度は１２０℃であり、２００℃、１０分硬化後のガラス転移点（Ｔｇ）は１４５℃であった。
【００１３】
（２）電極の位置合わせと接続
前記の接着剤付き基板に、ＩＣチップ３個（高さ０．３、０．５５、１．０ｍｍ、バンプ高さ２０μｍ）を配置し、ＣＣＤカメラによる電極の位置合わせを行った。接着剤は室温でも若干の粘着性がある状態であり、室温で接着面に押しつけることで基板に簡単に保持でき、チップの仮付け基板を得た。チップの仮付け基板を、ＡＣ−ＳＣ４５０Ｂ（日立化成工業（株）製ＣＯＢ接続装置）の定盤上に基板面の来るように載せた。チップ面の上に緩衝層としてＴＣ−８０Ａ（信越化学（株）製放熱用シリコンゴム、厚み０．８ｍｍ、ＪＩＳゴム硬度７５、熱伝導率３×１０-³ｃａｌ／ｃｍ／ｓｅｃ／℃）を基板と同一サイズでチップ接続部を覆ってかぶせた。２０ｋｇｆ／ｍｍ² 、１０秒間の加熱加圧により接続した。なお温度は、２０秒間に接着剤が１７０℃となるようにした。
（３）基板の張り合わせ
２種の基板間に、（１）の接着剤（実施例１）および導電性粒子の添加なし（実施例２）を形成し両基板を張り合わせ、ＡＣ−ＳＣ４５０Ｂを用いて１３０℃、２０ｋｇｆ／ｍｍ² 、５分間の加熱加圧を行った。
（４）評価
各チップの電極と基板電極は良好に接続が可能であった。接着剤はチップ近傍にみに存在しているので、基板表面に不要接着剤は殆どなかった。
本実施例では、高さの異なるＩＣチップ３個を基板の両面に接続できた。
実施例１の場合、基板が絶縁性のため、チップ接続と全く同一の接着剤の使用が可能であり工程が簡単であった。また、導電粒子が基板間のギャップ調整材となり同一厚みで基板間の接着が可能であった。実施例２の場合は、両基板のＩＣチップ高さにある程度順応した形で接着していた。
【００１４】
実施例３
実施例１と同様であるが、チップの仮付け基板を得た後で、電極間の電気的接続を検査する中間検査工程を設けた。まず、７０℃、１０ｋｇｆ／ｍｍ^２で、スプリング装置で加圧しながら各接続点の接続抵抗をマルチメータで測定検査したところ、各基板について１個のＩＣチップが異常であった。そこで異常チップを剥離して新規チップで前記同様の接続を行ったところ良好であった。本実施例では、接着剤の硬化反応が不十分な状態なので、チップの剥離や、その後のアセトンを用いた清浄化も極めて簡単であり、リペア作業が容易であった。また、チップの周囲の余剰接着剤も同様にアセトンで簡単に除去可能であった。以上の通電検査工程およびリペア工程の後で、実施例１のＡＳ−ＳＣ４５０Ｂの代わりにオートクレーブに入れて処理したところ、良好な接続特性を示した。接着剤の硬化後であると、チップの剥離や、その後の溶剤による清浄化が極めて困難であるが、本実施例によれば、狭い基板状に多数のチップが存在する場合も、リペア作業が極めて容易であった。
【００１５】
実施例４〜５
実施例２の基板張り合わせ用接着剤である導電性粒子の添加なし接着剤を用いて同様にチップを実装し、実施例１〜２と同様に基板を張り合わせた。接着層は導電性粒子を添加した接着剤（実施例４）および導電性粒子の添加なし（実施例５）とした。また、両基板の張り合わせはＡＣ−ＳＣ４５０Ｂではなく、オートクレーブで１２０℃、１０ｋｇｆ／ｍｍ² 、２０分間空気圧で処理後に室温に冷却して取出した。
本実施例では、高さの異なるＩＣチップ３個を絶縁性接着剤を用いて基板の両面に接続できた。また両基板の張り合わせは、オートクレーブで行うことが可能であった。オートクレーブの場合、加圧釜の中に同時に沢山の基板の張り合わせが可能なので生産性が増大する。
【００１６】
【発明の効果】
以上詳述したように本発明によれば、チップ高さの異なる場合や基板の両面に実装する場合に有効で、かつリペアに対応可能な、基板の両面に実装する場合に有効なマルチチップ実装法を提供できる。
【図面の簡単な説明】
【図１】本発明の一実施例を説明する、基板上の電極とチップ電極間に、接着剤を介在させ位置合わせした状態を説明する断面模式図である。
【図２】本発明の一実施例を説明する、チップ付き基板の間に接着剤層を介在させ、両基板を接着することを説明する断面模式図である。
【図３】本発明の一実施例を説明する、チップ付き基板の間に接着剤層を介在させ、両基板を接着する工程を説明する断面模式図である。
【符号の説明】
１基板
２チップ
３接着剤
４電極Ａ
５電極Ｂ
６定盤
７加圧型
８チップ付き基板Ａ
９チップ付き基板Ｂ
１０接着剤層[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a multichip mounting method on a substrate surface.
[0002]
[Prior art]
With the miniaturization and thinning of semiconductor chips and electronic components, the circuits and electrodes used for these have become higher in density and higher in definition. For the connection of such fine electrodes, a method using an adhesive has recently been frequently used. In this case, the conductive particles are blended in the adhesive, and electrical connection is obtained in the thickness direction of the adhesive by pressurization (for example, Japanese Patent Application Laid-Open No. 55-104007). There is one that obtains an electrical connection by direct contact of fine irregularities on the electrode surface by pressure (for example, JP-A-60-262430).
The connection method using an adhesive enables connection at a relatively low temperature, and the connection part is flexible, so it has excellent reliability. In addition, when a film or tape adhesive is used, it has a certain length. Since it is supplied in the form of a scale, it is attracting attention because the mounting line can be automated.
In recent years, a multi-chip module (MCM) that has developed the above-described method and mounts a plurality of chips on a relatively small substrate with high density has attracted attention. In this case, it is a general practice to first form an adhesive layer on the entire surface of the substrate, then peel off the separator, if any, and then align and bond the substrate electrode and the chip electrode. As chips used for MCM, there are many types (hereinafter referred to as chips) such as a semiconductor chip, an active element, a passive element, a resistor, and a capacitor.
[0003]
[Problems to be solved by the invention]
There are many types of chips used for MCM, and there are many types of chip sizes (area, height) accordingly. For this reason, when connecting to the substrate using an adhesive, unprecedented problems have arisen due to the thermocompression bonding method with the substrate. For example, when the chip height is different or when mounting on both sides of the board, the conventional method of pressing the parallel installed mold by hydraulic or pneumatic pressure, or the parallel installation of rubber or metal In the so-called roll method in which compression is performed with a pressure roll, as shown in FIG. 3, there is a drawback that heating and pressurization are not performed uniformly if the chip height is different.
That is, in these press methods and roll methods, pressure is applied between molds and rolls, for example, between the parallel surface plate 6 and the pressure die 7, so that the chip height is different (2, 2a, 2b). Or 2 ', 2a'2b') or a chip mounted on both sides of the substrate (such as 2 and 2 '), the pressurization state is not constant, so that the connection between the electrodes is insufficient and connection reliability is obtained. Absent.
In particular, when mounting on both surfaces (3 and 3 'surfaces) of the substrate, there are few cases where the chip position is placed in the target state on the front and back sides, so the joining of the fine electrodes that require uniform pressure without pressure unevenness In this state, there is no appropriate means for applying pressure. The same can be said for a case where a substrate on which chips are mounted on one side is laminated on another substrate having irregularities by wiring, electronic parts, or the like.
Still another problem is chip repair. This is considered to be extremely difficult if the adhesive has undergone a curing reaction when the chip after mounting is replaced because the chip is difficult to peel off and the adhesive is difficult to remove. In particular, in the case of multi-chip mounting, the distance between adjacent chips is narrow and mechanical removal is difficult, and the substrate is also attacked by an organic solvent if the substrate is an organic substrate such as glass, epoxy, film, etc. It seemed impossible because of restrictions.
The present invention has been made in view of the above-described drawbacks, and provides a multi-chip mounting method that is effective when mounting chips of different heights on both sides of a substrate and is compatible with repair.
[0004]
[Means for Solving the Problems]
In the present invention, at least one of two substrates, each of which is an organic substrate, is mounted with an IC chip having a different height on the electrode surface of each substrate with an adhesive to obtain electrical connection, and then an adhesive is interposed between the back surfaces of the substrates. The present invention relates to a multichip mounting method characterized in that both substrates are bonded at a temperature lower than the glass transition point of the chip mounting adhesive. In addition, IC chips with different heights are mounted on the electrode surfaces of two substrates , at least one of which is an organic substrate, under conditions where the adhesive is not sufficiently cured, and a continuity test is performed in this state as necessary. Thereafter, an adhesive layer is interposed between the back surfaces of the substrates to bond both the substrates at a temperature lower than the glass transition point of the chip mounting adhesive, thereby promoting the curing reaction of the adhesive in the mounting portion. The present invention relates to a multi-chip mounting method.
[0005]
DETAILED DESCRIPTION OF THE INVENTION
The present invention will be described below with reference to the drawings.
FIG. 1 shows a state in which an adhesive 3 is interposed between a formation surface of an electrode 5 on a substrate 1 and the electrodes 4 of a plurality of chips 2, 2a, 2b, and the electrodes of the chips facing each other are aligned. It is a cross-sectional schematic diagram shown. Either the electrode B5 on the substrate 1 or the electrode A4 on the chip 2 may use the wiring circuit as a connection terminal as it is, or may further form a protruding electrode. It is preferable that the electrodes 4 and / or 5 have a protruding shape because electrical connection is easy because pressure is concentrated between the electrodes facing each other. The adhesive 3 may be a film, a liquid, or a paste. Further, the adhesive layer may be divided into two and a multilayer substrate such as a double-sided board may be disposed between the substrates with adhesive.
As a method of aligning the electrode of the chip with adhesive to be connected and the electrode of the substrate, the electrode 5B of the substrate 1 to be connected and the electrode A4 of the chip 2 are aligned using a microscope or an image storage device. At this time, the use or use of the alignment mark is also effective.
The substrate 1 and the chip 2 after the alignment can be held by temporarily connecting them using the adhesive property of the adhesive 3 and the cohesive force. In addition, auxiliary means such as a clip and an adhesive tape can be applied alone or in combination. Since the temporary connection may be non-uniform as long as the heating and pressurization is performed to some extent, a conventionally used thermocompression bonding apparatus can be used.
[0006]
A chip electrode connection on the substrate is obtained by heating and pressurizing the electrode of the chip and the electrode of the substrate that have been aligned. At this time, when the height from the substrate 1 is different as in the chips 2, 2 a, 2 b, a buffer layer such as rubber is formed between the chip surface and the pressure mold 7, or hydrostatic pressure can be achieved by an autoclave or the like. A substrate with a chip can be produced by applying pressure, pressing between rubber rolls having cushioning properties, or applying pressure independently for each chip. It is also possible to perform a continuity test between the electrodes to be connected in the electrode positioning step and the electrical connection step. Since the adhesive can be inspected for continuity in an uncured state or in a state where the curing reaction is insufficient, the repair work of the adhesive is easy. Similarly, it is possible to add a step of removing excess adhesive around the chip. According to this method, since a good connection product that has completed the continuity test advances the curing reaction of the adhesive in the next step, the defective product is regenerated and the process loss time is short.
[0007]
FIG. 2 is a schematic cross-sectional view showing an embodiment of the present invention for explaining that an adhesive layer 10 is interposed between the substrates with chips 8 and 9 manufactured as shown in FIG. is there. The bonding temperature at this time is preferably lower than the glass transition point of the adhesive 3 that is the chip mounting material because the adhesion of the chip to the substrate does not deteriorate.
As an adhesion method, the above-described buffer layer, rubber roll, and hydrostatic pressure can be applied. Further, at the time of bonding the two substrates, it is sufficient that the chip is aligned and fixed to the substrates, and the cured state of the adhesive on each substrate is not limited.
That is, chip connection to the substrate can be performed by performing the curing reaction of the adhesive 3 and the adhesive layer 10 at the same time in the bonding process of both substrates in a state where the adhesive is uncured or the curing reaction is insufficient. The adhesive for chip connection may be one in which the curing reaction has been completed. In the former case, it is effective for shortening the manufacturing process time and repair work, and in the latter case, since the variation of the chip connection state to the substrate during storage is small, stable characteristics can be obtained.
[0008]
As described above, a multi-chip module (see FIG. 1 or 3) in which the electrodes 4 of a plurality of chips 2 (ac) having various shapes and sizes are mounted on both sides of the substrate with high density using the adhesive 3 ( MCM) is obtained. Examples of the substrate 1 of the present invention include plastic films such as polyimide and polyester, composites such as glass fiber / epoxy, semiconductors such as silicon, and inorganic materials such as glass and ceramics.
[0009]
As the adhesive 3 and the adhesive layer 10 used in the present invention, thermoplastic materials and materials that exhibit curability by heat and light can be widely applied. Since these are excellent in heat resistance and moisture resistance after connection, application of a curable material is preferable. Among them, an epoxy adhesive containing a latent curing agent is particularly preferable because it can be cured for a short time, has good connection workability, and is excellent in adhesion due to its molecular structure. The latent curing agent has a relatively clear active site of reaction initiation by heat and / or pressure, and is suitable for the present invention involving heat and pressure processes.
Examples of latent curing agents include imidazole series, hydrazide series, boron trifluoride-amine complex, amine imide, polyamine salt, onium salt, dicyandiamide, and modified products thereof. These may be used alone or in combination of two or more. Can be used as a body.
These are so-called ion polymerizable catalyst-type curing agents such as anion or cation polymerization type, and are preferable because they are easy to obtain fast curability and less chemical equivalent considerations are required. Among these, imidazole compounds are non-metallic, are less susceptible to electrolytic corrosion, and are particularly preferable in terms of reactivity and connection reliability. In addition, polyamines, polymercaptans, polyphenols, acid anhydrides, and the like can be used as the curing agent, and the catalyst-type curing agent can be used in combination. Moreover, it is preferable that a microcapsule type curing agent having a curing agent as a core and having a surface coated with a polymer material or an inorganic material has both contradictory properties of long-term storage and fast curing.
As for the active temperature of the hardening | curing agent of this invention, 40-200 degreeC is preferable. If the temperature is less than 40 ° C, the temperature difference from room temperature is small and a low temperature is required for storage. If the temperature exceeds 200 ° C, the other members of the connection are affected by heat. More preferred. The active temperature of the present invention indicates an exothermic peak temperature when the temperature is raised from room temperature to 10 ° C./min using a DSC (differential scanning calorimeter) as a sample of a mixture of an epoxy resin and a curing agent. The active temperature is determined in consideration of these because the low temperature side tends to have better reactivity but lower storage stability.
In the present invention, the storability of the substrate with adhesive is improved by temporary connection by a heat treatment below the activation temperature of the curing agent, and a multi-chip connection with excellent reliability at the activation temperature or higher is obtained.
[0010]
It is preferable to add conductive particles or insulating particles to these adhesives 3 because they act as a thickness maintaining material during heating and pressurization at the time of manufacturing a chip with adhesive. In this case, the ratio of conductive particles or insulating particles is about 0.1 to 30% by volume, and 0.5 to 15% by volume for anisotropic conductivity. As the adhesive layer 4, a multi-layer component in which an insulating layer and a conductive layer are separately formed can be applied. In this case, since the resolution is improved, electrode connection with a high pitch is possible.
Examples of the conductive particles include metal particles such as Au, Ag, Pt, Ni, Cu, W, Sb, Sn, and solder, carbon, graphite, and the like. These conductive particles are used as a core material or non-conductive. A core material made of a polymer such as glass, ceramics, or plastic may be coated with a conductive layer made of the material described above. Furthermore, insulating coating particles formed by coating a conductive material with an insulating layer, or a combination of conductive particles and insulating particles such as glass, ceramics, and plastics can be applied because the resolution is improved.
Among these conductive particles, those in which a conductive layer is formed on a polymer core material such as plastic, and hot-melt metal such as solder are deformable by heating or pressurization, and contact with a circuit for connection This is preferable because the area is increased and the reliability is improved. In particular, a polymer as a core is particularly preferable because it does not show a melting point like solder and the curing state can be widely controlled by the connection temperature, and it is easy to deal with variations in electrode thickness and flatness. Also, for example, in the case of hard metal particles such as Ni and W, or particles having a large number of protrusions on the surface, the conductive particles pierce the electrode and the wiring pattern, so that even when an oxide film or a contaminated layer exists, a low connection resistance is obtained. It is preferable because it is obtained and reliability is improved.
In the above description, the case where a film adhesive is used has been described, but the present invention can be similarly applied to a liquid or paste. Further, the case where the chip heights are different has been described, but the case where the chip heights are equivalent is also applicable. Furthermore, the number of chips mounted on the substrate may be single, and the present invention is similarly applicable to a case where, for example, a circuit with large irregularities is used instead of the chip on the other substrate surface.
[0011]
According to the multichip mounting method of the present invention, after the chips are mounted on the surfaces of the two substrates, respectively, the adhesive layer is interposed between the back surfaces of the substrates to bond the two substrates. The effect is distributed in half, and uniform pressurization without pressure unevenness is obtained. This is very effective for bonding fine electrodes that require uniform pressure without pressure unevenness because the chip position is rarely placed in the target state on both sides when mounted on both sides of the substrate.
According to the multichip mounting method of the present invention, since both substrates are bonded with an adhesive layer interposed between the back surfaces of the substrates, it is possible to cope with a variety of combinations of substrate types. In other words, an expensive substrate that can handle a high-definition pitch is placed on one side, and the other surface can be a combination of characteristics such as an inexpensive general substrate or a price-compatible combination, or a combination of materials such as a glass substrate and an organic substrate. Become.
According to the multichip mounting method of the present invention, both substrates are bonded with an adhesive layer interposed therebetween, so that the adhesive can be used in various forms such as sheet, liquid, paste, and prepreg, depending on the required characteristics. The adhesive can be selected, and the degree of freedom of selection is improved. Furthermore, by setting the adhesive to an appropriate thickness, it acts as a cushioning material at the time of connection, and uniform pressure without pressure unevenness can be obtained. In addition, the heat curing reaction of the chip mounting portion can be promoted by heating at the time of bonding the substrate, which is also effective for repairing the chip mounting portion. In other words, a characteristic check such as continuity inspection is performed with insufficient curing reaction of the chip mounting part to the substrate, and the chip is reconnected when the characteristic is poor, but at this time the adhesive curing reaction is insufficient So peeling is easy.
According to a preferred embodiment of the present invention, the bonding temperature of the two substrates is lower than the glass transition point of the chip mounting material, so that the influence of the heat of the mounting portion of the chip is reduced and the connection yield is improved.
The multi-chip mounting method on both sides has been described above, but the same can be said for the case where a substrate on which chips are mounted on one side is laminated on another substrate having unevenness by wiring, electronic parts, or the like.
[0012]
【Example】
Hereinafter, the present invention will be described in more detail with reference to examples, but the present invention is not limited thereto.
Examples 1-2
(1) Preparation of substrate with adhesive 30% solution of ethyl acetate with a ratio of liquid epoxy resin (epoxy equivalent 185) containing phenoxy resin (high molecular weight epoxy resin) and microcapsule type latent curing agent to 25/75 Got. To this solution, 2% by volume of conductive particles having a Ni / Au thickness of 0.2 / 0.02 μm formed on polystyrene particles having a particle diameter of 3 ± 0.2 μm were added and mixed and dispersed.
This dispersion was applied to a separator (silicone-treated polyethylene terephthalate film) with a roll coater and dried at 100 ° C. for 20 minutes to obtain a film adhesive having a thickness of 40 μm.
An IC having a circuit of 18 μm in height on a 5 mm × 11 mm glass epoxy substrate (FR-4 great) having a thickness of 0.4 mm and an FPC (50 μm thick polyimide substrate) of the same size and having a circuit end portion described later. The film adhesive was applied to the connection region of two types of substrates having connection electrodes corresponding to the bump pitch of the chip, and the separator was peeled off. The activation temperature by DSC of this adhesive layer was 120 ° C., and the glass transition point (Tg) after curing at 200 ° C. for 10 minutes was 145 ° C.
[0013]
(2) Positioning and connection of electrodes Three IC chips (height 0.3, 0.55, 1.0 mm, bump height 20 μm) are arranged on the above-mentioned substrate with adhesive, and the electrodes of the CCD camera are arranged. Alignment was performed. The adhesive was in a state where there was a slight stickiness even at room temperature, and it could be easily held on the substrate by pressing against the adhesive surface at room temperature, and a temporary substrate for chip was obtained. The temporary mounting substrate of the chip was placed on the surface plate of AC-SC450B (COB connecting device manufactured by Hitachi Chemical Co., Ltd.) so that the substrate surface would come. TC-80A (Shin-Etsu Chemical Co., Ltd. heat dissipation silicon rubber, thickness 0.8 mm, JIS rubber hardness 75, thermal conductivity 3 × 10 ⁻³ cal / cm / sec / ° C.) as a buffer layer on the chip surface. The chip connection part was covered and covered with the same size as the substrate. The connection was established by heating and pressing at 20 kgf / mm ² for 10 seconds. The temperature was such that the adhesive was 170 ° C. for 20 seconds.
(3) Bonding of substrates Between the two types of substrates, the adhesive (Example 1) and no addition of conductive particles (Example 2) were formed, and the two substrates were bonded together, using AC-SC450B. Heating and pressing were performed at 130 ° C. and 20 kgf / mm ² for 5 minutes.
(4) Evaluation The electrode of each chip and the substrate electrode could be satisfactorily connected. Since the adhesive was present only near the chip, there was almost no unnecessary adhesive on the substrate surface.
In this example, three IC chips having different heights could be connected to both sides of the substrate.
In the case of Example 1, since the substrate is insulative, it is possible to use the same adhesive as the chip connection, and the process is simple. In addition, the conductive particles became a gap adjusting material between the substrates, and it was possible to bond the substrates with the same thickness. In the case of Example 2, the two substrates were bonded in a form that conformed to the IC chip height to some extent.
[0014]
Example 3
Although it is the same as that of Example 1, the intermediate | middle test process which test | inspects the electrical connection between electrodes was provided after obtaining the temporary attachment board | substrate of the chip | tip. First, when the connection resistance at each connection point was measured and inspected with a multimeter while applying pressure with a spring device at 70 ° C. and 10 kgf / mm ² , one IC chip was abnormal for each substrate. Therefore, the abnormal chip was peeled off and the same connection as described above was performed with a new chip. In this example, since the curing reaction of the adhesive was insufficient, the chip peeling and the subsequent cleaning with acetone were extremely simple, and the repair work was easy. Also, the excess adhesive around the chip could be easily removed with acetone as well. After the energization inspection process and the repair process described above, the sample was put in an autoclave instead of the AS-SC450B of Example 1, and showed good connection characteristics. After the adhesive is cured, chip peeling and subsequent cleaning with a solvent are extremely difficult.According to this embodiment, even when a large number of chips exist on a narrow substrate, the repair work can be performed. It was very easy.
[0015]
Examples 4-5
A chip was mounted in the same manner using an adhesive without addition of conductive particles, which was an adhesive for substrate bonding in Example 2, and the substrates were bonded in the same manner as in Examples 1-2. For the adhesive layer, an adhesive to which conductive particles were added (Example 4) and no conductive particles were added (Example 5). In addition, the substrates were bonded to each other not by AC-SC450B but by an autoclave at 120 ° C., 10 kgf / mm ² and air pressure for 20 minutes, and then cooled to room temperature and taken out.
In this example, three IC chips having different heights could be connected to both sides of the substrate using an insulating adhesive. In addition, the substrates could be bonded together by an autoclave. In the case of an autoclave, productivity can be increased because a large number of substrates can be bonded together in a pressure vessel.
[0016]
【The invention's effect】
As described above in detail, according to the present invention, multi-chip mounting is effective when mounting on both sides of a substrate, which is effective when mounting on both sides of the substrate or on different surfaces of the substrate, and is compatible with repair. Can provide law.
[Brief description of the drawings]
BRIEF DESCRIPTION OF DRAWINGS FIG. 1 is a schematic cross-sectional view illustrating a state in which an adhesive is interposed between an electrode on a substrate and a chip electrode for explaining an embodiment of the present invention.
FIG. 2 is a schematic cross-sectional view for explaining one embodiment of the present invention and explaining that an adhesive layer is interposed between substrates with chips and that the two substrates are bonded together.
FIG. 3 is a schematic cross-sectional view for explaining an embodiment of the present invention and explaining a step of bonding both substrates by interposing an adhesive layer between the substrates with chips.
[Explanation of symbols]
1 Substrate 2 Chip 3 Adhesive 4 Electrode A
5 Electrode B
6 Surface plate 7 Pressurizing type 8 Substrate with chip A
9 Substrate with chip B
10 Adhesive layer

Claims

After mounting IC chips of different heights on the electrode surfaces of two substrates, at least one of which is an organic substrate, using an adhesive to obtain electrical connection , the adhesive is interposed between the back surfaces of the substrates, and chip mounting A multi-chip mounting method characterized in that both substrates are bonded at a temperature lower than the glass transition point of the adhesive.

After mounting IC chips with different heights on the electrode surfaces of two substrates, at least one of which is an organic substrate, under conditions where the adhesive is not sufficiently cured, and conducting a continuity test as necessary in this state A multi-chip characterized in that an adhesive layer is interposed between the back surfaces of the substrates to bond the two substrates at a temperature lower than the glass transition point of the chip mounting adhesive to accelerate the curing reaction of the adhesive in the mounting portion. Implementation method.