JP3464826B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [0001] BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device,
The semiconductor chip via bumps on the wiring board.
The present invention relates to a semiconductor device mounted in a down state. [0002] 2. Description of the Related Art Technology for high-speed and high-density electronic devices
Recently, there are many methods to connect bare chips directly to the substrate.
Well developed. Specifically, these methods
Wire bonding method, TAB method, flip chip method
and so on. Wire bonding
The method is to place the semiconductor chip face-up and
Connect the electrode pad and the pad on the substrate with a wire such as gold.
It is a method of connecting. But wire bondin
Very small pitch such as 50 μm pitch
Is difficult at present and suitable for high density
Not. The TAB method uses a copper foil on a polyimide film.
To form wiring, and to reconnect the electrode pads of the semiconductor chip and the copper foil.
This is a method of connecting the circuit board via a bump. This way
Is that polyimide film itself is expensive and
In the case of connection, the dimensional system depends on the heat shrinkage of the film etc.
It has the disadvantage that it cannot be obtained sufficiently. On the other hand, the flip-chip method uses a semiconductor
Metal bumps are deposited on the pads on the chip by vapor deposition, dipping,
This metal bump and the wiring board are formed by plating, etc.
It is a method of aligning and connecting with the surface metal pad.
You. This flip chip method uses the entire surface of the semiconductor chip.
Connection can be made using
Connection at very fine pitch.
Due to such things as wire bonding method and TAB
Technology enables high-density mounting compared to other methods.
It can be shaped. Also, the semiconductor chip and the wiring base
Because the board is directly connected by metal bumps,
Extra wiring such as tape is not required, and signal transmission delay
Can reduce the power consumption of electronic devices.
You. Conventional connection method by flip chip method
Is performed as described below. That is, as shown in FIG.
First, on the semiconductor chip 1, the evaporation method, the dip
The metal bump 2 is formed by a method, a plating method, or the like. Next
Semiconductor chip 1 on which electrode bumps are formed and wiring substrate
4 and align the bumps 2 and the pads 3 of the substrate.
Connect by pressure heating reflow. Then the semiconductor chip
Silicone, acrylic, air
It is sealed with a liquid resin 8 such as a oxy resin. [0006] However, the conventional flip chip method is as follows.
It had the following disadvantages. (1) Liquid resin for sealing between the semiconductor chip and the wiring board
Is a hard resin with a large Young's modulus.
It is difficult to get between the chip and the wiring board, resulting in poor reliability.
Conversion had occurred. (2) Bump between semiconductor chip and wiring board
Occurs when connecting at high temperature when connecting via
Reliable semiconductor without mechanical strain relief
Could not provide body device. (3) A tree between the semiconductor chip and the wiring board
When sealing the grease, the liquid resin spreads on the wiring board.
wait. Next, flip chip in high temperature and high humidity environment
In the case of mounting, the wiring
There is a problem that eclipse and deterioration of the joint occur.
In order to solve the problem, as described above, the semiconductor element and the wiring board
To prevent moisture from entering by resin sealing
Although the method is generally used, a protruding electrode such as solder
(Bump), the semiconductor element and the wiring board, and the sealing resin.
Cracks in joints due to mismatch in coefficient of thermal expansion
There is a problem that a defect such as a failure occurs. Further, there is the following problem. That is,
Chip mounting is wire bonding mounting or TAB
Semiconductor chips can be mounted on the board at a higher density than mounting.
The advantage is that That is, wire bonding or T
When mounting a semiconductor chip using AB mounting, use a semiconductor
The mounting area including the lead pulled out from the body chip is half
Flip chips are required because they require two to three times the size of conductor chips.
Mounting density is 1/2 to 1/3 compared to
You. . Therefore, wire bonding mounting or TAB mounting
Has a limit in increasing the density. In contrast, flip flip
In chip mounting, the mounting area is the chip area of the semiconductor chip.
Therefore, chips can be mounted adjacent to each other. So flip
Chip mounting enables high-density mounting. [0010] This flip chip mounting method is enabled.
In order to achieve this, projecting
A bump electrode having a shape must be formed. this
Various methods have been proposed for bump formation.
"Semiconductor Packaging Handbook" Science Forum
This is described in detail in pp131. For example, FIG.
As shown in FIG.
75, and a bump electrode metal 54 is
Some are formed by a key, etc.
It is called a lumpy bump. Further, as shown in FIG.
Form a barrier metal 75 on the bonding pad 71
Using a thick-film resist with an open pad
The one in which the bump 54 is formed vertically by electroplating or the like
Yes, this is called a straight wall bump
You. The flip-chip mounting is performed on the semiconductor chip 53.
The position of the bump electrode 54 and the connection electrode portion 80 of the substrate 51 are aligned.
After that, the solder 85 is reflowed for connection. this
Chip 53 and circuit board when connected by various methods
FIG. 20 shows a cross-sectional structure of the connection portion 51. many
In this case, the solder 85 is formed on the bump 54 in advance.
In the case of supplying in the form of spare solder on the wiring board 51
Perform either one or a combination of both. In general, flip-chip mounting is generally performed using a semiconductor.
The stress generated from the difference between the thermal expansion coefficient of the device and the circuit board
In order to prevent concentration on bumps,
A method of installing a resin between road substrates has been performed. free
Since chip mounting is face-down mounting,
The heating surface of the semiconductor element faces the substrate,
The amount is easily stored in the semiconductor chip. The amount of heat stored is half
This causes a failure of the conductor element. Especially semiconductor elements and substrates
When resin is injected in between, the effect of heat storage is significant. This tree
Failure due to thermal expansion due to the installation of fat
Can be reduced, but not always enough. In particular, semiconductor devices
If the thermal expansion coefficient of the
The stress is concentrated on the interface between the resin and the resin, and the bump is broken. this
The bumps are electrically connected, so if they break down,
In this case, the electrical characteristics are affected, resulting in a failure of the semiconductor device. Therefore, the thermal expansion coefficient of the substrate is determined by the thermal expansion coefficient of silicon.
Attempts have been made to approach the coefficient of expansion. For example, on the substrate
COW (Chip On Wafer) using silicon
r) has been proposed, but the same
Or more complicated processes,
It will be a high strike. [0014] On the other hand, at the bump junction due to thermal stress,
The bump structure to thermal stress to solve the failure
A structure that is resistant to the problem is being used. example
If you want to make the bump shape concavity type considering the connection method
A law has been proposed. This method uses a semiconductor with bumps
When connecting the device to the board, the bumps melt the semiconductor device.
The distance from the substrate of the semiconductor device once connected in the molten state
By pulling apart, it becomes a continuous type, but this
If the method does not calculate the separation distance sufficiently, poor connection will occur.
With the problem that shape control cannot be performed sufficiently.
The effect is not exhibited unless the bump height is increased.
There was a title. Reliability of flip-chip mounted semiconductor devices
As shown in Japanese Patent Application No. 4-19855,
The bumps of the semiconductor chip to be mounted on the center
A method of changing the layout has also been proposed.
Recon semiconductor chip on glass / epoxy substrate
As in the case of flip chip mounting
If the numbers are significantly different, sufficient reliability is obtained.
There was a problem that could not be done. Conventional wire bondin
In the bonding method and the TAB method, the semiconductor element and the substrate are connected to each other.
Can absorb the stress and strain generated at the connection part.
Came. However, flip-chip mounting technology has a rigid connection.
Distortion at the connection is a major problem in reliability
Will cause In any case, the conventional method uses bump bumps.
Although the body can be formed, the semiconductor device having the bumps can be formed.
If the device is mounted on a board,
Breakage occurs at bumps due to differences in expansion coefficients
A serious reliability problem has arisen. So the substrate is silicon
To make suggestions, inject resin or consider thermal stress
Method to make bump structure continuous by controlling in process
However, there are some
Both methods are problematic due to insufficient connection.
Was. Further change the layout of the bumps and execute
To improve reliability by reducing the amount of dynamic displacement has also been proposed.
However, if the coefficient of thermal expansion varies significantly,
Has not been able to exert sufficient effects. [0018] As described above, the conventional
In the flip chip method, the encapsulating resin is distributed with the semiconductor chip.
Does not easily penetrate between wire substrates and when connecting at high temperatures
Distortion is not mitigated and the semiconductor
There is a problem that a body device cannot be obtained. The coefficient of thermal expansion between the substrate and the semiconductor element is
Breakage at bumps due to thermal stress caused by differences
There is also a problem that occurs. The present invention takes the above circumstances into consideration.
Between the semiconductor chip and the wiring board.
Easily penetrates and reduces distortion when connecting, reliability
It is an object to provide a high semiconductor device. Further, the present invention provides a method for improving the sealing property of grease.
Corrosion resistance and moisture resistance by suppressing deterioration of the bonding interface
Improves the grease's moderate softness (thixotro
Due to its picky nature, bump electrodes (such as bumps)
Difference in coefficient of thermal expansion between semiconductor device and wiring board
The purpose of the present invention is to suppress the deterioration due to. Further, according to the present invention, the semiconductor device is extremely severe.
Even when subjected to temperature cycling, bumps that carry electrical connections
Providing highly reliable semiconductor devices that are not destroyed
Aim. [0022] Means for Solving the Problems The present inventionConnect pad
Having a wiring board and metal on connection pads of the wiring board
A semiconductor chip connected via bumps,
Seal the grease between the wiring board and the semiconductor chip.
StoppedA semiconductor device is provided. [0023] [0024] The semiconductor device according to the first aspect of the present invention comprises:
A sheet-like room temperature solid between the semiconductor chip and the wiring board
Sealing with thermosetting resin or thermoplastic resin
Things. Such a semiconductor device has a connection pad.
Thermal curing of solid at room temperature on parts other than connection pads on wiring board
Provide a resin sheet made of conductive resin or thermoplastic resin
Process, a semiconductor chip having the above-mentioned metal bumps on a wiring board.
And align the metal bumps with the connection pads
Pressurizing and heating the wiring board and the semiconductor chip.
To melt the metal bumps and the resin sheet,
A step of connecting to a semiconductor chip, wherein the thermosetting
The curing temperature of the resin or the heat deformation temperature of the thermoplastic resin is
Same or higher than the melting point of the metal that makes up the metal bump
It can be manufactured by a method characterized by high cost
It is. As a thermosetting resin which is a solid at room temperature, for example,
For example, high molecular weight polybutadiene having unsaturated bonds in the molecule
Polyester, silicone resin, maleimide,
Ryl oligomers, etc.
Use epoxy, urethane, novolak phenol, etc.
Can be. As a thermoplastic resin, for example,
For example, polysulfone, polyacrylate, polyphenylene
Oxide, polyamide, polymethylpentene, polyether
-Terimide, polyethylene terephthalate, polycarbonate
Bones, fluorinated resins (PFA, ETFE, etc.)
Can be used. The thermal expansion coefficient of these resins is
It is preferable to approximate the thermal expansion coefficient of These resins
Add an inorganic filler to adjust the coefficient of thermal expansion
May be. As an inorganic filler, for example, glass fiber, silicon
Lica, calcium calcium carbonate, calcium oxide, alumina,
Silicon nitride, talc, or the like can be used. these
Oil and rubber components as stress relievers for inorganic fillers
Any may be added. Also, use a cup to improve adhesion.
A ring agent may be added. As a coupling agent
For example, silane, titanium, aluminum, zirconium
System, phosphorus, etc. are used. The amount of inorganic filler added to the resin
Preferably, it is 5 to 50% by weight of the amount of fat. Also, nothing
The size of the filler is more than 1/3 of the height of the metal bump
It is preferably below. The semiconductor device according to the second aspect of the present invention comprises:
Grease is used instead of the sealing resin. here
"Grease" means that a thickener is dispersed in lubricating oil.
It is a generic term for semi-solid or solid
It is semi-solid or solid when it is not subjected to
When sheared on the lubricated surface, it becomes fluid like oil,
When settled, returns to its original semi-solid or solid state.
It has a picky property. The sealing resin is hard once
Such functionality (thixotropic)
It is not possible to express such properties. In the semiconductor device according to the third aspect of the present invention,
The virtual center line is defined as each side of a rectangular chip or rectangular substrate.
, And a pair of straight lines perpendicular to each other. Some
Refers to a pair of diagonal lines of a rectangular chip or rectangular substrate. What
Note that these pairs of straight lines are in each case rectangular tips
Or, it passes through the center of the rectangular substrate. The virtual center lines are perpendicular to each other and bisect each side
When the semiconductor element is a pair of straight lines,
At a position away from the virtual center line, for example, the diagonal position of the substrate
It is desirable to be arranged in a place. On the other hand, the virtual center line
In the case of a square line, the semiconductor element has a pair of virtual center lines.
Away from, for example, near the center of each side
Is desirable. [0032] According to a first aspect of the present invention, a semiconductor chip and a wiring
Room temperature solid resin is interposed between substrates in advance
Resin between the semiconductor chip and the wiring board
The problem of difficulty in intrusion does not occur. Also, resin sheet
The curing temperature of the thermosetting resin that constitutes
Whether the heat distortion temperature is the same as the melting point of the metal that composes the bump,
Or higher than that, forming bumps
When the temperature of the metal falls below the melting point and cures,
The mechanical strain applied when the board and chip are connected is
Alleviated by the sheet. Also, reduce the size of the resin sheet.
By making the resin suitable, when the resin softens,
There is no danger of flowing and spreading. First aspect of the present invention
Now, with such an operation, a highly reliable semiconductor device
Can be obtained. According to a second aspect of the present invention, a semiconductor chip
Because it is sealed with grease between the wiring board,
Suppresses the deterioration of the bonding interface and improves corrosion resistance and moisture resistance
It can be improved. In addition, moderate grease
Due to its softness (thixotropic properties),
Thermal expansion of electrodes (bumps), semiconductor elements, wiring boards
Deterioration due to a difference in the number can be suppressed. Further, the physical properties of the grease include a freezing point
Is low, the boiling point is preferably high, and the freezing point is -70 ° C.
Hereinafter, the boiling point is preferably 250 ° C. or higher. Ma
In addition, the properties of the above grease include heat dissipation, insulation, and thermal acid.
Use a material with excellent chemical stability, shear resistance and chemical resistance
Is preferred. Furthermore, the wiring surface on the wiring board is
By coating with grease, corrosion resistance of wiring
And moisture resistance can be improved. According to a third aspect of the present invention, a semiconductor chip
The virtual center line is the virtual center of the wiring board to be flip-chip mounted.
The wiring board is arranged so that it does not overlap the center line.
The coefficient of thermal expansion of the semiconductor chip is significantly different from that of the semiconductor chip.
This makes it possible to reduce the amount of displacement of the substrate due to temperature changes.
Even in the case, the deformation amount in the part where the semiconductor chip is mounted
Can be reduced, and as a result, the semiconductor chip
It is possible to reduce the stress at the pump portion. That is, as shown in FIG.
Wiring board 5 whose entire surface is fixed to substrate 52 or housing
1 on which semiconductor chips 53a and 53b are mounted.
When a temperature cycle is applied to the circuit board, the wiring board 51 and the board 5
2 is deformed, but the virtual center line 62a of the wiring board 51 and
A semiconductor chip separated from a virtual center line 63a of the substrate 52;
The wiring board 51 and the base at the portion where the 53a and 53b are mounted
The amount of deformation of the plate 52 is small. FIG. 14 shows the distance from the center of the substrate.
It shows the amount of deformation. As shown in FIG.
When a temperature cycle is applied to the body device, the amount of deformation is
Largest at the heart, but at a greater distance from the center
, The amount of deformation becomes smaller. Therefore the virtual center of the substrate
The virtual center line of the semiconductor chip mounted on the line does not overlap
Flip chip mounting of the semiconductor chip in such a positional relationship
The stress applied to the bumps can be reduced.
As a result, semiconductor devices with high reliability can be easily realized.
Can be done. [0038] EXAMPLES Various examples according to the first to third aspects of the present invention will be described below.
The present invention will be described in more detail.
1 to 6 show an embodiment according to the first aspect of the present invention.
FIG. 9 is a cross-sectional view illustrating each step of a method for manufacturing a semiconductor device.
You. First, as shown in FIG.
6 inches thick 5 with electrode pads (not shown) consisting of
A semiconductor chip wafer 1 of 00 μm is prepared. This semi
10mm square semiconductor chips are arranged on the body chip wafer
Have been. Aluminum pad size is 80μm
Corner and pad pitch are 150μm, these are semiconductor
It is formed around the chip. Next, a barrier metal is placed on the semiconductor wafer 1.
Metal complex film as electron beam evaporation equipment, sputtering equipment
The film is formed using a device. As the metal composite film, for example, Ti
(Film thickness 0.1 μm), Cr (film thickness 0.1 μm), Cu
(Film thickness 1.0 μm), Ni (film thickness 1.0 μm) and
Can be used. Next, a metal bump 2 is formed on the barrier metal.
Is formed by a vapor deposition method, a dipping method, a plating method, or the like. metal
As the bump 2, tin, lead, bismuth, indium,
Cadmium, gold, silver, antimony, gallium, etc.
Body, or an alloy of two or more of these
You. In particular, tin-lead alloy solder, tin-indium alloy
For example, a lead-indium alloy solder is desirable. On the other hand, as shown in FIG.
Room temperature solid thermosetting resin or thermoplastic resin in sheet form
5 is bonded with an adhesive or by heating. Wiring board 4
As silicon, aluminum nitride, alumina
System, a resin substrate system, or the like can be used. As a sheet-like room temperature solid thermosetting resin
Is, for example, a high molecular weight polymer having an unsaturated bond in the molecule.
Butadiene, polyester, silicone resin, maleimi
, Acrylic oligomers, etc.
Epoxy, urethane, novolak phenol
And other resins. Also thermoplastic
As the resin, for example, polysulfone, polyarelay
, Polyphenylene oxide, polyamide, polymethyl
Lupentene, polyetherimide, polyethylene teref
Tarates, polycarbonates, fluorinated resins (PFA, E
TFE etc.) can be used. These resins were used to adjust the coefficient of thermal expansion.
For this purpose, an inorganic filler may be added. As an inorganic filler
For example, glass fiber, silica, calcium carbonate,
Calcium oxide, alumina, silicon nitride, taluk, etc.
Can be mentioned. In addition, oil
And rubber components may be added. In addition, improved adhesion
For this purpose, a coupling agent may be added. Capri
Examples of the coating agent include silane-based, titanium-based, and aluminum
Nitride, zirconium, phosphorus, etc. can be used
I can do it. The coefficient of thermal expansion of the resin is determined by the metal used for the bump.
It is desirable that the coefficient of thermal expansion be substantially close to the coefficient of thermal expansion. For example, tin,
When lead solder is used, the coefficient of thermal expansion is (25 ± 5) × 1
0^-6It is preferable to adjust to. The thickness of the sheet-like room temperature solid resin 5 is half
5 μm higher than the height of the bump 2 formed on the conductor chip 1
It is preferable to keep the distance by about m. Next, FIG.
As shown in FIG.
The semiconductor chip 1 is joined to the wiring board 4. Wiring board 4
A connection pad 3 made of copper or the like is formed thereon.
You. When joining, the metal bumps 2 on the semiconductor chip 1
And the connection pad 3 on the wiring board 4 by, for example, a half mirror.
Contact using a positioning device that uses a key. At this time, the substrate 4 has a switch having a heating mechanism.
Metal that is installed on the stage and forms the metal bump 2
Is preheated to about 30 ° C. higher than the melting point of For example,
Eutectic solder (Sn / Pb = 63: 3) as metal bump 2
When using 7), since the melting point is 183 ° C, the stay
The die is heated to about 213 ° C. Meanwhile, a semiconductor chip
The stage for fixing 1 is also in a nitrogen atmosphere at the same temperature as the stage temperature.
Heat in the air to melt the metal that constitutes the metal bump 2
By melting, the semiconductor chip 1 is
It is electrically connected and mounted, and as shown in FIG.
can get. At this time, the curing temperature of the resin 5 is set
2 or higher than the melting point
The resin 5 is cured when the metal bump 2 is cured,
The connection between the semiconductor chip 1 and the wiring board 4 can be made. Further
In addition, the mechanical strain applied to the metal bump 2 by the resin 5
Be relaxed. For example, a bun made as described above
A 10 mm square semiconductor chip having 200
Mounted on a wiring board. This sample was taken at -65 ° C for 3 hours.
0 minutes, 5 minutes at 25 ° C, 30 minutes at 150 ° C, 25 ° C
5000 cycles of 5 minutes temperature cycle at
No break was observed at the connection point. The semiconductor chip 1 described above and the wiring
After connection with the substrate 4, furthermore, as shown in FIG.
Fill the gap between the chip 1 and the wiring board 4 with silicone resin 6 or the like.
It may be filled and cured. Also, as shown in FIG.
Cover the semiconductor chip 1 with a resin 7
Sealing may be further performed. The first embodiment of the present invention is a modification of the above-described embodiment.
It is not limited. As metal bumps to be connected
For example, tin, lead, bismuth, indium, cadmium
Gold, silver, antimony, gallium, or any of these
Alloys may be used. Of course, the wiring substrate is also silicon-based, nitrided
Various uses such as aluminum type, alumina type, resin substrate type
It is possible. Next, an embodiment according to the second aspect of the present invention will be described.
explain about. FIG. 7 shows a second embodiment of the present invention.
FIG. 3 is a cross-sectional view illustrating a semiconductor device according to one example. Real truth
The example relates to the mounting of a semiconductor chip for driving a liquid crystal panel.
Things. In FIG. 7, the semiconductor chip 11 and the glass
The wiring 14 on the substrate 13 is connected via the bump 12
ing. In this case, the bar formed on the semiconductor chip 11
Solid-state diffusion bonding between the pump 12 and the wiring 14 by thermal pressure welding
Have been. Here, a gold bump is used as the bump 12,
Aluminum was used for the wiring 14. For mounting, first, the sealing grease 15 is removed.
Potting on glass substrate 13 supplied from spencer
Then, when the semiconductor chip 11 side is heated to 370 ° C.
In both cases, the glass substrate 13 is heated to 80 ° C.
Press for 1.5 seconds while applying a load of 25 g per
And by According to this method, the entire semiconductor device is green.
Was able to be sealed. Group used in this example
Lease is a petroleum-based grits mainly composed of paraffin oil.
Freezing point -70 ° C, boiling point 250 ° C, thermal conductivity
1.1 [W / mK], electric conductivity 1 × 10^-16 [Ωc
m], coefficient of thermal expansion 6.2 × 10^-Four[/ ° C]
An oiliness improver and an antioxidant are contained as components.
Therefore, this grease has heat dissipation, insulation, and thermal oxidation stability.
Excellent effect on properties such as resistance, shear resistance, chemical resistance and water resistance
It is something. There was no electrical connection failure after sealing. The sample was subjected to a high temperature and high humidity test (60
° C, 90% R.C. H. , 1000 hours)
Of course, the fluctuation of contact resistance is within ± 20% and extremely stable
It turned out that a good connection was obtained. In addition, thermal shock test
(-40 ° C / 100 ° C, 30 minutes / 30 minutes)
However, the variation of the contact resistance is within ± 22% and extremely
Stable connections have been obtained, and it is
It has been certified. Grease has a low freezing point and a high boiling point,
It did not melt and flow or solidify. FIG. 8 shows a second embodiment according to the second aspect of the present invention.
FIG. 3 is a cross-sectional view illustrating a semiconductor device according to an example. This embodiment
Is involved in mounting semiconductor chips on glass epoxy substrates.
Things. In FIG. 8, the semiconductor chip 21 and the glass
The wiring 24 on the epoxy substrate 23 is
Connected. In this case, the shape is formed on the semiconductor chip 21.
The formed bump 22 and the wiring 24 melt the bump 22.
Are joined by In this embodiment, the bump
A solder bump is used as 22 and a copper is used as the wiring 24.
Was. Mounting is performed on the glass epoxy substrate 23 first.
Flux (rosin) to improve solder wettability
System), and then the semiconductor chip 21 and the glass epoxy
While applying a load of 25 g per bump to the substrate 23
For 5 seconds, and then reflow at 260 ° C for 1 minute.
It was done by doing. And remove the flux,
Finally, the sealing grease 25 is supplied from the dispenser,
Grease the bottom of the semiconductor device (the bump joint).
And sealed. The grease used in this example was paraffin.
Oil-based petroleum grease with a freezing point of -72
° C, boiling point 252 ° C, thermal conductivity 2.1 [W / mK], electricity
Conductivity 2 × 10^-16 [Ωcm], coefficient of thermal expansion 3.2 × 1
0^-Four[/ ° C] with oiliness improver and acid as trace components
Contains antioxidants. Therefore, this grease is released
Heat resistance, insulation property, thermal oxidation stability, shear resistance, chemical resistance, resistance
It shows an excellent effect on water and the like. Electricity after mounting
There was no poor connection. For this sample, a high-temperature high-humidity test (6
0 ° C., 90% R.C. H. , 1000 hours)
In addition, the contact resistance fluctuation is within ± 15% and extremely stable
Connection was obtained. In addition, thermal shock test (-40 ° C /
(100 ° C, 30 minutes / 30 minutes), the contact resistance
The fluctuation of the resistance is within ± 17%, and extremely stable connection is obtained.
It has been confirmed that there is no problem in reliability. Guri
Has a low freezing point, high boiling point and excellent thixotropic
-It has the property of melting and flowing out,
It did not change. FIG. 9 shows a third embodiment according to the second aspect of the present invention.
FIG. 2 is a cross-sectional view illustrating a semiconductor device according to an example. This embodiment
Is related to the mounting of semiconductor chips on ceramic substrates.
It is. In FIG. 9, the semiconductor chip 31 and the ceramic
The wiring 34 on the substrate 33 is connected via the bump 32.
ing. In this case, the bar formed on the semiconductor chip 31
The pump 32 and the wiring 34 are
They are joined by compressive force. In this embodiment, the bump 32
And gold as the wiring 34. First, the mounting on the ceramic substrate 33 is performed.
Line 34 and bump 32 are aligned,
Hooking the protrusion 36 on the protrusion 37 on the ceramic substrate 33
Electrical and mechanical bonding, and then the sealing grease 3
5 through the opening 38 of the silicone rubber connector 36
And the lower part of the semiconductor device (the bump junction)
This was performed by sealing. The grease used in this embodiment was paraffin.
Petroleum grease containing oil as a main component, freezing point -75
° C, boiling point 255 ° C, thermal conductivity 5.1 [W / mK], electricity
Conductivity 1 × 10^-16 [Ωcm], coefficient of thermal expansion 5.2 × 1
0^-Four[/ ° C] with oiliness improver and acid as trace components
Contains antioxidants. Therefore, this grease is released
Heat resistance, insulation property, thermal oxidation stability, shear resistance, chemical resistance, resistance
It shows an excellent effect on water and the like. Electricity after mounting
There was no poor connection. The sample was subjected to a high temperature and high humidity test (60
° C, 90% R.C. H. , 1000 hours)
Of the contact resistance is within ± 10% and extremely stable
Connection was obtained. In addition, thermal shock test (-40 ° C /
(100 ° C, 30 minutes / 30 minutes), the contact resistance
The fluctuation of the resistance is within ± 15%, and extremely stable connection is obtained.
It has been confirmed that there is no problem in reliability. Guri
Has a low freezing point, high boiling point and excellent thixotropic
-It has the property of melting and flowing out,
It did not change. FIG. 10 shows a fourth embodiment according to the second aspect of the present invention.
FIG. 4 is a cross-sectional view illustrating a semiconductor device according to an example. This implementation
The example concerns the mounting of a semiconductor chip that drives a liquid crystal panel
Things. In FIG. 10, the semiconductor chip 41 and the glass
The wiring 44 on the substrate 43 is connected via the bump 42.
ing. In this case, the bus formed on the semiconductor chip 41
Electrical connection between the pump 42 and the wiring 44 without forming an alloy
Have been. The mechanical connection between the projection 46 and the pad 47 is fixed.
It is performed by phase diffusion bonding. In this embodiment, a gold bump is used as the bump 42.
And ITO as the wiring 44. Also, the protrusion 46
, And aluminum as the pad 47.
First, the pad 47 and the projection 4 on the glass substrate 43 are mounted.
6, and heat the semiconductor chip side to 370 ° C
And heat the glass substrate side to 80 ° C,
Press for 1.5 seconds while applying a load of 25 g per
And by Finally, dispensing the sealing grease 45
Supplied from the sensor to the lower part of the semiconductor device (bump junction)
Was sealed with grease. The grease used in this embodiment was paraffin.
Petroleum grease containing oil as its main component, having a freezing point of-
75 ° C, boiling point 250 ° C, thermal conductivity 1.5 [W / mK],
Electric conductivity 1 × 10^-16 [Ωcm], coefficient of thermal expansion 4.2
× 10^-Four[/ ° C], improves oiliness as a trace component
Agents and antioxidants. Therefore, this grease
Is heat dissipation, insulation, thermal oxidation stability, shear resistance, chemical resistance
It exhibits excellent effects on properties, water resistance and the like. After sealing
There was no electrical connection failure. The sample was subjected to a high temperature and high humidity test (60
° C, 90% R.C. H. , 1000 hours)
Of course, the fluctuation of contact resistance is within ± 20% and extremely stable
Connection was obtained. In addition, thermal shock test (-40 ° C /
(100 ° C, 30 minutes / 30 minutes), the contact resistance
The fluctuation of the resistance is within ± 20%, and extremely stable connection is obtained.
It has been confirmed that there is no problem in reliability. Guri
Has a low freezing point, high boiling point and excellent thixotropic
-It has the property of melting and flowing out,
It did not change. Comparative Example 1 This comparative example shows the mounting of a semiconductor chip that drives a liquid crystal panel.
(Not shown). Semiconductor chips and glass
Wiring on the substrate is connected via bumps. semiconductor
The bumps and wiring formed on the chip are connected by thermal pressure welding.
Solid phase diffusion bonding. In this comparative example, as a bump
Gold bumps were used and aluminum was used for the wiring. Implementation
Heats the semiconductor chip side to 370 ° C and
The glass substrate side is heated to 80 ° C.
Performed by pressing for 1.5 seconds while applying a load
Was. At this time, a material is placed between the semiconductor element and the glass substrate.
Was not sealed. The sample was subjected to a high temperature and high humidity test (60
C., 90% RH, 1000 hours).
Connection resistance increased about 10 times. Comparative Example 2 This comparative example shows the mounting of a semiconductor chip that drives a liquid crystal panel.
(Not shown). Semiconductor chips and glass
Wiring on the substrate is connected via bumps. semiconductor
The bumps and wiring formed on the chip are connected by thermal pressure welding.
Solid phase diffusion bonding. In this comparative example, as a bump
Gold bumps were used and aluminum was used for the wiring. Implementation
Heats the semiconductor chip side to 370 ° C and
The glass substrate side is heated to 80 ° C.
Performed by pressing for 1.5 seconds while applying a load
Was. Next, the heat for the sealing resin is supplied from the dispenser.
Supplying curable epoxy resin and potty on glass substrate
To impregnate between the semiconductor element and the glass substrate. That
As a result, there was no electrical connection failure of the sealing resin. The sample was subjected to a high temperature and high humidity test (60
° C, 90% R.C. H. , 1000 hours)
Of course, the fluctuation of contact resistance is within ± 20% and extremely stable
It turned out that a good connection was obtained. But thermal shock
Test (-40 ℃ / 100 ℃, 30min / 30min)
As a result, the contact resistance increased about 10 times. This is
Pumps, semiconductor devices, glass substrates and thermosetting epoxy resin
Changes due to differences in thermal expansion coefficient with
It was found to be due to racking. Next, a third embodiment of the present invention will be described.
You. FIG. 11 shows a semiconductor device according to a third embodiment of the present invention.
FIG. 12 is a perspective view showing the body device, and FIG. 12 is a sectional view thereof. FIG.
1 and FIG. 12, the second substrate 52 is disposed on the second substrate 52.
On the first substrate 51, semiconductor chips 53a, 53b
Are provided via the bump electrodes 54a and 54b.
You. A first external connection terminal 55 is provided on the first substrate 51.
A second external connection terminal 56 is provided on the second substrate 52.
Have been killed. In the figures, reference numerals 61a and 61b are half
Virtual center lines of the conductor chips 53a and 53b, 62a and 62
b is a virtual center line of the first substrate 51, and 63a and 63b are
The virtual center lines of the two substrates 52 are shown. Here, the virtual center line is defined as shown in FIG.
In this way, each side of the rectangular chip or rectangular substrate is bisected,
A pair of straight lines that go straight. Or a rectangular tip or
Denotes a pair of diagonal lines of the rectangular substrate. In addition, these pair
The straight line in each case is inside the rectangular chip or rectangular substrate.
You will pass through your heart. As shown in FIG. 11 and FIG.
The virtual center line 61a of the tops 53a and 53b is
The virtual center line 62a of 51 and the virtual center of the second substrate 52
It does not overlap with any of the lines 63a. In addition, the first group
The virtual center line 62a of the plate 51 is the virtual center line of the second substrate.
63a does not overlap. Also, the semiconductor chips 53a,
Virtual center line 61b of 53b, virtual center of first substrate 51
About the line 62b and the virtual center line 63b of the second substrate 52.
But they do not overlap as well. The semiconductor device shown in FIG. 11 and FIG.
When the cycle is added, the semiconductor device is as shown in FIG.
The first substrate 51 is deformed as follows.
The virtual center line 62a and the virtual center line 63 of the second substrate 52
semiconductor chips 53a and 53b deviated from a are mounted
The part that is being done is less. FIG. 14 shows the semiconductor shown in FIG. 11 and FIG.
First substrate 5 when temperature cycle is applied to the device
The relationship between the distance from the first virtual center line 62a and the deformation amount of the substrate.
FIG. 7 is a characteristic diagram showing a relationship. From FIG. 14, the first substrate 51
The deformation amount is large near the virtual center line 62a, and ΔT is 20
At 0 ° C, the maximum shear strength of the bump electrode must be exceeded.
You can see that it goes. Next, referring to FIGS. 15 and 16, FIG.
The manufacturing process of the semiconductor device shown in FIGS.
You. First, as shown in FIG.
A bonding pad 71 is formed on the
A passivation film 72 is formed except for the portion of the pad 71.
A semiconductor chip wafer 53 is prepared. Next
Then, on this wafer 53, as shown in FIG.
To deposit a Cu / Ti laminated film 73 on the entire surface
Is formed. Next, as shown in FIG.
Resist (trade name AZ4903: Hoechst Japan)
Spin coat) to form a 50 μm thick resist film.
Formed, has an opening of 100 μm square by exposure and development
20 μm smaller on one side than the bonding pad
A resist pattern 74 having an opening having a size of 0 μm is formed.
Form. Thus, the portion corresponding to the bonding pad
Opening smaller in size than the bonding pad 71
Wafer on which a resist pattern 74 having
51 is made of copper sulfate 250 g / l and sulfuric acid (specific gravity 1.84) 5
Immersion in a solution consisting of 0 g / l,
The i / Cu film 73 is used as a cathode, the high-purity copper plate is used as an anode,
Flow density 5A / dm^Two And gently stir copper for 30 minutes.
Plating to a thickness of μm to form a copper plating layer. Next, the plating bath was changed to a total tin of 40 g / l,
35 g / l tin, 44 g / l lead, 40 g free boric acid /
l, boric acid 25 g / l, glue 3.0 g / l
The Ti / Cu film 73 is replaced with a cathode as in the previous case.
And a current density of 3.2 A using 40% tin as an anode.
/ Dm^Two At a bath temperature of 25 ° C. with gentle stirring
/ Sn = 40/60 alloy is continuously plated to a thickness of 20μm
Then, a Pb / Sn alloy plating layer is formed. Thereafter, as shown in FIG.
54 made of a Pb / Sn alloy plating layer
From the wafer 53 formed only on the padding pad 71,
The resist pattern 74 is removed with acetone. Next, as shown in FIG.
/ Sn alloy plating layer as a mask,
With a mixed solution consisting of monium / sulfuric acid / ethanol,
The Cu layer of the Ti / Cu film 73 was removed by etching.
After that, it is further composed of EDTA, ammonia, and hydrogen peroxide
The Ti layer is removed by etching with a solution, and OFPR-8 is further removed.
00 is removed with acetone. Next, as shown in FIG.
Between the semiconductor chip 53 on which the semiconductor substrate 4 is formed and the FR-4 substrate.
The connection method is described below with reference to FIGS.
I will explain. First, as shown in FIG.
Steps 53a and 53b face down with respect to substrate 51
Of the semiconductor chips 53a, 53b.
The electrodes 54a and 54b and the electrodes of the substrate 51 are connected by a known technique.
Alignment using a half mirror
And bump electrodes 54a, 54b of body chips 53a, 53b.
The electrode made of Cu wiring on the FR-4 substrate 51 is brought into contact with the electrode.
You. At this time, the semiconductor chips 53a and 53b are
Held by a collet having a
Has also been heated to 280 ° C. Bump electrodes of semiconductor chips 53a and 53b
A holder for holding the chip in a state where the chip is in contact with 54a, 54b.
At the same temperature as the stage on which the substrate 51 is mounted.
Heat to 0 ° C. in a nitrogen atmosphere to form bumps 54a and 54b.
By melting the solder that has been formed, the semiconductor chip
The steps 53a and 53b are electrically connected to the substrate 51. At this time, the semiconductor chips 53a, 53b
The virtual center line does not overlap with the virtual center line of the substrate 51.
Relationship is maintained. Next, the semiconductor chips 53a, 5
3b to cover the semiconductor chips 53a, 53
The gap between 3b and substrate 51 is filled. Further, the semiconductor chip shown in FIG.
The substrate assembled with the above is mounted on an ILB
Using a method similar to that of TAB using
To make electrical connection. The first substrate and the second substrate
It is fixed by die bond connection. At this time, the first group
The virtual center line of the plate and the virtual center line of the second substrate are
The structure is not arranged on the line. Therefore, heat
It is possible to reduce the effect of stress due to strain on the chip.
It is possible to realize semiconductor devices with high heat resistance
Become. Semiconductor device having the above-described bump structure
Was evaluated according to the following procedure. That is, thermal expansion
Expansion coefficient is 14-17 × 10^-6/ ℃ and 3.5 × of silicon
10^-6/ ° C different by about one digit on a FR-4 substrate
Flip chip mounted with the connection structure shown in FIG.
30 minutes at -55 ° C, 5 minutes at 25 ° C, 1
Temperature cycle test at 50 ° C for 30 minutes and 25 ° C for 5 minutes
000 cycles, connection resistance increased
Was not. In addition, the semiconductor device was used for high-temperature and high-humidity storage tests.
As a result, no failure was observed up to 3000H.
Furthermore, when resin is injected between the semiconductor chip and the substrate,
No failure was observed up to 5000H. Therefore, from the above results, the half of the present invention
The conductor device has a structure that does not directly receive strain due to stress.
Therefore, it can be seen that the device has sufficient reliability. In addition,
The third aspect of the present invention is not limited to the above embodiment.
It is possible to make various changes without departing from the gist.
You. For example, an alloy having a different melting point to be formed is C
u, Pb / Sn, but not limited to In, S
b and the like may be added, and these are the main components.
It may be an alloy, and its height is limited
is not. Further, at the time of electroplating shown in the examples,
In addition, the barrier metal used as the cathode depends on its size, thickness and composition.
The same applies to resists.
It is not limited to this. The same applies to the method of forming the bumps.
Other methods may be used, and the metal to be formed is not limited.
No. Further, in the above embodiment, the semiconductor element is an FR-4 substrate.
The case of mounting on the board is described,
May be the case. Further on the second substrate of the first substrate
The mounting method for SM uses gull wings at both ends.
Although T has been described, the connection method is not particularly limited. [0093] As described above, the first aspect of the present invention is as follows.
According to the method, the semiconductor chip and the wiring board are sealed with resin.
In the case of sheet-shaped solid thermosetting resin or thermoplastic
Because resin is sandwiched during assembly,
Make sure that the resin penetrates sufficiently between the semiconductor chip and the wiring board.
Can be. Also, the curing temperature of the sheet-like thermosetting resin
Temperature, or thermal deformation temperature of thermoplastic resin, as bump
Keep it at or above the melting point of the metal used
Mechanical problems that occur when connecting the semiconductor chip to the wiring board
The distortion is reduced. In addition, adjust the size of the sheet
The resin around the semiconductor chip
There is no danger of protruding. In this way, resin sealing is simple
Possible to obtain more reliable semiconductor devices
It is. According to a second aspect of the present invention,
The semiconductor device is sealed with a
Suppresses deterioration of the coating interface and improves corrosion resistance and moisture resistance
The grease and the softness of the grease
Due to the sootropic property), bumps (bumps) such as solder
Pump), the difference in the coefficient of thermal expansion between semiconductor devices and wiring boards
It is possible to suppress the deterioration due to. As a result, trust
It is possible to obtain a semiconductor device with significantly improved reliability.
You. Further, according to a third aspect of the present invention, a semiconductor device is provided.
The virtual center line of the body element is temporarily
Is formed so that it does not overlap the center line of the
The coefficient of expansion and the coefficient of thermal expansion of the semiconductor chip are significantly different,
Large mechanical displacement of substrate due to temperature change of semiconductor device
Even in critical situations, the area where the semiconductor chip is mounted
It is possible to reduce the amount of deformation. That is, temperature
When the cycle is applied to the semiconductor device, the most stress concentration
To avoid areas where the substrate deformation is large
The stress at the bump connection portion of the body chip can be reduced.
Therefore, substrates with significantly different coefficients of thermal expansion from semiconductor elements
However, reliable flip-chip mounting is possible.
You.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sectional view showing a manufacturing process of a semiconductor device according to an embodiment of the present invention. FIG. 2 is a sectional view showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention; FIG. 3 is a sectional view showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention; FIG. 4 is a cross-sectional view showing a step of manufacturing the semiconductor device of the example according to the first aspect of the present invention. FIG. 5 is a sectional view showing a semiconductor device of another example according to the first embodiment of the present invention. FIG. 6 is a sectional view showing a semiconductor device of another example according to the first embodiment of the present invention. FIG. 7 is a sectional view showing a semiconductor device of a first example according to a second aspect of the present invention. FIG. 8 is a sectional view showing a semiconductor device of a second example according to the second aspect of the present invention. FIG. 9 is a sectional view showing a semiconductor device of a third example according to the second aspect of the present invention. FIG. 10 is a sectional view showing a semiconductor device of a fourth embodiment according to the second aspect of the present invention. FIG. 11 is a perspective view showing a semiconductor device of an example according to a third aspect of the present invention. FIG. 12 is a sectional view showing a semiconductor device of an example according to a third aspect of the present invention. FIG. 13 is a cross-sectional view illustrating deformation of a substrate when a temperature cycle is applied to a semiconductor device. FIG. 14 is a characteristic diagram showing a relationship between a deformation amount of a substrate and a distance from a virtual center line of the substrate when a temperature cycle is applied to the semiconductor device. FIG. 15 is a sectional view showing a manufacturing process of the semiconductor device according to the example of the third aspect of the present invention. FIG. 16 is a sectional view showing the manufacturing process of the semiconductor device according to the example of the third aspect of the present invention. FIG. 17 is a cross-sectional view showing a conventional resin-sealed semiconductor device. FIG. 18 is a cross-sectional view showing a conventional semiconductor chip having mashroom bumps. FIG. 19 is a cross-sectional view showing a conventional semiconductor chip having straight wall type bumps. FIG. 20 is a cross-sectional view showing a connection structure between a semiconductor chip and a wiring board in a conventional semiconductor device. [Description of Signs] 1,11,21,31,41,53a, 53b ... semiconductor chips 2,12,22,32,42,54a, 54b ... bumps 3,14,24,34,44,71 ... connection pads 4, 13, 23, 33, 43, 51, 52 ... substrate 5 ... resin sheet 15, 25, 35, 45 ... grease 60 ... sealing resin 61a, 61b ... semiconductor chip virtual center lines 62a, 62b ... Virtual center lines 63a, 63b of the first substrate ... virtual center lines of the second substrate

Continued on the front page (72) Inventor Miki Mori 33 Shinisogo-cho, Isogo-ku, Yokohama-shi, Kanagawa Prefecture Inside the Toshiba Institute of Industrial Science (72) Inventor Akinori Motomiya Komukai Toshiba-cho, Kouki-ku, Kawasaki-shi, Kanagawa 1st Co., Ltd. In the Toshiba Research and Development Center (72) Inventor Hiroshi Yamada 33 in Shinisogo-cho, Isogo-ku, Yokohama-shi, Kanagawa Prefecture In-house Toshiba Institute of Industrial Technology (56) References JP-A-3-222339 (JP, A) JP-A-62 JP-A-281361 (JP, A) JP-A-2-96343 (JP, A) JP-A-4-22144 (JP, A) JP-A-5-315396 (JP, A) JP-A-6-168981 (JP, A) JP-A-6-232208 (JP, A) JP-A-64-10637 (JP, A) JP-A-5-182971 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/60

Claims (1)

(57) Claims 1. A wiring board having a connection pad, and a semiconductor chip connected to the connection pad of the wiring board via a metal bump, wherein the wiring board and the semiconductor A semiconductor device characterized by being sealed with grease between a chip and the chip.