JP2004047510A - Electrode structure and its forming method - Google Patents

Electrode structure and its forming method Download PDF

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Publication number
JP2004047510A
JP2004047510A JP2002199076A JP2002199076A JP2004047510A JP 2004047510 A JP2004047510 A JP 2004047510A JP 2002199076 A JP2002199076 A JP 2002199076A JP 2002199076 A JP2002199076 A JP 2002199076A JP 2004047510 A JP2004047510 A JP 2004047510A
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Prior art keywords
solder
electrode
film
electrode structure
diffusion
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Japanese (ja)
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Kaoru Hashimoto
橋本　薫
Isao Watanabe
渡辺　勲
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Fujitsu Ltd
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Fujitsu Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
    • H01L2224/11849—Reflowing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13005—Structure
    • H01L2224/13006—Bump connector larger than the underlying bonding area, e.g. than the under bump metallisation [UBM]

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  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To perform highly reliable soldering at a low cost through simple processes. <P>SOLUTION: A circuit pattern 2a is formed on the upper layer of a circuit board 1, and an electrode 2b is formed on the circuit pattern 2a. Furthermore, a solder diffusion preventive film 3 is formed of a material having a function of preventing the diffusion of solder components to cover the entire surface of the exposed part of the electrode 2b. Solder resists 6 and 7 are formed again on the circuit board 1, and a solder bump 4 is formed on the upper layer of the solder diffusion preventive film 3. The solder bump 4 is formed not on the upper layer of the solder diffusion preventive film 3 but on the electrode part of an opposing electronic component (e.g., a semiconductor element). In order to prevent the diffusion/reaction (formation of compounds) of the solder and the pattern 2a, a material exhibiting proper wettability to the solder components may additionally be formed to cover the entire surface of the exposed part of the solder diffusion preventive film 3. <P>COPYRIGHT: (C)2004,JPO

Description

【０００１】
【発明の属する技術分野】
本発明は回路基板の入出力端子に施す電極構造体および形成方法に関し、特に半導体素子および回路基板の入出力端子に施す電極構造体およびその形成方法に関する。
【０００２】
【従来の技術】
近年、半導体素子の高集積化・高速化にともない、この半導体素子の性能を最大限に生かす高密度実装技術も進歩している。
【０００３】
このような状況の中で、これらの実装技術の１つとして、裸の半導体素子（ベアチップ）を回路基板に直接はんだ付けする方式がある。このとき、半導体素子や回路基板の電極表面は、はんだ付け可能な状態にしておくことが不可欠となる。
【０００４】
そこで、通常、たとえば半導体素子がアルミニウム（Ａｌ）配線のとき、Ａｌ膜の上に密着層としてチタン（Ｔｉ）膜を形成し、その上にニッケル（Ｎｉ）層を重ねる構成、あるいはＮｉ層の上にさらに金（Ａｕ）膜を重ねて形成する膜構成などが適用される。
【０００５】
また、最近、半導体素子のより一層の高速化・高性能化のために、配線材料としてＡｌに替え銅（Ｃｕ）を適用しようとする趨勢にある。この場合にも、入出力端子用電極の構造体は、前述のＡｌの場合と同様に、Ｃｕの表面にＮｉ層を重ねて形成するなどの構成が用いられる。
【０００６】
一方、回路基板にも、同様な目的で、半導体素子の電極に対応した配列・配置で電極が形成される。この回路基板の配線材料は通常Ｃｕであることから、電極の構造体はＣｕを配線材料とする半導体素子のときと同じである。
【０００７】
また、はんだ付けについても、一般的には、半導体素子上の電極にはんだバンプが形成されて回路基板とはんだ付けされるが、回路基板側のみ、あるいは半導体素子と回路基板の両方にはんだバンプを形成するなどの形態がある。
【０００８】
通常、これらの膜は、周囲が絶縁体（はんだ付けが生じない）で被覆されているが、位置合わせの不具合から、被覆されない場合がある。この場合には、側面がむき出しの状態で使用されることになる。その結果、はんだ付け時に溶融したはんだが側面を流れ、これらの膜材料とはんだとの間に拡散・反応が生じる（図４にて後述）。そして、最悪の場合には、本来はんだとは接触しないはずの膜成分（金属）がはんだ中に溶解してしまい、接合の信頼性を低下させるなど重大な影響を及ぼす。
【０００９】
図４は、従来の電極構造体を示す図であり、図４（ａ）ははんだ溶融前の電極構造体の断面図、図４（ｂ）ははんだ溶融後の電極構造体の断面図である。
図４（ａ）に示すように、電極構造体は、回路基板１１０の上層に回路パターン１１１を形成し、この回路パターン１１１の上部にＣｕ電極部１１２を形成する。また、このＣｕ電極部１１２の上層に、Ｎｉ膜１１３、Ａｕ層１１４を形成する。さらに、再び回路基板１１０上層には、ソルダーレジスト１１６，１１７を形成する。そして、Ａｕ層１１４の上層あるいは半導体素子上の電極部には、Ｓｎ−Ａｇ（錫‐銀）系のはんだ１１５を形成する。
【００１０】
このような電極の構造体にて、図４（ｂ）に示すように、はんだ溶融した場合は、溶融して流れ込んだはんだが、Ｃｕ電極部１１２に対して反応化合物Ｒ１１１，Ｒ１１２を生じる。なお、図４（ｂ）では、はんだ中に溶け込んでいるため、Ａｕ層１１４は図示していない。
【００１１】
さらに、最近適用が増加しているボール・グリッド・アレイ（ＢＧＡ）およびチップ・サイズ・パッケージ（ＣＳＰ）の実装においては、はんだ接合部の長期接合信頼性を向上させる目的で、回路基板上の電極部は、絶縁膜で被覆するのではなく、それらとは離れた形態（すき間がある形態）で形成されるようになってきている。すなわち、電極を構成する膜の側面は、むき出しの状態で使用される。その結果、はんだ付け時、前述と同様の現象が生じる恐れが高い。
【００１２】
図５は、ＣＳＰの実装において、はんだ接合の信頼性に及ぼす電極形状の影響を示す図である。なお、この図は、−４０〜８０℃の環境下で、各３０分、温度サイクル寿命試験を実施した結果である。図５に示すように、接合形態には２通りの形態があり、接合形態３００はすき間が無い形態を示し、接合形態４００はすき間がある形態を示す。すなわち、この接合形態３００は、ＣＳＰ３１０がプリント配線板３２０上の電極部３２２と、はんだバンプ３３０を介して接合されており、ソルダーレジスト３２１と電極部３２２との間ですき間が無い形態を示す。この接合形態４００は、ＣＳＰ４１０がプリント配線板４２０上の電極部４２２と、はんだバンプ４３０を介して接合されており、ソルダーレジスト４２１と電極部４２２との間ですき間がある形態を示す。また、記号Ａ，Ｂはランド露出部の大きさを示す。このような形態に対して、ＣＳＰの実装におけるはんだ接合の信頼性に及ぼす電極形状の影響を表しているのが、図５下の表（温度サイクル寿命（相対値））である。この表は、接合形態３００の場合に、例えば、比率Ｂ／Ａ＝１．０において温度サイクル寿命が１．０であるのに対して、接合形態４００の場合は温度サイクル寿命が８．６である。この表から、ランド露出部の大きさの比率Ｂ／Ａに対応した寿命は、接合形態４００の方が長いことが分かる。
【００１３】
このため、電極膜を形成し終わってから、フォトリソグラフィ技術を用いて電極膜の周囲を被覆する（パシベーション膜を形成する）方法において、従来技術では、上記の問題点を解決するために、パターンニングの際に極めて高い位置合わせ精度を有する装置を必要とする。
【００１４】
【発明が解決しようとする課題】
しかし、このような装置は高価であり、また精度維持のためのメンテナンス費用も要するので、高コスト化が避けられない。また、何段階もの工程（フォトリソグラフィ工程）を経ることから、製造コストが高くなるといった問題がある。
【００１５】
本発明はこのような点に鑑みてなされたものであり、簡単な工程により高信頼性、かつ低コストのはんだ付けができる電極構造体およびその形成方法を提供することを目的とする。
【００１６】
【課題を解決するための手段】
本発明では上記課題を解決するために、回路基板の入出力端子に施す電極構造体において、電極の露出部全面を覆うように、はんだ成分の拡散を防ぐ能力を有する材料から成るはんだ拡散防止膜を形成したことを特徴とする電極構造体が提供される。
【００１７】
このような回路基板側の電極構造体によれば、電極の露出部全面を覆うように、はんだ成分の拡散を防ぐ能力を有する材料から成るはんだ拡散防止膜が形成される。
【００１８】
また、上記課題を解決するために、半導体素子の入出力端子に施す電極構造体において、電極の露出部全面を覆うように、はんだ成分の拡散を防ぐ能力を有する材料から成るはんだ拡散防止膜を形成したことを特徴とする電極構造体が提供される。
【００１９】
このような半導体素子側の電極構造体によれば、電極の露出部全面を覆うように、はんだ成分の拡散を防ぐ能力を有する材料から成るはんだ拡散防止膜が形成される。
【００２０】
【発明の実施の形態】
本発明では、パシベーション膜を形成する代わりに、フォトリソグラフィ技術の不要な無電解めっき法によって、はんだ成分の拡散を防ぐ能力を有する材料の膜を形成し、この膜で電極部全体を被覆する。この無電解めっきは、プロセス条件を制御することで、金属膜部のみに選択的に所望の金属膜を形成できる方法であり、高コストのフォトリソグラフィ・プロセスが不要であることから、低コスト化が期待できる。
【００２１】
以下、本発明の実施の形態を図面を参照して説明する。
図１は、本発明の原理構成図であり、図１（ａ）は溶融前の電極構造体の断面図、図１（ｂ）は溶融後の電極構造体の断面図である。
【００２２】
図１（ａ）に示すように、回路基板１の上層には回路パターン２ａが形成されており、回路パターン２ａの上部には電極部２ｂが形成されている。さらに電極部２ｂの露出部全面を覆うように、はんだ成分の拡散を防ぐ能力を有する材料から成るはんだ拡散防止膜３を形成する。このはんだ拡散防止膜３は、さらに電極とはんだとの密着を確保するために適した材料から成る。また、再び回路基板１の上部には、ソルダーレジスト６，７を形成する。そして、はんだ拡散防止膜３の上層には、はんだバンプ４を形成する。なお、はんだバンプ４は、はんだ拡散防止膜３の上層ではなく、対向する電子部品（例えば、半導体素子）の電極部に形成してもよい。また、はんだと回路パターン２ａとの拡散・反応（化合物形成）を防止するために、はんだ拡散防止膜３の露出部全面を覆うように、さらにはんだ成分とのぬれ性が良い材料を形成してもよい。
【００２３】
このような構成により、図１（ｂ）に示すようにはんだ溶融した場合であっても、溶融して流れ込んだはんだが回路パターン２ａ、電極部２ｂに対して、拡散・反応（化合物形成）を起こさない。この結果、何段階もの工程を経ずに簡単な工程で、高信頼性、かつ低コストのはんだ付けが可能となる。
【００２４】
なお、はんだ（成分）の拡散を防ぐ能力を有する材料としてＮｉを使用し、めっき法として無電解Ｎｉめっき法を使用する。しかし、この材料は一例であり、同等の拡散防止能や無電解めっき可能な材料であれば、他の材料でも良く、とくにＮｉに限定されることはない。また、ぬれ性が良い材料についても、はんだ成分とのぬれ性が良い材料がよく、例えばＡｕが使用でき、Ｎｉと同様に無電解Ａｕメッキ法を適用することができる。
【００２５】
以下、本発明の実施の形態について、具体的に説明する。
一般のＬＳＩ素子では、Ａｌ電極の周囲がパシベーション膜で被覆されている。さらに具体的には、内部配線のＡｌ膜の電極部にＴｉあるいは窒化チタン（ＴｉＮ）を形成し、その上にＡｌ膜を形成した構造になっている。そして、このＡｌ膜上に、蒸着法、スパッタ法、めっき法等の１種あるいは複数の手法を用いてニッケル（Ｎｉ）膜を形成している。さらに、必要に応じてＮｉの上に、はんだ付け性確保のためのＡｕの薄い膜が形成される。あるいは、はんだのバンプが形成されることもある。
【００２６】
一方、このＬＳＩ素子を実装する回路基板では、通常銅（Ｃｕ）配線が形成されており、電極もＣｕの上にＮｉ層、さらにその上にＡｕ層（薄）という構成となっている。そして、電極部の周辺および電極以外の部分にはソルダーレジストが塗布されている。このソルダーレジストによる被覆が位置ずれして、電極部の側壁が露出している場合がある。さらに、ＢＧＡおよびＣＳＰ実装用の基板では、電極部の周辺は、意識的に、絶縁膜による被覆を実施していない。ここでは、このような形態の基板を、以下の実施例における比較例とした。
【００２７】
まず、本実施例に適用するＬＳＩ素子（半導体素子）では、電極の周囲を確実にパシベーション膜で被覆する。この電極の膜構成は、上層からＡｕ／Ｎｉ／Ａｌ／ＴｉＮ／Ａｌ（配線）である。
【００２８】
図２は、本発明の実施例を示す電極の膜構成を示す図であり、図２（ａ）ははんだ溶融前の電極構造体の断面図、図２（ｂ）ははんだ溶融後の電極構造体の断面図である。
【００２９】
図２（ａ）に示すように、通常のアルミナ回路基板１０の上層に回路パターン１１を形成し、さらに回路パターン１１の上部にＣｕ電極部１２を形成する。また、無電解Ｎｉめっき液、プロセス条件を用いて、Ｃｕ電極部１２の上層および側壁を含む全体を覆うようにＮｉ膜１３を形成する。さらに、Ｎｉ膜１３の上に、Ａｕフラッシュめっき液を用いてＡｕ層１４を同様に積み重ねる。この結果、電極膜の側面を含めてすべての露出面がＡｕ／Ｎｉ膜で覆われた状態となる。なお、無電解ニッケルめっき液の標準成分は、例えば以下のものである。
【００３０】
・硫酸ニッケル
・次亜りん酸ナトリウム
・乳酸などの添加剤
これらを混合しためっき液中の重量は、単位当たり（例えば、１リットル）でほぼ同等である。また、回路パターン１１の上部かつＣｕ電極部１２を囲む（非接触）部位には、ソルダーレジスト１６，１７を形成する。
【００３１】
そして、Ａｕ層１４の上層、あるいは前述のＬＳＩ素子の電極部に、通常の手法によってＳｎ−Ａｇ系はんだによるはんだバンプ１５を形成する。
上記のような構成により、図２（ｂ）に示すようにはんだ溶融した場合であっても、溶融して流れ込んだはんだが回路パターン１１およびＣｕ電極部１２に対して、拡散・反応（化合物形成）を起こさない。なお、図２（ｂ）では、はんだ中に溶け込んでいるため、Ａｕ層１４は図示していない。
【００３２】
以下、本発明に係わる電極構造体およびその形成方法をもとに、実際にはんだバンプを形成し、その接合信頼性における評価結果を比較例と比較して説明する。なお、以下の実施例では、はんだバンプ１５をＡｕ層１４の上層ではなく、ＬＳＩ素子の電極部に形成した。
【００３３】
［第１の実施例］
第１の実施例では、まず、ＬＳＩ素子の電極部に形成したはんだバンプ１５を、アルミナ回路基板１０のＡｕ／Ｎｉ膜で被覆したＣｕ電極部１２に突き合わせて、はんだの融点よりも１００℃程度高い３３０℃の温度で３０分加熱して、ＬＳＩ素子を回路基板上に接合した試料を得る。なお、このＡｕ／Ｎｉ膜は、Ｎｉ膜を２μｍの厚さに形成し、このＮｉ膜の上層にＡｕ膜を０．１μｍ以下の厚さに形成したものである。この試料について、Ｃｕ電極部１２とはんだバンプ１５との界面を顕微鏡観察した結果、はんだが電極膜のＮｉ層１３を突き破って、Ｃｕ電極部１２と反応している様子は観察されなかった。
【００３４】
一方、比較例として、上述の実施形態と同じＡｕ／Ｎｉ／Ｃｕ構成による従来の回路基板を用意した（図４参照）。これは、ＣＳＰ実装用基板（回路基板１１０）で、電極の周囲にはんだレジスト層はなく、その側面にはＣｕ電極部１１２が露出しているものである。この基板を用いて、前述と同様に、３３０℃の温度で３０分加熱して、ＬＳＩ素子を回路基板１１０上に接合した試料を得る。この試料について、Ｃｕ電極部１１２とはんだバンプ１１５との界面を顕微鏡観察した結果、側壁からＣｕ電極部１１２中にはんだ成分であるＳｎが拡散して反応化合物Ｒ１１１，Ｒ１１２が形成されている様子が観察された。この化合物は、接合部に応力が加えられたときに破断し易く、接合信頼性を損なう。
【００３５】
また、第１の実施例において、温度サイクル試験を実施し、はんだ劣化の過程（信頼性データ）を図３のようにまとめた。
図３は、第１の実施例におけるはんだ劣化の過程（信頼性データ）を示す図である。
【００３６】
図３によると、従来法の例と第１の実施例とにおいて、温度サイクル試験の評価結果として、はんだ劣化の過程を示している。なお、縦軸に累積故障率（％）を示し、横軸に経過したサイクル数（サイクル）を示す。ここで、図３より明らかなように、温度サイクル試験では、従来法よりも第１の実施例の方が、経過サイクル数当たりの故障率が高いという結果となった。
【００３７】
これらの結果から、第１の実施例における効果が確認できた。
［第２の実施例］
次に、第２の実施例について説明する。
【００３８】
回路基板としてポリイミド樹脂基板（Ｃｕ配線）を用い、その他の条件はすべて第１の実施例と同じ条件とした。
その結果、Ｃｕ電極部１２とはんだとの反応は、いずれの場所にも認められず、第２の実施例における効果が確認できた。
【００３９】
［第３の実施例］
次に、第３の実施例について説明する。
回路基板としてエポキシ樹脂基板（Ｃｕ配線）を用い、はんだ接合条件を２６０℃、３分（はんだ耐熱試験規格に準拠）とした以外、その他の条件はすべて第１の実施例と同じ条件とした。
【００４０】
その結果、Ｃｕ電極部１２とはんだとの反応は、いずれの場所にも認められず、第３の実施例における効果が確認できた。
さらに、この試料を１５０℃で１００時間放置した後にも、Ｃｕ電極部１２とはんだとの反応はいずれの場所にも認められず、第３の実施例における効果が確認できた。
【００４１】
なお、上記の説明では、電極部を銅として説明したが、銀を適用することもできる。しかし、これらの材料は一例であり、電気伝導性が良ければどのような導体材料でもよく、特に銅や銀に限定されることはない。
【００４２】
また、上記の説明では、回路基板側の電極構造体として説明したが、半導体素子側の電極構造体として適用することもできる。
（付記１）　回路基板の入出力端子に施す電極構造体において、
電極の露出部全面を覆うように、はんだ成分の拡散を防ぐ能力を有する材料から成るはんだ拡散防止膜を形成したことを特徴とする電極構造体。
【００４３】
（付記２）　前記はんだ拡散防止膜は、さらに前記電極とはんだとの密着を確保するために適した材料から成ることを特徴とする付記１記載の電極構造体。
（付記３）　前記はんだ拡散防止膜は、無電解めっき法を用いた無電解Ｎｉめっき膜であることを特徴とする付記２記載の電極構造体。
【００４４】
（付記４）　さらに、前記はんだ拡散防止膜の上に、必要に応じて、前記はんだ成分とのぬれ性が良い材料から成る膜をつみ重ねることを特徴とする付記１記載の電極構造体。
【００４５】
（付記５）　前記ぬれ性が良い材料から成る膜は、無電解めっき法を用いた無電解Ａｕめっき膜であることを特徴とする付記４記載の電極構造体。
（付記６）　前記回路基板は、アルミナ回路基板であることを特徴とする付記１記載の電極構造体。
【００４６】
（付記７）　前記回路基板は、ポリイミド樹脂基板であることを特徴とする付記１記載の電極構造体。
（付記８）　前記回路基板は、エポキシ樹脂基板であることを特徴とする付記１記載の電極構造体。
【００４７】
（付記９）　半導体素子の入出力端子に施す電極構造体において、
電極の露出部全面を覆うように、はんだ成分の拡散を防ぐ能力を有する材料から成るはんだ拡散防止膜を形成したことを特徴とする電極構造体。
【００４８】
（付記１０）　前記はんだ拡散防止膜は、さらに前記電極とはんだとの密着を確保するために適した材料から成ることを特徴とする付記９記載の電極構造体。
（付記１１）　前記はんだ拡散防止膜は、無電解めっき法を用いた無電解Ｎｉめっき膜であることを特徴とする付記１０記載の電極構造体。
【００４９】
（付記１２）　さらに、前記はんだ拡散防止膜の上に、必要に応じて、前記はんだ成分とのぬれ性が良い材料から成る膜をつみ重ねることを特徴とする付記９記載の電極構造体。
【００５０】
（付記１３）　前記ぬれ性が良い材料から成る膜は、無電解めっき法を用いた無電解Ａｕめっき膜であることを特徴とする付記１２記載の電極構造体。
（付記１４）　回路基板の入出力端子に施す電極形成方法において、
電極の露出部全面を覆うように、はんだ成分の拡散を防ぐ能力を有する材料から成るはんだ拡散防止膜を形成することを特徴とする電極形成方法。
【００５１】
（付記１５）　前記はんだ拡散防止膜は、さらに前記電極とはんだとの密着を確保するために適した材料から成ることを特徴とする付記１４記載の電極形成方法。
【００５２】
（付記１６）　前記はんだ拡散防止膜は、無電解めっき法を用いた無電解Ｎｉめっき膜であることを特徴とする付記１５記載の電極形成方法。
（付記１７）　さらに、前記はんだ拡散防止膜の上に、必要に応じて、前記はんだ成分とのぬれ性が良い材料から成る膜をつみ重ねることを特徴とする付記１４記載の電極形成方法。
【００５３】
（付記１８）　前記ぬれ性が良い材料から成る膜は、無電解めっき法を用いた無電解Ａｕめっき膜であることを特徴とする付記１７記載の電極形成方法。
（付記１９）　半導体素子の入出力端子に施す電極形成方法において、
電極の露出部全面を覆うように、はんだ成分の拡散を防ぐ能力を有する材料から成るはんだ拡散防止膜を形成することを特徴とする電極形成方法。
【００５４】
（付記２０）　前記はんだ拡散防止膜は、さらに前記電極とはんだとの密着を確保するために適した材料から成ることを特徴とする付記１９記載の電極形成方法。
【００５５】
（付記２１）　前記はんだ拡散防止膜は、無電解めっき法を用いた無電解Ｎｉめっき膜であることを特徴とする付記２０記載の電極形成方法。
（付記２２）　さらに、前記はんだ拡散防止膜の上に、必要に応じて、前記はんだ成分とのぬれ性が良い材料から成る膜をつみ重ねることを特徴とする付記１９記載の電極形成方法。
【００５６】
（付記２３）　前記ぬれ性が良い材料から成る膜は、無電解めっき法を用いた無電解Ａｕめっき膜であることを特徴とする付記２２記載の電極形成方法。
【００５７】
【発明の効果】
以上説明したように本発明では、電極の露出部全面を覆うように、はんだ成分の拡散を防ぐ能力を有する材料から成るはんだ拡散防止膜を形成するようにしたので、はんだ成分の電極への拡散・反応を防止することができる。その結果、簡単な工程により高信頼性、かつ低コストのはんだ付けが可能となる。
【図面の簡単な説明】
【図１】本発明の原理構成図であり、図１（ａ）は溶融前の電極構造体の断面図、図１（ｂ）は溶融後の電極構造体の断面図である。
【図２】本発明の実施例を示す電極の膜構成を示す図であり、図２（ａ）ははんだ溶融前の電極構造体の断面図、図２（ｂ）ははんだ溶融後の電極構造体の断面図である。
【図３】第１の実施例におけるはんだ劣化の過程（信頼性データ）を示す図である。
【図４】従来の電極構造体を示す図であり、図４（ａ）ははんだ溶融前の電極構造体の断面図、図４（ｂ）ははんだ溶融後の電極構造体の断面図である。
【図５】ＣＳＰの実装において、はんだ接合の信頼性に及ぼす電極形状の影響を示す図である。
【符号の説明】
１　回路基板
２ａ　回路パターン
２ｂ　電極部
３　はんだ拡散防止膜
４　はんだバンプ
６，７　ソルダーレジスト[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an electrode structure applied to input / output terminals of a circuit board and a method of forming the same, and more particularly to a semiconductor element and an electrode structure applied to input / output terminals of a circuit board and a method of forming the same.
[0002]
[Prior art]
2. Description of the Related Art In recent years, with high integration and high speed of semiconductor devices, high-density packaging technology for maximizing the performance of the semiconductor devices has been advanced.
[0003]
Under such circumstances, as one of these mounting techniques, there is a method of directly soldering a bare semiconductor element (bare chip) to a circuit board. At this time, it is essential that the electrode surfaces of the semiconductor element and the circuit board are in a solderable state.
[0004]
Therefore, usually, for example, when the semiconductor element is an aluminum (Al) wiring, a titanium (Ti) film is formed as an adhesion layer on the Al film, and a nickel (Ni) layer is laminated thereon, or In addition, a film configuration in which a gold (Au) film is further stacked is applied.
[0005]
In recent years, there is a trend to apply copper (Cu) instead of Al as a wiring material in order to further increase the speed and performance of semiconductor devices. Also in this case, the structure of the input / output terminal electrode structure is such that a Ni layer is formed on a Cu surface in the same manner as in the case of Al described above.
[0006]
On the other hand, electrodes are formed on the circuit board for the same purpose in an arrangement and arrangement corresponding to the electrodes of the semiconductor element. Since the wiring material of this circuit board is usually Cu, the structure of the electrodes is the same as that of the semiconductor element using Cu as the wiring material.
[0007]
Regarding soldering, generally, solder bumps are formed on the electrodes on the semiconductor element and soldered to the circuit board. However, solder bumps are applied only on the circuit board side or on both the semiconductor element and the circuit board. There is a form such as forming.
[0008]
Normally, these films are covered with an insulator (no soldering occurs), but may not be covered due to alignment problems. In this case, it is used with the side face exposed. As a result, the solder melted at the time of soldering flows on the side surfaces, and diffusion and reaction occur between these film materials and the solder (described later with reference to FIG. 4). In the worst case, the film component (metal) that should not be in contact with the solder is dissolved in the solder, which has a serious effect such as lowering the reliability of the joint.
[0009]
4A and 4B are views showing a conventional electrode structure. FIG. 4A is a cross-sectional view of the electrode structure before solder melting, and FIG. 4B is a cross-sectional view of the electrode structure after solder melting. .
As shown in FIG. 4A, in the electrode structure, a circuit pattern 111 is formed on an upper layer of a circuit board 110, and a Cu electrode portion 112 is formed on the circuit pattern 111. Further, a Ni film 113 and an Au layer 114 are formed on the Cu electrode portion 112. Further, solder resists 116 and 117 are formed on the circuit board 110 again. Then, a Sn-Ag (tin-silver) solder 115 is formed on the upper layer of the Au layer 114 or on the electrode portion on the semiconductor element.
[0010]
In such an electrode structure, as shown in FIG. 4B, when the solder is melted, the molten solder flows into the Cu electrode portion 112 to generate reactive compounds R111 and R112. In FIG. 4B, the Au layer 114 is not shown because it is dissolved in the solder.
[0011]
Furthermore, in the mounting of a ball grid array (BGA) and a chip size package (CSP), which have been increasingly used recently, an electrode on a circuit board is used in order to improve long-term bonding reliability of a solder bonding portion. The parts are not covered with an insulating film but are formed in a form separated from them (a form having a gap). That is, the side surface of the film constituting the electrode is used in a bare state. As a result, at the time of soldering, the same phenomenon as described above is likely to occur.
[0012]
FIG. 5 is a diagram showing the effect of the electrode shape on the reliability of the solder joint in mounting the CSP. In addition, this figure is a result of performing a temperature cycle life test for 30 minutes in an environment of -40 to 80 ° C. As shown in FIG. 5, there are two types of bonding modes, a bonding mode 300 shows a mode without a gap, and a bonding mode 400 shows a mode with a gap. That is, this bonding mode 300 shows a mode in which the CSP 310 is bonded to the electrode portion 322 on the printed wiring board 320 via the solder bump 330, and there is no gap between the solder resist 321 and the electrode portion 322. This bonding form 400 shows a form in which the CSP 410 is bonded to the electrode part 422 on the printed wiring board 420 via the solder bump 430, and there is a gap between the solder resist 421 and the electrode part 422. Symbols A and B indicate the size of the exposed land portion. The table (temperature cycle life (relative value)) in FIG. 5 shows the effect of the electrode shape on the reliability of the solder joint in the mounting of the CSP in such a form. This table shows that, for example, the temperature cycle life is 1.0 at the ratio B / A = 1.0 in the case of the joint form 300, whereas the temperature cycle life is 8.6 in the case of the joint form 400. is there. From this table, it can be seen that the life corresponding to the ratio B / A of the size of the land exposed portion is longer in the bonding form 400.
[0013]
For this reason, in a method of forming a passivation film around the electrode film by using photolithography technology after the formation of the electrode film, in the conventional technology, a pattern is formed in order to solve the above problem. In this case, a device having extremely high positioning accuracy is required.
[0014]
[Problems to be solved by the invention]
However, such a device is expensive and requires maintenance costs for maintaining accuracy, so that an increase in cost is inevitable. In addition, there is a problem that the manufacturing cost is increased because the process involves a number of steps (photolithography step).
[0015]
The present invention has been made in view of such a point, and an object of the present invention is to provide an electrode structure that can be soldered with high reliability and low cost by a simple process, and a method for forming the same.
[0016]
[Means for Solving the Problems]
In the present invention, in order to solve the above problems, in an electrode structure applied to input / output terminals of a circuit board, a solder diffusion preventing film made of a material having a capability of preventing the diffusion of solder components so as to cover the entire exposed portion of the electrode. An electrode structure characterized by forming is provided.
[0017]
According to such an electrode structure on the circuit board side, a solder diffusion preventing film made of a material capable of preventing the diffusion of solder components is formed so as to cover the entire exposed portion of the electrode.
[0018]
Further, in order to solve the above-mentioned problem, in an electrode structure applied to an input / output terminal of a semiconductor element, a solder diffusion preventing film made of a material having a capability of preventing the diffusion of a solder component is provided so as to cover the entire exposed portion of the electrode. An electrode structure characterized by being formed is provided.
[0019]
According to such an electrode structure on the semiconductor element side, a solder diffusion preventing film made of a material having a capability of preventing the diffusion of a solder component is formed so as to cover the entire exposed portion of the electrode.
[0020]
BEST MODE FOR CARRYING OUT THE INVENTION
In the present invention, instead of forming a passivation film, a film of a material having a capability of preventing the diffusion of solder components is formed by an electroless plating method that does not require a photolithography technique, and the entire electrode portion is covered with this film. This electroless plating is a method by which the desired metal film can be selectively formed only on the metal film portion by controlling the process conditions. Since a high-cost photolithography process is not required, the cost can be reduced. Can be expected.
[0021]
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a diagram illustrating the principle of the present invention. FIG. 1A is a cross-sectional view of an electrode structure before melting, and FIG. 1B is a cross-sectional view of the electrode structure after melting.
[0022]
As shown in FIG. 1A, a circuit pattern 2a is formed on an upper layer of the circuit board 1, and an electrode portion 2b is formed on the circuit pattern 2a. Further, a solder diffusion preventing film 3 made of a material having a capability of preventing the diffusion of the solder component is formed so as to cover the entire exposed portion of the electrode portion 2b. The solder diffusion preventing film 3 is made of a material suitable for further ensuring the close contact between the electrode and the solder. Further, solder resists 6 and 7 are formed again on the circuit board 1. Then, a solder bump 4 is formed on the solder diffusion preventing film 3. Note that the solder bumps 4 may be formed not on the upper layer of the solder diffusion preventing film 3 but on the electrodes of opposing electronic components (for example, semiconductor elements). Further, in order to prevent diffusion and reaction (compound formation) between the solder and the circuit pattern 2a, a material having better wettability with a solder component is formed so as to cover the entire exposed portion of the solder diffusion preventing film 3. Is also good.
[0023]
With such a configuration, even when the solder is melted as shown in FIG. 1B, the melted and flowing solder diffuses and reacts (compound formation) to the circuit pattern 2a and the electrode portion 2b. Don't wake up. As a result, high-reliability and low-cost soldering can be performed in a simple process without going through many steps.
[0024]
Note that Ni is used as a material having the ability to prevent the diffusion of solder (component), and electroless Ni plating is used as a plating method. However, this material is merely an example, and other materials may be used as long as they have the same diffusion preventing ability and electroless plating capability, and are not particularly limited to Ni. Also, as for a material having good wettability, a material having good wettability with a solder component is preferable. For example, Au can be used, and an electroless Au plating method can be applied similarly to Ni.
[0025]
Hereinafter, embodiments of the present invention will be specifically described.
In a general LSI element, the periphery of an Al electrode is covered with a passivation film. More specifically, the structure is such that Ti or titanium nitride (TiN) is formed on the electrode portion of the Al film of the internal wiring, and the Al film is formed thereon. Then, a nickel (Ni) film is formed on the Al film by using one or more methods such as a vapor deposition method, a sputtering method, and a plating method. Further, a thin film of Au for securing solderability is formed on Ni if necessary. Alternatively, solder bumps may be formed.
[0026]
On the other hand, in a circuit board on which this LSI element is mounted, usually, a copper (Cu) wiring is formed, and the electrodes also have a Ni layer on Cu and an Au layer (thin) thereon. Then, a solder resist is applied to the periphery of the electrode portion and to portions other than the electrode. There is a case where the coating with the solder resist is displaced and the side wall of the electrode portion is exposed. Furthermore, in the substrate for BGA and CSP mounting, the periphery of the electrode portion is not intentionally covered with an insulating film. Here, such a substrate was used as a comparative example in the following examples.
[0027]
First, in the LSI element (semiconductor element) applied to this embodiment, the periphery of the electrode is surely covered with the passivation film. The film configuration of this electrode is Au / Ni / Al / TiN / Al (wiring) from the upper layer.
[0028]
2A and 2B are diagrams showing a film configuration of an electrode according to an embodiment of the present invention. FIG. 2A is a cross-sectional view of an electrode structure before solder melting, and FIG. 2B is an electrode structure after solder melting. It is sectional drawing of a body.
[0029]
As shown in FIG. 2A, a circuit pattern 11 is formed on an ordinary alumina circuit board 10, and a Cu electrode portion 12 is formed on the circuit pattern 11. Further, using an electroless Ni plating solution and process conditions, a Ni film 13 is formed so as to cover the whole including the upper layer and the side wall of the Cu electrode portion 12. Further, an Au layer 14 is similarly stacked on the Ni film 13 using an Au flash plating solution. As a result, all exposed surfaces including the side surfaces of the electrode film are covered with the Au / Ni film. The standard components of the electroless nickel plating solution are, for example, the following.
[0030]
Additives such as nickel sulfate, sodium hypophosphite, lactic acid, etc. The weight in the plating solution in which these are mixed is almost the same per unit (for example, 1 liter). In addition, solder resists 16 and 17 are formed on the circuit pattern 11 and at a portion (non-contact) surrounding the Cu electrode portion 12.
[0031]
Then, a solder bump 15 made of Sn-Ag-based solder is formed on the Au layer 14 or on the electrode portion of the above-described LSI element by an ordinary method.
With the above configuration, even when the solder is melted as shown in FIG. 2B, the melted and flowing solder diffuses and reacts with the circuit pattern 11 and the Cu electrode portion 12 (compound formation). ) Does not occur. In FIG. 2B, the Au layer 14 is not shown because it is dissolved in the solder.
[0032]
Hereinafter, solder bumps are actually formed based on the electrode structure and the method for forming the same according to the present invention, and the evaluation results on the bonding reliability of the solder bumps will be described in comparison with comparative examples. In the following examples, the solder bumps 15 were formed not on the Au layer 14 but on the electrode portions of the LSI element.
[0033]
[First Embodiment]
In the first embodiment, first, the solder bump 15 formed on the electrode portion of the LSI element is brought into contact with the Cu electrode portion 12 covered with the Au / Ni film of the alumina circuit board 10 and is about 100 ° C. lower than the melting point of the solder. Heating is performed at a high temperature of 330 ° C. for 30 minutes to obtain a sample in which the LSI element is bonded on a circuit board. The Au / Ni film is obtained by forming a Ni film to a thickness of 2 μm and forming an Au film on the Ni film to a thickness of 0.1 μm or less. As a result of microscopic observation of the interface between the Cu electrode portion 12 and the solder bumps 15 of this sample, it was not observed that the solder penetrated the Ni layer 13 of the electrode film and reacted with the Cu electrode portion 12.
[0034]
On the other hand, as a comparative example, a conventional circuit board having the same Au / Ni / Cu configuration as the above-described embodiment was prepared (see FIG. 4). This is a CSP mounting board (circuit board 110), in which there is no solder resist layer around the electrodes, and the Cu electrode portions 112 are exposed on the side surfaces. Using this substrate, heating is performed at a temperature of 330 ° C. for 30 minutes in the same manner as described above to obtain a sample in which the LSI element is bonded onto the circuit board 110. As a result of microscopic observation of the interface between the Cu electrode portion 112 and the solder bump 115 for this sample, it was found that Sn as a solder component diffused into the Cu electrode portion 112 from the side wall to form reactive compounds R111 and R112. Was observed. This compound easily breaks when stress is applied to the joint, and impairs joint reliability.
[0035]
Further, in the first embodiment, a temperature cycle test was performed, and the process of solder deterioration (reliability data) was summarized as shown in FIG.
FIG. 3 is a diagram showing a process (reliability data) of solder deterioration in the first embodiment.
[0036]
According to FIG. 3, in the example of the conventional method and the first embodiment, the process of solder deterioration is shown as the evaluation result of the temperature cycle test. The vertical axis indicates the cumulative failure rate (%), and the horizontal axis indicates the number of elapsed cycles (cycles). Here, as is clear from FIG. 3, the temperature cycle test resulted in a higher failure rate per number of elapsed cycles in the first embodiment than in the conventional method.
[0037]
From these results, the effect in the first example was confirmed.
[Second embodiment]
Next, a second embodiment will be described.
[0038]
A polyimide resin substrate (Cu wiring) was used as a circuit board, and all other conditions were the same as those in the first embodiment.
As a result, no reaction between the Cu electrode portion 12 and the solder was observed anywhere, and the effect of the second example was confirmed.
[0039]
[Third embodiment]
Next, a third embodiment will be described.
Except that an epoxy resin substrate (Cu wiring) was used as the circuit board and the soldering conditions were 260 ° C. and 3 minutes (conforming to the soldering heat test standard), all other conditions were the same as in the first embodiment.
[0040]
As a result, no reaction between the Cu electrode portion 12 and the solder was observed anywhere, and the effect of the third example was confirmed.
Further, even after the sample was left at 150 ° C. for 100 hours, no reaction between the Cu electrode portion 12 and the solder was observed at any place, and the effect of the third example was confirmed.
[0041]
In the above description, the electrode portion is described as copper, but silver can be applied. However, these materials are merely examples, and any conductive material may be used as long as it has good electric conductivity, and is not particularly limited to copper or silver.
[0042]
In the above description, the electrode structure on the circuit board side has been described, but the present invention can also be applied as an electrode structure on the semiconductor element side.
(Appendix 1) In the electrode structure applied to the input / output terminals of the circuit board,
An electrode structure, wherein a solder diffusion preventing film made of a material having a capability of preventing the diffusion of a solder component is formed so as to cover the entire exposed portion of the electrode.
[0043]
(Supplementary Note 2) The electrode structure according to Supplementary Note 1, wherein the solder diffusion prevention film is further made of a material suitable for ensuring the close contact between the electrode and the solder.
(Supplementary note 3) The electrode structure according to supplementary note 2, wherein the solder diffusion preventing film is an electroless Ni plating film using an electroless plating method.
[0044]
(Supplementary Note 4) The electrode structure according to Supplementary Note 1, wherein a film made of a material having good wettability with the solder component is stacked on the solder diffusion preventing film as needed.
[0045]
(Supplementary note 5) The electrode structure according to supplementary note 4, wherein the film made of a material having good wettability is an electroless Au plating film using an electroless plating method.
(Supplementary Note 6) The electrode structure according to Supplementary Note 1, wherein the circuit board is an alumina circuit board.
[0046]
(Supplementary Note 7) The electrode structure according to Supplementary Note 1, wherein the circuit board is a polyimide resin substrate.
(Supplementary Note 8) The electrode structure according to supplementary note 1, wherein the circuit board is an epoxy resin substrate.
[0047]
(Supplementary Note 9) In the electrode structure applied to the input / output terminals of the semiconductor element,
An electrode structure, wherein a solder diffusion preventing film made of a material having a capability of preventing the diffusion of a solder component is formed so as to cover the entire exposed portion of the electrode.
[0048]
(Supplementary Note 10) The electrode structure according to Supplementary Note 9, wherein the solder diffusion preventing film is further made of a material suitable for ensuring close contact between the electrode and the solder.
(Supplementary Note 11) The electrode structure according to supplementary note 10, wherein the solder diffusion preventing film is an electroless Ni plating film using an electroless plating method.
[0049]
(Supplementary Note 12) The electrode structure according to Supplementary Note 9, wherein a film made of a material having good wettability with the solder component is stacked on the solder diffusion preventing film as needed.
[0050]
(Supplementary note 13) The electrode structure according to supplementary note 12, wherein the film made of the material having good wettability is an electroless Au plating film using an electroless plating method.
(Supplementary Note 14) In an electrode forming method applied to input / output terminals of a circuit board,
An electrode forming method, comprising forming a solder diffusion preventing film made of a material having a capability of preventing the diffusion of a solder component so as to cover the entire exposed portion of the electrode.
[0051]
(Supplementary note 15) The electrode forming method according to Supplementary note 14, wherein the solder diffusion preventing film is further made of a material suitable for ensuring close contact between the electrode and the solder.
[0052]
(Supplementary note 16) The electrode forming method according to supplementary note 15, wherein the solder diffusion preventing film is an electroless Ni plating film using an electroless plating method.
(Supplementary Note 17) The electrode forming method according to Supplementary Note 14, wherein a film made of a material having good wettability with the solder component is stacked on the solder diffusion preventing film as needed.
[0053]
(Supplementary note 18) The electrode forming method according to supplementary note 17, wherein the film made of the material having good wettability is an electroless Au plating film using an electroless plating method.
(Supplementary Note 19) In the method of forming electrodes for input / output terminals of a semiconductor element,
An electrode forming method, comprising forming a solder diffusion preventing film made of a material having a capability of preventing the diffusion of a solder component so as to cover the entire exposed portion of the electrode.
[0054]
(Supplementary note 20) The electrode forming method according to Supplementary note 19, wherein the solder diffusion prevention film is further made of a material suitable for ensuring close contact between the electrode and the solder.
[0055]
(Supplementary note 21) The electrode forming method according to supplementary note 20, wherein the solder diffusion preventing film is an electroless Ni plating film using an electroless plating method.
(Supplementary Note 22) The electrode forming method according to Supplementary Note 19, wherein a film made of a material having good wettability with the solder component is stacked on the solder diffusion preventing film as needed.
[0056]
(Supplementary note 23) The electrode forming method according to supplementary note 22, wherein the film made of the material having good wettability is an electroless Au plating film using an electroless plating method.
[0057]
【The invention's effect】
As described above, in the present invention, the solder diffusion preventing film made of a material having the ability to prevent the diffusion of the solder component is formed so as to cover the entire exposed portion of the electrode.・ Reaction can be prevented. As a result, high-reliability and low-cost soldering can be performed by a simple process.
[Brief description of the drawings]
FIGS. 1A and 1B are principle configuration diagrams of the present invention. FIG. 1A is a sectional view of an electrode structure before melting, and FIG. 1B is a sectional view of the electrode structure after melting.
2A and 2B are diagrams illustrating a film configuration of an electrode according to an embodiment of the present invention. FIG. 2A is a cross-sectional view of an electrode structure before solder melting, and FIG. 2B is an electrode structure after solder melting. It is sectional drawing of a body.
FIG. 3 is a view showing a process (reliability data) of solder deterioration in the first embodiment.
4A and 4B are diagrams showing a conventional electrode structure, wherein FIG. 4A is a sectional view of the electrode structure before solder melting, and FIG. 4B is a sectional view of the electrode structure after solder melting. .
FIG. 5 is a diagram showing the influence of the electrode shape on the reliability of the solder joint in mounting the CSP.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Circuit board 2a Circuit pattern 2b Electrode part 3 Solder diffusion prevention film 4 Solder bump 6,7 Solder resist

Claims (10)

回路基板の入出力端子に施す電極構造体において、
電極の露出部全面を覆うように、はんだ成分の拡散を防ぐ能力を有する材料から成るはんだ拡散防止膜を形成したことを特徴とする電極構造体。In the electrode structure applied to the input / output terminals of the circuit board,
An electrode structure, wherein a solder diffusion preventing film made of a material having a capability of preventing the diffusion of a solder component is formed so as to cover the entire exposed portion of the electrode. 前記はんだ拡散防止膜は、さらに前記電極とはんだとの密着を確保するために適した材料から成ることを特徴とする請求項１記載の電極構造体。2. The electrode structure according to claim 1, wherein the solder diffusion preventing film is further made of a material suitable for ensuring close contact between the electrode and the solder. 前記はんだ拡散防止膜は、無電解めっき法を用いた無電解Ｎｉめっき膜であることを特徴とする請求項２記載の電極構造体。The electrode structure according to claim 2, wherein the solder diffusion preventing film is an electroless Ni plating film using an electroless plating method. さらに、前記はんだ拡散防止膜の上に、必要に応じて、前記はんだ成分とのぬれ性が良い材料から成る膜をつみ重ねることを特徴とする請求項１記載の電極構造体。2. The electrode structure according to claim 1, wherein a film made of a material having good wettability with the solder component is stacked on the solder diffusion preventing film as needed. 前記ぬれ性が良い材料から成る膜は、無電解めっき法を用いた無電解Ａｕめっき膜であることを特徴とする請求項４記載の電極構造体。The electrode structure according to claim 4, wherein the film made of a material having good wettability is an electroless Au plating film using an electroless plating method. 半導体素子の入出力端子に施す電極構造体において、
電極の露出部全面を覆うように、はんだ成分の拡散を防ぐ能力を有する材料から成るはんだ拡散防止膜を形成したことを特徴とする電極構造体。In an electrode structure applied to an input / output terminal of a semiconductor element,
An electrode structure, wherein a solder diffusion preventing film made of a material having a capability of preventing the diffusion of a solder component is formed so as to cover the entire exposed portion of the electrode. 前記はんだ拡散防止膜は、さらに前記電極とはんだとの密着を確保するために適した材料から成ることを特徴とする請求項６記載の電極構造体。7. The electrode structure according to claim 6, wherein the solder diffusion preventing film is further made of a material suitable for ensuring close contact between the electrode and the solder. さらに、前記はんだ拡散防止膜の上に、必要に応じて、前記はんだ成分とのぬれ性が良い材料から成る膜をつみ重ねることを特徴とする請求項６記載の電極構造体。7. The electrode structure according to claim 6, wherein a film made of a material having good wettability with the solder component is stacked on the solder diffusion preventing film as needed. 回路基板の入出力端子に施す電極形成方法において、
電極の露出部全面を覆うように、はんだ成分の拡散を防ぐ能力を有する材料から成るはんだ拡散防止膜を形成することを特徴とする電極形成方法。In an electrode forming method applied to input / output terminals of a circuit board,
An electrode forming method, comprising forming a solder diffusion preventing film made of a material having a capability of preventing the diffusion of a solder component so as to cover the entire exposed portion of the electrode. 半導体素子の入出力端子に施す電極形成方法において、
電極の露出部全面を覆うように、はんだ成分の拡散を防ぐ能力を有する材料から成るはんだ拡散防止膜を形成することを特徴とする電極形成方法。In an electrode forming method applied to input / output terminals of a semiconductor element,
An electrode forming method, comprising forming a solder diffusion preventing film made of a material having a capability of preventing the diffusion of a solder component so as to cover the entire exposed portion of the electrode.
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