JP5280807B2 - Switching power supply - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a switching power unit which is free of faults and is capable of being made compact and reduced in cost, by controlling a switching element without fail to be turned on and off, with respect to drop in the input voltage, in a switching power unit of digital control that uses a low-speed digital processor. <P>SOLUTION: A digital pulse width modulation signal generator 44 provided in the digital processor 34 generates a first pulse width modulation signal V1, which is of specified cycles and in which specified maximum on-duty value is set. A comparator circuit 60 receives the input of a triangular wave signal V3, the inclination of which changes according to an input voltage Vin, and an output voltage control signal V4, and generates the second pulse width modulation signal V5. An AND circuit 62 outputs a second pulse width modulation signal V5, when the on-duty value of the second pulse width modulation signal V5 is below its maximum on-duty value and the first pulse width modulation signal V1 in case that the on-duty value of the second pulse width modulation signal V5 is at or over its maximum on-duty, as drive signals V6 to the switching element 18. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

The present invention relates to a switching power supply device for converting a DC voltage into a desired voltage and supplying the same to an electronic device, and more particularly to a switching power supply device to which digital control and input voltage feedforward control are applied.

  Conventionally, as a method for improving the output voltage stability of a switching power supply apparatus when the input voltage fluctuates rapidly, an input voltage feed, which is a control method for adjusting the on-duty of a switching element with respect to the input voltage of the switching power supply apparatus Forward control is known.

  For example, Patent Document 1 discloses an example in which input voltage feedforward control is applied to a step-down chopper circuit that is a non-insulated DC / DC converter. In addition, in the Patent Document 2, the present inventor discloses an example in which the input voltage feedforward control is applied to an insulated single-ended forward converter.

  FIG. 17 shows an example of a switching power supply device in which input voltage feedforward control is applied to an insulated single-ended forward converter. FIG. 18 shows the operation waveforms of the switching power supply device of FIG. 17 separately for a case where the input voltage is low and a case where the input voltage is high.

  In the switching power supply device of FIG. 17, the primary winding 104 and the switching element 108 of the transformer 102 are connected in series to the input power supply 100, and the synchronous rectification elements 136 and 138 and the synchronous rectification control circuit are connected to the secondary winding 106 of the transformer 102. 140, a rectifying / smoothing circuit 110 having a choke coil 142 and a smoothing capacitor 144 is connected, a switching control circuit 114 is connected to the switching element 108, and the switching control circuit 114 controls the on-duty of the switching element 108, whereby the output voltage Vo is controlled to a predetermined voltage.

  The switching control circuit 114 includes a triangular wave generation circuit 116, a drive circuit 120, and an output voltage control signal generation circuit 118. The triangular wave generation circuit 116 includes a current source circuit 122 having a resistor 124 that outputs a current I proportional to the input power supply voltage Vin, a capacitor 126 that generates a triangular wave voltage, and a reset circuit 128.

Here, when the voltage of the capacitor 126 is V11, the output current I of the current source circuit 122 is a current flowing through the resistor 124 having the resistance value R, and
I = (Vin−V11) / R
It becomes.

  When Vin >> V11, since I≈Vin / R, the current source circuit 122 outputs a current I proportional to the input voltage Vin. That is

となる。

It becomes.

  Next, the operation of the switching power supply of FIG. 17 will be described with reference to a time chart showing signal waveforms of respective parts of FIG. FIG. 18 shows a signal waveform when the input voltage changes from a high value to a low value in the middle.

  First, as shown in FIG. 18A, the reset circuit 128 instantaneously outputs a reset signal at a predetermined period T to discharge and reset the capacitor 126 of the triangular wave generation circuit 116. The reset period T This is the switching frequency of the device. When the capacitor 126 is reset, the drive circuit 120 turns on the switching element 108.

  Subsequently, the capacitor 126 is charged with the current I, and the capacitor voltage V11 changes according to the equation (2) with respect to time t.

ここで、Ｖ１１は三角波発生回路１１６の出力電圧、Ｖｉｎは入力電圧、tは充電時間、
Ｃはコンデンサ１２６の容量、Ｒは抵抗１２４の値である。

Here, V11 is the output voltage of the triangular wave generation circuit 116, Vin is the input voltage, t is the charging time,
C is the capacitance of the capacitor 126, and R is the value of the resistor 124.

  The capacitor voltage V11 from the triangular wave generation circuit 116 is output to the inverting input terminal of the comparison circuit 134 provided in the drive circuit 120.

  On the other hand, the output voltage control signal generation circuit 118 generates, as an output voltage control signal V12, an error voltage obtained by amplifying the difference between the reference voltage Vref from the reference voltage source 132 and the output voltage Vo of the switching power supply device by the error amplifier 130. Is output to the non-inverting input terminal.

The comparison circuit 134 compares the capacitor voltage V11 and the output voltage control signal V12. When V12> V11, the drive signal V13 is at a high level and turns on the switching element 108. When V12 <V11, the drive signal V13 is at a low level. By turning off the switching element 108, the ON period Ton of the switching element 108, that is, the on-duty Don = (Ton / T)
To control.

  By repeating the ON / OFF operation of the switching element 108 by the switching control circuit 114, a pulse voltage is applied to the primary winding 104 of the transformer 102 and transmitted to the secondary side. The pulsed voltage generated in the secondary winding 106 of the transformer 102 is converted into direct current by the rectifying and smoothing circuit 110 and becomes the output voltage Vo of the switching power supply device.

  Next, output voltage control when the switching power supply device of FIG. 17 operates ideally will be described.

  When the ideal operation is performed, the output voltage of the switching power supply device of FIG. 17 is determined as shown in Expression (3).

ここで、Ｖｏは出力電圧、Ｖｉｎは入力電圧、Ｎ１はトランス１０２の１次巻線１０４の巻数、Ｎ２はトランス１０２の２次巻線１０６の巻数、Ｔはスイッチング周期、Ｔｏｎはスイッチング素子１０８のオン時間である。

Here, Vo is the output voltage, Vin is the input voltage, N1 is the number of turns of the primary winding 104 of the transformer 102, N2 is the number of turns of the secondary winding 106 of the transformer 102, T is the switching period, and Ton is the switching element 108. It is on time.

The on-time Ton of the switching element 108 is determined by the time until the capacitor voltage V11 reaches the error voltage V12.
V ₁₁ = V ₁₂ formula (4)
The following formulas are obtained from formulas (1) to (4).

式(５)から、理想的に動作する図１７のスイッチング電源装置は、出力電圧制御信号Ｖ１２が一定の値となるように制御を行なうことで、入力電圧Ｖｉｎが変動しても出力電圧Ｖｏを一定とすることができることが分かる。

From the equation (5), the switching power supply device of FIG. 17 that operates ideally performs the control so that the output voltage control signal V12 becomes a constant value, so that the output voltage Vo is changed even if the input voltage Vin varies. It can be seen that it can be constant.

  Expressing the expression (5) qualitatively, as shown on the left side of FIG. 18, when the input voltage Vin is low, the rising speed of the capacitor voltage V11 input to the comparison circuit 134 is slow, so the switching element 108 is turned on. Period Ton becomes longer. On the other hand, as shown on the right side of FIG. 18, when the input voltage Vin is high, the rising speed of the capacitor voltage V11 input to the comparison circuit 134 is fast, and therefore, Ton becomes short during the period when the switching element 108 is on.

The switching power supply device of FIG. 17 can control the output voltage Vo to a constant value even when the input voltage Vin suddenly fluctuates only by controlling the output voltage control signal V12 to a constant value. The switching element 108 has a feature that it can respond to the on-duty of the switching element 108 at high speed and can stabilize the output voltage of the switching power supply device.

JP-A-3-183357 JP 2008-131721 A

  However, in the isolated converter using the input voltage feedforward control used in such a conventional switching power supply device, when the input voltage is lowered, the transformer is saturated and an excessive stress is applied to a semiconductor such as a switching element. In the worst case, there is a problem that the semiconductor is destroyed, and this problem can be explained as follows.

  The on period Ton of the switching element of the isolated single-ended forward converter using the input voltage feedforward control is determined by the above equation (3). When the input voltage Vin decreases, the switching power supply device performs an operation of controlling the output voltage to be constant by increasing the turn-on time Ton of the switching element.

  However, in the control of this switching power supply device, if the input voltage Vin becomes too small, the switching element cannot be turned off, the transformer is saturated, a large current flows through the switching element, and an excessive stress is applied to the switching element. In the worst case, the phenomenon of destroying the switching element occurs. This is because, in the above equation (3), in the input voltage Vin in which the ON period Ton of the switching element is equal to or greater than one switching period T, the ON period Ton of the switching element is actually 1 This occurs because it cannot be greater than the period T. This phenomenon is shown in FIG.

  In FIG. 19, the input voltage Vin greatly decreases at an arbitrary time tn, the rising speed of the capacitor voltage V11 becomes slow, and before the capacitor voltage V11 reaches the output voltage control signal V12 during the switching period T. The switching element 108 cannot be turned off by being reset by the reset signal.

  If the time during which the switching element 108 is not turned off continues for a long time, the transformer 102 is saturated and a large current flows through the switching element 108. When a large current flows, an excessive stress is applied to the switching element 108, and at the worst, the switching element 108 is destroyed.

  The following solutions can be considered for such problems. The first solution is to provide a maximum on-duty limiting circuit 146 between the drive circuit 120 and the switching element 108 as shown in FIG. By providing the maximum on-duty limiting circuit 146, it is possible to create a period in which the switching element is forcibly turned off with respect to one switching period, and to prevent the transformer from being saturated, thereby preventing the power supply device from being destroyed.

  However, this method has a problem that the number of parts and the cost due to the electronic components necessary for the maximum on-duty limit circuit increase, and the maximum on-duty limit circuit varies depending on the electronic components constituting the maximum on-duty limit circuit. There arises a new problem that the duty limit value varies, the switching element cannot be operated with a wide on-duty, and the conversion efficiency of the switching power supply device is lowered.

  Generally, in a switching power supply device that outputs the same power, conversion efficiency can be improved by widely using the on-duty of the switching element. By widening the on-duty of switching elements, the conduction time of components such as semiconductor elements and transformers can be lengthened. Therefore, the effective value of the current flowing through these elements is reduced, and the loss due to the resistance of these elements is reduced. This is because it can be reduced.

  For this reason, a switching power supply device with high conversion efficiency is designed so that the on-duty of the switching element is increased, but operates at an on-duty close to the maximum on-duty limit value limited by the maximum on-duty limit circuit 146. If the switching power supply is made, when the limit value of the maximum on-duty limit circuit 146 varies, a phenomenon occurs in which the on-duty of the switching element cannot be expanded to a target size.

  Therefore, unless the design is made sufficiently different from the duty value limited by the maximum on-duty limit circuit 146, the value of the on-duty of the switching element when the switching power supply device performs normal operation is sufficiently separated. There is a possibility that a switching power supply device that cannot take out a target output voltage is produced.

  Therefore, at the expense of conversion efficiency, the switching power supply device is designed to reduce the on-duty of the switching element during normal operation, and as a result, a switching power supply device with high conversion efficiency is obtained. I can't.

  Another possible solution is to provide a switching power supply device with a stop circuit that operates at high speed. For example, consider a case where a switching power supply device with a rated input voltage of 48 volts and a rated output voltage of 5 volts is configured with a transformer turns ratio of N1: N2 = 4: 1 using the circuit of the switching power supply device of FIG. .

  From Equation (3), in this switching power supply device, Ton = T when Vin = 20 volts. That is, if this switching power supply device is operated at Vin = 20 volts or less, the switching element cannot be turned off, transformer saturation occurs, excessive stress is applied to the switching element, and the power supply device is destroyed.

  Here, in a switching power supply with a rated input voltage of 48 volts, the required input voltage range is generally set to about 35 to 75 volts. Therefore, when Vin = 30 volts or less, the power supply is stopped. There is no real harm.

  Therefore, a circuit that monitors the input voltage is provided in the switching power supply device, and the power supply is destroyed by performing control so that the operation of the switching power supply device is surely stopped before Vin = 20 volts or less. Can be prevented.

  However, this method requires a stop circuit that has a short delay time and operates at a high speed so that the switching power supply can be reliably stopped even when the input voltage suddenly drops. Will be increased.

  In recent years, it has been studied to perform digitally controlled switching power supply control using a high-performance digital processor known as a DSP or the like. In a digitally controlled switching power supply, information such as the input voltage, ambient temperature, output current, and output voltage of the switching power supply is taken into the digital processor, and calculation is performed based on a program built in the digital processor. Control the behavior.

  In digital control, the number of parts has been reduced by replacing many of the circuits previously configured with analog components with operations based on digital processor programs, and the state of switching power supplies has been detected and the program to be executed has been changed ( (Conditional control) can be easily realized and has many advantages such as that it is possible to perform advanced control that was not possible with analog control, and therefore it is being energetically developed.

  However, the digitally controlled switching power supply device has a drawback that response processing is delayed with respect to a change in the state of the switching power supply because the operation of the switching power supply is controlled by a program.

  This is due to the fact that a digital processor can only process serially various items to be processed. That is, when the digital processor performs an operation on any item, even if the state of the other item changes, it cannot be detected that the state change has occurred.

For example, let us consider a case where four items of input voltage, ambient temperature, output current, and output voltage are monitored by a digital processor and calculation is performed. In this case, a certain time is required for each process, and each process is executed in order.
That means
(1) Monitoring and calculation of input voltage,
(2) Monitoring and calculation of ambient temperature,
(3) Monitoring and calculation of output current,
(4) Monitoring and calculation of output voltage,
(5) Return to (1) above.
A flow that performs processing in the order of saying is made, and after everything is finished, a loop operation is performed in which processing is repeated from the beginning.

  For example, if 10 μsec is required for each process, the calculation for the input voltage can be performed only every 40 μsec. Here, if the switching operation of the switching power supply device with respect to the input voltage is controlled by the digital processor, even if the input voltage is equal to or lower than the stop voltage, a voltage drop cannot be detected for 40 μsec.

  Also, in digital control, in order to avoid a digital processor from making an erroneous determination due to noise or the like, the state change determination is generally programmed to execute a process by multiple detections. Multiple detections are performed by repeating the processing loop multiple times.

  For example, when programmed to stop the power supply with three detections against a power supply stop due to a decrease in input voltage, a 40 μsec loop will be repeated three times, resulting in a delay time of 120 μsec. It will be.

  For this reason, if the digital processor performs a stop operation when an input voltage of 30 V or less is detected, there is a delay time of 120 μsec from the detection until the power supply is actually stopped. During this time, when the input voltage becomes 20 V or less, the power supply is turned off. There is a possibility of destruction.

  In order to solve this problem, the switching power supply must be designed so that the time for the input voltage to drop from 30 V to 20 V is 120 μsec or longer. In order to suppress the change speed of the input voltage, a capacitor is provided at the input of the switching power supply.

  Assume that the switching power supply device in FIG. 17 outputs an output voltage of 5 volts and an output current of 10 amperes. Considering the moment when the switching power supply is disconnected from the input power supply, the input voltage of the switching power supply is supplied from a capacitor provided on the input side of the switching power supply.

  When calculating a capacitor necessary for preventing the switching power supply device from being destroyed, the following four simultaneous equations are obtained. When the simultaneous equations are solved, Equation (6) is obtained.

ここで、Ｃｉｎはスイッチング電源装置の入力側に設けられたコンデンサの容量、ΔＶＣｉｎはスイッチング電源装置の入力側に設けられたコンデンサの電圧変化、Ｉｉｎはスイッチング電源装置の入力電流、Ｖｉｎはスイッチング電源装置の入力電圧、Ｉｏはスイッチング電源装置の出力電流（＝１０Ａ）、Ｖｏはスイッチング電源装置の出力電圧（＝５Ｖ）、Ｖｓｔｏｐは停止検出電圧(＝３０Ｖ)、Ｖｆａｉｌはスイッチング電源装置が故障する電圧(＝２０Ｖ)、ｔはスイッチング電源装置の入力電圧ＶｉｎがＶｓｔｏｐからＶｆａｉｌの達するまでの時間（＝１２０μｓｅｃ）、Ｅｆｆはスイッチング電源装置の変換効率である。

Here, Cin is a capacitance of a capacitor provided on the input side of the switching power supply, ΔVCin is a voltage change of the capacitor provided on the input side of the switching power supply, Iin is an input current of the switching power supply, and Vin is a switching power supply. , Io is the output current (= 10A) of the switching power supply, Vo is the output voltage (= 5V) of the switching power supply, Vstop is the stop detection voltage (= 30V), and Vfail is the voltage at which the switching power supply fails ( = 20 V), t is the time (= 120 μsec) until the input voltage Vin of the switching power supply reaches Vfail from Vstop, and Eff is the conversion efficiency of the switching power supply.

  Assuming that the conversion efficiency is 1, and solving the above equation, it can be calculated that a large capacitor of C = 30 μF or more is required. This is a factor that prevents the switching power supply device from being reduced in size and cost. To reduce the capacitor, a high-speed digital processor can be used to shorten the delay time. However, since the high-speed digital processor is expensive, the cost cannot be reduced.

The present invention is capable of downsizing and cost reduction without device failure by controlling on and off of the switching element reliably against a decrease in input voltage by digital control using a low-speed digital processor known as a one-chip microcomputer or the like. An object of the present invention is to provide a simple switching power supply device.

In the present invention, a primary winding of a transformer and a switching element are connected in series to an input power source, a rectifying and smoothing circuit is connected to a secondary winding of the transformer, a switching control circuit is connected to the switching element, and the switching control circuit is In the switching power supply device that controls the output voltage to a predetermined voltage by controlling the on-duty of the switching element,
Switching control circuit
A digital pulse width modulation signal generating section that is provided in the digital processor and generates a first pulse width modulation signal having a predetermined period and a predetermined maximum on-duty;
A triangular wave generating circuit that repeatedly generates a triangular wave signal in synchronism with the first pulse width modulation signal, the inclination of which changes according to the input voltage;
An output voltage control signal generating circuit for generating an output voltage control signal for controlling the output voltage to a predetermined voltage;
A comparison circuit for inputting a triangular wave signal and an output voltage control signal, and generating a second pulse width modulation signal having an on-duty according to the output voltage control signal;
The first pulse width modulation signal and the second pulse width modulation signal are input, and when the on-duty of the second pulse width modulation signal is less than the maximum on-duty, the second pulse width modulation signal is output as a drive signal to the switching element. A logic circuit that outputs the first pulse width modulation signal as a drive signal to the switching element when the on-duty of the second pulse width modulation signal is greater than or equal to the maximum on-duty;
It is provided with.

Here, the digital pulse width modulation signal generation unit provided as the logic circuit unit of the digital processor is:
A counter for counting clock signals;
A first register for setting a first clock number N1 corresponding to the maximum on-duty;
A second register for setting a second clock number N2 corresponding to a predetermined period;
A first comparison circuit that outputs when the count clock number of the counter reaches the first clock number N1,
A second comparison circuit that outputs when the count clock number of the counter reaches the first clock number N2,
A flip-flop that is reset at the output of the first comparison circuit, is set at the output of the second comparison circuit, and outputs a first pulse width modulation signal having a maximum on-duty;
A function to reset and start the counter by the output of the second comparison circuit;
Is provided.

The triangular wave generator circuit
A current source circuit that outputs a current proportional to the input voltage;
A capacitor that is charged by a current source circuit to generate a triangular wave voltage;
A reset circuit that operates for a short time from the start timing at which the first pulse width modulation signal changes from low level to high level and discharges and resets the capacitor;
Is provided.

The reset circuit
A differentiating circuit for generating a differential pulse signal in synchronization with the rising of the first pulse width modulation signal from a low level to a high level;
A switching element for resetting that is turned on by a differential pulse signal to reset the discharge of the capacitor;
Is provided.

The triangular wave generator circuit
A current source circuit that outputs a current proportional to the input voltage;
A capacitor that is charged by a current source circuit to generate a triangular wave voltage;
A reset circuit that operates only during a low level period of the first pulse width modulation signal to discharge and reset the capacitor;
Is provided.

  The reset circuit includes a diode having an anode connected to the positive potential side of the capacitor and a cathode connected to an output terminal of a digital processor that outputs the first pulse width modulation signal.

  The logic circuit is a 2-input AND circuit (AND circuit) to which the first pulse width modulation signal and the second pulse width modulation signal are input.

The digital pulse width modulation signal generator outputs an inverted first pulse width modulation signal obtained by inverting the first pulse width modulation signal,
The triangular wave generator circuit
A current source circuit that outputs a current proportional to the input voltage;
A capacitor that is charged by a current source circuit to generate a triangular wave voltage;
A reset circuit that operates for a short time from the start timing when the inverted first pulse width modulation signal changes from a high level to a low level and discharges and resets the capacitor;
Is provided.

The reset circuit in this case is
A differentiating circuit for generating a differential pulse signal in synchronization with the fall of the inverted first pulse width modulation signal from a high level to a low level;
A switching element for resetting that is turned on by a differential pulse signal to reset the discharge of the capacitor;
Is provided.

The digital pulse width modulation signal generator outputs an inverted first pulse width modulation signal obtained by inverting the first pulse width modulation signal,
The triangular wave generator circuit
A current source circuit that outputs a current proportional to the input voltage;
A capacitor that is charged by a current source circuit to generate a triangular wave voltage;
A reset circuit that operates only during a high level period of the inverted first pulse width modulation signal to discharge and reset the capacitor;
Is provided.

  The reset circuit in this case includes a reset switching element that is turned on during the high level period of the inverted first pulse width control signal to discharge and reset the capacitor.

The digital pulse width modulation signal generator outputs an inverted first pulse width modulation signal obtained by inverting the first pulse width modulation signal,
The logic circuit
A two-input OR circuit (OR circuit) that receives the inverted first pulse width modulation signal and the second pulse width modulation signal;
An inverter that inverts the output of the OR circuit and outputs a drive signal to the switching element;
Is provided.

The digital processor can execute
When the power supply is turned on, the on-duty of the first pulse width modulation signal or the off-duty of the inverted first pulse width modulation signal is changed at a predetermined increase rate based on the program over time, and the output voltage is directed to the predetermined voltage Soft start processing part to raise,
When the power supply is stopped, the output voltage is decreased from the predetermined voltage by changing the on-duty of the first pulse width modulation signal or the off-duty of the inverted first pulse width modulation signal at a predetermined reduction rate based on the program over time. Soft stop processing unit,
Realize the function.

The soft start processing unit changes the on-duty increase rate so that it is inversely proportional to the magnitude of the input voltage, so that the time until the output voltage rises to the specified voltage is not affected by the input voltage. Done
The soft stop processing unit changes the on-duty reduction rate so that it is inversely proportional to the magnitude of the input voltage, so that the time until the output voltage drops to a predetermined voltage is not affected by the input voltage. Do.

For example, the output voltage control signal generation circuit generates an output voltage control signal of an output voltage signal and a predetermined reference voltage signal.

  According to the present invention, even if the switching element cannot be turned off by the second pulse width modulation signal based on the comparison of the triangular wave voltage and the output voltage control signal due to the decrease in the input voltage, the switching control cycle is determined by the clock of the digital processor and The switching element can always be turned off by the first pulse width modulation signal having the maximum on-duty, and the phenomenon that the switching element cannot be turned off even when the input voltage is lowered does not occur. Device failure can be reliably prevented without the need for a circuit or a high-speed digital processor.

  In addition, since the first pulse width modulation signal generated by the digital processor has an accurate correlation between the switching period and the pulse width, the maximum on-duty limit does not vary, and the switching power supply device performs normal operation. It is possible to design the on-duty of the switching element widely, and a switching power supply device with high conversion efficiency can be obtained.

  As a result, a low-cost and low-cost digital processor can be used to obtain a switching power supply device with a small number of parts, no failure, and high conversion efficiency.

  Further, according to the present invention, it is possible to realize soft start and soft stop of a switching power supply device using a low-speed and low-cost digital processor without adding any special parts, and the number of parts is small, so Thus, a switching power supply device having a soft start function and a soft stop function with high conversion efficiency can be obtained.

Further, the output voltage change amount at the time of soft start and soft stop can be controlled to be constant with respect to the voltage change of the input power supply without adding any special parts, so that stable start and stop can be performed.

  FIG. 1 is a circuit block diagram showing a first embodiment of a switching power supply device according to the present invention. In FIG. 1, the switching power supply device of this embodiment includes an input power supply 10, a transformer 12, a switching element 18 using a MOS-FET, a rectifying / smoothing circuit 20 connected to output terminals 22a and 22b, and a switching control circuit 24. Is done.

  The input power supply 10 receives an input voltage Vin, and the input power supply 10 may be a DC power supply such as a battery, or DC power may be input by rectifying and smoothing the AC power supply.

  The transformer 12 has a primary winding 14 and a secondary winding 16. A switching element 18 is connected in series with the primary winding 14 of the transformer 12, and a DC power supply voltage Vin is input thereto.

  In this embodiment, the rectifying / smoothing circuit 20 uses a synchronous rectification type. That is, the rectifying / smoothing circuit 20 includes a forward-side synchronous rectifying element 25, a flywheel-side synchronous rectifying element 26, a synchronous rectifying drive circuit 28, a choke coil 30, and a smoothing capacitor 32.

  The switching control circuit 24 is provided with a digital processor 34, a triangular wave generation circuit 36, an output voltage control signal generation circuit 38, and a drive circuit 40. The switching control circuit 24 controls the on-duty of the switching element 18 to control the output voltage Vo from the rectifying / smoothing circuit 20 at a constant voltage.

  The digital processor 34 provided in the switching control circuit 24 is provided with a soft start / stop processor 42 and a digital pulse width modulation signal generator 44. Here, the digital processor 34 is a low-speed and low-cost computer known as a one-chip microcomputer. The CPU, RAM, ROM, various input / output devices, etc. are mounted on one IC chip, and the low-speed one is several MHz. Even a high-speed processor uses a processor that operates at a clock frequency up to about several tens of MHz.

  The soft start / stop processing unit 42 provided in the digital processor 34 is a function realized by execution of a program by the CPU.

  The digital pulse width modulation signal generation unit 44 is realized by a logic circuit provided in the digital processor 34, and is a first pulse width modulation signal in which a maximum on-time Ton (max) having a predetermined switching period T and a maximum on-duty is set. V1 is generated.

  The triangular wave generating circuit 36 is connected with a capacitor 50 in series with a current source circuit 46 using a resistor 48, and with a reset circuit 52 in parallel with the capacitor 50. The reset circuit 52 receives the first pulse width modulation signal V1 from the digital pulse width modulation signal generator 44.

  The reset circuit 52 forms a differentiating circuit with a capacitor 54 and a resistor 56, the output of this differentiating circuit is input to the base of the NPN transistor 58, and the collector of the NPN transistor 58 is connected to the positive potential side of the capacitor 50.

  For this reason, the reset circuit 52 outputs a pulse-like reset signal that becomes a very short time in synchronization with the rising of the first pulse width modulation signal V1 from the low level to the high level, and resets the capacitor 50 by discharging.

  The current source circuit 46 charges the capacitor 50 by flowing a current I proportional to the input voltage Vin from the input power supply 10, whereby the terminal voltage of the capacitor 50 increases linearly according to the above equation (2). The voltage of the capacitor 50 becomes a triangular wave voltage by alternately repeating charging by the current source circuit 46 and discharging by the reset circuit 52. The triangular wave generation circuit 36 outputs the voltage of the capacitor 50 as a triangular wave signal V3.

  The output voltage control signal generation circuit 38 inputs the output voltage Vo to the inverting input terminal of the error amplifier 64, and outputs an error voltage with respect to the reference voltage Vref from the reference voltage source 66 connected to the non-inverting input terminal. Output as signal V4.

The drive circuit 40 is provided with a comparison circuit 60 and a logical product circuit (AND circuit) 62. The comparison circuit 60 inputs the triangular wave signal V3 from the triangular wave generation circuit 36 to the inverting input terminal, and inputs the output voltage control signal V4 from the output voltage control signal generation circuit 38 to the non-inverting input terminal,
V3 <V4
To output a high level signal,
V3> V4
To output a low level signal.

  The output signal from the comparison circuit 60 is output to the AND circuit 62 as the second pulse width modulation signal V5 whose on-time changes according to the level of the output voltage control signal V4.

  The AND circuit 62 receives the first pulse width modulation signal V1 from the digital pulse width modulation signal generator 44 provided in the digital processor 34 and the second pulse width modulation signal V5 from the comparison circuit 60. The on-duty of the switching element 18 is controlled by generating the drive signal V6 and driving the switching element 18 by taking the logical product of these.

  That is, the AND circuit 62 is configured such that the on-time Ton of the second pulse width modulation signal V5 output from the comparison circuit 60 is less than the maximum on-time Ton (max) corresponding to the maximum on-duty in the first pulse width modulation signal V1. Outputs the second pulse width modulation signal V5 as the drive signal V6 to the switching element 18, while the on-time Ton of the second pulse width modulation signal V5 is equal to or greater than the maximum on-time Ton (max), the first pulse The width modulation signal V1 is output to the switching element 18 as the drive signal V6.

  FIG. 2 is a block diagram showing details of the digital processor 34 provided in the first embodiment of FIG. In FIG. 2, the digital processor 34 includes a CPU 68, a clock generation circuit 70, and a digital pulse width modulation signal generation unit 44. The CPU 68 is provided with a soft start / stop processing unit 42 as a function realized by executing the program. The digital processor 34 is provided with a RAM, a ROM, an AD converter, various input / output units, etc. in addition to this, but the description thereof is omitted.

  The digital pulse width modulation signal generator 44 is provided with a counter 72, a first register 74, a second register 76, a first comparison circuit 78, a second comparison circuit 80, and an RS flip-flop 82.

The counter 72 is an up counter, counts the clock signal from the clock generation circuit 70, and outputs count values (D _{C0 to} D _Cn ) to the first comparison circuit 78 and the second comparison circuit 80. In the first register 74, the first clock number corresponding to the maximum on-duty, that is, the maximum on-time Ton (max) in the first pulse width modulation signal V1 is set as the register value N1 (= D _{N10 to} D _N1n ). In the second register 76, the second clock number corresponding to the period T in the first pulse width modulation signal V1 is set as the register value N2 (= D _{N20 to} D _N2n ).

  The register values N1 and N2 of the first register 74 and the second register 76 are output to the first comparison circuit 78 and the second comparison circuit 80, respectively. Each of the first comparison circuit 78 and the second comparison circuit 80 includes n NAND circuits and one NOR circuit.

  When the count value reaches the register value N1 corresponding to the maximum on-time Ton (max) with respect to the increase in the count value due to the count of the clock signal for each period T by the counter 72, the first comparison circuit 78 starts from the low level output. It becomes a high level output, and the RS flip-flop 82 is reset.

  When the count value of the counter 72 reaches the register N2 corresponding to the cycle T, the second comparison circuit 80 changes from the low level output to the high level output, sets the RS flip-flop 82, and simultaneously resets and starts the counter 72. Then, the counting of the next period T is started.

  FIG. 3 is an explanatory diagram showing a signal generation operation using a counter by the digital pulse width modulation signal generation unit of FIG. FIG. 3A shows a clock signal, for example, a clock signal of several tens MHz determined by the operating frequency of the digital processor 34 is output. FIG. 3B shows the operation of the counter 72, and the counter value increases in accordance with the clock signal.

  For example, the register value N1 of the first register 74 is set to N1 = 500, for example, and the register value N2 of the second register 76 is set to N2 = 1000, for example. In this case, when the operation of the digital pulse width modulation signal generation unit 44 is started, the outputs of the first comparison circuit 78 and the second comparison circuit 80 are initially at a low level (L), and the RS flip-flop 82 is initially in the initial state. In the set state, the first pulse width modulation signal V1 rises from the low level (L) to the high level (H) as shown in FIG.

  When the count value increases in this state and reaches the register value N1 = 500, the output of the first comparison circuit 78 rises from the low level (L) to the high level (H), and the RS flip-flop 82 is reset. The first pulse width modulation signal V1 falls from the high level (H) to the low level (L).

  Thereafter, when the count value further increases and reaches the register value N2 = 1000, the output of the second comparison circuit 80 rises from the low level (L) to the high level (H), and the RS flip-flop 82 is set. The first pulse width modulation signal V1 rises from the low level (L) to the high level (H). At the same time, when the counter 72 starts resetting, counting from the count value 0 is started again, and this is repeated.

  In the description of the operation of FIG. 3, for the sake of easy understanding, the case where the register value N1 = 500 and the register value N2 = 1000 is taken as an example. However, in the embodiment of FIG. N1 is set to the maximum on-time Ton (max) corresponding to the maximum on-duty, and the on-duty such as 90% is actually set for the duty 50% of the first pulse width modulation signal V1 in FIG. become.

  Next, the operation of the first embodiment shown in FIG. 1 will be described with reference to a time chart showing signal waveforms of respective parts in FIG. 4A is the input voltage Vin, FIG. 4B is the first pulse width modulation signal V1, FIG. 4C is the input signal of the NPN transistor 58, and FIG. 4D is the input of the comparison circuit 60. 4 (E) shows the second pulse width modulation signal V5, and FIG. 4 (F) shows the drive signal V6.

  First, the digital pulse width modulation signal generator 44 provided in the digital processor 34 repeats the first pulse width modulation signal V1 having a pulse width corresponding to the maximum on-duty, that is, the maximum on-time Ton (max) with a constant period T. The period T is the switching frequency of the switching power supply device.

  At the timing when the first pulse width modulation signal V1 changes from the low level to the high level for every fixed period, the transistor 58 operates for a short time by the differential operation of the capacitor 54 and the resistor 56 of the reset circuit 52, and the capacitor 50 is discharged and reset. . After the discharge reset, the capacitor 50 is charged with the current I corresponding to the input voltage Vin determined by the resistor 48 of the current source circuit 46, and the charging voltage of the capacitor 50 increases according to the previous equation (2) with the passage of time. Then, the triangular wave signal V3 is output.

  On the other hand, the output voltage control signal generation circuit 38 outputs an output voltage as an output of the error amplifier 64 due to a difference between the output voltage Vo and the reference voltage Vref of the reference voltage source 66 in order to set the output voltage Vo of the switching power supply device as a target voltage. A control signal V4 is generated and applied to a non-inverting input terminal of a comparison circuit 60 provided in the drive circuit 40.

  The comparison circuit 60 compares the triangular wave signal V3 with the output voltage control signal V4, and outputs a high level during the time t1 to t2 until the triangular wave signal V3 reaches the output voltage control signal V4. At time t2, the triangular wave signal V3 is output. When the output voltage control signal V4 is exceeded, the output is switched to a low level. Subsequently, when the period T is reached at time t3, the reset circuit 52 operates again for a very short time, resets the capacitor 50, and after the discharge reset, charging of the capacitor 50 starts again, and the triangular wave signal V3 starts increasing.

  The second pulse width modulation signal V5 in the period T from time t1 to t3 is input to one of the AND circuits 62. At this time, the first pulse width modulation signal V1 is input to the other of the AND circuits 62. Yes. At this time, since the ON time Ton of the second pulse width modulation signal V5 is shorter than the maximum ON time Ton (max) of the first pulse width modulation signal V1, the second pulse width modulation signal V5 is output from the AND circuit 62 as the drive signal V6. The signal is output to the switching element 18 to turn on / off the switching element 18.

  In the next period from time t3 to t6, after the triangular wave signal V3 reaches the output voltage control signal V4 at time t4, the second pulse width modulation signal V5 of the comparison circuit 60 changes from high level to low level. At time t5, the power supply voltage Vin changes from the previous voltage to a lower voltage.

  When the input voltage Vin decreases at time t5, the current I flowing from the current source circuit 46 of the triangular wave generation circuit 36 to the capacitor 50 decreases, and the capacitor 50 is charged slowly, so that the inclination of the triangular wave signal V3 decreases. Will increase moderately.

  Thereafter, the period T is reached at time t6, and the reset circuit 52 performs the reset operation of the capacitor 50. The triangular wave signal V3 in the next period gradually increases as the input voltage Vin decreases, and the period T has elapsed. Even at time t8, the output voltage control signal V4 is not reached, and therefore the second pulse width modulation signal V5 output from the comparison circuit 60 remains at the high level.

  In this case, the first pulse width modulation signal V1 from the digital pulse width modulation signal generation unit 44 input to the AND circuit 62 reaches the maximum on-time Ton (max) at time t7 and becomes high level. The output of the AND circuit 62 changes from the high level to the low level in synchronization with this.

  Therefore, after the input voltage Vin decreases at time t5, the drive signal V6 corresponding to the first pulse width modulation signal V1 from the digital pulse width modulation signal generation unit 44 is input to the switching element 18, and the switching element 18 is maximized. It will be controlled by on-duty.

  That is, the triangular wave signal V3 from the triangular wave generation circuit 36 and the output voltage control signal V4 from the output voltage control signal generation unit 38 are compared by the comparison circuit 60, whereby the switching element 18 is turned on / off in the second pulse width modulation signal V5. Even if a situation in which the control is impossible and the state is always on is generated, the switching element 18 is forcibly controlled by the maximum on-duty by the first pulse width modulation signal V1 from the digital pulse width modulation signal generator 44. Will be.

  For this reason, in the present embodiment, even when the input voltage Vin is low, there is no occurrence of a phenomenon that the switching element 18 cannot be turned off. Even if a digital processor is not used, the problem that the switching element breaks down can be prevented.

  Further, since the first pulse width modulation signal V1 is generated by the digital pulse width modulation signal generation unit 44 based on the clock count by the digital processor 34, the switching cycle and the pulse width can be accurately correlated, There is no variation in the on-duty limitation, and it is possible to set a wide on-duty of the switching element when the switching power supply device performs a normal operation, and a switching power supply device with high conversion efficiency can be made. .

  In the present invention, since the low-speed and low-cost digital processor 34 is used, the switching power supply device as a whole has a small number of parts, is free of failure, and has a high conversion efficiency at low cost. Can do.

  FIG. 5 is a time chart showing a soft start operation by the soft start / stop processing unit 42 provided in the digital processor 34 of FIG. 5A shows the first pulse width modulation signal V1, FIG. 5B shows the input signal of the comparison circuit 60, FIG. 5C shows the drive signal V6, and FIG. 5E shows the output voltage Vo. Show.

  The soft start process in the embodiment of FIG. 1 is realized by executing a program by the digital processor 34, and controls the output voltage Vo stepwise as shown in FIG. 5 (E) with the passage of time when the power is turned on. An output voltage rise process for increasing the target constant voltage is executed.

  In this soft start, as shown in FIG. 5A, the ON time in the first pulse width modulation signal V1 is increased at an increase rate α as indicated by Ton1, Ton2, Ton3,. increase. In the example of FIG. 5, the time t1 to t2 is the soft start period, and the time t2 and subsequent times indicate normal operation.

  The increase of the on-time Ton1, 2, 3,... In the first pulse width modulation signal V1 is the time when the register value N1 of the first register 74 provided in the digital pulse width modulation signal generator 44 shown in FIG. It can be realized by increasing in steps as the process progresses. At this time, the register value N2 of the second register 76 is a constant value corresponding to the period T.

  On the other hand, even during the soft start period, as shown in FIG. 5B, the comparison circuit 60 performs the second pulse width modulation signal V5 based on the comparison between the triangular wave signal V3 and the output voltage control signal V4 every period T. However, since the ON time of the first pulse width modulation signal V1 is shorter than the ON time of the second pulse width modulation signal V5 until the time t2 is reached, the AND circuit 62 performs the first pulse width modulation. The signal V1 is output as the drive signal V6, whereby the ON time of the switching element 18 increases stepwise and the output voltage increases stepwise.

  After time t2, the ON times Ton6 and Ton7 of the first pulse width modulation signal V1 become longer than the ON time of the second pulse width modulation signal V5 output from the comparison circuit 60, so the second pulse width modulation signal V5 is The AND circuit 62 outputs the drive signal V6. As a result, the normal operation in which the output voltage Vo is controlled to a constant voltage is performed.

  In FIG. 5, the on-time of the first pulse width modulation signal V1 is gradually increased to Ton6 and Ton7 after the time t2, but after the predetermined time, the first pulse width modulation signal V1 is increased. Reaches the maximum on-time Ton (max) required for normal operation, and thereafter maintains a constant value.

  In FIG. 5, the first pulse width modulation signal V1 is increased every cycle with respect to the switching cycle. However, in actual operation, the first pulse width modulation signal is generated once every several cycles. Control for increasing V1 may be performed.

  FIG. 6 is a time chart showing a soft start operation for controlling the increasing rate α of the on-duty according to the input voltage.

  The output voltage Vo when the switching power supply device of FIG. 1 performs an ideal operation follows the above equation (3). Therefore, if the on-duty of the switching element 18 is determined by the pulse width of the first pulse width modulation signal V1 output from the digital pulse width modulation signal generator 44, it is proportional to the input voltage Vin when the pulse width is the same. Output voltage increases. For this reason, in the soft start process shown in FIG. 5, the rising speed of the output voltage Vo at the time of soft start is influenced by the input voltage Vin due to the input voltage Vin.

  Therefore, as shown in the time chart of FIG. 6, when the input voltage Vin is low, the increase rate α of the ON time of the first pulse width modulation signal V1 in the soft start process output from the digital pulse width modulation signal generator 44 is increased. When the input voltage Vin is high, the increase rate α of the first pulse width modulation signal V1 on time is controlled to be small. Specifically, the control is performed so that the change rate α of the ON time of the first pulse width modulation signal V1 is inversely proportional to the input voltage Vin.

  In FIG. 6, the same input voltage Vin as in FIG. 5 is indicated by a solid line, and the case where the input voltage Vin is higher than that is indicated by a dotted line. That is, when the input voltage Vin is low, as shown by the solid line, the first pulse width modulation signal V1 in FIG. 6A increases the increase rate α so that the ON time is indicated by Ton1 to Ton7.

  On the other hand, when the input voltage Vin is high, the on-time is set so as to decrease the increase rate α as shown by Ton11 to Ton17 as shown by the broken line, and as shown in FIG. When the input voltage Vin is low, the on-duty is increased as shown by a solid line, and when the input voltage is high, the on-duty is reduced as shown by a broken line. As a result, even if the input voltage fluctuates, FIG. As shown in FIG. 4B, it is possible to realize a soft start that increases the output voltage Vo stepwise at the same rate.

  FIG. 7 is a flowchart showing control processing by the digital processor 34 of FIG. In FIG. 7, when the operation is started by turning on the switching power supply device of FIG. 1, first, in step S1, the digital processor 34 executes a soft start process by the soft start / stop processing unit 42, as shown in FIG. 5 or FIG. As described above, the output voltage rising process for increasing the output voltage at a constant rate over the soft start period is executed.

  When this soft start process is completed, a normal operation is performed in step S2. If it is determined in step S3 that the stop condition is satisfied during normal operation, the process proceeds to step S4, and a soft stop process is executed.

  In contrast to the soft start process, the soft stop process is a process of lowering the output voltage Vo by gradually reducing the ON time of the first pulse width modulation signal V1 with a constant decrease rate β as time passes. It becomes.

  In this soft stop process, in addition to the reverse soft stop process corresponding to the soft start not considering the input voltage Vin in FIG. 5, the soft start process corresponding to the soft start process considering the fluctuation of the input voltage Vin shown in FIG. Stop processing may be performed. That is, the soft stop process considering the input voltage Vin is a process of changing the on-time decrease rate β in the first pulse width modulation signal V1 to be inversely proportional to the input voltage.

  FIG. 8 is a flowchart showing details of the soft start process in step S1 of FIG. In FIG. 8, in step S11, the soft start process starts from the input voltage Vin to the on-duty of the first pulse width modulation signal V1, that is, a register for the first register 74 provided in the digital pulse width modulation signal generator 44 in FIG. An increase rate α of the value N1 is determined.

  Subsequently, in step S12, the first register 74 is set so that the register value N1 becomes α. Subsequently, in step S13, the second register 76 is set so that the register value N2 becomes a set value corresponding to the switching period T. Subsequently, in step S14, the operation of the digital pulse width modulation signal generator 44 is started. As a result, a pulse width modulation signal having an ON time corresponding to the register value N1 of the first pulse width modulation signal V1 in the first cycle is output.

  Subsequently, in step S15, other processing at the time of soft start, for example, processing of output current, temperature, remote on / off terminal, input voltage, communication function, etc., is executed, and wait processing is started in step S16.

  This wait process is a process for taking a timing so that a new register value N1 is updated in the first register 74 immediately after the counter 72 is reset. Specifically, in the other processes in step S15 Wait processing is performed so that the number of clocks plus the number of execution clocks for wait processing is an integral multiple of the register value N2 giving the period T.

  Subsequently, when it is determined in step S17 that the wait process is completed, the register value N1 is updated by an increase rate α in step S18 and transferred to the first register 74. In step S19, the register value N2 is a specified value, that is, the maximum on-time. The processing from step S15 is repeated until the value corresponding to Ton (max) is reached.

FIG. 9 is a flowchart showing details of the soft stop process in step S4 of FIG. In FIG. 9, the soft stop process determines an on-duty, that is, a decrease rate β of the register value N1 with respect to the first register 74 from the input voltage Vin in step S21.

  Subsequently, after performing other processes in the soft stop process in step S22, a wait process is performed to take a timing so that the first register 74 is changed immediately after the counter 72 is reset in step S23, and a wait process is performed in step S24. When the end of the process is determined, the register value N1 is decreased by the decrease rate β in step S25 and transferred to the first register 74. In step S26, the process from step S22 is performed until the register value N1 becomes equal to or less than the specified value. repeat.

  If it is determined in step S26 that the register value N1 has fallen below the specified value, the process proceeds to step S27 to stop the operation of the digital pulse width modulation signal generator, and in step S28, other stop processing is performed. A series of soft stop processing is completed.

  FIG. 10 is a circuit block diagram showing a second embodiment of the present invention using a triangular wave generating circuit for discharging and resetting the capacitor only during the low level period of the first pulse width modulation signal.

  In FIG. 10, in the switching power supply device of the second embodiment, the positive potential side of the capacitor 50 is connected to the output of the digital pulse width modulation signal generation unit 44 via the diode 84 as the reset circuit 52 provided in the triangular wave generation circuit 36. doing. As a result, the capacitor 50 is discharged and reset while the first pulse width modulation signal V1 is at a low level. Other circuit configurations and operations are the same as those of the first embodiment shown in FIG.

  FIG. 11 is a time chart showing signal waveforms of respective parts in the second embodiment of FIG. 11A is the input voltage Vin, FIG. 11B is the first pulse width modulation signal V1, FIG. 11C is the input signal of the comparison circuit 60, and FIG. 11D is the second pulse width modulation. The signal V5 and FIG. 11E show the drive signal V6.

  The reset circuit 52 of the triangular wave generation circuit 36 in FIG. 10 is at a low level for the remaining time after the on-time Ton (max) within the period T of the first pulse width modulation signal V1 elapses. Looking at the period T of t4, the triangular wave signal V3 input to the comparison circuit 60 is reset by the reset circuit 52 when the first pulse width modulation signal V1 falls from high level to low level at time t3. Is started, and the capacitor 50 continues to be reset during the period from time t4 until it rises to the high level in the next cycle, that is, from time t3 to t4.

  Here, at times t1 to t6, since the input voltage Vin is high, the triangular wave signal V3 reaches the output voltage control signal V4 within the on-time Ton (max) of the first pulse width modulation signal V1, and the second pulse width is reached. The modulation signal V5 is changed from the high level to the low level to determine the on-time Ton of the drive signal V6. The second pulse width modulation signal V5 is supplied from the AND circuit 62 to the switching element 18 as the drive signal V6. Thus, the switching element 18 is on / off controlled.

  On the other hand, the input voltage Vin changes to a low value at time t6, and when the reset of the capacitor 50 is started at time t8, the triangular wave signal V3 has not reached the output voltage control signal V4. The 1-pulse width modulation signal V1 is output to the switching element 18 as the drive signal V6, and the switching control of the switching element 18 is performed with the maximum on-duty.

  FIG. 12 is a circuit block diagram showing a third embodiment of the present invention, and the third embodiment is characterized in that the first pulse width modulation signal is configured to operate with reverse logic.

  In FIG. 12, a digital pulse width modulation signal generator 44 provided in the digital processor 34 outputs an inverted first pulse width modulation signal −V1 with the first pulse width modulation signal V1 generated in FIG. doing.

  Along with the inverted first pulse width modulation signal -V1, the reset circuit 52 provided in the triangular wave generating circuit 36 includes a capacitor 54, a resistor 86, and a PNP transistor 88 so as to have inverted logic. That is, the reset circuit 52 performs a differential operation when the inverted first pulse width modulation signal -V1 changes from a high level to a low level, and turns on the PNP transistor 88 for a short time to reset the capacitor 50 to discharge. ing.

  Further, the comparison circuit 60 provided in the drive circuit 40 inputs the triangular wave signal V3 from the triangular wave generation circuit 36 to the non-inverting input terminal contrary to the embodiment of FIG. The output voltage control signal V4 from the signal generator 38 is input to the inverting input terminal.

  The output of the comparison circuit 60 is input to the logical sum circuit (OR circuit) 90 together with the inverted first pulse width modulation signal −V1 instead of the logical product circuit of the embodiment of FIG. The output signal V7 of the OR circuit 90 is further inverted by the inverter circuit 92 and input to the switching element 18 as the drive signal V8. The logical sum circuit 90 and the inverter circuit 92 may be inverted logical sum circuits (NOR circuits).

  FIG. 13 is a block diagram showing the digital pulse width modulation signal generator 44 provided in the first embodiment of FIG. 13, the digital processor 34 is provided with a CPU 68 having a function of the soft start processing unit 42, a clock generation circuit 70, and a digital pulse width modulation signal generation unit 44, which are basically the same as those in the embodiment of FIG. It is.

  The difference is that the output from the RS flip-flop 82 provided in the output stage of the digital pulse width modulation signal generation unit 44 is output from -Q, which is an inverted output instead of the output Q, so that the inverted first pulse width modulated signal -V1.

  FIG. 14 is a time chart showing signal waveforms of respective parts in the third embodiment of FIG. 12, where FIG. 14A shows the input voltage Vin, FIG. 14B shows the inverted first pulse width modulation signal -V1, and FIG. 14 (C) shows the input signal of the PNP transistor 88, FIG. 14 (D) shows the input signal of the comparison circuit 60, FIG. 14 (E) shows the second pulse width modulation signal V5, and FIG. 14 (F) shows the OR circuit output signal. The drive signal V8 is shown in FIG.

  First, the inverted first pulse width modulation signal −V1 output from the digital pulse width modulation signal generator 44 is set to the low level during the maximum on-time Ton (max) in the period T as shown in FIG. The remaining period is at a high level, which is an inverted signal with respect to the first pulse width modulation signal V1 shown in FIG.

  The input signal of the PNP transistor 88 in FIG. 14C is a signal that is instantaneously changed from the high level to the low level in synchronization with the fall of the inverted first pulse width modulation signal -V1 from the high level to the low level. With this, the capacitor 50 is discharged and reset instantaneously.

  The operation of the comparison circuit 60 in FIG. 14D is performed as shown in the time t1 to t2 until the triangular wave signal V3 reaches the output voltage control signal V4 until the second pulse width modulation signal V5 that is output from the comparison circuit 60 is reached. Is at a low level. When the output voltage control signal V4 is reached at time t2, it rises to a high level, and at time t3 again becomes a low level with a reset operation.

  The logical sum circuit 40 takes out the logical sum of the inverted first pulse width modulation signal -V1 and the second pulse width modulation signal V5, and in this case, the logical sum circuit output signal corresponding to the second pulse width modulation signal V5. V7, which further drives the switching element 18 on and off as the drive signal V8 inverted by the inverter circuit 92.

  In FIG. 14, the input voltage Vin is high until time t5, but the input voltage Vin is reduced at time t5, and the increase rate in the triangular wave signal V3 is reduced. Therefore, in the period T from time t6 to t7, the triangular wave signal V3 does not reach the output voltage control signal V4 even if it reaches the period T at time t8.

  Accordingly, the second pulse width modulation signal V5 output from the comparison circuit 60 at this time continues in the low level state, and therefore the OR circuit 90 outputs the OR circuit output corresponding to the inverted first pulse width modulation signal −V1. The signal V7 is output and inverted by the inverter circuit 92, and the switching element 18 is turned on / off at the maximum on-duty as the drive signal V8.

  FIG. 15 shows a fourth embodiment of the present invention using a triangular wave generating circuit that discharges and resets a capacitor only during a high level period of an inverted first pulse width modulation signal for a switching power supply device using the same inverse logic as FIG. It is the circuit block diagram shown.

  In FIG. 15, the reset circuit 52 provided in the triangular wave generation circuit 36 includes a MOS-FET that is a reset switching element 94, and the drain and source of the MOS-FET that becomes the switching element 94 are connected to both ends of the capacitor 50. The inverted first pulse width modulation signal -V1 from the digital pulse width modulation signal generator 44 is input to the gate. Other circuit configurations and operations are the same as those of the fourth embodiment shown in FIG.

  FIG. 16 is a time chart showing signal waveforms of respective parts in the fourth embodiment of FIG. 15, FIG. 16A shows the input voltage Vin, FIG. 16B shows the inverted first pulse width modulation signal −V1, and FIG. 16 (C) shows the input signal of the comparison circuit 60, FIG. 16 (D) shows the second pulse width modulation signal V5, and FIG. 16 (E) shows the drive signal V8.

  In the fourth embodiment, the reset circuit 52 during the high level of the second half time t3 to t4 of the inverted first pulse width modulation signal −V1 in FIG. 16B, for example, in the period T from time t1 to t4. When the reset switching element 94 is turned on, the capacitor 50 is discharged and reset, and when the inverted first pulse width modulation signal -V1 changes from the high level to the low level at time t4, the generation of the triangular wave signal in the next cycle is started. ing.

  FIG. 16 shows the case where the input voltage Vin is high until time t6. During this period, the on / off control of the switching element 18 by the drive signal V8 synchronized with the second pulse width modulation signal V5 output from the comparison circuit 60 is performed. However, when the input voltage Vin decreases at time t6, at time t7 to t9, the switching element 18 is used as the drive signal V8 by the maximum on-time Ton (max) determined by the inverted first pulse width modulation signal −V1. Is controlled with a maximum on-duty.

  In the above embodiment, the soft start / stop processing unit 42 is provided as a function by program control in the digital processor, but without providing this function, the digital processor 34 generates a digital pulse width modulation signal. It is good also as a structure which provided only the part 44. FIG.

  As long as the digital pulse width modulation signal generator 44 has an equivalent function, in addition to the first register 74, the first comparison circuit 78, and the flip-flop 82, a plurality of registers, a plurality of comparison circuits, and a plurality of comparison circuits are provided. By providing a flip-flop, it is possible to use one that generates a plurality of digital pulse width modulation signals and to extract the output from one of them.

  The digital pulse width modulation signal generation unit 44 uses an up counter, but may use a down counter to realize a similar function.

  The current source circuit 46 may be configured using a semiconductor element instead of a resistor as long as it has an equivalent function.

  Although the input power supply voltage Vin is directly input to the current source circuit 46, a tertiary winding may be provided in the transformer 12 to input the voltage of the tertiary winding.

  The output voltage control signal generation circuit 38 compares the output voltage Vo with the voltage Vref of the reference voltage source 66 using the error amplifier 64 and outputs the output voltage control signal V4. The output voltage control signal V4 may be output under the control of the digital processor 34.

  The increase rate α and decrease rate β of the first pulse width modulation signal V1 are constant. For example, a table is provided in the program, and values are read out from the table as time elapses to change α and β. It may be.

  In addition, the above embodiment is an example of an isolated single-ended forward converter. However, an isolated converter may be applied to all circuits such as a bridge type, a push-pull type, and a flyback type. it can.

  In the above embodiment, electronic components such as MOS-FETs, PNP transistors, NPN transistors, diodes, and resistors are used as circuit elements. However, the elements are limited to these as long as the elements perform the same function. An appropriate electronic component can be used without any problem.

Further, the present invention includes modifications that do not impair the object and advantages thereof, and is not limited by the numerical values shown in the above embodiments.

The circuit block diagram which showed 1st Embodiment of the switching power supply device by this invention The block diagram which showed the detail of the digital processor provided in 1st Embodiment of FIG. Explanatory drawing which showed the signal generation operation using the counter by the digital pulse width modulation signal generation part of FIG. FIG. 1 is a time chart showing signal waveforms at various parts in the first embodiment of FIG. Time chart showing the soft start operation by the soft start processing unit of FIG. Time chart showing soft-start operation that controls on-duty increase rate according to input voltage The flowchart which showed the control processing by the digital processor of FIG. The flowchart which showed the detail of the soft start process by FIG.7 S2 The flowchart which showed the detail of the soft stop process by step S4 of FIG. The circuit block diagram which showed 2nd Embodiment of this invention using the triangular wave generation circuit which carries out discharge reset of a capacitor only during the low level period of the 1st pulse width modulation signal The time chart which showed the signal waveform of each part in 2nd Embodiment of FIG. The circuit block diagram which showed 3rd Embodiment of this invention which operate | moves by the reverse logic using an inversion 1st pulse width modulation signal The block diagram which showed the detail of the digital processor provided in 3rd Embodiment of FIG. The time chart which showed the signal waveform of each part in 3rd Embodiment of FIG. The circuit block diagram which showed 4th Embodiment of this invention which operate | moves by reverse logic using the triangular wave generation circuit which carries out discharge reset of a capacitor only during the high level period of the 1st pulse width modulation signal The time chart which showed the signal waveform of each part in 4th Embodiment of FIG. Circuit block diagram showing a conventional switching power supply Time chart showing signal waveforms of each part in the conventional device divided into cases where the input voltage is low and high Time chart showing the signal waveform of each part in the conventional device when the input voltage drops in the middle Circuit block diagram showing a conventional device with a maximum on-duty limit circuit

Explanation of symbols

10: input power supply 12: transformer 14: primary winding 16: secondary winding 18: switching element 20: rectifying / smoothing circuits 22a, 22b: output terminal 24: switching control circuit 25: forward side synchronous rectifying element 26: flywheel Side synchronous rectification element 28: synchronous rectification control circuit 30: choke coil 32: smoothing capacitor 34: digital processor 36: triangular wave generation circuit 38: output voltage control signal generation circuit 40: drive circuit 42: soft start / stop processing unit 44: digital Pulse width modulation signal generator 46: current source circuit 48: resistor 50: capacitor 52: reset circuit 58: NPN transistor 60: comparison circuit 62: AND circuit 64: error amplifier 66: reference voltage source 68: CPU
70: Clock generation circuit 72: Counter 74: First register 76: Second register 84: Diode 88: PNP transistor 90: OR circuit 92: Inverter

Claims (15)

A primary winding and a switching element of the transformer are connected in series to the input power source, a rectifying and smoothing circuit is connected to the secondary winding of the transformer, a switching control circuit is connected to the switching element, and the switching control circuit is In the switching power supply device that controls the output voltage to a predetermined voltage by controlling the on-duty of the switching element,
The switching control circuit includes:
A digital pulse width modulation signal generating unit that is provided in the digital processor and generates a first pulse width modulation signal having a predetermined period and a predetermined maximum on-duty;
A triangular wave generating circuit that changes a slope according to an input voltage and repeatedly generates a triangular wave signal in synchronization with the first pulse width modulation signal;
An output voltage control signal generating circuit for generating an output voltage control signal for controlling the output voltage to a predetermined voltage;
A comparison circuit that inputs the triangular wave signal and the output voltage control signal and generates a second pulse width modulation signal having an on-duty according to the output voltage control signal;
When the first pulse width modulation signal and the second pulse width modulation signal are input, and the on-duty of the second pulse width modulation signal is less than the maximum on-duty set by the first pulse width modulation signal, the first When a two-pulse width modulation signal is output as a drive signal to the switching element, and the on-duty of the second pulse-width modulation signal is greater than or equal to the maximum on-duty set by the first pulse-width modulation signal, the first pulse width A logic circuit for outputting a modulation signal as a drive signal to the switching element;
Equipped with a,
The digital pulse width modulation signal generator is
A counter for counting clock signals;
A first register for setting a first clock number N1 corresponding to the maximum on-duty;
A second register for setting a second clock number N2 corresponding to a predetermined period;
A first comparison circuit that outputs when the count clock number of the counter reaches the first clock number N1,
A second comparison circuit that outputs when the count clock number of the counter reaches the second clock number N2,
A flip-flop that is reset at the output of the first comparison circuit, is set at the output of the second comparison circuit, and outputs the first pulse width modulation signal having the maximum on-duty;
A function of resetting and starting the counter by an output of the second comparison circuit;
A switching power supply device comprising: The switching power supply device according to claim 1, wherein the triangular wave generation circuit includes:
A current source circuit that outputs a current proportional to the input voltage;
A capacitor that is charged by the current source circuit to generate a triangular wave voltage;
A reset circuit that operates for a short time at a timing when the first pulse width modulation signal changes from a low level to a high level to discharge-reset the capacitor;
A switching power supply device comprising: The switching power supply device according to claim 2 , wherein the reset circuit includes:
A differentiating circuit for generating a differential pulse signal in synchronization with a rise from a low level to a high level of the first pulse width modulation signal;
A reset switching element that is turned on by the differential pulse signal to reset the capacitor discharge;
A switching power supply device comprising: The switching power supply device according to claim 1, wherein the triangular wave generation circuit includes:
A current source circuit that outputs a current proportional to the input voltage;
A capacitor that is charged by the current source circuit to generate a triangular wave voltage;
A reset circuit that operates only during a low level period of the first pulse width modulation signal to discharge-reset the capacitor;
A switching power supply device comprising: 5. The switching power supply device according to claim 4 , wherein the reset circuit has an anode connected to a positive potential side of the capacitor and a cathode connected to an output terminal of the digital processor that outputs the first pulse width modulation signal. A switching power supply comprising a diode.   2. The switching power supply device according to claim 1, wherein the logic circuit is an AND circuit to which the first pulse width modulation signal and the second pulse width modulation signal are input. In the switching power supply device according to claim 1,
The digital pulse width modulation signal generator outputs an inverted first pulse width modulation signal obtained by inverting the first pulse width modulation signal;
The triangular wave generating circuit is
A current source circuit that outputs a current proportional to the input voltage;
A capacitor that is charged by the current source circuit to generate a triangular wave voltage;
A reset circuit that operates for a short time from the timing when the inverted first pulse width modulation signal changes from a high level to a low level to discharge-reset the capacitor;
A switching power supply device comprising: The switching power supply device according to claim 7 , wherein the reset circuit includes:
A differentiating circuit for generating a differential pulse signal in synchronization with a fall from the high level to the low level of the inverted first pulse width modulation signal;
A reset switching element that is turned on by the differential pulse signal to reset the capacitor discharge;
A switching power supply device comprising: In the switching power supply device according to claim 1,
The digital pulse width modulation signal generator outputs an inverted first pulse width modulation signal obtained by inverting the first pulse width modulation signal;
The triangular wave generating circuit is
A current source circuit that outputs a current proportional to the input voltage;
A capacitor that is charged by the current source circuit to generate a triangular wave voltage;
A reset circuit that operates only during a high level period of the inverted first pulse width modulation signal to discharge-reset the capacitor;
A switching power supply device comprising: 10. The switching power supply device according to claim 9 , wherein the reset circuit includes a reset switching element that is turned on during a high level period of the inverted first pulse width modulation signal to discharge and reset the capacitor. Switching power supply device. In the switching power supply device according to claim 7 or 9 ,
The logic circuit is:
An OR circuit that receives the inverted first pulse width modulation signal and the second pulse width modulation signal;
An inverter circuit that inverts the output of the OR circuit and outputs a drive signal to the switching element;
A switching power supply device comprising: In the switching power supply device according to claim 1 or 4, wherein said digital processor, the execution of the program,
A soft-start processing unit that changes the on-duty of the first pulse width modulation signal at a predetermined increase rate based on a program to increase the output voltage toward a predetermined voltage when the switching power supply device is activated;
A soft stop processing unit that changes the on-duty of the first pulse width modulation signal at a predetermined decrease rate based on a program with respect to the passage of time to lower the output voltage from the predetermined voltage when the switching power supply device is stopped;
A switching power supply device that realizes the function as: The switching power supply device according to claim 7 or 9 , wherein the digital processor is configured by executing a program.
A soft start processing unit for changing the off-duty of the inverted first pulse width modulation signal at a predetermined increase rate based on a program over time to increase the output voltage toward a predetermined voltage when the switching power supply device is started up ,
A soft-stop processing unit that changes the off-duty of the inverted first pulse width modulation signal at a predetermined reduction rate based on a program over time to decrease the output voltage from the predetermined voltage when the switching power supply is stopped;
A switching power supply device that realizes the function as: In the switching power supply device according to claim 12 or 13 ,
The soft start processing unit changes an increasing rate of an on-duty of the first pulse width modulation signal or an increasing rate of an off-duty of the inverted first pulse width modulation signal so as to be inversely proportional to the magnitude of an input voltage. By doing so, the time until the output voltage rises to the predetermined voltage is processed so as not to be affected by the input voltage,
The soft stop processing unit changes the decreasing rate of the on-duty of the first pulse width modulation signal or the decreasing rate of the off-duty of the inverted first pulse width modulation signal so as to be inversely proportional to the magnitude of the input voltage. Thus, the switching power supply device is characterized in that the time until the output voltage drops to a predetermined voltage is not affected by the input voltage. 2. The switching power supply device according to claim 1, wherein the output voltage control signal generation circuit generates an output voltage control signal by amplifying an error voltage between the output voltage signal and a predetermined reference voltage signal. Switching power supply.

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