JP6529128B2 - Reference voltage generating circuit and switching power supply - Google Patents

Description

  The present invention relates to a reference voltage generation circuit and a switching power supply device that enable control of changing a reference voltage by a digital processor or the like.

  Conventionally, a switching power supply device capable of obtaining a DC output voltage by converting an input voltage into an intermittent voltage by turning on and off a switching element, and rectifying and smoothing this is widely used.

  The switching power supply device generally includes a feedback control circuit for controlling the output voltage to a stable constant voltage. In addition, the feedback control circuit is provided with a reference voltage generation circuit in order to set the output voltage of the switching power supply device to a predetermined value.

  There is known a switching power supply device in which a reference voltage generation circuit is configured by a DA converter (Patent Document 1). The reference voltage generation circuit configured by the DA converter can control the output voltage of the switching power supply with high accuracy by controlling the DA converter by the digital processor. For example, by performing control of the soft start operation of the switching power supply using a DA converter and a digital processor, overshoot at the time of starting the switching power supply is suppressed.

  When a DA converter is used as a reference voltage generation circuit of a switching power supply, the practicability of the switching power supply is reduced unless the resolution of the DA converter is sufficiently high. For example, it is assumed that an 8-bit DA converter is used for the reference voltage generation circuit of the switching power supply that outputs 5 V. Since the resolution of the 8-bit DA converter is 256, the voltage setting of the DA converter is 5 V コ ン バ ー タ 256 = 19.5 mV units, and the switching power supply device can only set the output voltage discretely.

  In this case, it is difficult to use as a switching power supply device for a semiconductor device such as a digital signal processor (DSP) or a field programmable gate array (FPGA) that requires high-precision voltage setting.

  In order to obtain practical output voltage setting accuracy as a switching power supply, at least 12 bits (resolution 4096, 1.22 mV units for 5V output switching power supply) in the reference voltage generation circuit, 14 bits if possible It is necessary to use a D / A converter with a resolution of 16,035 mV in the case of a switching power supply having a resolution of 16,384 and 5 V output.

  By the way, since the high resolution DA converter is expensive, the reference voltage generation circuit using it becomes expensive, and the switching power supply device also becomes expensive.

(Digital PWM circuit)
As a method of controlling the reference voltage generating circuit of the switching power supply by a digital processor,
A method using a pulse width modulation circuit (hereinafter referred to as "digital PWM circuit") controllable by a digital processor is known (Patent Document 2). In this method, a reference voltage generation circuit is configured using a digital PWM circuit, a resistor, and a capacitor, and a DC voltage obtained by smoothing the output of the digital PWM circuit with the resistor and the capacitor is used as a reference voltage.

  The digital PWM circuit is generally built in a digital processor such as a commercially available one-chip microcomputer, and may be called a timer in the microcomputer. Since the digital PWM circuit is also incorporated in an inexpensive microcomputer, the reference voltage generating circuit can be configured inexpensively.

  However, when the output voltage setting accuracy of the switching power supply device is enhanced by the reference voltage generation circuit using the digital PWM circuit, it has a disadvantage that it can not be used for applications where the output voltage of the switching power supply device is changed at high speed. The reason will be described below.

(Operation of digital PWM circuit)
FIG. 8 is a circuit block diagram showing a digital PWM circuit and a conventional reference voltage generating circuit using the same. As shown in FIG. 8, the digital PWM circuit 100 includes a counter circuit 104, a first comparison circuit 106, a second comparison circuit 108, and an RS-flip flop circuit 110.

  The clock oscillation circuit 102 is a circuit that outputs a clock signal E1 in which H level and L level are repeated in a fixed cycle Tck. When the digital PWM circuit 100 is built in a microcomputer, a clock oscillation circuit for supplying a clock signal to the CPU and a clock oscillation circuit for supplying a clock signal to the digital PWM circuit are often used in common.

  The counter circuit 104 counts the clock signal E1 output from the clock oscillation circuit 102, and outputs a count value N to the first comparison circuit 106 and the second comparison circuit 108. When the reset signal E2 is input, the count value N is reset to zero.

  The first comparison circuit 106 has a first set value S1 that can be set externally, and at the timing when the count value N output from the counter circuit 104 becomes equal to the first set value S1 and the next clock signal E1 is input. The reset signal E2 is output.

  The second comparison circuit 108 has a second set value S2 that can be set from the outside, and outputs the output inverted signal E3 at the timing when the count value N output from the counter circuit 104 becomes equal to the second set value S2.

  When the reset signal E2 output from the first comparison circuit 106 is input to the RS-flip flop circuit 110, the output QB is maintained at H level and the output Q is maintained at L level, and the second comparison circuit 108 outputs When the output inverted signal E3 is input, the output QB is L level and the output Q is H level, and this is maintained, and a rectangular wave signal (PWM signal) E4 is output from the output QB.

  With such a configuration, assuming that the clock cycle of the clock signal E1 is Tck, the digital PWM circuit 100 outputs a square wave signal E4 having a duty of S2 / (S1 + 1) in a cycle of Tck × (S1 + 1). can do.

  FIG. 9 is a time chart showing the operation of the digital PWM circuit of FIG. 8, taking as an example the case where the clock cycle Tck = 100 nS, the first set value S1 = 3999, and the second set value S2 = 1600. 9A shows the clock signal E1, FIG. 9B shows the count value N of the counter circuit, FIG. 9C shows the reset signal E2, and FIG. 9D shows the output inversion. A signal E3 is shown, and FIG. 9E shows a rectangular wave signal E4.

(Operation of period A)
Period A in FIG. 9 is a period from when the count value N of the counter circuit 104 reaches 0 to the second set value S2. Here, in the RS-flip flop circuit 110, the output QB is H level and the output Q is L level.

  In the counter circuit 104, the count value N is increased by 1 at the timing when the clock signal E1 changes from L level to H level. At the moment when the count value N reaches the second set value S2 = 1600, the second comparison circuit 108 outputs the output inverted signal E3 to the set terminal S of the RS flip-flop circuit 110. At this time, the output QB of the RS-flip flop circuit 110 is L level and the output Q is H level.

(Operation of period B)
A period B is a period from immediately before the count value N of the counter circuit 104 reaches (S1 + 1) where 0 is added to the first set value S1.

  In the counter circuit 104, the count value N is increased by 1 at the timing when the clock signal E1 changes from L level to H level. When the count value N becomes equal to the first set value S1 and the next clock signal is input, the first comparison circuit 106 outputs the reset signal E2 and resets the counter circuit 104. That is, by outputting the reset signal E2 at the timing when the count value N becomes (S1 + 1) = 4000, the count value N is reset to 0.

At this time, since the reset signal E2 is also output to the reset terminal R of the RS-flip flop circuit 110, the output QB of the RS-flip flop circuit 110 changes from the L level to the H level. Therefore, the rectangular wave signal E4 output from the digital PWM circuit 100 is
100 nS × (3999 + 1) = 400 μS
Will have a period of

As described above, the digital PWM circuit 100 outputs the rectangular wave signal E4 having the duty duty of (period A) / (period B) and the period Tpwm of the period B. Since the period A is (Tck × S2) and the period B is {Tck × (S1 + 1)}, the period Tpwm of the digital PWM circuit 100 and the duty duty are expressed by the following equations.
Tpmw = Tck × (S1 + 1) (1)
duty = S2 / (S1 + 1) (2)
For example, a rectangular wave signal E4 having a period of 400 μS and a duty of 0.4 is output from the digital PWM circuit 100 of FIG. 8 which is the operation shown in FIG.

  The first set value S1 of the first comparison circuit 106 and the second set value S2 of the second comparison circuit 108 can be externally changed by using a digital processor or the like. The duty and cycle can be set freely.

(Operation of reference voltage generation circuit using digital PWM circuit)
The reference voltage generation circuit using the digital PWM circuit 100 uses a voltage obtained by smoothing the rectangular wave signal E4 output from the digital PWM circuit 100 using the resistor 112 and the capacitor 114 as the reference voltage Vref. The reference voltage Vref is determined by the H-level output voltage of the digital PWM circuit 100, the L-level output voltage, and the duty of the digital PWM circuit 100.

For example, assuming that the H-level output voltage of digital PWM circuit 100 is VH, the L-level output voltage is VL, and the duty of digital PWM circuit 100 is duty, reference voltage Vref can be expressed by the following equation.
Vref = (VH−VL) × duty + VL (3)
For example, assuming that VH = 5 V, VL = 0 V, S1 = 3999, and S2 = 1600 in FIGS. 8 and 9, since duty = 0.4, the reference voltage generation circuit of FIG. 8 generates 2 V as the reference voltage Vref. Output.

(resolution)
The voltage resolution of the reference voltage Vref output by the reference voltage generation circuit using the digital PWM circuit 100 is determined by the duty resolution of the digital PWM circuit 100. The digital PWM circuit 100 generates the cycle Tpmw and the duty duty by counting the clock signal E1. When the second set value S2 is set to 0, the duty duty becomes 0 and the set value S2 is (S1 + 1). The duty is 1 when it is set to.

Therefore, the duty resolution of the digital PWM circuit 100 is determined by the first set value S1, and the minimum change width Vstep which becomes the voltage resolution of the reference voltage Vref is determined by the following equation.
Vstep = (VH−VL) / (S1 + 1) (4)
For example, in FIG. 8 and FIG. 9, when VH = 5 V, VL = 0 V, and S1 = 3999, the minimum change width Vstep as the voltage resolution of the reference voltage Vref in FIG. 8 is 1.25 mV.

  As described above, in the reference voltage generation circuit using the digital PWM circuit 100, in order to improve the voltage resolution of the reference voltage Vref, it is necessary to increase the first set value S1 of the first comparison circuit 106.

(Ripple voltage)
The reference voltage generation circuit using the digital PWM circuit 100 smoothes the rectangular wave signal E4 that is the output of the digital PWM circuit 100 to generate the reference voltage Vref, so the resistance value R0 of the resistor 112, the capacitance C0 of the capacitor 114, and The ripple voltage Vrip determined by the value of the cycle Tpwm of the rectangular wave signal E4 is superimposed. In the case of a switching power supply that controls the output voltage Vo based on the reference voltage Vref, when the ripple voltage is superimposed on the reference voltage Vref, the ripple voltage is also superimposed on the output voltage Vo.

  For example, consider a switching power supply in which the output voltage Vo = 12 V when the reference voltage Vref = 2 V. Since the control is performed so that the output voltage Vo is six times the reference voltage Vref, the ripple voltage of the output voltage Vo is six times the ripple voltage Vrip of the reference voltage Vref.

  In a general switching power supply, the ripple voltage of the output voltage Vo is designed to be about 0.2% of the output voltage, but the smaller the better, the better. For example, the ripple voltage of the switching power supply that outputs 12 V is 24 mV. In the switching power supply in which the output voltage Vo = 12 V when the reference voltage Vref = 2 V, when the ripple voltage of the output voltage is 24 mV or less, the ripple voltage Vrip of the reference voltage Vref needs to be 4 mV or less. Then, the ripple voltage Vrip superimposed on the reference voltage Vref is obtained as follows.

The output voltage when the digital PWM circuit 100 is at H level is VH, and the output voltage at L level is 0 V. The following description will be made. Further, the resistance value of the resistor 112 is R0, and the capacitance of the capacitor 114 is C0. When the output of digital PWM circuit 100 is at H level, current Ir0 flowing through resistor 112 is expressed by the following equation.
Ir0 = (VH−Vref) / R0 (5)

The current Ir 0 flowing through the resistor 112 is a current flowing into the capacitor 114. The time during which the digital PWM circuit 100 is outputting the H level is the product of the period Tpwm of the digital PWM circuit 100 and the duty duty. Therefore, the capacitor 114
Time T = Tpwm × duty
In the meantime, the current Ir0 flows in. The voltage fluctuation ΔVc0 of the capacitor 114 during this time becomes the ripple voltage Vrip of the digital PWM circuit 100.

For example, in FIG. 8 and FIG. 9, since VH = 5 V, Vref = 2 V, Tpwm = 400 μS, and duty = 0.4, the condition of Vrip ≦ 4 mV is expressed by the following equation.
C0 · R0 ≧ {(VH−Vref) · Tpwm · duty} / 4 mV
= 0.12 (7)
For example, if C0 = 10 μF and R0 = 12 kΩ, Vrip = 4 mV is obtained.

  From the above, when attempting to reduce the ripple voltage, it is necessary to increase the capacitance C0 of the capacitor 114 and the resistance value R0 of the resistor 112.

  Further, as another method for reducing the ripple voltage, there is a method of shortening the period Tpwm of the digital PWM circuit 100 to increase the frequency from Equation (6).

(Reference voltage change time)
In the reference voltage generation circuit using the digital PWM circuit 100, when changing the reference voltage Vref, the duty of the rectangular wave signal E4 output from the digital PWM circuit 100 is changed. For example, in FIG. 8, by changing the second set value S2 of the second comparison circuit 108, the duty of the rectangular wave signal is changed to change the reference voltage Vref.

  When changing the reference voltage Vref from the voltage Vref1 to the voltage Vref2, consider the time required for the change. The reference voltage generation circuit using the digital PWM circuit 100 internally includes the smoothing circuit using the resistor 112 and the capacitor 114. Therefore, by calculating the time constant τ of the smoothing circuit, the reference voltage Vref can be calculated as the voltage Vref1. The time to change to the voltage Vref2 can be obtained from

Generally, the time constant τ can be obtained by τ = RC. Therefore, when time τ determined by the product of the capacitance C0 of the capacitor 114 and the resistance value R0 of the resistor 112 elapses after changing the duty of the digital PWM circuit 100, the reference voltage Vref becomes
Vref = (Vref2-Vref1) × 0.632 + Vref1
It has become.

  For example, in the reference voltage generation circuit using the digital PWM circuit 100 of FIGS. 8 and 9, when the second set value S2 is 1600, the reference voltage Vref is 2 V, but when the second set value S2 is changed to 2000 digital The duty of the PWM circuit 100 is 0.5, and the reference voltage Vref changes toward 2.5 V, and after 0.12 sec (= 10 μF × 12 kΩ), 2.316 V (= (2.5 V−2 V) × 0 .632 + 2V).

JP, 2010-028951, A JP, 2014-128110, A

  As described above, the method of using the DA converter as the reference voltage generation circuit for controlling the output voltage of the switching power supply device requires an expensive DA converter since the reference voltage generation circuit is required to have high resolution. There is a problem that the reference voltage generating circuit becomes expensive.

  As a method of solving this problem, as described above, the reference of the switching power supply is a voltage obtained by smoothing the rectangular wave signal output from the digital PWM circuit using a resistor and a capacitor, which can set the cycle and duty externally. Although there is a method of using a voltage, this method smoothes a rectangular wave signal with a resistor and a capacitor, so a ripple voltage is superimposed on the reference voltage, and the ripple voltage of the reference voltage becomes the ripple voltage of the output voltage. I will.

  In general, it is better for switching power supply devices that the smaller the ripple voltage of the output voltage, and the shorter the time required to change the set value of the output voltage, the better. However, to reduce the ripple voltage of the reference voltage It is conceivable to increase the frequency of the signal, and if the frequency is to be increased, a digital PWM circuit using a high-speed clock is required, which causes a problem that the reference voltage generating circuit becomes expensive.

  In addition, it is necessary to increase the product of the capacitor and the resistor in order to reduce the ripple voltage. However, to reduce the time required to change the output voltage setting of the switching power supply, the product of the capacitor and the resistor should be used. Need to be small, can not meet both.

  Therefore, in the reference voltage generation circuit using the conventional digital PWM circuit, there is a problem that the elements of resolution, ripple voltage and setting change time can not be realized at low cost.

  The present invention provides a reference voltage generation circuit and a switching power supply using a digital PWM circuit that can achieve both high resolution output voltage setting, reduction of output voltage ripple voltage, and short setting voltage change time at low cost. The purpose is to

(Reference voltage generation circuit : Relationship of output resistance of two pulse width modulation circuits )
The present invention relates to a reference voltage generating circuit,
A plurality of pulse width modulation circuits that output a rectangular wave signal whose cycle and duty can be set externally;
A plurality of resistors connected at one end to each of the outputs of the plurality of pulse width modulation circuits,
A capacitor with the other ends of multiple resistors connected in common ,
A configuration in which the voltage generated at the connection point between multiple resistors and capacitors is taken as a reference voltage ,
Equipped with
When the plurality of pulse width modulation circuits are divided into groups of two in order so as to overlap each other, and the first pulse width modulation circuit and the second pulse width modulation circuit are arranged in order within each group, the first pulse width modulation The resistance value (R _{i +1} ) of the second resistor connected to the second pulse width modulation circuit with respect to the resistance value (R _i ) of the first resistor connected to the circuit is the rectangular wave signal output from the plurality of pulse width modulation circuits. It is characterized in that the reference voltage is adjusted by a combination of voltage changes and set to a sufficiently large value to reduce the ripple voltage of the reference voltage .

( Reference voltage generation circuit: Set the output resistance ratio of two pulse width modulation circuits based on duty resolution)
The present invention relates to a reference voltage generating circuit,
A plurality of pulse width modulation circuits that are three or more circuits that output a rectangular wave signal whose cycle and duty can be set externally;
A plurality of resistors connected at one end to each of the outputs of the plurality of pulse width modulation circuits,
A capacitor with the other ends of multiple resistors connected in common,
A configuration in which a voltage generated at a connection point between the plurality of resistors and the capacitor is taken as a reference voltage,
Equipped with
The plurality of pulse width modulation circuits have a predetermined duty resolution and
When the plurality of pulse width modulation circuits are divided into groups of two in order so as to overlap each other, and the first pulse width modulation circuit and the second pulse width modulation circuit are arranged in order within each group, the first pulse width modulation The ratio (R _{i + 1} / R _i ) of the resistance value (R _i ) of the first resistor connected to the circuit to the resistance value (R _{i + 1} ) of the second resistor connected to the second pulse width modulation circuit is the first pulse width The first pulse in a range in which the reference voltage is adjusted to a minute voltage unit corresponding to a value obtained by multiplying the duty resolution of the modulation circuit and the duty resolution of the second pulse width modulation circuit to reduce the ripple voltage of the reference voltage. It is characterized in that resistance values of the first resistor and the second resistor are set to be substantially equal to the duty resolution of the width modulation circuit.

(Details of pulse width modulation circuit and duty resolution)
The pulse width modulation circuit includes a counter circuit, a first comparison circuit, a second comparison circuit, and an output inverting circuit.
The counter circuit counts an externally supplied clock signal to output a count value, and is reset by a reset signal output from the first comparison circuit.
The first comparison circuit compares the count value of the counter circuit with a predetermined first set value set from the outside, and outputs a reset signal when the count value matches the first set value.
The second comparison circuit compares the count value of the counter circuit with a second set value set from the outside below the first set value and outputs an output inverted signal when the count value matches the second set value.
The output inverting circuit raises the output from L level to H level when the reset signal is obtained, and inverts the output from H level to L level when the output inverted signal is obtained, and outputs a rectangular wave signal. .

(Switching power supply : relationship of output resistance of two pulse width modulation circuits )
The present invention
A power conversion unit, a switching element drive circuit, and a reference voltage generation circuit;
The power conversion unit converts an input voltage supplied by the input power supply into an intermittent voltage by turning on and off the switching element, and rectifying and smoothing the intermittent voltage to generate a DC voltage,
In the switching power supply device, the switching element drive circuit controls the on-duty of the switching element in response to the reference voltage from the reference voltage generation circuit,
The reference voltage generator is
A plurality of pulse width modulation circuits that output a rectangular wave signal whose cycle and duty can be set externally;
A plurality of resistors connected at one end to each of the outputs of the plurality of pulse width modulation circuits,
A capacitor with the other ends of multiple resistors connected in common ,
A configuration in which the voltage generated at the connection point between multiple resistors and capacitors is taken as a reference voltage ,
Equipped with
When the plurality of pulse width modulation circuits are divided into groups of two in order so as to overlap each other, and the first pulse width modulation circuit and the second pulse width modulation circuit are arranged in order within each group, the first pulse width modulation The resistance value (R _{i +1} ) of the second resistor connected to the second pulse width modulation circuit with respect to the resistance value (R _i ) of the first resistor connected to the circuit is the rectangular wave signal output from the plurality of pulse width modulation circuits. It is characterized in that the reference voltage is adjusted by a combination of voltage changes and set to a sufficiently large value to reduce the ripple voltage of the reference voltage .

( Switching power supply: Output resistance ratio of 2 pulse width modulation circuits is set based on duty resolution)
The present invention
A power conversion unit, a switching element drive circuit, and a reference voltage generation circuit;
The power conversion unit converts an input voltage supplied by the input power supply into an intermittent voltage by turning on and off the switching element, and rectifying and smoothing the intermittent voltage to generate a DC voltage,
In the switching power supply device, the switching element drive circuit controls the on-duty of the switching element in response to the reference voltage from the reference voltage generation circuit ,
The reference voltage generator is
A plurality of pulse width modulation circuits that output a rectangular wave signal whose cycle and duty can be set externally;
A plurality of resistors connected at one end to each of the outputs of the plurality of pulse width modulation circuits,
A capacitor with the other ends of multiple resistors connected in common,
A configuration in which the voltage generated at the connection point between multiple resistors and capacitors is taken as a reference voltage,
Equipped with
The plurality of pulse width modulation circuits have a predetermined duty resolution and
When the plurality of pulse width modulation circuits are divided into groups of two in order so as to overlap each other, and the first pulse width modulation circuit and the second pulse width modulation circuit are arranged in order within each group, the first pulse width modulation the first resistance of the resistance value connected to a circuit _{(R i)} and the second resistor resistance value connected to the second pulse width modulation circuit ratio of the resistance values of _{(R i + 1) (R} i + 1 / R i) is, first The reference voltage is adjusted to a minute voltage unit corresponding to the resolution obtained by multiplying the duty resolution of the pulse width modulation circuit and the duty resolution of the second pulse width modulation circuit to reduce the ripple voltage of the reference voltage, so as to be substantially equal to the duty resolution of the first pulse width modulation circuit, wherein the resistance value of the first resistor and the second resistor is set.

(Details of pulse width modulation circuit and duty resolution)
The pulse width modulation circuit provided in the switching power supply device includes a counter circuit, a first comparison circuit, a second comparison circuit, and an output inverting circuit.
The counter circuit counts an externally supplied clock signal to output a count value, and is reset by a reset signal output from the first comparison circuit.
The first comparison circuit compares the count value of the counter circuit with a predetermined first set value set from the outside, and outputs a reset signal when the count value matches the first set value.
The second comparison circuit compares the count value of the counter circuit with a second set value set from the outside below the first set value and outputs an output inverted signal when the count value matches the second set value.
The output inverting circuit inverts the output when the reset signal is obtained, and inverts the output when the output inverted signal is obtained, and outputs a rectangular wave signal.

(Basic effect of reference voltage generation circuit)
According to the present invention, in the reference voltage generation circuit, one end is connected to each of a plurality of pulse width modulation circuits that output a rectangular wave signal whose cycle and duty can be set from the outside, and each of the plurality of pulse width modulation circuits. A low-speed pulse width modulation circuit is provided with a configuration in which a plurality of resistors and a capacitor in which the other ends of the plurality of resistors are connected in common and the voltage generated at the connection point between the plurality of resistors and the capacitor is extracted as a reference voltage Even if a digital PWM circuit operating with a clock is used with a low duty resolution, the resolution of the reference voltage can be increased, so a rectangular wave can be used without using an expensive digital PWM circuit operating with a high-speed clock. The period of the signal can be shortened, and the duty resolution of the digital PWM circuit is set low, so the period of the rectangular wave signal can be reduced. Since it can be shortened, the ripple voltage of the reference voltage does not increase even when the time constant of the resistor and capacitor connected to the output of the digital PWM circuit is reduced in order to shorten the set voltage change time of the reference voltage. The output voltage setting of resolution, the reduction of the ripple voltage of the output voltage, and the short setting voltage change time can be compatible at low cost.

(Effect due to the relationship between the output resistances of two pulse width modulation circuits)
In addition, when a plurality of pulse width modulation circuits are divided into groups of two circuits in order so as to overlap each other, and the first pulse width modulation circuit and the second pulse width modulation circuit are arranged in order within each group, the first pulse Since the resistance value (R _{i + 1} ) of the second resistor connected to the second pulse width modulation circuit is set to a sufficiently large value with respect to the resistance value (R _i ) of the first resistor connected to the width modulation circuit, the reference For the voltage, the voltage change due to the rectangular wave signal from the first comparison circuit is directly reflected on the voltage change of the reference voltage, thereby acting as a rough adjustment, and the voltage change due to the rectangular wave signal from the first comparison circuit is It works as a fine adjustment by being reflected in the reference voltage as a small voltage change based on the magnitude relationship between the first resistor and the second resistor, and by combining the two, high resolution output voltage setting, reduction of ripple voltage of output voltage, setting voltage Change time The short and compatible with low cost.

(Effect of setting the output resistance ratio of two pulse width modulation circuits based on duty resolution)
Also, the plurality of pulse width modulation circuits have predetermined duty resolution, and the plurality of pulse width modulation circuits are divided into groups of two circuits in order so as to overlap each other, and the first pulse width modulation is arranged in the order in each group If the circuit and the second pulse width modulation circuit, the first resistor resistance value connected to the first pulse width modulation circuit (R _i) and the second resistor resistance value connected to the second pulse width modulation circuit (R _i The resistances of the first resistor and the second resistor are set such that the ratio (R _{i + 1} / R _i ) of ₊₁ ) is approximately equal to the duty resolution of the first pulse width modulation circuit. By setting the ratio of the second resistance approximately equal to the duty resolution of the first pulse width modulation circuit, the digital processor etc. controls the cycle, duty resolution and duty from the outside to change the reference voltage from eg 0 V to a rectangular wave In the range of the H level voltage of the signal, it becomes possible to adjust the minute voltage unit corresponding to the resolution obtained by multiplying the duty resolution of the first pulse width modulation circuit and the duty resolution of the second pulse width modulation circuit. It is possible to control

  Also, since the reference voltage is generated based on the resolution obtained by multiplying the duty resolution of the first pulse width modulation circuit and the duty resolution of the second pulse width modulation circuit, the first pulse width modulation circuit and the second pulse width modulation circuit The duty resolution can be reduced, and if the duty resolution is small, with the same clock cycle as the conventional one, the cycle of the rectangular wave signal is shortened and the high speed operation is performed, and the resistor connected to the output of the pulse width modulation circuit Even if the time constant of the capacitor and the capacitor is reduced, the ripple of the reference voltage can be reduced.

  As a result, high resolution output voltage setting, reduction of output voltage ripple voltage, and short setting voltage change time can be achieved at low cost.

(Details of pulse width modulation circuit and effect by duty resolution)
Further, the pulse width modulation circuit includes a counter circuit, a first comparison circuit, a second comparison circuit, and an output inverting circuit. The counter circuit counts clock signals supplied from the outside and outputs a count value as well as the first When reset by the reset signal output from the comparison circuit, the first comparison circuit compares the count value of the counter circuit with a predetermined first set value set from the outside, and the count value matches the first set value The second comparison circuit compares the count value of the counter circuit with the second set value set from the outside, and outputs an output inverted signal when the count value matches the second set value. Since the output inverting circuit inverts the output when the reset signal is obtained, and inverts the output to output the rectangular wave signal when the output inverted signal is obtained, such a configuration The first pulse width modulation circuit and the second pulse width modulation circuit can be controlled to change the cycle and duty resolution of the rectangular wave signal by externally changing the first set value by a digital processor or the like, and By changing the second set value, the control of changing the duty of the rectangular wave signal becomes possible, and a minute corresponding to the resolution obtained by multiplying the duty resolution of the first pulse width modulation circuit and the duty resolution of the second pulse width modulation circuit. The reference voltage can be adjusted on a voltage basis, and the reference voltage can be controlled with high accuracy.

  Also, since the reference voltage is generated based on the resolution obtained by multiplying the duty resolution of the first pulse width modulation circuit and the duty resolution of the second pulse width modulation circuit, the first pulse width modulation circuit and the second pulse width modulation circuit The duty resolution can be reduced by setting the first set value of to a small value, and if the duty resolution is small, the cycle of the rectangular wave signal is shortened by shortening the cycle of the clock with the same clock cycle as the conventional one. The ripple of the reference voltage can be reduced even if the time constant of the resistor and capacitor connected to the output of the pulse width modulation circuit is reduced.

  As a result, high resolution output voltage setting, reduction of output voltage ripple voltage, and short setting voltage change time can be achieved at low cost.

(Effect of switching power supply)
The present invention includes a power conversion unit, a switching element drive circuit, and a reference voltage generation circuit, and the power conversion unit converts an input voltage supplied by the input power supply into an intermittent voltage and rectifies and smoothes the intermittent voltage by turning on and off the switching element. In a switching power supply in which a DC voltage is generated and a switching element drive circuit controls the on-duty of the switching element corresponding to a reference voltage from a reference voltage generation circuit, the reference voltage generation circuit externally has a cycle and a duty. A plurality of pulse width modulation circuits that output rectangular wave signals that can be set from a plurality of resistors, a plurality of resistors whose one end is connected to each of the outputs of the plurality of pulse width modulation circuits, and a capacitor whose other ends are connected in common And the configuration in which the voltage generated at the connection point between the multiple resistors and the capacitor is taken out as the reference voltage. The effect of the reference voltage generating circuit according to the invention as, with high accuracy and fast response in a digital processor or the like to control the output voltage, the output voltage ripple is small switching power supply unit can be made at low cost.

  The effects of the other features of the switching power supply device are basically the same as those of the reference voltage generation circuit.

A circuit block diagram schematically showing a reference voltage generation circuit provided with two digital PWM circuits A circuit block diagram showing a specific circuit configuration of a digital PWM circuit for the reference voltage generation circuit of FIG. 1 A circuit block diagram showing an equivalent circuit when the capacitance of the reference voltage generating circuit is infinite. A circuit block diagram schematically showing a reference voltage generation circuit provided with three or more digital PWM circuits A circuit block diagram showing a first embodiment of a switching power supply device provided with a reference voltage generation circuit according to the present invention A circuit block diagram showing a second embodiment of a switching power supply device provided with a reference voltage generation circuit according to the present invention The circuit block diagram which showed 3rd Embodiment of the switching power supply device which does not have the feedback control circuit which provided the reference voltage generation circuit of this invention. A circuit block diagram showing a reference voltage generating circuit using a conventional digital PWM circuit The time chart which showed the operation waveform of each part in the digital PWM circuit of FIG. 7

First Embodiment of Reference Voltage Generation Circuit
FIG. 1 is a circuit block diagram schematically showing a reference voltage generating circuit provided with two digital PWM circuits, and FIG. 2 is a circuit showing the reference voltage generating circuit of FIG. 1 including a specific circuit configuration of the digital PWM circuit. FIG. 3 is a circuit block diagram showing an equivalent circuit in the case where the capacitance of the reference voltage generation circuit is infinite.

(Outline of reference voltage generation circuit)
As shown in FIG. 1, the reference voltage generation circuit 10 of this embodiment includes a first digital PWM circuit 12-1 functioning as a first pulse width modulation circuit and a second digital PWM circuit functioning as a second pulse width modulation circuit. An output of the first digital PWM circuit 12-1 is connected to one end of the first resistor 14-1, and an output of the second digital PWM circuit 12-2 is connected to one end of the second resistor 14-2. The other ends of the first resistor 14-1 and the second resistor 14-2 are commonly connected to one end of the capacitor 16, and the output terminal is connected to the connection point of the first resistor 14-1, the second resistor 14-2, and the capacitor 16 It is connected to 18 to obtain a reference voltage Vref.

(First digital PWM circuit)
As shown in FIG. 2, the first digital PWM circuit 12-1 provided in the reference voltage generation circuit 10 includes a counter circuit 20-1, a first comparison circuit 22-1, a second comparison circuit 24-1, and an RS-flip. It comprises the loop circuit 26-1.

  The counter circuit 20-1 counts the clock signal E11 output from the clock oscillation circuit 15-1, and outputs the count value N1 to the first comparison circuit 22-1 and the second comparison circuit 24-1. When the reset signal E12 is input to the counter circuit 20-1, the count value N1 is reset to zero.

  The first comparison circuit 22-1 has a first set value S11 that can be set from the outside, the count value N1 output from the counter circuit 20-1 becomes equal to the first set value S11, and the next clock signal E11 is input. The reset signal E12 is output at the timing as

  The second comparison circuit 24-1 has a second set value S12 which can be set externally, and outputs the output inverted signal E13 at the timing when the count value N1 output from the counter circuit 20-1 becomes equal to the second set value S12. Do.

  The RS flip-flop circuit 26-1 functions as an output inverting circuit, and when the reset signal E12 output from the first comparison circuit 22-1 is input, the output QB becomes H level and the output Q becomes L level. When the output inverted signal E13 output from the second comparison circuit 24-1 is input, the output QB is at L level and the output Q is at H level, and this is maintained, and the rectangular wave signal (PWM Signal) E14 is output.

As a result, the first digital PWM circuit 12-1 outputs a rectangular wave signal E14 having a cycle Tpwm1 and a duty of ₁ . Here, the period Tpwm1 and the duty duty ₁ are given by the following equations.
Tpwm1 = Tck1 × (S11 + 1)
duty ₁ = S12 / (S11 + 1)

(2nd digital PWM circuit)
As shown in FIG. 2, the second digital PWM circuit 12-2 provided in the reference voltage generation circuit 10 includes a counter circuit 20-2, a first comparison circuit 22-2, a second comparison circuit 24-2, and an RS-flip. It comprises the loop circuit 26-2.

  The counter circuit 20-2 counts the clock signal E21 output from the clock oscillation circuit 15-2, and outputs the count value N2 to the first comparison circuit 22-2 and the second comparison circuit 24-2. When the reset signal E22 is input to the counter circuit 20-2, the count value N2 is reset to zero.

  The first comparison circuit 22-2 has a first set value S21 which can be set from the outside, the count value N2 output from the counter circuit 20-2 becomes equal to the first set value S21, and the next clock signal E21 is input. The reset signal E22 is output at the timing which is set.

  The second comparison circuit 24-2 has a second set value S22 that can be set externally, and outputs the output inverted signal E23 at the timing when the count value N2 output from the counter circuit 20-2 becomes equal to the second set value S22. Do.

  The RS-flip flop circuit 26-2 functions as an output inverting circuit, and when the reset signal E22 output from the first comparison circuit 22-2 is input, the output QB becomes H level and the output Q becomes L level. When the output inversion signal E23 output from the second comparison circuit 24-2 is input, the output QB is at L level and the output Q is at H level, and this is maintained, and the rectangular wave signal (PWM Signal) E24 is output.

As a result, the second digital PWM circuit 12-2 outputs a rectangular wave signal (PWM signal) E24 having a cycle Tpwm2 and a duty of ₂ . Here, the period Tpwm2 and the duty duty ₂ are given by the following equations.
Tpwm2 = Tck2 × (S21 + 1)
duty ₂ = S22 / (S21 + 1)

(Rectifying smoothing)
The output of the first digital PWM circuit 12-1 and the output of the second digital PWM circuit 12-2 are connected via the first resistor 14-1 and the second resistor 14-2. The capacitor 16 is connected to the connection point of the first resistor 14-1 and the second resistor 14-2, and the voltage of the capacitor 16 is taken out from the output terminal 18 as the reference voltage Vref.

(Operation to generate reference voltage)
The generation operation of the reference voltage Vref of the reference voltage generation circuit 10 shown in FIGS. 1 and 2 will be described below.

  Assuming that the capacitance C1 of the capacitor 16 is infinite, the output voltages of the first digital PWM circuit 12-1 and the second digital PWM circuit 12-2 viewed from the reference voltage Vref side are rectangular wave signals of pulse voltages respectively output Can be considered as a DC voltage source that outputs a smoothed voltage.

  Therefore, assuming that H level output voltages of the rectangular wave signals E14 and E24 from the first and second digital PWM circuits 12-1 and 12-2 are VH1 and VH2, and L level output voltages are VL1 and VL2, respectively. The voltage VSM1 obtained by smoothing the output of the digital PWM circuit 12-1 and the voltage VSM2 obtained by smoothing the output of the second digital PWM circuit 12-2 are represented by the following equations.

VSM1 = (VH1−VL1) × S12 / (S11 + 1) + VL1
= (VH1-VL1) · duty ₁ + VL1 (8)
VSM2 = (VH2-VL2) * S22 / (S21 + 1) + VL2
= (VH2-VL2)-duty ₂ + VL2 (9)

  The first digital PWM circuit 12-1 and the second digital PWM circuit 12-2 are connected via the first resistor 14-1 and the second resistor 14-2, and the first resistor 14-1 and the second resistor 14 are connected. Since the voltage at the connection point of −2 is the reference voltage Vref, the reference voltage generation circuit 10 can be represented as shown in FIG.

  As shown in FIG. 3, when the current flowing to the second digital PWM circuit 12-2 from the first digital PWM circuit 12-1 through the first resistor 14-1 and the second resistor 14-2 is calculated as i1, the reference The voltage Vref can be obtained.

Assuming that the resistance value of the first resistor 14-1 is R1, the current i1 flowing through the first resistor 14-1 holds the following equation from the voltage difference between both ends of the first resistor 14-1 and the resistance value R1.
i1 = (VSM1-Vref) / R1 (10)

In addition, since the same current i1 flows through the second resistor 14-2, if the resistance value of the second resistor 14-2 is R2, the following equation holds similarly.
i1 = (Vref-VSM2) / R2 (11)

The relationship between the resistance value R1 of the first resistor 14-1 and the resistance value R2 of the second resistor 14-2 is A = R2 / R1.
Then, the reference voltage Vref can be obtained by the following equation.
Vref = {A / (A + 1)} VSM1 + {1 / (A + 1)} VSM2 (12)

Here, in order to satisfy A >> 1, that is, the resistance value R2 of the second resistor 14-2 becomes sufficiently larger than the resistance value R1 of the first resistor 14-1, When you set the value,
A + 1 A A
Therefore, the reference voltage Vref can be expressed by the following equation.
Vref V VSM1 + (1 / A) VSM2 (13)

  From the relationship of this equation (13), for the reference voltage Vref, the voltage change of the smoothed voltage VSM1 is directly reflected in the voltage change of the reference voltage Vref, and the voltage change of the smoothed voltage VSM2 is (1 / A) times It can be seen that the change in voltage of the reference voltage Vref is reflected.

  The smoothed voltage VSM1 from the first digital PWM circuit 12-1 can work as a rough adjustment to the voltage change of the reference voltage Vref, and the smoothed voltage VSM2 from the second digital PWM circuit 12-2 is a reference It can work as a fine adjustment to the voltage change of the voltage Vref.

  Further, the voltage resolution of the reference voltage Vref is such that the duty resolution in the first digital PWM circuit 12-1 is 1 (S11 + 1) obtained by adding 1 to the first set value S11 of the first comparison circuit 12-1, and the second digital The duty resolution of the PWM circuit 12-2 is 1 (S21 + 1) obtained by adding 1 to the first set value S21 of the first comparison circuit 22-1, and the voltage resolution of the reference voltage Vref is a resolution obtained by multiplying both duty resolutions. (S11 + 1) can be determined as (S21 + 1). Therefore, even if the duty resolution of each of the first digital PWM circuit 12-1 and the second digital PWM circuit 12-2 is low, the voltage resolution of the reference voltage Vref can be increased.

  Further, the fact that the voltage resolution of the reference voltage Vref can be determined by the resolution (S11 + 1) (S21 + 1) obtained by multiplying the duty resolutions of the first and second digital PWM circuits 12-1 and 12-2 means that the first digital PWM circuit This means that the duty resolution of 12-1 and the second digital PWM circuit 12-2 may be small.

  As described above, when the duty resolution of the first digital PWM circuit 12-1 and the second digital PWM circuit 12-2 can be reduced, the periods Tpwm1 and Tpwm2 of both can be used short.

(Merit of this embodiment)
The reference voltage generation circuit 10 of the present embodiment shown in FIGS. 1 to 3 can increase the resolution of the reference voltage Vref even if the digital PWM circuit operating with a low speed clock is used with a low duty resolution. Since the first and second digital PWM circuits 12-1 and 12-2 do not use expensive digital PWM circuits operating with a high-speed clock, the period of the rectangular wave signal output from the digital PWM circuit can be The output of the digital PWM circuit can be shortened in order to shorten the set voltage change time of the reference voltage Vref because the cycle of the rectangular wave signal can be shortened by setting the duty resolution of the digital PWM circuit low. Even if the time constants of the resistors and capacitors connected to the circuit are reduced, the ripples of the reference voltage Vref can be reduced. Will be that can output voltage setting of the high resolution, reduction of the ripple voltage of the output voltage can be both all short set voltage change time at low cost.

(Modification of the first embodiment)
FIG. 4 is a circuit block diagram schematically showing a reference voltage generation circuit provided with a plurality of circuits each of which includes three or more digital PWM circuits.

  In the reference voltage generation circuit of the first embodiment shown in FIGS. 1 to 3, two digital PWM circuits are connected to a capacitor via resistors, respectively, but a plurality of digital PWM circuits having three or more circuits are used. May be circuits connected to capacitors via resistors, respectively, and the same effect can be obtained in this case as well.

  In the reference voltage generation circuit 10 of FIG. 4, one end of each of the resistors 14-1 to 14-n is connected to the output of each of the plurality of digital PWM circuits 12-1 to 12-n having three or more circuits. All the other ends 1 to 14-n are connected to the capacitor 16 to obtain the voltage Vref from the capacitor 16.

In this case, the plurality of digital PWM circuits 12-1 to 12-n and the resistors 14-1 to 14-n are divided into groups G1 to Gn-1 of two circuits each in the order of overlapping so as to overlap each other, i-th and i + 1 The first digital PWM circuit 12-i and the second digital PWM circuit 12- (i + 1) are digital PWM circuits of an arbitrary group Gi including the second digital PWM circuit in the order of arrangement in the group. set to a value sufficiently the resistance R _{i + 1} of the second digital PWM circuit with respect to the resistance value R _i 12- _(i + 1) connected to the second resistor 14- (i + 1) of the first resistor 14-i connected to the The relationship of the above equation (13) may be obtained for each group. Here, i is an integer of 1 to n.

Here, the relationship between the resistance values R1 to Rn of the resistors 14-1 to 14-n is
R2 / R1 = A ₁
R3 / R2 = A ₂
...
Rn / Rn-1 = A _n-1
Then, from the relationship of the above equation (13), the reference voltage Vref by the reference voltage generation circuit 10 of the present embodiment can be expressed by the following equation.
Vref = VSM1 + (1 / A ₁ ) VSM2 + (1 / A ₂ ) VSM3 +
... + (1 / _An-1 ) VSMn (14)

  Also in the modification of the first embodiment, as in the first embodiment, all of the high resolution output voltage setting, the reduction of the ripple voltage of the output voltage, and the shortness of the set voltage change time can be achieved at low cost.

Second Embodiment of Reference Voltage Generating Circuit
The reference voltage generation circuit of the second embodiment has the same configuration as that of the first embodiment shown in FIGS. 1 and 2, but the resistance value R1 of the first resistor 14-1 and the second resistor 14-2 By setting the ratio (R2 / R1) of the resistance value R2 to the duty resolution (Rd ₁ -1) of the first digital PWM circuit 12-1 as in the following equation (15), the reference voltage Vref can be made high. It can be controlled to the accuracy.
R2 / R1 = Rd ₁ -1 (15)

  Hereinafter, the generation operation of the reference voltage according to the present embodiment is performed by setting both the H level output voltages of the first digital PWM circuit 12-1 and the second digital PWM circuit 12-2 shown in FIG. 1 and FIG. The explanation is given assuming that the output voltage is zero.

  The present embodiment can be described by the following equations obtained from the equations (8) to (15) shown in the first embodiment.

  Assuming that the H level output voltage of the rectangular wave signal from the first digital PWM circuit 12-1 and the second digital PWM circuit 12-2 is VH, then VH1 = VH2 = VH. Further, since the L level output voltage is 0, VL1 = VL2 = 0. This condition is given in equations (8) and (9).

Further, A = R2 / R1 used to describe the relationship between the resistance values of the first resistor 14-1 and the second resistor 14-2 in equation (12).
Is substituted into equation (15): A = Rd ₁ −1
Therefore, this is substituted into the equation (12). From this, the following equation is obtained.
_{Vref = (VH · duty 1)} + (1 / Rd 1) (VH · duty 2) (16)

The duty ₁ of the first digital PWM circuit 12-1 can change from 0 to ₁ with (1 / Rd ₁ ) as the minimum unit. The duty ₂ of the second digital PWM circuit 12-2 can change from 0 to 1 with (1 / Rd ₂ ) as the minimum unit.

From Equation (16), the contribution ratio of the duty _{2 of} the second digital PWM circuit 12-2 to the voltage change of the reference voltage Vref is (1 / Rd ₁ ). When the duty _{2 of} the second digital PWM circuit 12-2 changes in the range of 0 to 1, the influence of the second digital PWM circuit 12-2 on the voltage change of Vref is the duty of the first digital PWM circuit 12-1. The smallest unit of (1 / Rd ₁ ) minutes.

It will become as follows when a numerical value is concretely given and demonstrated regarding the above point. First,
H level output voltage VH = 5 V of rectangular wave signal,
First set value S11 of first digital PWM circuit 12-1 = 99
First set value S21 of the second digital PWM circuit 12-2 = 99
I assume.

The duty duty ₁ of the rectangular wave signal from the first digital PWM circuit 12-1 is
duty ₁ = S12 / (S11 + 1)
Therefore, when the first set value S12 = 0, the duty duty ₁ = 0 and when the second set value S12 = 100, the duty duty ₁ = 1. Second setting value S12 resolution Rd ₁ duty duty ₁ since it can take a value from 0 to 100 becomes Rd ₁ = 100.

Then, resistance value R1, R2 of 1st resistance 14-1 and 2nd resistance 14-2
R1 = 1 kΩ
R2 = 99 kΩ
With can satisfy the relationship of _{(R2 / R1 = Rd 1 -1} ).

Further, the duty duty ₂ of the rectangular wave signal output from the second digital PWM circuit 12-2 is
duty ₂ = S22 / (S21 + 1)
Because it is the duty duty ₂ becomes duty duty ₂ = 1 when the duty ₂ = 0, and the second set value S22 = 100 when the second set value S22 = 0. Thereby, equation (16) can be transformed into the following equation.
Vref = (5 · S12 / 100) + (1/100) (5 · S22 / 100)
(17)

When the first setting value S12 = 0 of the first digital PWM circuit 12-1 (the output is fixed at 0 V with a cycle Tpwm = 1), the second setting value S22 of the second digital PWM circuit 12-2 is 0 to 100. When changing in the range, from the second term on the right side of the equation (17), the reference voltage Vref can be changed in the range of 0 to 50 mV. Here, since the second set value S22 is an integer, assuming that S22 = 1, the reference voltage Vref is obtained from the second term of the right side of equation (17).
(1/100) · 5 · (1/100) = 0.5 mV
You can set the value in units.

  On the other hand, the reference voltage Vref = 50 mV when the first set value S12 = 0 and the second set value S22 = 100 may be generated as the first set value S12 = 1 and the second set value S22 = 0. it can. When the second setting value S22 of the second digital PWM circuit 12-2 is changed in the range of 0 to 100 when the first setting value S12 of the first digital PWM circuit 12-1 is 1, the reference voltage Vref is 50 mV The value can be set in the unit of 0.5mV in the range of 100mV as above.

  As described above, in the present embodiment, the reference voltage Vref can be changed in 50 mV units by the set value of the first set value S12 of the first digital PWM circuit 12-1 (coarse adjustment), At the same time, it is understood that it is possible to change (fine adjustment) the reference voltage Vref in units of 0.5 mV by the second set value S22 of the second digital PWM circuit 12-2.

Therefore, by adjusting the first set value S12 of the first digital PWM circuit 12-1 and the second set value S22 of the second digital PWM circuit 12-2, the reference voltage Vref is 0.5 mV in the range of 0 to 5 V. It can be set in units. In this case, resolution of the reference voltage Vref, the first digital PWM circuit 12-1 duty resolution Rd ₁ = 100 and the second digital PWM circuit 12-2 duty resolution Rd ₂ = 100 a multiplying allowed resolution Rd ₁ × Rd ₂ = 100 x 100 = 10000
It becomes.

(Merit of the second embodiment)
In this embodiment, in the reference voltage generation circuit 10 shown in FIGS. 1 and 2, the H level output voltages of the first digital PWM circuit 12-1 and the second digital PWM circuit 12-2 are both VH and L level output. The voltage is set to 0, and the ratio (R2 / R1) of the resistance values R1 and R2 of the first resistor 14-1 and the second resistor 14-2 is reduced by ₁ from the duty resolution Rd1 of the first digital PWM circuit 12-1. By setting the value (Rd ₁ -1), that is, the first setting value S11 of the first digital PWM circuit 12-1, the reference voltage Vref can be set in the range of 0 to VH with the first digital PWM circuit 12-1. VH / (Rd ₁ × Rd ₂ ) divided by a value obtained by multiplying the duty resolution of the second digital PWM circuit 12-2
The reference voltage Vref can be controlled with high accuracy.

  Compared with the first embodiment, the ratio (R2 / R1) of the resistance values R1 and R2 of the first resistor 14-1 and the second resistor 14-2 is set to the resolution of the first digital PWM circuit 12-1. This is an advantage of the second embodiment that the adjustment when changing the reference voltage Vref can be adjusted with an equal change width.

  Further, as in the first embodiment, the period can be set short without using the expensive digital PWM that operates with the high-speed clock in the first and second digital PWM circuits 12-1 and 12-2. It becomes. For example, in comparison with the conventional digital PWM circuit 102 of FIG.

  First, in the conventional example of FIG. 8, since the first set value S1 of the first comparison circuit 106 is S1 = 3999, the resolution Rd is Rd = S1 + 1 = 4000, and the digital PWM circuit 102 of the clock cycle Tck = 100 nS. The period is Tpwm = 400 μS.

On the other hand, in the present embodiment, for example, the first setting value S11 = 99 of the first comparison circuit 22-1 in the first digital PWM circuit 12-1 is set, and the first comparison circuit 22- in the second digital PWM circuit 12-2 is A first set value S21 = 99 of 2;
(S11 + 1) × (S21 + 1) = (99 + 1) × (99 + 1) = 10000
Thus, the resolution is 10000, and in the case of the clock cycle Tck = 100 nS, the cycle of the rectangular wave signal from the first and second digital PWM circuits 12-1 and 12-2 is Tpwm = 10 μS.

  Therefore, in the present embodiment, the cycle is as short as 400 μs to 10 μs, and the operation is performed at a frequency 40 times faster than that in the related art, although the duty resolution is 4000 to 10000 and 2.5 times. I understand that. Therefore, even if the time constants of the first and second resistors 14-1 and 14-2 connected to the outputs of the first and second digital PWM circuits 12-1 and 12-2 and the capacitor 16 are reduced, the reference voltage The ripple voltage of Vref can be reduced, and high resolution output voltage setting, reduction of the ripple voltage of the output voltage, and shortness of the set voltage change time can all be achieved at low cost.

(Modification 1 of the second embodiment)
In the reference voltage generation circuit of the second embodiment, the ratio of the resistance value R1 of the first resistor 14-1 to the resistance value R2 of the second resistor 14-2 is equal to the duty resolution of the first digital PWM circuit 12-1 (Rd ₁ − In the actual circuit, the ratio of the resistance value R1 of the first resistor 14-1 to the resistance value R2 of the second resistor 14-2 is set to the first digital value in the actual circuit as shown in equation (18) below. The above effect can be obtained even when the duty resolution Rd ₁ of the PWM circuit 12-1 is substantially close.
R2 / R1 Rd Rd ₁ (18)

(Modification 2 of the second embodiment)
In the reference voltage generation circuit of the second embodiment, the two digital PWM circuits are connected to the capacitors via the respective resistors. However, as shown in FIG. One end of each of the resistors 14-1 to 14-n is connected to the output of each of 1 to 12-n, and the other end of each of the resistors 14-1 to 14-n is connected to the capacitor 16. Can be obtained.

In this case, in the same manner as shown in FIG. 4, a plurality of digital PWM circuits 12-1 to 12-n and resistors 14-1 to 14-n are arranged in groups G1 to Gn- of two circuits in the order of arrangement so as to overlap each other. When the digital PWM circuits of an arbitrary group Gi including i-th and i + 1-th are divided into 1 and made into the first digital PWM circuit 12-i and the second digital PWM circuit 12- (i + 1) in order of arrangement in the group When the resolution of the first digital PWM circuit 12-i and Rd _i, in the form of the following equation resistance R _{i + 1} of the resistance value R _i and a second resistor 14- (i + 1) of the first resistor 14-i Just do it.
R _{i + 1} / R _i = Rd _i −1 (19)

As a result, the reference voltage Vref generated by the reference voltage generation circuit 10 of this embodiment is as follows. The relationship between the resistance values R1 to Rn of the resistors 14-1 to 14-n provided in the reference voltage generation circuit 10 of the present embodiment is R2 / R1 = Rd ₁ -1.
R3 / R2 = Rd ₂ −1
...
Rn / Rn-1 = Rd _n-1 -1
Then, from the relationship of equation (16), the reference voltage Vref by the reference voltage generation circuit 10 of the present embodiment can be expressed by the following equation.
Vref = (VH · duty ₁ ) + (1 / Rd ₁ ) (VH · duty ₂ ) +
.... + (1 / Rd _{n -1} ) (VH · duty _n )
(20)

  Therefore, also in the modification of the second embodiment, all of the high resolution output voltage setting, the reduction of the ripple voltage of the output voltage, and the shortness of the setting voltage change time can be all achieved at low cost as in the second embodiment. .

Moreover, even in this case, the ratio of the resistance values R _{i + 1} of the resistance value R _i and a second resistor 14- (i + 1) of the first resistor 14-i, as shown in the following expression, the first digital PWM circuit 12 The same effect as described above can be obtained even when the duty resolution Rd _i is approximately the same as the duty resolution Rd _{i of} −i.
R _{i + 1} / R _i Rd Rd _i (21)

[Switching power supply unit]
First Embodiment of Switching Power Supply Device
FIG. 5 is a circuit block diagram showing a first embodiment of a switching power supply device provided with a reference voltage generation circuit according to the present invention.

  As shown in FIG. 5, the switching power supply device 30 of the present embodiment includes a power conversion unit 34, a switching element drive circuit 38, a feedback control circuit 36, and a reference voltage generation circuit 10.

  Power conversion unit 34 includes a switching element for converting input voltage Vin supplied by input power supply 28 into an intermittent voltage, and a rectifying and smoothing circuit that rectifies and smooths the intermittent voltage generated by the switching element to generate DC output voltage Vo. Internally.

  The switching element drive circuit 38 is a circuit that receives the feedback control signal FBA and generates a drive signal for the switching element, and controls the duty of the switching element. That is, switching element drive circuit 38 is configured of triangular wave oscillator 48 and PWM comparator 46, and when triangular wave voltage Vtri is lower than feedback signal FBA, the switching element is turned on and triangular wave voltage Vtri is higher than feedback signal FBA. At the same time, control is performed to turn off the switching element. Thereby, control is performed to widen the duty of the switching element when the feedback signal FBA rises, and to narrow the duty of the switching element when the feedback signal FBA decreases.

  The feedback control circuit 36 compares the output voltage Vo with the reference voltage Vref by the error amplifier 44, and adjusts the feedback signal FBA to a predetermined value determined by the reference voltage Vref.

    That is, the error amplifier 44 lowers the feedback signal FBA when the output voltage Vo is higher than the reference voltage Vref, and raises the feedback signal FBA when the output voltage Vo is lower than the reference voltage Vref. Thus, the output voltage Vo is controlled to be a predetermined value determined by the reference voltage Vref.

  The reference voltage generation circuit 10 is a circuit shown in the first embodiment, a modification of the first embodiment, a modification of the first embodiment or a modification of the second embodiment shown in FIGS. The reference voltage Vref is controlled with high accuracy and high speed response by controlling the period, duty resolution and duty of a plurality of digital PWM circuits provided in the voltage generation circuit 10, and as a result, the output voltage of the switching power supply device It is possible to control at high accuracy and high speed response and to make a switching power supply with low output voltage ripple at low cost.

Second Embodiment of Switching Power Supply Device
FIG. 6 is a circuit block diagram showing a second embodiment of a switching power supply device provided with a reference voltage generation circuit according to the present invention.

  In the first embodiment of FIG. 5, the output of the reference voltage generation circuit 10 is connected to the feedback control circuit 36. However, in the present embodiment, the non-inverting input of the error amplifier 44 provided in the feedback control circuit 36 is specified. The output voltage information Vo1 obtained by dividing the output voltage Vo by the resistors 40 and 42 is input to the inverting input of the error amplifier 44. The output of the reference voltage generation circuit 10 is connected to the point where the voltage information Vo1 is input via the resistor 50, and the reference voltage Vref is added. The other configuration is the same as that of the first embodiment of FIG.

  In the switching power supply device 30 of FIG. 6, when the reference voltage Vref from the reference voltage generation circuit 10 is increased, the feedback control signal FBA from the error amplifier 44 provided in the feedback control circuit 36 is reduced to reduce the duty of the switching element. To reduce the output voltage Vo. Further, when the reference voltage Vref from the reference voltage generation circuit 10 is decreased, the feedback control signal FBA from the error amplifier 44 provided in the feedback control circuit 36 is increased to widen the duty of the switching element and raise the output voltage Vo. I can do it.

  The reference voltage generation circuit 10 of this embodiment is the same as the first embodiment of the switching power supply device of FIG. 5 in the first embodiment shown in FIGS. 1 to 4, a modification of the first embodiment, and the second embodiment. Alternatively, the reference voltage can be increased by controlling the period, the duty resolution, and the duty of a plurality of digital PWM circuits provided in the reference voltage generation circuit 10 with a digital processor or the like. Control is performed with high accuracy and high speed response, and as a result, the output voltage of the switching power supply can be controlled with high accuracy and high speed, and a switching power supply with small output voltage ripple can be manufactured at low cost.

(Third Embodiment of Switching Power Supply Device)
FIG. 7 is a circuit block diagram showing a third embodiment of a switching power supply device provided with a reference voltage generation circuit according to the present invention.

  5 and 6, the reference voltage generation circuit 10 according to the present invention is applied to the switching power supply having the feedback control circuit 36. However, as shown in the present embodiment of FIG. 7, the switching power supply does not have the feedback control circuit. You may apply to a power supply device.

  In the switching power supply device 30 according to the third embodiment of FIG. 7, the duty of the switching element provided in the power conversion unit 34 is directly input by inputting the output of the reference voltage generation circuit 10 to the PWM comparator 46 of the switching element drive circuit 38. It controls and converts it into an output voltage determined by the duty of the switching element.

  The reference voltage generation circuit 10 of this embodiment is the same as the first and second embodiments of FIGS. 5 and 6 in the first embodiment shown in FIGS. 1 to 4, the modification of the first embodiment, and the second embodiment. The circuit shown in the embodiment or the modification of the second embodiment, which controls the period, the duty resolution, and the duty of the plurality of digital PWM circuits provided in the reference voltage generation circuit 10 by a digital processor or the like, Can be controlled with high accuracy and high speed response, and as a result, the output voltage of the switching power supply device can be controlled with high accuracy and high speed response, and a switching power supply device with small output voltage ripple can be manufactured at low cost.

[Modification of the present invention]
Further, the present invention is not limited to the above-described embodiment, includes appropriate modifications that do not impair the objects and advantages thereof, and is not limited by the numerical values shown in the above-described embodiment.

10: reference voltage generation circuit 12-1: first digital PWM circuit 12-2: second digital PWM circuit 14-1: first resistance 14-1: second resistance 15-1 and 15-2: clock oscillation circuit 16 : Capacitors 20-1, 20-2: Counter circuits 22-1, 22-2: First comparison circuits 24-1, 24-2: Second comparison circuits 26-1, 26-2: RS-flip flop circuit 28 : Input power supply 30: Switching power supply 32: Load 34: Power converter 36: Feedback control circuit 38: Switching element drive circuit 44: Error amplifier 45: Reference voltage source 46: PWM comparator 48: Triangular wave oscillator

Claims (6)

A plurality of pulse width modulation circuits that output a rectangular wave signal whose cycle and duty can be set externally;
A plurality of resistors, one end of which is connected to each of the outputs of the plurality of pulse width modulation circuits;
A capacitor in which the other ends of the plurality of resistors are connected in common ;
Configuration and taking out a voltage generated at the connection point of the capacitor and the plurality of resistors as a reference voltage,
Equipped with
When the plurality of pulse width modulation circuits are divided into groups of two circuits in order so as to overlap each other, and the first pulse width modulation circuit and the second pulse width modulation circuit are arranged in order within each group, the first pulse The plurality of pulse width modulation circuits output the resistance value (R _{i + 1} ) of the second resistor connected to the second pulse width modulation circuit with respect to the resistance value (R _i ) of the first resistor connected to the width modulation circuit. A reference voltage generating circuit characterized in that the reference voltage is adjusted by a combination of voltage changes of a rectangular wave signal and set to a sufficiently large value to reduce the ripple voltage of the reference voltage.
A plurality of pulse width modulation circuits that output a rectangular wave signal whose cycle and duty can be set externally;
A plurality of resistors, one end of which is connected to each of the outputs of the plurality of pulse width modulation circuits;
A capacitor in which the other ends of the plurality of resistors are connected in common;
A configuration in which a voltage generated at a connection point between the plurality of resistors and the capacitor is extracted as a reference voltage;
Equipped with
The plurality of pulse width modulation circuits have a predetermined duty resolution.
When the plurality of pulse width modulation circuits are divided into groups of two circuits in order so as to overlap each other, and the first pulse width modulation circuit and the second pulse width modulation circuit are arranged in order within each group, the first pulse the first resistance of the resistance values connected to the width modulating circuit ratio _{(R i)} and the second pulse width second resistor resistance value connected to the modulation circuit _{(R i + 1) (R} i + 1 / R i) is the first In a range in which the reference voltage is adjusted to a minute voltage unit corresponding to a value obtained by multiplying the duty resolution of the one pulse width modulation circuit and the duty resolution of the second pulse width modulation circuit to reduce the ripple voltage of the reference voltage the so as to be substantially equal to the duty resolution of the first pulse width modulation circuit, the reference voltage generating circuit, wherein a resistance value of said first resistor and said second resistor is set.
In the reference voltage generation circuit according to claim 1 or 2 ,
The pulse width modulation circuit includes a counter circuit, a first comparison circuit, a second comparison circuit, and an output inverting circuit.
The counter circuit counts a clock signal supplied from the outside to output a count value, and is reset by a reset signal output from the first comparison circuit.
The first comparison circuit compares the count value of the counter circuit with a predetermined first set value set from the outside, and outputs the reset signal when the count value matches the first set value.
The second comparison circuit compares the count value of the counter circuit with a second set value set from the outside, and outputs an output inverted signal when the count value matches the second set value.
The output inverting circuit normally rotates the output when the reset signal is obtained, and inverts the output when the output inverted signal is obtained, and outputs a rectangular wave signal. circuit.
A power conversion unit, a switching element drive circuit, and a reference voltage generation circuit;
The power conversion unit converts an input voltage supplied by the input power supply into an intermittent voltage by turning on and off the switching element and rectifying and smoothing the intermittent voltage to generate a DC voltage.
The switching element drive circuit is a switching power supply device that controls the on-duty of the switching element in accordance with the reference voltage from the reference voltage generation circuit.
The reference voltage generation circuit
A plurality of pulse width modulation circuits that output a square wave signal whose period and duty can be set from the outside;
A plurality of resistors, one end of which is connected to each of the outputs of the plurality of pulse width modulation circuits;
A capacitor in which the other ends of the plurality of resistors are connected in common ;
Configuration and taking out a voltage generated at a connection point of the capacitor and the plurality of resistors as a reference voltage,
Equipped with
When the plurality of pulse width modulation circuits are divided into groups of two circuits in order so as to overlap each other, and the first pulse width modulation circuit and the second pulse width modulation circuit are arranged in order within each group, the first pulse The plurality of pulse width modulation circuits output the resistance value (R _{i + 1} ) of the second resistor connected to the second pulse width modulation circuit with respect to the resistance value (R _i ) of the first resistor connected to the width modulation circuit. A switching power supply device characterized in that the reference voltage is adjusted by a combination of voltage changes of a rectangular wave signal and set to a sufficiently large value to reduce a ripple voltage of the reference voltage .
A power conversion unit, a switching element drive circuit, and a reference voltage generation circuit;
The power conversion unit converts an input voltage supplied by the input power supply into an intermittent voltage by turning on and off the switching element and rectifying and smoothing the intermittent voltage to generate a DC voltage.
The switching element drive circuit is a switching power supply device that controls the on-duty of the switching element in accordance with the reference voltage from the reference voltage generation circuit .
The reference voltage generation circuit
A plurality of pulse width modulation circuits that output a rectangular wave signal whose cycle and duty can be set externally;
A plurality of resistors, one end of which is connected to each of the outputs of the plurality of pulse width modulation circuits;
A capacitor in which the other ends of the plurality of resistors are connected in common;
A configuration in which a voltage generated at a connection point between the plurality of resistors and the capacitor is extracted as a reference voltage;
Equipped with
The plurality of pulse width modulation circuits have a predetermined duty resolution.
When the plurality of pulse width modulation circuits are divided into groups of two circuits in order so as to overlap each other, and the first pulse width modulation circuit and the second pulse width modulation circuit are arranged in order within each group, the first pulse The ratio ( R _{i + 1} / R _i ) of the resistance values of the resistance value ( R _i ) of the first resistor connected to the width modulation circuit and the resistance value ( R _{i +1} ) of the second resistor connected to the second pulse width modulation circuit is Adjusting the reference voltage to a minute voltage unit corresponding to a value obtained by multiplying the duty resolution of the first pulse width modulation circuit and the duty resolution of the second pulse width modulation circuit to reduce the ripple voltage of the reference voltage the extent to, so as to be substantially equal to the duty resolution of the first PWM circuit, a switching power supplies, wherein the resistance value of said first resistor and said second resistor is set .
The switching power supply device according to claim 4 or 5
The pulse width modulation circuit includes a counter circuit, a first comparison circuit, a second comparison circuit, and an output inverting circuit.
The counter circuit counts a clock signal supplied from the outside to output a count value, and is reset by a reset signal output from the first comparison circuit.
The first comparison circuit compares the count value of the counter circuit with a predetermined first set value set from the outside, and outputs the reset signal when the count value matches the first set value.
The second comparison circuit compares the count value of the counter circuit with a second set value set from the outside below the first set value, and the output is inverted when the count value matches the second set value. Output a signal,
The output inverter reverses the output when the reset signal is obtained when the reset signal is obtained, and inverts the output when the output inverted signal is obtained and outputs a rectangular wave signal. The switching power supply characterized by doing.

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