JP2013198253A - Dc/dc converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To optimize the phase compensation constant, the pulse skip reference voltage, and the inclination of a sawtooth wave signal according to an output voltage without trimming, in a DC/DC converter in which the output voltage is set using an external resistor.SOLUTION: An output-set-voltage detection circuit 20 generates an output-set-voltage detection signal S20 indicating whether an output set voltage VOUTs is larger than a predetermined output-set-voltage threshold and outputs the signal to resistance controllers 81c, 94c, and 108c. The resistance controllers 81c, 94c, and 108c adjust resistance values of variable resistors 81, 94, and 108 to preset optimum values according to the output set voltage VOUTs, respectively, on the basis of the output-set-voltage detection signal S20.

Description

  The present invention relates to a DC / DC converter that sets an output voltage using an external resistor.

  The DC / DC converter converts a predetermined input voltage into an output voltage by performing on / off control of the switching element and outputs the output voltage to a load, and performs feedback control so that the output voltage becomes a predetermined set voltage. In general, in a DC / DC converter, in order to prevent an output voltage from oscillating with a sudden change in the output voltage, an error voltage is generated at an output terminal of an error amplifier that generates an error voltage between the set voltage and the output voltage. A phase compensation circuit for compensating the phase is provided. At this time, the optimum value of the phase compensation constant of the phase compensation circuit differs depending on the input voltage and the output voltage (see, for example, Patent Documents 1 and 2). Further, when switching to pulse frequency modulation (hereinafter referred to as PFM) control or pulse width modulation (hereinafter referred to as PWM) control according to the load current, PFM control and PWM control are switched. The optimum value of the pulse skip reference voltage for setting the timing and the slope of the sawtooth signal compared with the error voltage in PWM control also differ depending on the output voltage.

  When the output voltage setting voltage is generated using an internal circuit of a DC / DC converter such as a D / A converter, the above-described phase compensation constant and pulse are generated based on the generated setting voltage and the output voltage fed back. Each element value such as resistance and capacitance for setting the slope of the skip reference voltage and the sawtooth signal can be adjusted and optimized.

  A DC / DC converter that divides the output voltage from the DC / DC converter using a resistance voltage dividing circuit provided outside the DC / DC converter, and compares the divided output voltage with a predetermined reference voltage (hereinafter referred to as a “reference voltage”). In the external adjustment type DC / DC converter), the user can obtain a desired output voltage by adjusting the resistance value of the resistance voltage dividing circuit. However, since the output voltage after the voltage division is controlled to be a predetermined reference voltage on the DC / DC converter side, it cannot be determined at what output voltage the DC / DC converter is used. For this reason, each element value such as a resistance and a capacitance for setting the phase compensation constant, the pulse skip reference voltage, and the slope of the sawtooth signal cannot be adjusted based on the output voltage. Although it is possible to obtain output voltage information by newly providing an output voltage terminal in the DC / DC converter, there is a problem that the cost increases due to an increase in mounting area and chip size accompanying the addition of the terminal. .

  For this reason, in the external adjustment type DC / DC converter, the output voltage when the DC / DC converter is used is clarified in advance, and trimming is performed for each output voltage (circuit adjustment performed at the time of manufacturing the DC / DC converter). ), The element values such as resistance and capacitance for setting the phase compensation constant, the pulse skip reference voltage, and the slope of the sawtooth signal are adjusted. However, after trimming, each element value described above is adjusted to an optimum value at a predetermined output voltage, and therefore there is a problem that the output voltage cannot be changed.

  The object of the present invention is to solve the above problems. For example, in an external adjustment type DC / DC converter, the phase compensation constant, the pulse skip reference voltage, and the slope of the sawtooth wave signal can be set without adjusting the output voltage. An object of the present invention is to provide a DC / DC converter that can be optimized according to a value.

  A DC / DC converter according to the present invention converts an input voltage input via an input terminal into a predetermined output voltage by performing on / off control of a switch element connected between the input terminal and the output terminal. The output voltage is output via the output terminal, and the output voltage is input as a feedback voltage via an inductor and an external voltage dividing circuit having a predetermined first voltage dividing ratio so that the feedback voltage becomes a predetermined reference voltage. In addition, in the DC / DC converter that performs pulse width modulation control or pulse frequency modulation control on the switch element, the first voltage division ratio is the reference voltage so that the output voltage becomes a predetermined output set voltage. And a predetermined detection voltage is divided by the voltage dividing circuit at the first voltage dividing ratio before the DC / DC converter is started up. Before the start of the DC / DC converter, the detection voltage is divided by a predetermined second voltage division ratio, and the detection voltage is divided by the first voltage division ratio. An output setting voltage that compares a feedback voltage that is a voltage with a detection voltage that has been divided by the second voltage dividing ratio and outputs a signal indicating the comparison result as an output setting voltage detection signal that indicates the output setting voltage And a detection circuit.

  According to the DC / DC converter according to the present invention, the detection voltage is divided by a predetermined second voltage division ratio before the DC / DC converter is started, and the detection voltage is divided by the first voltage division ratio. An output setting voltage detection circuit is provided that compares a feedback voltage with a detection voltage after being divided by a second voltage dividing ratio and outputs a signal indicating the comparison result as an output setting voltage detection signal indicating an output setting voltage. Therefore, the phase compensation constant, the pulse skip reference voltage, and the slope of the sawtooth signal can be optimized according to the output setting voltage without performing trimming.

1 is a block diagram showing a configuration of a DC / DC converter according to a first embodiment of the present invention. It is a block diagram which shows the structure of the DC / DC converter which concerns on the 2nd Embodiment of this invention. It is a block diagram which shows the structure of the DC / DC converter which concerns on the 3rd Embodiment of this invention.

  Hereinafter, embodiments according to the present invention will be described with reference to the drawings. In addition, in each following embodiment, the same code | symbol is attached | subjected about the same component.

First embodiment.
FIG. 1 is a block diagram showing a configuration of a DC / DC converter according to a first embodiment of the present invention. 1, the DC / DC converter according to the present embodiment includes a switching control circuit 1, a buffer circuit 2, a switch element 3 that is a P-channel MOS field effect transistor, and a rectifier that is an N-channel MOS field effect transistor. Element 4, reference voltage generation circuit 12, error amplifier 5, phase compensation circuit 8, skip comparator 7, pulse skip reference voltage generation circuit 10, one-pulse generation circuit 14, PWM comparator 6, and slope circuit 9 And a current detection circuit 14, a limit circuit 11, an oscillation circuit 13, an output setting voltage detection circuit 20, a ground terminal GND, an input terminal VCC, an output terminal LX, and a feedback terminal VFB. The

As will be described in detail later, the DC / DC converter according to the present embodiment is
(A) a switching control circuit 1 that controls the input voltage VIN to be divided by the voltage dividing ratio R52 / (R51 + R52) and input as the feedback voltage Vf0 before starting the DC / DC converter;
(B) Before starting the DC / DC converter, the input voltage VIN is divided by a predetermined voltage dividing ratio R23 / (R22 + R23) to generate the reference voltage Vref1, the feedback voltage Vf0 is compared with the reference voltage Vref1, and the comparison result And an output setting voltage detection circuit 20 for outputting an output setting voltage detection signal S20 indicating the output setting voltage VOUTs.

Furthermore, the DC / DC converter according to the present embodiment is
(C) A phase compensation circuit that compensates the phase of the error voltage between the reference voltage V12 and the feedback voltage Vf with a predetermined phase compensation constant set in advance according to the output set voltage VOUTs based on the output set voltage detection signal S20. 8 and
(D) A pulse that generates a predetermined pulse skip reference voltage V10 that is preset according to the output setting voltage VOUTs and used for switching to pulse width modulation control or pulse frequency modulation control based on the output setting voltage detection signal S20. A skip reference voltage generation circuit 10;
(C) Based on the output set voltage detection signal S20, a sawtooth wave signal S10 having a predetermined slope set in advance according to the output set voltage VOUTs and compared with the error voltage V8 in the pulse width modulation control is generated. A slope circuit 10 is further provided.

  The DC / DC converter in FIG. 1 is a non-insulated DC / DC converter that converts an input voltage VIN input via an input terminal VCC into an output voltage and outputs the output voltage from an output terminal LX. The switch element 3 is connected between the input terminal VCC and the output terminal LX, and the rectifying switch element 4 is connected between the output terminal LX and the ground. The voltage at the output terminal LX is output as an output voltage VOUT to a load circuit (not shown) through a high-frequency rejection and smoothing low-pass filter configured by including an inductor L and a smoothing capacitor Cout. The voltage is output to the voltage dividing circuit 50. Here, the switching element 3 charges the inductor L with the input voltage VIN, and the rectifying element 4 discharges the inductor L when the switching element 3 is turned off and charging to the inductor 3 is stopped. The voltage dividing circuit 50 includes resistors 51 and 52 connected in series between a connection point between the inductor L and the smoothing capacitor Cout and the ground, and a capacitor Cf connected in parallel to the resistor 51 and operating as a noise filter. And is configured. The voltage dividing circuit 50 divides the input voltage into the resistance values of the resistors 51 and 52 at a predetermined voltage dividing ratio set by R51 and R52, and the divided voltage is used as a feedback voltage Vf for the feedback terminal VFB. To the inverting input terminal of the error amplifier 5.

  In FIG. 1, the reference voltage generation circuit 12 includes a voltage source 121 that outputs a predetermined constant voltage VRI1, a resistor 122, and a variable resistor 123. The resistor 122 and the variable resistor 123 divide the constant voltage VRI1 from the voltage source 121 at a predetermined voltage dividing ratio, and output the divided voltage as a reference voltage V12 to the non-inverting input terminal of the error amplifier 5. The error amplifier 5 amplifies the difference voltage between the feedback voltage Vf and the reference voltage V12, and sets the voltage proportional to the difference voltage as the error voltage V8 via the phase compensation circuit 8 and the PWM comparator 6 and skip. Output to each inverting input terminal of the comparator 7. Here, the phase compensation circuit 8 includes a phase compensation resistor 81 and a phase compensation capacitor 82 connected in series between the output terminal of the error amplifier 5 and the ground, and a resistance controller 81c. Compensate the phase of the voltage from. The phase compensation resistor 81 is a variable resistor, and the resistance controller 81c changes the resistance value of the phase compensation resistor 81 based on the output setting voltage detection signal S20 from the output setting voltage detection circuit 20 as described in detail later. The phase compensation constant of the phase compensation circuit 9 is changed.

  Further, in FIG. 1, the current detection circuit 14 detects a current flowing through the switch element 3 during a period in which the switch element 3 is on, and supplies the sense voltage V14 corresponding to the detected current to the limit circuit 11 and the slope circuit 9. Output to. The limit circuit 11 includes a current source 111, a voltage source 113 that outputs a predetermined constant voltage VRI2, resistors 112, 114, and 115, and a limit comparator 116. Here, the current source 111 generates a predetermined constant current from the sense voltage V14. The resistor 112 is connected between the current source 111 and the ground, and the voltage between the resistor 112 and the current source 111 is output to the non-inverting input terminal of the limit comparator 116. The resistors 114 and 115 divide the constant voltage VRI2 from the voltage source 113 at a predetermined voltage dividing ratio, and output the divided voltage as an overcurrent threshold voltage to the inverting input terminal of the limit comparator 116. Then, the limit comparator 116 compares the voltage corresponding to the sense voltage V14 with the overcurrent threshold voltage and outputs an overcurrent detection signal S11 indicating the comparison result to the switching control circuit 1. The constant voltage VRI2 from the voltage source 113 is set to be equal to the constant voltage VRI1 from the voltage source 121.

  Further, in FIG. 1, the pulse skip reference voltage generation circuit 10 includes a current source 107 and a variable resistor 108 connected between the input terminal VCC and the ground, and a resistance controller 108c. The current source 107 generates a predetermined constant current from the input voltage VIN input from the input terminal VCC. The variable resistor 108 is connected between the current source 107 and the ground, and the voltage at the connection point between the variable resistor 108 and the current source 107 is output to the non-inverting input terminal of the skip comparator 7 as the pulse skip reference voltage V10. The Based on the output set voltage detection signal S20 from the output set voltage detection circuit 20, the resistance controller 108c changes the pulse skip reference voltage V10 by changing the resistance value of the variable resistor 108 as will be described in detail later.

  The skip comparator 7 compares the error voltage V8 with the pulse skip reference voltage V10 and outputs a pulse skip detection signal S7 indicating the comparison result to the one-pulse generation circuit 14 and the switching control circuit 1. The one pulse generation circuit 14 generates a one pulse signal S14 having a predetermined pulse width in response to the pulse skip detection signal S7 indicating that the error voltage V8 is larger than the pulse skip detection signal S7, and outputs the one pulse signal S14 to the switching control circuit 1. .

  In FIG. 1, the slope circuit 9 includes current sources 91 and 92, a current addition circuit 93, a variable resistor 94, and a resistance controller 94c. The current source 91 generates a predetermined slope current from the input voltage VIN input from the input terminal VCC, and the current source 92 generates a predetermined constant current from the sense voltage V14. The currents from the current sources 91 and 92 are added by the current adding circuit 93 and flow to the variable resistor 94. The variable resistor 94 has one end grounded and the other end connected to the current adding circuit 93. The voltage at the other end of the variable resistor 94 is output to the non-inverting input terminal of the PWM comparator 6 as a sawtooth signal S9. Is done. Here, the sawtooth signal S9 has a predetermined frequency fs. Based on the output set voltage detection signal S20 from the output set voltage detection circuit 20, the resistance controller 94c changes the slope of the sawtooth wave signal S9 by changing the resistance value of the variable resistor 94 as will be described in detail later. The PWM comparator 6 compares the error voltage V8 with the voltage level of the sawtooth signal S9, generates a pulse width modulation signal S6 indicating the comparison result, and outputs it to the switching control circuit 1.

  In FIG. 1, the oscillation circuit 13 generates a clock signal S13 having a predetermined frequency fs and indicating the detection timing of the pulse skip detection signal S7 and outputs the clock signal S13 to the switching control circuit 1. In addition, the switching control circuit 1 generates a control signal for controlling on / off of the switch element 3 and the rectifier element 4 and outputs the control signal to the gates of the switch element 3 and the rectifier element 4 via the buffer 2. Here, when the switching control circuit 1 detects that the error voltage V8 is higher than the pulse skip reference voltage V10 based on the pulse skip detection signal S7, for example, at the detection timing which is the rising timing of the clock signal S13, the pulse width modulation is performed. In accordance with the signal S6, a PWM control operation is performed to turn on / off the switching element 3 and the rectifying element 4 at a frequency fs. The switching control circuit 1 detects that the error voltage V8 is lower than the pulse skip reference voltage V10 based on the pulse skip detection signal S7 at the detection timing described above, and then detects the error voltage V8 based on the pulse skip detection signal S7. Is detected to exceed the pulse skip reference voltage V10, a PFM control operation is performed to control the switch element 3 to be turned on and the rectifier element 4 to be turned off in accordance with the one-pulse signal S14.

  Accordingly, in a light load state in which the load current is relatively small, the switching control circuit 1 fixes the ON time of the switch element 3 to the pulse width of the one-pulse signal S14 and based on the error voltage V8 and the pulse skip reference voltage V10. Take control. In a heavy load state where the load current is relatively large, the switching control circuit 1 fixes the switching frequency of the switch element 3 to the frequency fs of the clock signal S13 and switches the switch element 3 based on the error voltage V8 and the sawtooth wave signal S9. PWM control for determining the ON time 3 is performed. Thus, feedback control is performed so that the feedback voltage Vf (= VOUT × R52 / (R51 + R52)) becomes the reference voltage V12 during the operation of the DC / DC converter.

  Next, the configuration and operation of the output set voltage detection circuit 20 will be described. In FIG. 1, the output set voltage detection circuit 20 includes a comparator 21 and resistors 22 and 23. Here, the resistors 22 and 23 have resistance values R22 and R23, respectively, and are connected between the input terminal VCC and the ground. The input voltage VIN is divided by resistors 22 and 23 at a voltage dividing ratio R23 / (R22 + R23), and the divided reference voltage Vref1 is output to the inverting input terminal of the comparator 21. The reference voltage Vref1 is expressed by the following equation.

Vref1 = VIN × R23 / (R22 + R23)

  On the other hand, the feedback voltage Vf is output to the non-inverting input terminal of the comparator 21. The switching control circuit 1 applies the input voltage VIN to the input terminal VCC before starting the DC / DC converter, and turns on the switch element 3. At this time, since the input voltage VIN is divided by the voltage dividing circuit 50, the feedback voltage Vf0 before starting the DC / DC converter is expressed by the following equation using the resistance values R51 and R52 of the resistors 51 and 52. The

Vf0 = VIN × R52 / (R51 + R52)

  Here, since V12 = VOUTs × R52 / (R51 + R52), the feedback voltage Vf0 before activation of the DC / DC converter is expressed by the following equation using the output setting voltage VOUTs.

Vf0 = V12 × VIN / VOUTs

  That is, the feedback voltage Vf0 before starting the DC / DC converter is inversely proportional to the output setting voltage VOUTs. The comparator 21 compares the feedback voltage Vf0 with the reference voltage Vref1 before starting the DC / DC converter. When the feedback voltage Vf0 is equal to or higher than the reference voltage Vref1, the comparator 21 generates a high-level output setting voltage detection signal S20. When the feedback voltage Vf0 is less than the reference voltage Vref1, a low-level output setting voltage detection signal S20 is generated. Therefore, when the output setting voltage VOUTs is equal to or lower than V12 × (R22 + R23) / R23 (hereinafter referred to as the output setting voltage threshold Vth1), the high level output setting voltage detection signal S20 is generated, and the output setting voltage VOUTs is When it is larger than the output set voltage threshold Vth1, a low level output set voltage detection signal S20 is generated. The output set voltage detection signal S20 is output to the resistance controllers 81c, 94c and 10c. The resistance values R22 and R23 are set so that the output setting voltage threshold value Vth1 is a value within the settable range of the output setting voltage VOUTs.

  In FIG. 1, in order to set the output voltage VOUT to a desired output setting voltage VOUTs, the user sets each resistance of the resistors 51 and 51 so that the feedback voltage Vf during operation of the DC / DC converter becomes the reference voltage V12. Values R51 and R52 (that is, the voltage dividing ratio of the voltage dividing circuit 50) are set. For example, in order to set the output setting voltage VOUTs to 1.2 V when the reference voltage V12 is set to 0.6 V, the resistance values R51 and R52 are set to the same value (for example, 100 kΩ). Good. Further, when the settable range of the output setting voltage VOUTs is 0.6 V or more and 3.4 V or less, the output setting voltage threshold value Vth1 is set to 1.8 V, for example.

  In FIG. 1, before starting the DC / DC converter, the resistance controller 81c calculates the resistance value of the variable resistor 81 of the phase compensation circuit 8 as the output setting voltage VOUTs based on the output setting voltage detection signal S20. The value is switched to a value corresponding to the optimum value of the phase compensation constant when it is larger than the threshold value Vth1, or to a value corresponding to the optimum value of the phase compensation constant when the output setting voltage VOUTs is equal to or lower than the output setting voltage threshold value Vth1. Then, after starting the DC / DC converter, the resistance value of the variable resistor 81 is held at a value switched before starting the DC / DC converter. As a result, the phase compensation constant of the phase compensation circuit 8 is set to a predetermined phase compensation constant that is preset according to the output setting voltage VOUTs.

  Further, the resistance controller 108c determines the resistance value of the variable resistor 108 of the pulse skip reference voltage generation circuit 10 based on the output setting voltage detection signal S20 and the output setting voltage VOUTs as the output setting voltage before starting the DC / DC converter. A value corresponding to the optimum value of the pulse skip reference voltage V10 when it is larger than the threshold value Vth1, or a value corresponding to the optimum value of the pulse skip reference voltage V10 when the output setting voltage VOUTs is equal to or lower than the output setting voltage threshold value Vth1. Switch to. Then, after starting the DC / DC converter, the resistance value of the variable resistor 108c is held at the value switched before starting the DC / DC converter. Thus, the pulse skip reference voltage V10 is set to a predetermined pulse skip reference voltage that is set in advance according to the output setting voltage VOUTs.

  Further, before starting the DC / DC converter, the resistance controller 94c determines the resistance value of the variable resistor 94 of the slope circuit 9 based on the output setting voltage detection signal S20, and the output setting voltage VOUTs is the output setting voltage threshold value Vth1. A value corresponding to the optimum value of the slope of the sawtooth wave signal S9 when greater than or a value corresponding to the optimum value of the slope of the sawtooth wave signal S9 when the output setting voltage VOUTs is equal to or lower than the output setting voltage threshold Vth1. . Then, after starting the DC / DC converter, the resistance value of the variable resistor 94c is held at a value switched before starting the DC / DC converter. Thereby, the slope of the sawtooth signal S9 is set to a predetermined slope set in advance according to the output setting voltage VOUTs.

  As described above, according to the DC / DC converter according to the present embodiment, the phase compensation constant of the phase compensation circuit 8 and the pulse skip reference according to the output setting voltage VOUTs detected by the output setting voltage detection circuit 20. The voltage V10 and the slope of the sawtooth signal S9 can be optimized. Therefore, it is not necessary to perform trimming for each output setting voltage VOUTs, and even if the output setting voltage VOUTs is changed, the same chip semiconductor can be used.

Second embodiment.
FIG. 2 is a block diagram showing a configuration of a DC / DC converter according to the second embodiment of the present invention. In FIG. 2, the DC / DC converter according to the present embodiment is further provided with a voltage source 16 and a switch SW as compared with the DC / DC converter according to the first embodiment (see FIG. 1). Different. Only differences from the first embodiment will be described below.

  In FIG. 2, the voltage source 16 outputs a predetermined detection voltage V16 to the output terminal LX via the switch SW. Here, the detection voltage V16 is set to be equal to the input voltage VIN, for example. The switching control circuit 1 turns on the switch SW and turns off the switch element 3 and the rectifying element 4 before starting the DC / DC converter, and turns off the switch SW and turns on the switch after starting the DC / DC converter. The element 3 and the rectifying element 4 are on / off controlled in the same manner as in the first embodiment. Furthermore, in this embodiment, the voltage dividing circuit of the resistors 22 and 23 is connected to the output terminal of the voltage source 16 instead of the input terminal VCC.

  In the DC / DC converter configured as described above, the feedback voltage Vf0 output to the non-inverting input terminal of the comparator 21 before starting the DC / DC converter is expressed by the following equation.

Vf0 = V16 × R52 / (R51 + R52)

Here, since V12 = VOUTs × R52 / (R51 + R52), the feedback voltage Vf0 before activation of the DC / DC converter is expressed by the following equation.

Vf0 = V12 × V16 / VOUTs

The reference voltage Vref1 output to the inverting input terminal of the comparator 21 is expressed by the following equation.

Vref1 = V16 × R23 / (R22 + R23)

  Therefore, as in the first embodiment, the comparator 21 outputs a high-level output setting voltage detection signal when the output setting voltage VOUTs is equal to or lower than the output setting voltage threshold Vth1 (= V12 × (R22 + R23) / R23). S20 is generated, and when the output set voltage VOUTs is larger than the output set voltage threshold Vth1, a low level output set voltage detection signal S20 is generated.

  This embodiment has the same operational effects as the first embodiment.

Third embodiment.
FIG. 3 is a block diagram showing a configuration of a DC / DC converter according to the third embodiment of the present invention. The DC / DC converter according to the present embodiment is different from the DC / DC converter according to the second embodiment (see FIG. 2) in that an output setting voltage detection circuit 20A is used instead of the output setting voltage detection circuit 20. The prepared point is different. Only differences from the second embodiment will be described below.

  In FIG. 3, the output setting voltage detection circuit 20 </ b> A is further provided with a comparator 24 and resistors 25 and 26, as compared with the output setting voltage detection circuit 20. Here, the resistors 25 and 26 have resistance values R25 and R26, respectively, the detection voltage V16 is divided by the resistors 25 and 26, and the divided reference voltage Vref2 is output to the inverting input terminal of the comparator 24. The Here, the reference voltage Vref2 is expressed by the following equation.

Vref2 = VIN × R26 / (R25 + R26)

  On the other hand, the feedback voltage Vf is output to the non-inverting input terminal of the comparator 24. When the switch SW is turned on and the voltage source 16 is operated before starting the DC / DC converter, the input detection voltage V16 is divided by the voltage dividing circuit 50. Therefore, the feedback voltage Vf0 before starting the DC / DC converter. Is expressed by the following equation, as in the second embodiment.

Vf0 = V12 × V16 / VOUTs

  Therefore, when the output setting voltage VOUTs is equal to or lower than the output setting voltage threshold value Vth2 (= V12 × (R25 + R26) / R26), the comparator 24 generates the high level output setting voltage detection signal S24 and outputs the output setting voltage VOUTs. Is greater than the output set voltage threshold Vth2, the low level output set voltage detection signal S24 is generated. The output set voltage detection signal S24 is output to the resistance controllers 81c, 94c and 10c. The resistance values R25 and R26 are set so that the output set voltage threshold Vth2 is a value within the settable range of the output set voltage VOUTs and is smaller than the output set voltage threshold Vth1.

  In FIG. 3, before starting the DC / DC converter, the resistance controller 81c sets the resistance value of the variable resistor 81 of the phase compensation circuit 8 based on the output setting voltage detection signals S20 and S24 as the output setting voltage VOUTs. A value corresponding to the optimum value of the phase compensation constant when it is larger than the voltage threshold Vth1, and the phase compensation constant when the output set voltage VOUTs is larger than the output set voltage threshold Vth2 and less than or equal to the output set voltage threshold Vth1 Or a value corresponding to the optimum value of the phase compensation constant when the output setting voltage VOUTs is equal to or lower than the output setting voltage threshold Vth2. Then, after starting the DC / DC converter, the resistance value of the variable resistor 81 is held at a value switched before starting the DC / DC converter. As a result, the phase compensation constant of the phase compensation circuit 8 is set to a predetermined phase compensation constant that is preset according to the output setting voltage VOUTs.

  Further, the resistance controller 108c outputs the resistance value of the variable resistor 108 of the pulse skip reference voltage generation circuit 10 based on the output setting voltage detection signals S20 and S24 before the start of the DC / DC converter as the output setting voltage VOUTs. A value corresponding to the optimum value of the pulse skip reference voltage V10 when it is greater than the set voltage threshold Vth1, and when the output set voltage VOUTs is greater than the output set voltage threshold Vth2 and less than or equal to the output set voltage threshold Vth1 The value is switched to a value corresponding to the optimum value of the pulse skip reference voltage V10 or a value corresponding to the optimum value of the pulse skip reference voltage V10 when the output set voltage VOUTs is equal to or lower than the output set voltage threshold Vth2. Then, after starting the DC / DC converter, the resistance value of the variable resistor 108c is held at the value switched before starting the DC / DC converter. Thus, the pulse skip reference voltage V10 is set to a predetermined pulse skip reference voltage V10 that is set in advance according to the output setting voltage VOUTs.

  Further, before starting the DC / DC converter, the resistance controller 94c determines the resistance value of the variable resistor 94 of the slope circuit 9 based on the output setting voltage detection signals S20 and S24, and the output setting voltage VOUTs is the output setting voltage threshold. A sawtooth wave signal when the output set voltage VOUTs is greater than the output set voltage threshold Vth2 and less than or equal to the output set voltage threshold Vth1 corresponding to the optimum value of the slope of the sawtooth wave signal S9 when the value Vth1 is greater The value is switched to a value corresponding to the optimum value of the slope of S9 or a value corresponding to the optimum value of the slope of the sawtooth signal S9 when the output set voltage VOUTs is equal to or lower than the output set voltage threshold Vth2. Then, after starting the DC / DC converter, the resistance value of the variable resistor 94c is held at a value switched before starting the DC / DC converter. Thereby, the slope of the sawtooth signal S9 is set to a predetermined slope set in advance according to the output setting voltage VOUTs.

  According to the present embodiment, the phase compensation constant of the phase compensation circuit 8, the pulse skip reference voltage V10, and the slope of the sawtooth wave signal S9 can be adjusted with higher accuracy than in the second embodiment. In the present embodiment, the phase compensation constant, the pulse skip reference voltage V10, and the slope of the sawtooth signal S9 are adjusted in three stages. However, the present invention is not limited to this and is adjusted in a plurality of stages of four or more. May be. In this case, in the output set voltage detection circuit 20A, three or more sets of comparators 21 and resistors 22 and 23 may be provided, and the set voltage of the output voltage VOU may be compared with three or more output set voltage thresholds. .

  Note that the circuit configurations of the phase compensation circuit 8, the slope circuit 9, and the pulse skip reference voltage generation circuit 10 are not limited to the circuit configurations shown in FIGS. If the phase compensation circuit compensates the phase of the error voltage between the reference voltage V12 and the feedback voltage Vf with a predetermined phase compensation constant set in advance according to the output setting voltage VOUTs based on the output setting voltage detection signal S20. Good. The pulse skip reference voltage generation circuit is preset according to the output set voltage VOUTs based on the output set voltage detection signal S20, and is used for switching to pulse width modulation control or pulse frequency modulation control. V10 may be generated. Based on the output set voltage detection signal S20, the slope circuit generates a sawtooth wave signal S9 having a predetermined slope set in advance according to the output set voltage VOUTs and compared with the error voltage V8 in the pulse width modulation control. do it.

1 ... switching control circuit,
2 ... buffer,
3 ... Switch element,
4 ... Rectifying element,
5 ... error amplifier,
6 ... PWM comparator,
7 ... Skip comparator,
8: Phase compensation circuit,
9 ... Slope circuit,
10: Pulse skip reference voltage generation circuit,
11 ... Limit circuit,
12 ... Reference voltage generation circuit,
13: Oscillator circuit,
14 ... current detection circuit,
20, 20A ... output setting voltage detection circuit,
50: A voltage dividing circuit.

JP 2010-130856 A Japanese Patent No. 3418906

Claims (6)

The input voltage input through the input terminal is converted to a predetermined output voltage by on / off control of a switch element connected between the input terminal and the output terminal, and is output through the output terminal. The output voltage is input as a feedback voltage through an inductor and an external voltage dividing circuit having a predetermined first voltage dividing ratio, and a pulse width is applied to the switch element so that the feedback voltage becomes a predetermined reference voltage. In a DC / DC converter that performs modulation control or pulse frequency modulation control,
The first voltage division ratio is preset based on the reference voltage so that the output voltage becomes a predetermined output setting voltage,
A control circuit that controls a predetermined detection voltage to be divided by the voltage dividing circuit at the first voltage dividing ratio and input as the feedback voltage before starting the DC / DC converter;
Before starting the DC / DC converter, the detection voltage is divided by a predetermined second voltage division ratio, and a feedback voltage, which is a detection voltage after voltage division by the first voltage division ratio, is converted into the second voltage. An output setting voltage detection circuit that compares a detection voltage after voltage division with a voltage dividing ratio and outputs a signal indicating the comparison result as an output setting voltage detection signal indicating the output setting voltage. DC / DC converter. A phase compensation circuit for compensating a phase of an error voltage between the reference voltage and the feedback voltage with a predetermined phase compensation constant set in advance according to the output set voltage based on the output set voltage detection signal;
Based on the output set voltage detection signal, a pulse skip reference that is preset according to the output set voltage and generates a predetermined pulse skip reference voltage used for switching to the pulse width modulation control or the pulse frequency modulation control. A voltage generation circuit;
A slope circuit that generates a sawtooth wave signal having a predetermined slope set in advance according to the output set voltage based on the output set voltage detection signal and compared with the error voltage in the pulse width modulation control; The DC / DC converter according to claim 1, further comprising:   3. The DC / DC converter according to claim 1, wherein the detection voltage is the input voltage.   3. The DC / DC converter according to claim 1, further comprising a voltage source for generating the detection voltage.   The output setting voltage detection circuit divides the detection voltage by a predetermined plurality of second voltage division ratios, and supplies a feedback voltage, which is a detection voltage after voltage division by the first voltage division ratio, to the plurality of second voltage division ratios. 5. The DC / DC converter according to claim 1, wherein the detection voltage is compared with each of the divided detection voltages at a voltage division ratio of 2. A rectifying element connected between the output terminal and ground;
An error amplifying circuit for generating the error voltage;
A first comparison circuit that compares the error voltage with the pulse skip reference voltage and outputs a pulse skip detection signal representing the comparison result;
A one-pulse generation circuit for generating a one-pulse signal having a predetermined pulse width for the pulse frequency modulation control in response to the pulse skip detection signal indicating that the error voltage exceeds the pulse skip reference voltage;
An oscillation circuit that generates a clock signal having the same frequency as that of the sawtooth wave signal and representing the detection timing of the pulse skip detection signal;
A second comparison circuit for comparing the error voltage with the sawtooth signal and outputting a pulse width modulation signal for the pulse width modulation control representing the comparison result;
6. The control circuit according to claim 1, wherein the control circuit performs the pulse width modulation control or the pulse frequency modulation control based on the pulse skip detection signal at the detection timing. DC / DC converter.

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