JP2017085744A - Reference voltage generating circuit and switching power supply device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To set a high-resolution output voltage, reduce a ripple voltage of the output voltage, and shorten a set voltage change period at low cost.SOLUTION: A reference voltage generating circuit 10 includes a first digital PWM circuit 12-1 and a second digital PWM circuit 12-2 for outputting voltage pulses in a rectangular wave with a period and a duty that can be externally set. Resistors 14-1 and 14-2 have one ends connected to respective outputs and the other ends commonly connected to a capacitor 16. A voltage generated at a connection point between the resistors 14-1 and 14-2 and the capacitor 16 is retrieved as a reference voltage Vref. Resistance values of the resistors 14-1 and 14-2 are set so that a resistance value R2 of the resistor 14-2 connected to the second digital PWM circuit 12-2 is sufficiently large with respect to a resistance value R1 of the resistor 14-1 connected to the first digital PWM circuit 12-1.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a reference voltage generation circuit and a switching power supply device that enable control to change a reference voltage by a digital processor or the like.

  2. Description of the Related Art Conventionally, switching power supply devices that can obtain a DC output voltage by converting an input voltage into an intermittent voltage by turning on and off the switching element, and rectifying and smoothing the same are widely used.

  A switching power supply device generally includes a feedback control circuit for controlling the output voltage to a stable and constant voltage. The feedback control circuit is provided with a reference voltage generation circuit for setting the output voltage of the switching power supply device to a predetermined value.

  A switching power supply device in which a reference voltage generation circuit is configured by a DA converter is known (Patent Document 1). The reference voltage generation circuit configured with a DA converter can control the output voltage of the switching power supply device with high accuracy by controlling the DA converter with a digital processor. For example, by controlling the soft start operation of the switching power supply device using a DA converter and a digital processor, overshoot when the switching power supply is activated is suppressed.

  When a DA converter is used as the reference voltage generation circuit of the switching power supply device, the practicality of the switching power supply device is reduced unless the resolution of the DA converter is sufficiently high. For example, assume that an 8-bit DA converter is used for the reference voltage generation circuit of a switching power supply device that outputs 5V. Since the resolution of the 8-bit DA converter is 256, the voltage setting of the DA converter is in units of 5V ÷ 256 = 19.5 mV, resulting in a switching power supply device in which the output voltage can only be set discretely.

  In this case, it is difficult to use as a switching power supply device for a semiconductor device such as a DSP (Digital Signal Processor) or an FPGA (Field Programmable Gate Array) that requires highly accurate voltage setting.

  In order to obtain a practical output voltage setting accuracy as a switching power supply device, the reference voltage generating circuit must have at least 12 bits (in units of 1.22 mV for a switching power supply device with a resolution of 4096, 5 V output), and 14 bits if possible ( It is necessary to use a DA converter having a resolution of 0.305 mV in a switching power supply with a resolution of 16384 and 5 V output.

  By the way, since a high-resolution DA converter is expensive, a reference voltage generation circuit using the DA converter is expensive, so that the switching power supply device is also expensive.

(Digital PWM circuit)
As a method of controlling the reference voltage generation circuit of the switching power supply device with a digital processor,
A method using a pulse width modulation circuit (hereinafter referred to as “digital PWM circuit”) that can be controlled by a digital processor is known (Patent Document 2). In this method, a reference voltage generating circuit is configured using a digital PWM circuit, a resistor, and a capacitor, and a DC voltage obtained by smoothing the output of the digital PWM circuit with a resistor and a capacitor is used as a reference voltage.

  The digital PWM circuit is generally built in a digital processor such as a commercially available one-chip microcomputer, and is sometimes called a timer in the microcomputer. Since the digital PWM circuit is also built in an inexpensive microcomputer, the reference voltage generating circuit can be configured at low cost.

  However, when the output voltage setting accuracy of the switching power supply device is increased by the reference voltage generation circuit using the digital PWM circuit, there is a disadvantage that it cannot be used for the purpose of changing the output voltage of the switching power supply device at high speed. The reason will be described below.

(Operation of digital PWM circuit)
FIG. 8 is a circuit block diagram showing a digital PWM circuit and a conventional reference voltage generation circuit using the digital PWM circuit. As shown in FIG. 8, the digital PWM circuit 100 includes a counter circuit 104, a first comparison circuit 106, a second comparison circuit 108, and an RS-flip flop circuit 110.

  The clock oscillation circuit 102 is a circuit that outputs a clock signal E1 in which the H level and the L level are repeated at a predetermined cycle Tck. When the digital PWM circuit 100 is built in a microcomputer, a clock oscillation circuit for supplying a clock signal to the CPU and a clock oscillation circuit for supplying a clock signal to the digital PWM circuit are often used in common.

  The counter circuit 104 counts the clock signal E1 output from the clock oscillation circuit 102 and outputs a count value N to the first comparison circuit 106 and the second comparison circuit 108. When the reset signal E2 is input, the count value N is reset to zero.

  The first comparison circuit 106 has a first set value S1 that can be set from the outside, and the count value N output from the counter circuit 104 becomes equal to the first set value S1, and the next clock signal E1 is input. A reset signal E2 is output.

  The second comparison circuit 108 has a second setting value S2 that can be set from the outside, and outputs an output inversion signal E3 at a timing when the count value N output from the counter circuit 104 becomes equal to the second setting value S2.

  When the reset signal E2 output from the first comparison circuit 106 is input, the RS flip-flop circuit 110 maintains the output QB at the H level and the output Q at the L level. When the output inversion signal E3 to be input is input, the output QB becomes L level and the output Q becomes H level and is maintained, and a rectangular wave signal (PWM signal) E4 is output from the output QB.

  With this configuration, the digital PWM circuit 100 outputs a rectangular wave signal E4 having a duty of S2 / (S1 + 1) with a period of Tck × (S1 + 1), where Tck is the clock period of the clock signal E1. can do.

  FIG. 9 is a time chart showing the operation of the digital PWM circuit of FIG. 8, taking as an example the case where the clock cycle Tck = 100 nS, the first set value S1 = 3999, and the second set value S2 = 1600. 9A shows the clock signal E1, FIG. 9B shows the count value N of the counter circuit, FIG. 9C shows the reset signal E2, and FIG. 9D shows the output inversion. A signal E3 is shown, and FIG. 9E shows a rectangular wave signal E4.

(Operation during period A)
A period A in FIG. 9 is a period from the time when the count value N of the counter circuit 104 reaches 0 to the second set value S2. Here, in the RS flip-flop circuit 110, the output QB is H level and the output Q is L level.

  In the counter circuit 104, the count value N increases by 1 at the timing when the clock signal E1 changes from L level to H level. At the moment when the count value N becomes the second set value S2 = 1600, the second comparison circuit 108 outputs the output inversion signal E3 to the set terminal S of the RS-flip flop circuit 110. At this time, the output flip-flop circuit 110 has the output QB at the L level and the output Q at the H level.

(Operation during period B)
The period B is a period from the time when the count value N of the counter circuit 104 reaches 0 to immediately before reaching 1 (S1 + 1) obtained by adding 1 to the first set value S1.

  In the counter circuit 104, the count value N increases by 1 at the timing when the clock signal E1 changes from L level to H level. The first comparison circuit 106 outputs the reset signal E2 at the timing when the count value N becomes equal to the first set value S1 and the next clock signal is input, and the counter circuit 104 is reset. That is, when the reset signal E2 is output at the timing when the count value N becomes (S1 + 1) = 4000, the count value N is reset to zero.

At this time, since the reset signal E2 is also output to the reset terminal R of the RS-flip flop circuit 110, the output QB of the RS-flip flop circuit 110 changes from L level to H level. Therefore, the rectangular wave signal E4 output from the digital PWM circuit 100 is
100 nS × (3999 + 1) = 400 μS
Will have a period of

Thus, the digital PWM circuit 100 outputs a rectangular wave signal E4 having a duty period of (period A) / (period B) and a period Tpwm of period B. Since the period A is (Tck × S2) and the period B is {Tck × (S1 + 1)}, the period Tpwm and the duty duty of the digital PWM circuit 100 are expressed by the following equations.
Tpmw = Tck × (S1 + 1) (1)
duty = S2 / (S1 + 1) (2)
For example, the digital PWM circuit 100 shown in FIG. 8 having the operation shown in FIG. 9 outputs a rectangular wave signal E4 having a cycle of 400 μS and a duty of 0.4.

  The first setting value S1 of the first comparison circuit 106 and the second setting value S2 of the second comparison circuit 108 can be changed from the outside by using a digital processor or the like. Duty and period can be set freely.

(Operation of reference voltage generation circuit using digital PWM circuit)
The reference voltage generation circuit using the digital PWM circuit 100 uses the voltage obtained by smoothing the rectangular wave signal E4 output from the digital PWM circuit 100 using the resistor 112 and the capacitor 114 as the reference voltage Vref. The reference voltage Vref is determined by the H level output voltage of the digital PWM circuit 100, the L level output voltage, and the duty of the digital PWM circuit 100.

For example, when the H level output voltage of the digital PWM circuit 100 is VH, the L level output voltage is VL, and the duty of the digital PWM circuit 100 is duty, the reference voltage Vref can be expressed by the following equation.
Vref = (VH−VL) × duty + VL (3)
For example, in FIGS. 8 and 9, when VH = 5V, VL = 0V, S1 = 3999, and S2 = 1600, the duty is 0.4. Therefore, the reference voltage generation circuit of FIG. 8 sets 2V as the reference voltage Vref. Output.

(resolution)
The voltage resolution of the reference voltage Vref output from the reference voltage generation circuit using the digital PWM circuit 100 is determined by the duty resolution of the digital PWM circuit 100. The digital PWM circuit 100 generates the period Tpmw and the duty duty by counting the clock signal E1, and when the second set value S2 is set to 0, the duty duty becomes 0 and the set value S2 is (S1 + 1). When set to, the duty duty becomes 1.

Accordingly, the duty resolution of the digital PWM circuit 100 is determined by the first set value S1, and the minimum change width Vstep that becomes the voltage resolution of the reference voltage Vref is determined by the following equation.
Vstep = (VH−VL) / (S1 + 1) (4)
For example, in FIG. 8 and FIG. 9, when VH = 5V, VL = 0V, and S1 = 3999, the minimum change width Vstep that provides the voltage resolution of the reference voltage Vref in FIG. 8 is 1.25 mV.

  From the above, in the reference voltage generation circuit using the digital PWM circuit 100, when the voltage resolution of the reference voltage Vref is improved, the first set value S1 of the first comparison circuit 106 needs to be increased.

(Ripple voltage)
Since the reference voltage generation circuit using the digital PWM circuit 100 smoothes the rectangular wave signal E4 that is the output of the digital PWM circuit 100 to generate the reference voltage Vref, the resistance value R0 of the resistor 112, the capacitance C0 of the capacitor 114, and The ripple voltage Vrip determined by the value of the period Tpwm of the rectangular wave signal E4 is superimposed. In the case of a switching power supply device that controls the output voltage Vo based on the reference voltage Vref, if the ripple voltage is superimposed on the reference voltage Vref, the ripple voltage is also superimposed on the output voltage Vo.

  For example, consider a switching power supply device in which the output voltage Vo = 12V when the reference voltage Vref = 2V. Since the output voltage Vo is controlled to be 6 times the reference voltage Vref, the ripple voltage of the output voltage Vo is 6 times the ripple voltage Vrip of the reference voltage Vref.

  In a general switching power supply device, the ripple voltage of the output voltage Vo is designed to be about 0.2% of the output voltage, but the smaller the better. For example, the ripple voltage of a switching power supply device that outputs 12 V is 24 mV. In the switching power supply device in which the output voltage Vo = 12V when the reference voltage Vref = 2V, when the ripple voltage of the output voltage is 24 mV or less, the ripple voltage Vrip of the reference voltage Vref needs to be 4 mV or less. Therefore, the ripple voltage Vrip superimposed on the reference voltage Vref is obtained as follows.

The following will be described assuming that the output voltage when the digital PWM circuit 100 is at the H level is VH, and the output voltage when the digital PWM circuit 100 is at the L level is 0V. The resistance value of the resistor 112 is R0, and the capacitance of the capacitor 114 is C0. When the output of the digital PWM circuit 100 is at the H level, the current Ir0 flowing through the resistor 112 is expressed by the following equation.
Ir0 = (VH−Vref) / R0 (5)

The current Ir0 flowing through the resistor 112 becomes a current flowing into the capacitor 114. The time during which the digital PWM circuit 100 outputs the H level is a product of the period Tpwm and the duty duty of the digital PWM circuit 100. Therefore, the capacitor 114 has
Time T = Tpwm × duty
During this period, current Ir0 flows. During this time, the voltage fluctuation ΔVc0 of the capacitor 114 becomes the ripple voltage Vrip of the digital PWM circuit 100.

For example, in FIGS. 8 and 9, since VH = 5V, Vref = 2V, Tpwm = 400 μS, and duty = 0.4, the condition for Vrip ≦ 4 mV is expressed by the following equation.
C0 · R0 ≧ {(VH−Vref) · Tpwm · duty} / 4 mV
= 0.12 (7)
For example, if C0 = 10 μF and R0 = 12 kΩ, Vrip = 4 mV is obtained.

  From the above, in order to reduce the ripple voltage, it is necessary to increase the capacitance C0 of the capacitor 114 and the resistance value R0 of the resistor 112.

  As another method for reducing the ripple voltage, there is a method of increasing the frequency by shortening the period Tpwm of the digital PWM circuit 100 from the equation (6).

(Reference voltage change time)
In the reference voltage generating circuit using the digital PWM circuit 100, when the reference voltage Vref is changed, the duty of the rectangular wave signal E4 output from the digital PWM circuit 100 is changed. For example, in FIG. 8, the reference voltage Vref is changed by changing the duty of the rectangular wave signal by changing the second setting value S2 of the second comparison circuit 108.

  When the reference voltage Vref is changed from the voltage Vref1 to the voltage Vref2, the time required for the change is considered. Since the reference voltage generation circuit using the digital PWM circuit 100 has a smoothing circuit using the resistor 112 and the capacitor 114, the reference voltage Vref is set to the voltage Vref1 by calculating the time constant τ of the smoothing circuit. The time for changing to voltage Vref2 can be obtained.

In general, the time constant τ is obtained by τ = RC. Therefore, when the time τ determined by the product of the capacitance C0 of the capacitor 114 and the resistance value R0 of the resistor 112 elapses after the duty of the digital PWM circuit 100 is changed, the reference voltage Vref is
Vref = (Vref2−Vref1) × 0.632 + Vref1
It has become.

  For example, in the reference voltage generation circuit using the digital PWM circuit 100 of FIGS. 8 and 9, when the second set value S2 is 1600, the reference voltage Vref is 2V, but when the second set value S2 is changed to 2000, the digital value is changed. The duty of the PWM circuit 100 becomes 0.5, the reference voltage Vref changes with a goal of 2.5 V, and after 0.12 sec (= 10 μF × 12 kΩ), 2.316 V (= (2.5 V−2 V) × 0 .632 + 2V).

JP 2010-028951 A JP 2014-128110 A

  As described above, the method using the DA converter as the reference voltage generation circuit for controlling the output voltage of the switching power supply apparatus requires an expensive DA converter because the reference voltage generation circuit is required to have high resolution. There is a problem that the reference voltage generating circuit becomes expensive.

  As a method of solving this problem, as described above, a voltage obtained by smoothing a rectangular wave signal output from the digital PWM circuit using a resistor and a capacitor that can set the period and duty from the outside is used as a reference of the switching power supply. There is a method of voltage, but this method smoothes the rectangular wave signal with a resistor and capacitor, so the ripple voltage is superimposed on the reference voltage, and the ripple voltage of the reference voltage becomes the ripple voltage of the output voltage End up.

  In general, the smaller the output voltage ripple voltage is, the better the switching power supply device is, and the shorter the time required for changing the output voltage setting value, the better. It is conceivable to increase the frequency of the signal. If the frequency is to be increased, a digital PWM circuit using a high-speed clock is required, which causes a problem that the reference voltage generation circuit becomes expensive.

  In order to reduce the ripple voltage, it is necessary to increase the product of the capacitor and the resistor.To shorten the time required to change the output voltage setting value of the switching power supply, the product of the capacitor and the resistor must be increased. It needs to be small and cannot satisfy both.

  Therefore, the conventional reference voltage generation circuit using the digital PWM circuit has a problem that the elements of resolution, ripple voltage, and setting change time cannot be realized at low cost.

  The present invention provides a reference voltage generation circuit and a switching power supply device using a digital PWM circuit that can achieve both high resolution output voltage setting, reduction of output voltage ripple voltage, and short setting voltage change time at low cost. The purpose is to do.

(Reference voltage generation circuit)
The present invention provides a reference voltage generating circuit,
A plurality of pulse width modulation circuits that output a rectangular wave signal whose period and duty can be set from the outside;
A plurality of resistors having one end connected to each of the outputs of the plurality of pulse width modulation circuits;
A capacitor in which the other ends of a plurality of resistors are connected in common;
With
A configuration is provided in which a voltage generated at a connection point between a plurality of resistors and a capacitor is extracted as a reference voltage.

(Relationship between output resistances of two pulse width modulation circuits)
When a plurality of pulse width modulation circuits are divided into groups of two circuits in order so as to overlap each other, and the first pulse width modulation circuit and the second pulse width modulation circuit are arranged in order within each group, the first pulse width modulation The resistance value (R _{i + 1} ) of the second resistor connected to the second pulse width modulation circuit is set to a sufficiently large value relative to the resistance value (R _i ) of the first resistor connected to the circuit.

(Set the output resistance ratio of two pulse width modulation circuits based on duty resolution)
The plurality of pulse width modulation circuits have a predetermined duty resolution,
When a plurality of pulse width modulation circuits are divided into groups of two circuits in order so as to overlap each other, and the first pulse width modulation circuit and the second pulse width modulation circuit are arranged in order within each group, the first pulse width modulation The ratio (R _{i + 1} / R _i ) of the resistance value (R _i ) of the first resistor connected to the circuit and the resistance value (R _{i + 1} ) of the second resistor connected to the second pulse width modulation circuit is the first. The resistance values of the first resistor and the second resistor are set so as to be substantially equal to the duty resolution of the pulse width modulation circuit.

(Details of pulse width modulation circuit and duty resolution)
The pulse width modulation circuit includes a counter circuit, a first comparison circuit, a second comparison circuit, and an output inversion circuit,
The counter circuit counts a clock signal supplied from the outside and outputs a count value, and is reset by a reset signal output from the first comparison circuit,
The first comparison circuit compares the count value of the counter circuit with a predetermined first set value set from the outside, and outputs a reset signal when the count value matches the first set value;
The second comparison circuit compares the count value of the counter circuit with a second set value set from outside that is equal to or less than the first set value, and outputs an output inversion signal when the count value matches the second set value;
The output inversion circuit raises the output from the L level to the H level when the reset signal is obtained, and outputs the rectangular wave signal by inverting the output from the H level to the L level when the output inversion signal is obtained. .

(Switching power supply)
The present invention
A power conversion unit, a switching element drive circuit and a reference voltage generation circuit;
The power conversion unit converts the input voltage supplied by the input power supply into an intermittent voltage by turning on and off the switching element and rectifies and smoothes the intermittent voltage to generate a DC voltage.
In the switching power supply device that controls the on-duty of the switching element in response to the reference voltage from the reference voltage generation circuit,
The reference voltage generator circuit
A plurality of pulse width modulation circuits that output a rectangular wave signal whose period and duty can be set from the outside;
A plurality of resistors having one end connected to each of the outputs of the plurality of pulse width modulation circuits;
A capacitor in which the other ends of a plurality of resistors are connected in common;
With
A configuration is provided in which a voltage generated at a connection point between a plurality of resistors and a capacitor is taken out as a reference voltage.

(Relationship between output resistances of two pulse width modulation circuits)
When a plurality of pulse width modulation circuits provided in the switching power supply device are divided into groups of two circuits in order so as to overlap each other, and the first pulse width modulation circuit and the second pulse width modulation circuit are arranged in order in each group The resistance value (R _{i + 1} ) of the second resistor connected to the second pulse width modulation circuit is set to a sufficiently large value relative to the resistance value (R _i ) of the first resistor connected to the first pulse width modulation circuit. Is done.

(Set the output resistance ratio of two pulse width modulation circuits based on duty resolution)
The plurality of pulse width modulation circuits provided in the switching power supply device have a predetermined duty resolution,
When a plurality of pulse width modulation circuits are divided into groups of two circuits in order so as to overlap each other, and the first pulse width modulation circuit and the second pulse width modulation circuit are arranged in order within each group, the first pulse width modulation Ratio (R _{i + 1} / R _i ) of the resistance value (R _i ) of the first resistor connected to the circuit and the resistance value (R _{i + 1} ) of the second resistor connected to the second pulse width modulation circuit Are set to be substantially equal to the duty resolution of the first pulse width modulation circuit, the resistance values of the first resistor and the second resistor are set.

(Details of pulse width modulation circuit and duty resolution)
The pulse width modulation circuit provided in the switching power supply device includes a counter circuit, a first comparison circuit, a second comparison circuit, and an output inversion circuit.
The counter circuit counts a clock signal supplied from the outside and outputs a count value, and is reset by a reset signal output from the first comparison circuit,
The first comparison circuit compares the count value of the counter circuit with a predetermined first set value set from the outside, and outputs a reset signal when the count value matches the first set value;
The second comparison circuit compares the count value of the counter circuit with a second set value set from outside that is equal to or less than the first set value, and outputs an output inversion signal when the count value matches the second set value;
The output inverting circuit normally rotates the output when the reset signal is obtained, and inverts the output and outputs a rectangular wave signal when the output inverted signal is obtained.

(Basic effects of the reference voltage generation circuit)
According to the present invention, in the reference voltage generating circuit, one end is connected to each of a plurality of pulse width modulation circuits that output a rectangular wave signal whose period and duty can be set from the outside, and each of the outputs of the plurality of pulse width modulation circuits. It is equipped with a plurality of resistors and a capacitor with the other ends of the plurality of resistors connected in common, and has a configuration for extracting the voltage generated at the connection point between the plurality of resistors and the capacitor as a reference voltage. Even if a digital PWM circuit that operates with a clock is used with a low duty resolution, the resolution of the reference voltage can be increased. Therefore, a rectangular wave can be used without using an expensive digital PWM circuit that operates with a high-speed clock. The period of the signal can be shortened, and the period of the rectangular wave signal can be reduced by setting the duty resolution of the digital PWM circuit low. Because it can be shortened, even if the time constant of the resistor and capacitor connected to the output of the digital PWM circuit is reduced in order to shorten the set voltage change time of the reference voltage, the ripple voltage of the reference voltage does not increase and is high. The resolution output voltage setting, output voltage ripple voltage reduction, and setting voltage change time can be reduced at a low cost.

(Effect due to the relationship between the output resistances of the two pulse width modulation circuits)
Further, when the plurality of pulse width modulation circuits are divided into groups of two circuits in the order of arrangement so as to overlap each other, and the first pulse width modulation circuit and the second pulse width modulation circuit are arranged in order in each group, the first pulse Since the resistance value (R _{i + 1} ) of the second resistor connected to the second pulse width modulation circuit is set to a sufficiently large value relative to the resistance value (R _i ) of the first resistor connected to the width modulation circuit, the reference For the voltage, the voltage change due to the rectangular wave signal from the first comparison circuit is directly reflected in the voltage change of the reference voltage, thereby acting as a rough adjustment, and the voltage change due to the rectangular wave signal from the first comparison circuit is Based on the magnitude relationship between the first resistor and the second resistor, a small voltage change is reflected in the reference voltage to work as a fine adjustment. By combining both, high resolution output voltage setting, output voltage ripple voltage reduction, setting voltage Change time The short and compatible with low cost.

(Effect of setting output resistance ratio of two pulse width modulation circuits based on duty resolution)
The plurality of pulse width modulation circuits have a predetermined duty resolution, and the plurality of pulse width modulation circuits are divided into groups of two circuits in the arrangement order so as to overlap each other, and the first pulse width modulation is arranged in the arrangement order in each group. If the circuit and the second pulse width modulation circuit, the first resistor resistance value connected to the first pulse width modulation circuit (R _i) and the second resistor resistance value connected to the second pulse width modulation circuit (R _{i +1} ) ratio (R _{i + 1} / R _i ) is set so that the resistance values of the first resistor and the second resistor are substantially equal to the duty resolution of the first pulse width modulation circuit. By setting the ratio of the second resistance to be substantially equal to the duty resolution of the first pulse width modulation circuit, the reference voltage is changed from, for example, 0 V to a rectangular wave by controlling the period, duty resolution, and duty from the outside by a digital processor or the like. Within the range of the H level voltage of the signal, it is possible to adjust to the minute voltage unit corresponding to the resolution obtained by multiplying the duty resolution of the first pulse width modulation circuit and the duty resolution of the second pulse width modulation circuit. It becomes possible to control to.

  Further, since the reference voltage is generated based on a resolution obtained by multiplying the duty resolution of the first pulse width modulation circuit and the duty resolution of the second pulse width modulation circuit, the first pulse width modulation circuit and the second pulse width modulation circuit If the duty cycle is the same as the conventional clock cycle, the cycle of the rectangular wave signal will be shortened, resulting in high-speed operation and a resistor connected to the output of the pulse width modulation circuit. Even if the time constant of the capacitor is reduced, the ripple of the reference voltage can be reduced.

  As a result, high resolution output voltage setting, reduction of ripple voltage of output voltage, and short setting voltage change time can be achieved at low cost.

(Details of pulse width modulation circuit and effect of duty resolution)
The pulse width modulation circuit includes a counter circuit, a first comparison circuit, a second comparison circuit, and an output inversion circuit. The counter circuit counts a clock signal supplied from the outside and outputs a count value. When reset by the reset signal output from the comparison circuit, the first comparison circuit compares the count value of the counter circuit with a predetermined first set value set from the outside, and the count value matches the first set value The second comparison circuit compares the count value of the counter circuit with a second set value set from the outside, and outputs an output inversion signal when the count value matches the second set value. The output inverting circuit normally rotates the output when the reset signal is obtained, and outputs the rectangular wave signal by inverting the output when the output inverted signal is obtained. The first pulse width modulation circuit and the second pulse width modulation circuit provided can be controlled to change the period and duty resolution of the rectangular wave signal by changing the first set value from the outside by a digital processor or the like. By changing the second set value, it is possible to control to change the duty of the rectangular wave signal, and the minute resolution corresponding to the resolution obtained by multiplying the duty resolution of the first pulse width modulation circuit and the duty resolution of the second pulse width modulation circuit. The reference voltage can be adjusted in units of voltage, and the reference voltage can be controlled with high accuracy.

  Further, since the reference voltage is generated based on a resolution obtained by multiplying the duty resolution of the first pulse width modulation circuit and the duty resolution of the second pulse width modulation circuit, the first pulse width modulation circuit and the second pulse width modulation circuit The duty resolution can be reduced by setting the first set value to a small value, and if the duty resolution is small, the period of the rectangular wave signal is shortened and the high-speed operation is performed with the same clock period as before. Therefore, the ripple of the reference voltage can be reduced even if the time constant of the resistor and the capacitor connected to the output of the pulse width modulation circuit is reduced.

  As a result, high resolution output voltage setting, reduction of ripple voltage of output voltage, and short setting voltage change time can be achieved at low cost.

(Effect of switching power supply)
The present invention includes a power conversion unit, a switching element drive circuit, and a reference voltage generation circuit. The power conversion unit converts an input voltage supplied from an input power source into an intermittent voltage by rectifying and smoothing the intermittent voltage by turning on and off the switching element. In a switching power supply device that generates a DC voltage and the switching element drive circuit controls the on-duty of the switching element in response to the reference voltage from the reference voltage generation circuit, the reference voltage generation circuit sets the cycle and duty to external A plurality of pulse width modulation circuits for outputting a settable rectangular wave signal, a plurality of resistors having one end connected to each of the outputs of the plurality of pulse width modulation circuits, and a capacitor having the other ends of the plurality of resistors connected in common And a configuration that takes out the voltage generated at the connection point of multiple resistors and capacitors as a reference voltage. The effect of the reference voltage generating circuit according to the invention as, with high accuracy and fast response in a digital processor or the like to control the output voltage, the output voltage ripple is small switching power supply unit can be made at low cost.

  The effects of the other features of the switching power supply device are basically the same as those of the reference voltage generation circuit.

A circuit block diagram showing an outline of a reference voltage generating circuit provided with two digital PWM circuits. 1 is a circuit block diagram showing a specific circuit configuration of a digital PWM circuit for the reference voltage generating circuit of FIG. Circuit block diagram showing an equivalent circuit when the capacitor capacity of the reference voltage generation circuit is infinite A circuit block diagram showing an outline of a reference voltage generating circuit provided with three or more digital PWM circuits. 1 is a circuit block diagram showing a first embodiment of a switching power supply device provided with a reference voltage generation circuit according to the present invention. The circuit block diagram which showed 2nd Embodiment of the switching power supply device provided with the reference voltage generation circuit of this invention The circuit block diagram which showed 3rd Embodiment of the switching power supply device which does not have the feedback control circuit which provided the reference voltage generation circuit of this invention A circuit block diagram showing a reference voltage generation circuit using a conventional digital PWM circuit FIG. 7 is a time chart showing operation waveforms of various parts in the digital PWM circuit of FIG.

[First Embodiment of Reference Voltage Generating Circuit]
1 is a circuit block diagram showing an outline of a reference voltage generating circuit provided with two digital PWM circuits. FIG. 2 is a circuit showing a specific circuit configuration of the digital PWM circuit for the reference voltage generating circuit of FIG. FIG. 3 is a circuit block diagram showing an equivalent circuit when the capacitor capacity of the reference voltage generating circuit is infinite.

(Outline of reference voltage generation circuit)
As shown in FIG. 1, the reference voltage generation circuit 10 of this embodiment includes a first digital PWM circuit 12-1 that functions as a first pulse width modulation circuit and a second digital PWM circuit that functions as a second pulse width modulation circuit. 12-2, one end of the first resistor 14-1 is connected to the output of the first digital PWM circuit 12-1, and one end of the second resistor 14-2 is connected to the output of the second digital PWM circuit 12-2. The other ends of the first resistor 14-1 and the second resistor 14-2 are connected in common to one end of the capacitor 16, and the output terminal is connected from the connection point of the first resistor 14-1, the second resistor 14-2, and the capacitor 16. 18 to obtain a reference voltage Vref.

(First digital PWM circuit)
As shown in FIG. 2, the first digital PWM circuit 12-1 provided in the reference voltage generation circuit 10 includes a counter circuit 20-1, a first comparison circuit 22-1, a second comparison circuit 24-1, and an RS flip-flop. Circuit 26-1.

  The counter circuit 20-1 counts the clock signal E11 output from the clock oscillation circuit 15-1, and outputs a count value N1 to the first comparison circuit 22-1 and the second comparison circuit 24-1. When the reset signal E12 is input to the counter circuit 20-1, the count value N1 is reset to zero.

  The first comparison circuit 22-1 has a first set value S11 that can be set from the outside. The count value N1 output from the counter circuit 20-1 becomes equal to the first set value S11, and the next clock signal E11 is input. The reset signal E12 is output at the timing.

  The second comparison circuit 24-1 has a second set value S12 that can be set from the outside, and outputs an output inversion signal E13 at the timing when the count value N1 output from the counter circuit 20-1 becomes equal to the second set value S12. To do.

  The RS flip-flop circuit 26-1 functions as an output inverting circuit. When the reset signal E12 output from the first comparison circuit 22-1 is input, the output QB becomes H level and the output Q becomes L level. When the output inversion signal E13 output from the second comparison circuit 24-1 is input, the output QB becomes L level and the output Q becomes H level, and this is maintained. From the output QB, the rectangular wave signal (PWM Signal) E14 is output.

Accordingly, the first digital PWM circuit 12-1 outputs a rectangular wave signal E14 having a cycle Tpwm1 and a duty duty ₁ . Here, the period Tpwm1 and the duty duty ₁ are given by the following equations.
Tpwm1 = Tck1 × (S11 + 1)
duty ₁ = S12 / (S11 + 1)

(Second digital PWM circuit)
As shown in FIG. 2, the second digital PWM circuit 12-2 provided in the reference voltage generation circuit 10 includes a counter circuit 20-2, a first comparison circuit 22-2, a second comparison circuit 24-2, and an RS flip-flop. Circuit 26-2.

  The counter circuit 20-2 counts the clock signal E21 output from the clock oscillation circuit 15-2, and outputs a count value N2 to the first comparison circuit 22-2 and the second comparison circuit 24-2. The counter circuit 20-2 resets the count value N2 to zero when the reset signal E22 is input.

  The first comparison circuit 22-2 has a first set value S21 that can be set from the outside. The count value N2 output from the counter circuit 20-2 becomes equal to the first set value S21, and the next clock signal E21 is input. The reset signal E22 is output at the timing.

  The second comparison circuit 24-2 has a second setting value S22 that can be set from the outside, and outputs an output inversion signal E23 at the timing when the count value N2 output from the counter circuit 20-2 becomes equal to the second setting value S22. To do.

  The RS flip-flop circuit 26-2 functions as an output inverting circuit. When the reset signal E22 output from the first comparison circuit 22-2 is input, the output QB becomes H level and the output Q becomes L level. When the output inversion signal E23 output from the second comparison circuit 24-2 is input, the output QB becomes L level and the output Q becomes H level, and this is maintained. From the output QB, the rectangular wave signal (PWM Signal) E24 is output.

As a result, the second digital PWM circuit 12-2 outputs a rectangular wave signal (PWM signal) E24 having a cycle Tpwm2 and a duty duty ₂ . Here, the cycle Tpwm2 and the duty duty ₂ are given by the following equations.
Tpwm2 = Tck2 × (S21 + 1)
duty ₂ = S22 / (S21 + 1)

(Rectifying and smoothing)
The output of the first digital PWM circuit 12-1 and the output of the second digital PWM circuit 12-2 are connected via a first resistor 14-1 and a second resistor 14-2. The capacitor 16 is connected to the connection point between the first resistor 14-1 and the second resistor 14-2, and the voltage of the capacitor 16 is taken out from the output terminal 18 as the reference voltage Vref.

(Reference voltage generation operation)
The operation of generating the reference voltage Vref of the reference voltage generation circuit 10 shown in FIGS. 1 and 2 will be described below.

  When the capacitance C1 of the capacitor 16 is infinite, the output voltage of the first digital PWM circuit 12-1 and the second digital PWM circuit 12-2 viewed from the reference voltage Vref side is a rectangular wave signal of a pulse voltage output from each. Can be considered as a DC voltage source that outputs a smoothed voltage.

  Therefore, when the H level output voltages of the rectangular wave signals E14 and E24 from the first and second digital PWM circuits 12-1 and 12-2 are VH1 and VH2, and the L level output voltages are VL1 and VL2, the first A voltage VSM1 obtained by smoothing the output of the digital PWM circuit 12-1 and a voltage VSM2 obtained by smoothing the output of the second digital PWM circuit 12-2 are represented by the following equations.

VSM1 = (VH1-VL1) * S12 / (S11 + 1) + VL1
= (VH1−VL1) · duty ₁ + VL1 (8)
VSM2 = (VH2−VL2) × S22 / (S21 + 1) + VL2
= (VH2-VL2) · duty ₂ + VL2 (9)

  The first digital PWM circuit 12-1 and the second digital PWM circuit 12-2 are connected via a first resistor 14-1 and a second resistor 14-2, and the first resistor 14-1 and the second resistor 14 are connected. Since the voltage at the connection point -2 is the reference voltage Vref, the reference voltage generation circuit 10 can be expressed as shown in FIG.

  As shown in FIG. 3, if the current flowing from the first digital PWM circuit 12-1 to the second digital PWM circuit 12-2 via the first resistor 14-1 and the second resistor 14-2 is calculated as i1, The voltage Vref can be obtained.

The current i1 flowing through the first resistor 14-1 is expressed by the following equation from the voltage difference between both ends of the first resistor 14-1 and the resistance value R1, where R1 is the resistance value of the first resistor 14-1.
i1 = (VSM1-Vref) / R1 (10)

Further, since the same current i1 also flows through the second resistor 14-2, the following equation holds similarly when the resistance value of the second resistor 14-2 is R2.
i1 = (Vref−VSM2) / R2 (11)

The relationship between the resistance value R1 of the first resistor 14-1 and the resistance value R2 of the second resistor 14-2 is A = R2 / R1.
Then, the reference voltage Vref is obtained by the following equation.
Vref = {A / (A + 1)} VSM1 + {1 / (A + 1)} VSM2 (12)

Here, the resistance values R1 and R2 are set so that A >> 1, that is, the resistance value R2 of the second resistor 14-2 is sufficiently larger than the resistance value R1 of the first resistor 14-1. If you set a value,
A + 1 ≒ A
Therefore, the reference voltage Vref can be expressed by the following equation.
Vref≈VSM1 + (1 / A) VSM2 (13)

  From the relationship of Equation (13), for the reference voltage Vref, the voltage change of the smoothing voltage VSM1 is directly reflected in the voltage change of the reference voltage Vref, and the voltage change of the smoothing voltage VSM2 is (1 / A) times. It can be seen that this is reflected in the voltage change of the reference voltage Vref.

  The smoothing voltage VSM1 from the first digital PWM circuit 12-1 can act as a rough adjustment with respect to the voltage change of the reference voltage Vref, and the smoothing voltage VSM2 from the second digital PWM circuit 12-2 is a reference voltage. It can serve as a fine adjustment for the voltage change of the voltage Vref.

  The voltage resolution of the reference voltage Vref is the duty resolution in the first digital PWM circuit 12-1 obtained by adding 1 to the first set value S11 of the first comparison circuit 12-1 (S11 + 1), and the second digital PWM circuit 12-1. The duty resolution of the PWM circuit 12-2 is 1 (S21 + 1) obtained by adding 1 to the first set value S21 of the first comparison circuit 22-1, and the voltage resolution of the reference voltage Vref is a resolution obtained by multiplying both duty resolutions. It can be determined as (S11 + 1) (S21 + 1). Therefore, the voltage resolution of the reference voltage Vref can be increased even if the duty resolution of each of the first digital PWM circuit 12-1 and the second digital PWM circuit 12-2 is low.

  Further, the fact that the voltage resolution of the reference voltage Vref can be determined by the resolution (S11 + 1) (S21 + 1) obtained by multiplying the duty resolutions of the first and second digital PWM circuits 12-1 and 12-2 is the first digital PWM circuit. The duty resolution of the 12-1 and the second digital PWM circuit 12-2 may be small.

  When the duty resolution of the first digital PWM circuit 12-1 and the second digital PWM circuit 12-2 can be reduced in this way, the periods Tpwm1 and Tpwm2 of both can be shortened.

(Advantages of this embodiment)
The reference voltage generation circuit 10 of the present embodiment shown in FIGS. 1 to 3 increases the resolution of the reference voltage Vref even when a digital PWM circuit operating with a low-speed clock is used with a low duty resolution. Therefore, the period of the rectangular wave signal output from the digital PWM circuit can be reduced without using an expensive digital PWM circuit that operates with a high-speed clock for the first and second digital PWM circuits 12-1 and 12-2. Since the period of the rectangular wave signal can be shortened by setting the duty resolution of the digital PWM circuit low, the output of the digital PWM circuit can be shortened in order to shorten the set voltage change time of the reference voltage Vref. Even when the time constant of the resistor and the capacitor connected to the capacitor is reduced, the ripple of the reference voltage Vref can be reduced. Will be that can output voltage setting of the high resolution, reduction of the ripple voltage of the output voltage can be both all short set voltage change time at low cost.

(Modification of the first embodiment)
FIG. 4 is a circuit block diagram showing an outline of a reference voltage generating circuit in which a plurality of digital PWM circuits including three or more circuits are provided.

  In the reference voltage generation circuit of the first embodiment shown in FIGS. 1 to 3, two digital PWM circuits are connected to capacitors via resistors, respectively, but a plurality of digital PWM circuits having three or more circuits are used. Each may be a circuit connected to a capacitor via a resistor, and in this case, the same effect can be obtained.

  In the reference voltage generation circuit 10 of FIG. 4, one end of resistors 14-1 to 14-n is connected to the output of each of a plurality of digital PWM circuits 12-1 to 12-n that are three or more circuits, and the resistor 14- All the other ends of 1 to 14 -n are connected to the capacitor 16, and the voltage Vref is obtained from the capacitor 16.

In this case, the plurality of digital PWM circuits 12-1 to 12-n and the resistors 14-1 to 14-n are divided into groups G1 to Gn-1 of two circuits in order so as to overlap each other. In the case where the digital PWM circuits of an arbitrary group Gi including the first are used as the first digital PWM circuit 12-i and the second digital PWM circuit 12- (i + 1) in the arrangement order in the group, the first digital PWM circuit 12-i set to a value sufficiently the resistance R _{i + 1} of the second digital PWM circuit with respect to the resistance value R _i 12- _(i + 1) connected to the second resistor 14- (i + 1) of the first resistor 14-i connected to the Then, the relationship of the above equation (13) may be obtained for each group. However, i is an integer of 1 to n.

Here, the relationship between the resistance values R1 to Rn of the resistors 14-1 to 14-n is
R2 / R1 = A ₁
R3 / R2 = A ₂
...
Rn / Rn-1 = A _n-1
Then, from the relationship of the above equation (13), the reference voltage Vref by the reference voltage generation circuit 10 of the present embodiment can be expressed by the following equation.
Vref = VSM1 + (1 / A ₁ ) VSM2 + (1 / A ₂ ) VSM3 +
... + (1 / A _n-1 ) VSMn (14)

  Also in the modification of the first embodiment, as in the first embodiment, all of the high-resolution output voltage setting, the reduction of the ripple voltage of the output voltage, and the short setting voltage change time can be achieved at low cost.

[Second Embodiment of Reference Voltage Generation Circuit]
The reference voltage generation circuit of the second embodiment has the same configuration as that of the first embodiment shown in FIGS. 1 and 2, but the resistance value R1 of the first resistor 14-1 and the resistance of the second resistor 14-2. By setting the ratio (R2 / R1) of the resistance value R2 to the duty resolution (Rd ₁ -1) of the first digital PWM circuit 12-1 as shown in the following equation (15), the reference voltage Vref is increased. It can be controlled with high accuracy.
R2 / R1 = Rd ₁ −1 (15)

  Hereinafter, the operation of generating the reference voltage according to the present embodiment is performed by setting both the H level output voltages of the first digital PWM circuit 12-1 and the second digital PWM circuit 12-2 shown in FIGS. The description will be made assuming that the output voltage is zero.

  This embodiment can be described by the following equations obtained from Equations (8) to (15) shown in the first embodiment.

  When the H level output voltage of the rectangular wave signal from the first digital PWM circuit 12-1 and the second digital PWM circuit 12-2 is VH, VH1 = VH2 = VH. Since the L level output voltage is 0, VL1 = VL2 = 0. This condition is given to Equation (8) and Equation (9).

In addition, A = R2 / R1 used to describe the relationship between the resistance values of the first resistor 14-1 and the second resistor 14-2 in Expression (12).
Is substituted into equation (15), A = Rd ₁ −1
Therefore, this is substituted into Expression (12). From this, the following equation is obtained.
Vref = (VH · duty ₁ ) + (1 / Rd ₁ ) (VH · duty ₂ ) (16)

The duty ₁ of the first digital PWM circuit 12-1 can vary from 0 to ₁ with (1 / Rd ₁ ) as the minimum unit. The duty ₂ of the second digital PWM circuit 12-2 can vary from 0 to 1 with (1 / Rd ₂ ) as the minimum unit.

From equation (16), the contribution ratio of the duty _{2 of} the second digital PWM circuit 12-2 to the voltage change of the reference voltage Vref is (1 / Rd ₁ ). When the duty _{2 of} the second digital PWM circuit 12-2 changes in the range of 0 to 1, the influence of the second digital PWM circuit 12-2 on the voltage change of Vref is the duty of the first digital PWM circuit 12-1. That is, the minimum unit (1 / Rd ₁ ).

The above point will be described below with specific numerical values. First,
H level output voltage of rectangular wave signal VH = 5V,
First set value S11 = 99 of the first digital PWM circuit 12-1.
First set value S21 = 99 of the second digital PWM circuit 12-2
And

The duty duty ₁ of the rectangular wave signal from the first digital PWM circuit 12-1 is
duty ₁ = S12 / (S11 + 1)
Therefore, when the first set value S12 = 0, the duty duty ₁ = 0, and when the second set value S12 = 100, the duty duty ₁ = 1. The second set value S12 resolution Rd ₁ duty duty ₁ since it can take a value from 0 to 100 becomes Rd ₁ = 100.

Therefore, the resistance values R1 and R2 of the first resistor 14-1 and the second resistor 14-2 are
R1 = 1kΩ
R2 = 99kΩ
Thus, the relationship (R2 / R1 = Rd ₁ −1) can be satisfied.

Also, the duty duty ₂ of the rectangular wave signal output from the second digital PWM circuit 12-2 is
duty ₂ = S22 / (S21 + 1)
Therefore, the duty ₂ becomes duty ₂ = 0 when the second set value S22 = 0, and becomes duty ₂ = 1 when the second set value S22 = 100. Thereby, Formula (16) can be transformed into the following formula.
Vref = (5 · S12 / 100) + (1/100) (5 · S22 / 100)
(17)

When the first set value S12 = 0 of the first digital PWM circuit 12-1 (the output is fixed at 0V in the cycle Tpwm = 1), the second set value S22 of the second digital PWM circuit 12-2 is set to 0 to 100. When changing in the range, the reference voltage Vref can be changed in the range of 0 to 50 mV from the second term on the right side of the equation (17). Here, since the second set value S22 is an integer, when S22 = 1, the reference voltage Vref is obtained from the second term on the right side of the equation (17):
(1/100) ・ 5 ・ (1/100) = 0.5mV
You can set the value in units.

  On the other hand, when the first set value S12 = 0 and the second set value S22 = 100, the reference voltage Vref = 50 mV can be made with the first set value S12 = 1 and the second set value S22 = 0. it can. When the first setting value S12 = 1 of the first digital PWM circuit 12-1 and the second setting value S22 of the second digital PWM circuit 12-2 are changed in the range of 0 to 100, the reference voltage Vref is 50 mV. Can be set in units of 0.5 mV in the same manner as before.

  As described above, in the present embodiment, the reference voltage Vref can be changed in units of 50 mV by the set value of the first set value S12 of the first digital PWM circuit 12-1 (coarse adjustment). At the same time, it can be seen that the reference voltage Vref can be changed (finely adjusted) in units of 0.5 mV by the second set value S22 of the second digital PWM circuit 12-2.

Therefore, by adjusting the first set value S12 of the first digital PWM circuit 12-1 and the second set value S22 of the second digital PWM circuit 12-2, the reference voltage Vref is 0.5 mV in the range of 0 to 5V. It can be set in units. At this time, the resolution of the reference voltage Vref, the first digital PWM circuit 12-1 duty resolution Rd ₁ = 100 and the second digital PWM circuit 12-2 duty resolution Rd ₂ = 100 a multiplying allowed resolution Rd ₁ × Rd ₂ = 100 × 100 = 10000
It becomes.

(Advantages of the second embodiment)
In this embodiment, in the reference voltage generation circuit 10 shown in FIGS. 1 and 2, the H level output voltages of the first digital PWM circuit 12-1 and the second digital PWM circuit 12-2 are both set to VH, and the L level output is performed. the voltage is 0, minus one duty resolution Rd ₁ of the first resistor 14-1 and the resistance value R1, the ratio of R2 to (R2 / R1) first digital PWM circuit 12-1 of the second resistor 14-2 By setting the value (Rd ₁ −1), that is, the first set value S11 of the first digital PWM circuit 12-1, the reference voltage Vref is set in the range of 0 to VH with the first digital PWM circuit 12-1. VH / (Rd ₁ × Rd ₂ ) divided by a value obtained by multiplying the duty resolution of the second digital PWM circuit 12-2.
Therefore, the reference voltage Vref can be controlled with high accuracy.

  Compared with the first embodiment, the ratio (R2 / R1) of the resistance values R1 and R2 of the first resistor 14-1 and the second resistor 14-2 is set with respect to the resolution of the first digital PWM circuit 12-1. Thus, it is an advantage of the second embodiment that the adjustment at the time of changing the reference voltage Vref can be adjusted with a uniform change width.

  Similarly to the first embodiment, the first and second digital PWM circuits 12-1 and 12-2 can be used with a short cycle without using an expensive digital PWM that operates with a high-speed clock. It becomes. For example, a comparison with the conventional digital PWM circuit 102 of FIG. 8 is as follows.

  First, since the first set value S1 of the first comparison circuit 106 is S1 = 3999 in the conventional example of FIG. 8, the resolution Rd is Rd = S1 + 1 = 4000, and the digital PWM circuit 102 in the case of the clock cycle Tck = 100 nS is used. The period is Tpwm = 400 μS.

On the other hand, in the present embodiment, for example, the first set value S11 of the first comparison circuit 22-1 in the first digital PWM circuit 12-1 is set to 99, and the first comparison circuit 22- in the second digital PWM circuit 12-2. First setting value S21 = 99 of 2,
(S11 + 1) × (S21 + 1) = (99 + 1) × (99 + 1) = 10000
Thus, the resolution is 10,000, and when the clock period Tck = 100 nS, the period of the rectangular wave signal from the first and second digital PWM circuits 12-1 and 12-2 is Tpwm = 10 μS.

  Therefore, in this embodiment, although the duty resolution is 2.5 times from 4000 to 10,000, the period is shortened from 400 μS to 10 μS, and the operation is performed at a frequency 40 times faster than the conventional one. I understand that. Therefore, even if the time constants of the first and second resistors 14-1 and 14-2 and the capacitor 16 connected to the outputs of the first and second digital PWM circuits 12-1 and 12-2 are reduced, the reference voltage is reduced. Since the ripple voltage of Vref can be reduced, high resolution output voltage setting, reduction of output voltage ripple voltage, and short setting voltage change time can all be achieved at low cost.

(Modification 1 of 2nd Embodiment)
In the reference voltage generation circuit according to the second embodiment, the ratio of the resistance value R1 of the first resistor 14-1 and the resistance value R2 of the second resistor 14-2 is determined as the duty resolution (Rd ₁ − of the first digital PWM circuit 12-1. In the actual circuit, the ratio of the resistance value R1 of the first resistor 14-1 and the resistance value R2 of the second resistor 14-2 is set to the first digital value as shown in the following equation (18). The above-described effect can be obtained even when the duty resolution Rd ₁ of the PWM circuit 12-1 is substantially close.
R2 / R1 ≒ Rd ₁ (18)

(Modification 2 of the second embodiment)
In the reference voltage generating circuit of the second embodiment, two digital PWM circuits are connected to capacitors via resistors, respectively. However, as shown in FIG. 4, three or more digital PWM circuits 12- One end of resistors 14-1 to 14-n is connected to each output of 1 to 12-n, and all the other ends of the resistors 14-1 to 14-n are connected to the capacitor 16, and the voltage Vref from the capacitor 16 is connected. Can be obtained.

In this case, as shown in FIG. 4, a plurality of digital PWM circuits 12-1 to 12-n and resistors 14-1 to 14-n are arranged in groups of two circuits G1 to Gn− in order so as to overlap each other. When the digital PWM circuits of an arbitrary group Gi including the i-th and i + 1-th divisions are set as the first digital PWM circuit 12-i and the second digital PWM circuit 12- (i + 1) in the arrangement order in the group, When the resolution of the first digital PWM circuit 12-i and Rd _i, in the form of the following equation resistance R _{i + 1} of the resistance value R _i and a second resistor 14- (i + 1) of the first resistor 14-i Just do it.
R _{i + 1} / R _i = Rd _i −1 (19)

As a result, the reference voltage Vref generated by the reference voltage generation circuit 10 of the present embodiment is as follows. The relationship between the resistance values R1 to Rn of the resistors 14-1 to 14-n provided in the reference voltage generation circuit 10 of the present embodiment is expressed as R2 / R1 = Rd ₁ −1.
R3 / R2 = Rd ₂ −1
...
Rn / Rn-1 = Rd _n-1 -1
Then, from the relationship of Expression (16), the reference voltage Vref by the reference voltage generation circuit 10 of this embodiment can be expressed by the following expression.
Vref = (VH · duty ₁ ) + (1 / Rd ₁ ) (VH · duty ₂ ) +
.... + (1 / Rd _n-1 ) (VH · duty _n )
(20)

  Therefore, in the modified example of the second embodiment, as in the second embodiment, all of the high-resolution output voltage setting, the reduction of the ripple voltage of the output voltage, and the short setting voltage change time can be achieved at low cost. .

Moreover, even in this case, the ratio of the resistance values R _{i + 1} of the resistance value R _i and a second resistor 14- (i + 1) of the first resistor 14-i, as shown in the following expression, the first digital PWM circuit 12 The same effect as described above can be obtained even when the duty resolution Rd _i is substantially close to −i.
R _{i + 1} / R _i ≒ Rd _i (21)

[Switching power supply]
(First Embodiment of Switching Power Supply Device)
FIG. 5 is a circuit block diagram showing a first embodiment of a switching power supply device provided with a reference voltage generating circuit according to the present invention.

  As shown in FIG. 5, the switching power supply device 30 of this embodiment includes a power converter 34, a switching element drive circuit 38, a feedback control circuit 36, and a reference voltage generation circuit 10.

  The power converter 34 includes a switching element for converting the input voltage Vin supplied from the input power supply 28 into an intermittent voltage, and a rectifying / smoothing circuit that rectifies and smoothes the intermittent voltage generated by the switching element to generate a DC output voltage Vo. Is provided inside.

  The switching element driving circuit 38 is a circuit that receives the feedback control signal FBA and generates a driving signal for the switching element, and controls the duty of the switching element. That is, the switching element driving circuit 38 is configured by a triangular wave oscillator 48 and a PWM comparator 46. When the triangular wave voltage Vtri is lower than the feedback signal FBA, the switching element is turned on, and the triangular wave voltage Vtri is higher than the feedback signal FBA. When the switching element is turned off. Thereby, when the feedback signal FBA rises, the duty of the switching element is widened, and when the feedback signal FBA falls, the duty of the switching element is narrowed.

  The feedback control circuit 36 compares the output voltage Vo and the reference voltage Vref with the error amplifier 44, and adjusts the feedback signal FBA to a predetermined value determined by the reference voltage Vref.

    That is, the error amplifier 44 decreases the feedback signal FBA when the output voltage Vo is higher than the reference voltage Vref, and increases the feedback signal FBA when the output voltage Vo is lower than the reference voltage Vref. Thereby, the output voltage Vo is controlled to be a predetermined value determined by the reference voltage Vref.

  The reference voltage generation circuit 10 is a circuit shown in the first embodiment, the modification of the first embodiment, the second embodiment, or the modification of the second embodiment shown in FIGS. By controlling the period, duty resolution, and duty of a plurality of digital PWM circuits provided in the voltage generation circuit 10, the reference voltage Vref is controlled with high accuracy and high speed response. As a result, the output voltage of the switching power supply device is controlled. A switching power supply device that is controlled with high accuracy and high-speed response and has a small output voltage ripple can be manufactured at low cost.

(Second Embodiment of Switching Power Supply Device)
FIG. 6 is a circuit block diagram showing a second embodiment of a switching power supply device provided with a reference voltage generating circuit according to the present invention.

  In the first embodiment of FIG. 5, the output of the reference voltage generation circuit 10 is connected to the feedback control circuit 36. However, in this embodiment, a predetermined value is applied to the non-inverting input of the error amplifier 44 provided in the feedback control circuit 36. Is connected to a reference voltage source 45 that generates a fixed reference voltage Vref1, and output voltage information Vo1 obtained by dividing the output voltage Vo by resistors 40 and 42 is input to the inverting input of the error amplifier 44. The reference voltage Vref is added by connecting the output of the reference voltage generation circuit 10 via a resistor 50 to the place where the voltage information Vo1 is input. Other configurations are the same as those of the first embodiment shown in FIG.

  In the switching power supply device 30 of FIG. 6, when the reference voltage Vref from the reference voltage generation circuit 10 is increased, the feedback control signal FBA from the error amplifier 44 provided in the feedback control circuit 36 is lowered, and the duty of the switching element is reduced. The output voltage Vo can be lowered by narrowing the voltage. Further, when the reference voltage Vref from the reference voltage generation circuit 10 is decreased, the feedback control signal FBA from the error amplifier 44 provided in the feedback control circuit 36 is increased, and the output voltage Vo is increased by increasing the duty of the switching element. I can do it.

  The reference voltage generation circuit 10 of the present embodiment is similar to the first embodiment of the switching power supply device of FIG. 5, the first embodiment shown in FIGS. 1 to 4, a modification of the first embodiment, the second embodiment. Alternatively, it is a circuit shown in a modification of the second embodiment, and the reference voltage is increased by controlling the period, duty resolution, and duty of a plurality of digital PWM circuits provided in the reference voltage generation circuit 10 by a digital processor or the like. As a result, it is possible to control the output voltage of the switching power supply device with high accuracy and high speed response, and to produce a switching power supply device with a small output voltage ripple at low cost.

(Third embodiment of the switching power supply device)
FIG. 7 is a circuit block diagram showing a third embodiment of a switching power supply device provided with a reference voltage generating circuit according to the present invention.

  5 and 6, the reference voltage generation circuit 10 according to the present invention is applied to the switching power supply device having the feedback control circuit 36. However, as shown in the present embodiment of FIG. 7, the switching without the feedback control circuit is used. You may apply to a power supply device.

  In the switching power supply 30 according to the third embodiment of FIG. 7, the output of the reference voltage generation circuit 10 is input to the PWM comparator 46 of the switching element drive circuit 38, whereby the duty of the switching element provided in the power conversion unit 34 is directly set. It is controlled and converted into an output voltage determined by the duty of the switching element.

  The reference voltage generation circuit 10 of the present embodiment is similar to the first and second embodiments of FIGS. 5 and 6 in the first embodiment shown in FIGS. The circuit shown in the modification of the embodiment or the second embodiment, and the reference voltage is controlled by controlling the period, duty resolution, and duty of a plurality of digital PWM circuits provided in the reference voltage generation circuit 10 by a digital processor or the like. Can be controlled with high accuracy and high speed response. As a result, the switching power supply device can be controlled with high accuracy and high speed response, and a switching power supply device with small output voltage ripple can be manufactured at low cost.

[Modification of the present invention]
The present invention is not limited to the above-described embodiment, includes appropriate modifications without impairing the object and advantages thereof, and is not limited by the numerical values shown in the above-described embodiment.

10: reference voltage generation circuit 12-1: first digital PWM circuit 12-2: second digital PWM circuit 14-1: first resistor 14-1: second resistor 15-1, 15-2: clock oscillation circuit 16 : Capacitors 20-1, 20-2: Counter circuits 22-1, 22-2: First comparison circuits 24-1, 24-2: Second comparison circuits 26-1, 26-2: RS-flip-flop circuit 28 : Input power supply 30: switching power supply device 32: load 34: power converter 36: feedback control circuit 38: switching element drive circuit 44: error amplifier 45: reference voltage source 46: PWM comparator 48: triangular wave oscillator

Claims (8)

A plurality of pulse width modulation circuits that output a rectangular wave signal whose period and duty can be set from the outside;
A plurality of resistors having one end connected to each of the outputs of the plurality of pulse width modulation circuits;
A capacitor commonly connected to the other ends of the plurality of resistors;
With
A reference voltage generation circuit comprising a configuration for extracting a voltage generated at a connection point of the plurality of resistors and capacitors as a reference voltage.
In the reference voltage generating circuit according to claim 1,
When the plurality of pulse width modulation circuits are divided into groups of two circuits in the order of arrangement so as to overlap each other, and the first pulse width modulation circuit and the second pulse width modulation circuit are arranged in order of each group, the first pulse The resistance value (Ri + 1) of the second resistor connected to the second pulse width modulation circuit is set to a sufficiently large value with respect to the resistance value (Ri) of the first resistor connected to the width modulation circuit. Reference voltage generation circuit.
In the reference voltage generating circuit according to claim 1,
The plurality of pulse width modulation circuits have a predetermined duty resolution,
When the plurality of pulse width modulation circuits are divided into groups of two circuits in the order of arrangement so as to overlap each other, and the first pulse width modulation circuit and the second pulse width modulation circuit are arranged in order of each group, the first pulse The ratio (Ri + 1 / Ri) of the resistance value (Ri) of the first resistor connected to the width modulation circuit and the resistance value (Ri + 1) of the second resistance connected to the second pulse width modulation circuit is the first pulse width modulation circuit. A reference voltage generating circuit, wherein resistance values of the first resistor and the second resistor are set so as to be substantially equal to a duty resolution of the first resistor.
In the reference voltage generating circuit according to claim 1,
The pulse width modulation circuit includes a counter circuit, a first comparison circuit, a second comparison circuit, and an output inversion circuit,
The counter circuit counts a clock signal supplied from the outside and outputs a count value, and is reset by a reset signal output from the first comparison circuit,
The first comparison circuit compares a count value of the counter circuit with a predetermined first set value set from the outside, and outputs the reset signal when the count value matches the first set value;
The second comparison circuit compares the count value of the counter circuit with a second set value set from the outside, and outputs an output inversion signal when the count value matches the second set value;
The output inverting circuit normally rotates the output when the reset signal is obtained, and outputs the rectangular wave signal by inverting the output when the output inverted signal is obtained. circuit.
A power conversion unit, a switching element drive circuit and a reference voltage generation circuit;
The power conversion unit converts the input voltage supplied by the input power source into an intermittent voltage by turning on and off the switching element and rectifies and smoothes the intermittent voltage to generate a DC voltage,
In the switching power supply device for controlling the on-duty of the switching element corresponding to the reference voltage from the reference voltage generating circuit,
The reference voltage generation circuit includes:
A plurality of pulse width modulation circuits that output rectangular voltage pulses whose period and duty can be set externally;
A plurality of resistors having one end connected to each of the outputs of the plurality of pulse width modulation circuits;
A capacitor commonly connected to the other ends of the plurality of resistors;
With
A switching power supply device comprising a configuration in which a voltage generated at a connection point of the plurality of resistors and capacitors is taken out as a reference voltage.
In the switching power supply device according to claim 5,
When the plurality of pulse width modulation circuits are divided into two groups in order so as to overlap each other, and the first pulse width modulation circuit and the second pulse width modulation circuit are arranged in order in each group, the first pulse The resistance value (Ri + 1) of the second resistor connected to the second pulse width modulation circuit is set to a sufficiently large value with respect to the resistance value (Ri) of the first resistor connected to the width modulation circuit. Reference voltage generation circuit.
In the switching power supply device according to claim 5,
The plurality of pulse width modulation circuits have a predetermined duty resolution,
When the plurality of pulse width modulation circuits are divided into two groups in order so as to overlap each other, and the first pulse width modulation circuit and the second pulse width modulation circuit are arranged in order in each group, the first pulse The ratio (Ri + 1 / Ri) of the resistance value (Ri) of the first resistor connected to the width modulation circuit and the resistance value (Ri + 1) of the second resistor connected to the second pulse width modulation circuit is the first pulse. A switching power supply device characterized in that resistance values of the first resistor and the second resistor are set so as to be substantially equal to a duty resolution of a width modulation circuit.
In the switching power supply device according to claim 5,
The pulse width modulation circuit includes a counter circuit, a first comparison circuit, a second comparison circuit, and an output inversion circuit,
The counter circuit counts a clock signal supplied from the outside and outputs a count value, and is reset by a reset signal output from the first comparison circuit,
The first comparison circuit compares a count value of the counter circuit with a predetermined first set value set from the outside, and outputs the reset signal when the count value matches the first set value;
The second comparison circuit compares the count value of the counter circuit with a second set value set from the outside that is equal to or less than the first set value, and inverts the output when the count value matches the second set value Output signal,
The output inverting circuit normally rotates the output when the reset signal is obtained and outputs a rectangular wave signal by inverting the output when the output inverted signal is obtained. A switching power supply device characterized in that:

Images