JP7177714B2 - power supply - Google Patents

Description

The present invention relates to a power supply device.

Generally, a power supply device has an output transistor provided between a terminal to which an input voltage is applied and a terminal to which an output voltage is applied, and controls the output transistor based on a feedback voltage corresponding to the output voltage and a predetermined reference voltage. It is well known that such a power supply device often performs a soft-start operation in order to reduce excessive inrush current and output voltage overshoot at startup (see Patent Document 1 below).

When a power supply device is configured using a power supply IC, the power supply IC may be provided with terminals for connecting an external capacitor for setting the soft start time. In this case, a built-in capacitor may be provided in the power supply IC in order to secure a minimum soft start time even when the external capacitor is not connected.

More specifically, some power supplies have a soft-start circuit that performs a soft-start operation to gradually increase the output voltage using a gradually increasing soft-start voltage when the power supply is started. When the power supply is started, the soft-start circuit has a first capacitor with a fixed capacitance value (equivalent to an internal capacitor) and a second capacitor with a variable capacitance value (equivalent to an external capacitor). equivalent) are individually charged with a constant charging current, and the soft start operation is performed using the lower terminal voltage of the terminal voltage of the first capacitor and the terminal voltage of the second capacitor as the soft start voltage. Then, by providing a second capacitor having a capacitance value larger than that of the first capacitor, it is possible to adjust the slope of the increase in the output voltage during the soft start operation through adjustment of the capacitance value of the second capacitor. can be done.

JP 2014-138523 A

After the soft start operation is completed, it is conceivable to perform a predetermined operation using the terminal voltage of the first or second capacitor. In this case, it is important which capacitor should be used to perform the predetermined operation. There is also Examples of the predetermined operation include a soft stop operation and a cool-down operation with hiccup-type protection, and a detailed explanation of which capacitor should be used in relation to these operations will be given later. .

In addition, in a power supply device in which a cool-down operation with hiccup type protection can be performed as a predetermined operation, it is important to effectively protect the device. Optimization of (cool-down operation) is important.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a power supply device that contributes to optimization of a predetermined operation using a capacitor that can be executed after a soft start operation is completed.

A first power supply device according to the present invention comprises an output transistor for generating an output voltage from an input voltage, and a control circuit for controlling the output transistor based on a feedback voltage corresponding to the output voltage and a predetermined reference voltage. and a soft-start circuit for executing a soft-start operation of gradually increasing the output voltage using a gradually increasing soft-start voltage at the time of starting the power supply, wherein the soft The start circuit separately charges a first capacitor having a fixed capacitance value and a second capacitor having a variable capacitance value with a constant charging current at the time of starting the power supply device. and the terminal voltage of the second capacitor, the lower one of the terminal voltage is used as the soft start voltage to execute the soft start operation, and the power supply device performs the soft start operation after the end of the soft start operation under a predetermined condition is established, a specific circuit that performs a predetermined operation using either one of the terminal voltage of the first capacitor and the terminal voltage of the second capacitor, and corresponding to the lower terminal voltage in the soft start operation a target capacitance setting circuit for setting the target capacitance to the target capacitance, wherein the specific circuit uses the terminal voltage of the capacitance set as the target capacitance, out of the first capacitance and the second capacitance, and the It is characterized by executing a predetermined operation.

Specifically, for example, in the first power supply device, the predetermined operation is performed using a gradually falling soft stop voltage when receiving a stop instruction signal instructing to stop the operation of the power supply device. a soft-stop operation for gradually decreasing the output voltage, the specific circuit including a soft-stop circuit for executing the soft-stop operation, and the soft-stop circuit being accumulated by the soft-start operation in the soft-stop operation; It is preferable to discharge the accumulated electric charge of the target capacity with a constant discharge current, and use the terminal voltage of the target capacity in the process of discharging as the soft stop voltage.

At this time, for example, in the first power supply device, the soft stop circuit reduces only the capacity set as the target capacity, out of the first capacity and the second capacity, to the discharge constant in the soft stop operation. It is better to discharge with electric current.

Alternatively, for example, in the first power supply device, the soft stop circuit discharges the accumulated charges of both the first capacitor and the second capacitor individually with the discharge constant current in the soft stop operation. , regardless of the terminal voltage of the non-objective capacity different from the capacity set as the object capacity, among the first capacity and the second capacity, the terminal voltage of the target capacity in the process of discharging is equal to the soft stop voltage. You can use it as

Specifically, for example, in the first power supply device, the control circuit controls the output transistor based on the feedback voltage and the soft stop voltage when the soft stop operation is being performed, After the soft start operation is completed, the output transistor may be controlled based on the feedback voltage and the reference voltage when the soft stop operation is not being performed.

Further, for example, the first power supply device may further include an abnormality detection circuit for detecting the presence or absence of a predetermined abnormality. Later, when the abnormality is detected, a cool-down operation is performed to keep the output transistor off, and then the power supply device is restarted with the soft-start operation again, and the predetermined operation is , the specific circuit includes a cool-down circuit for performing the cool-down operation, the cool-down circuit includes a first parallel switch connected in parallel to the first capacitor, and the first a second parallel switch connected in parallel to two capacitors, wherein in the cool-down operation, a unit operation is repeatedly performed a predetermined number of times, and each unit operation is performed by the first parallel switch and the second parallel switch; a discharge operation of discharging the charge accumulated in the target capacitor until a terminal voltage of the target capacitor becomes lower than a predetermined discharge completion voltage by turning on a parallel switch among the switches, which is connected in parallel to the target capacitor; a charging operation of charging the target capacity with the constant current for charging until a terminal voltage of the target capacity becomes higher than a predetermined charge completion voltage while turning off a parallel switch connected in parallel to the target capacity through a discharging operation; , preferably consisting of

At this time, for example, in the first power supply device, the cool-down circuit is set to the target capacity of the first capacity and the second capacity in the discharging operation and the charging operation during the cool-down operation. It is better to discharge and charge only the charged capacity.

Alternatively, for example, in the first power supply device, the cool-down circuit turns on both the first parallel switch and the second parallel switch in the discharge operation during the cool-down operation, but the first parallel switch is turned on. The target capacity is accumulated until the terminal voltage of the target capacity becomes lower than the discharge completion voltage regardless of the terminal voltage of the non-target capacity, which is different from the capacity set as the target capacity, among the capacity and the second capacity. Electric charges may be discharged.

Further, specifically, for example, in the first power supply device, the abnormality detection circuit causes the feedback voltage to fall to a predetermined protection determination voltage after the soft start operation executed at the time of starting the power supply device ends. The abnormality may be detected when the lower state continues for a predetermined period of time.

Further, for example, in the first power supply device, the control circuit preferably controls the output transistor based on the feedback voltage and the soft start voltage when the soft start operation is being performed.

At this time, for example, in the first power supply device, the target capacity setting circuit selects the lower of the terminal voltage of the first capacity and the terminal voltage of the second capacity in the process of charging with the charging constant current. one terminal voltage is compared with a predetermined soft-start completion determination voltage, and the terminal voltage of the first capacitor and the terminal voltage of the second capacitor when the lower terminal voltage becomes higher than the soft-start completion determination voltage. It is preferable to set the target capacity based on the comparison result.

A second power supply device according to the present invention comprises an output transistor for generating an output voltage from an input voltage, and a control circuit for controlling the output transistor based on a feedback voltage corresponding to the output voltage and a predetermined reference voltage. and a soft-start circuit for executing a soft-start operation to gradually increase the output voltage using a gradually increasing soft-start voltage at the time of starting the power supply device, and an abnormality for detecting the presence or absence of a predetermined abnormality. a detection circuit; and a cool-down circuit that performs a cool-down operation to keep the output transistor off when the abnormality is detected, wherein the soft-start circuit prevents electrostatic A first capacitor having a fixed capacitance value and a second capacitor having a variable capacitance value are individually charged with a constant charging current, and the terminal voltage of the first capacitor and the terminal voltage of the second capacitor are: The soft-start operation is performed using the lower terminal voltage as the soft-start voltage, and when the abnormality is detected after starting the power supply device, the soft-start operation is performed again after the cool-down operation. wherein the power supply is restarted with the cool-down circuit having a first parallel switch connected in parallel with the first capacitor and a second parallel switch connected in parallel with the second capacitor; In the cool-down operation, a unit operation is repeatedly performed a predetermined number of times, one or more times, and each unit operation turns on the first parallel switch and the second parallel switch, thereby turning on the terminal of the first capacitor. a discharge operation for discharging the charges accumulated in the first capacitor and the second capacitor until both the voltage and the terminal voltage of the second capacitor become lower than a predetermined discharge completion voltage; and the first parallel switch after the discharge operation. and while turning off each of the second parallel switches, each of the first capacitor and the second capacitor is operated until both the terminal voltage of the first capacitor and the terminal voltage of the second capacitor become higher than a predetermined charging completion voltage. and a charging operation of charging with the constant current for charging.

Specifically, for example, in the second power supply device, the abnormality detection circuit detects that the feedback voltage is lower than a predetermined protection judgment voltage after the soft start operation executed at the time of starting the power supply device ends. The abnormality may be detected when the low state continues for a predetermined time.

Further, for example, in the second power supply device, the control circuit preferably controls the output transistor based on the feedback voltage and the soft start voltage when the soft start operation is being performed.

Further, for example, the first or second power supply device is configured using a power supply IC formed by enclosing a semiconductor integrated circuit in a housing, and the power supply IC has an external terminal to which an external capacitor can be connected. wherein the first capacitor is formed by a capacitor built into the power supply IC, and when the external capacitor is connected to the external terminal, the second capacitor is formed by the external capacitor, It is preferable that the inclination of the rise of the output voltage in the soft start operation can be adjusted by adjusting the capacitance value of the external capacitor.

According to the present invention, it is possible to provide a power supply device that contributes to optimization of a predetermined operation using a capacitor that can be executed after the soft start operation ends.

1 is an overall configuration diagram of a switching power supply device according to an embodiment of the present invention; FIG. 1 is an external view of a switching power supply IC according to an embodiment of the present invention; FIG. FIG. 4 is an operation explanatory diagram of the constant on-time control system according to the embodiment of the present invention; 2 is a configuration diagram (a) and an operation waveform diagram (b) of the ripple voltage generation circuit of FIG. 1; FIG. 2 is a configuration diagram of an SS circuit in FIG. 1; FIG. FIG. 2 is a conceptual diagram of an operation using a built-in capacitor (C _INT ) realized by the SS circuit of FIG. 1; FIG. 2 is a conceptual diagram of the operation using an external capacitor (C _EXT ) realized by the SS circuit of FIG. 1; FIG. 2 is a waveform diagram relating to the switching power supply device of FIG. 1 and focusing on soft start operation and acquisition of mask information (case of “C _INT >C _EXT ”). FIG. 2 is a waveform diagram relating to the switching power supply device of FIG. 1 and focusing on soft start operation and acquisition of mask information (case of “C _INT <C _EXT ”). FIG. 10 is a waveform diagram focusing on the soft stop operation (case of “C _INT >C _EXT ”) according to the first embodiment of the present invention; FIG. 10 is a waveform diagram focusing on a soft stop operation (case of “C _INT <C _EXT ”) according to the first embodiment of the present invention; 9 is an operation flowchart of a switching power supply device according to a third embodiment of the present invention; FIG. 10 is a waveform diagram of cool-down operation according to the reference power supply device; FIG. 10 is a diagram showing how a switching period and a cool-down period are alternately repeated in a reference power supply device; FIG. 10 is a waveform diagram focusing on cool-down operation according to the third embodiment of the present invention; FIG. 11 is a configuration diagram of a cool-down determination circuit according to a fifth embodiment of the present invention; FIG. 11 is an operation flowchart of a switching power supply device according to a fifth embodiment of the present invention; FIG. It is a partial block diagram of the power supply device which concerns on 7th Example of this invention. FIG. 11 is a partial configuration diagram of another power supply device according to a seventh embodiment of the present invention; FIG. 11 is an external view of a copying machine according to an eighth embodiment of the present invention;

Hereinafter, examples of embodiments of the present invention will be specifically described with reference to the drawings. In each figure referred to, the same parts are denoted by the same reference numerals, and redundant descriptions of the same parts are omitted in principle. In this specification, for simplification of description, by describing symbols or codes that refer to information, signals, physical quantities, or members, etc., the names of information, signals, physical quantities, or members, etc. corresponding to the symbols or codes are It may be omitted or abbreviated. For example, a switching power supply IC referred to by "100" to be described later may be referred to as switching power supply IC100, or may be abbreviated as power supply IC100 or IC100, all of which refer to the same thing.

FIG. 1 is an overall configuration diagram of a switching power supply AA according to an embodiment of the present invention. The switching power supply device AA of FIG. 1 includes a switching power supply IC 100 and a plurality of discrete components externally connected to the switching power supply IC 100. The plurality of discrete components include capacitors C1 to C3 and a capacitor C _EXT . , resistors R1, R2 and inductor L1. The switching power supply AA is configured as a step-down switching power supply that generates a desired output voltage Vout from a desired input voltage Vin. The input voltage Vin and the output voltage Vout are positive DC voltages, and the output voltage Vout is lower than the input voltage Vin. An output voltage Vout appears at the output terminal OUT of the switching power supply AA. Here, it is assumed that the input voltage Vin is 12V. By adjusting the resistance values of the resistors R1 and R2, the output voltage Vout can be given a desired positive voltage value (for example, 1V or 5V) less than 12V.

The switching power supply IC 100 is an electronic component formed by enclosing a semiconductor integrated circuit in a housing (package) made of resin, as shown in FIG. A plurality of external terminals are exposed on the housing of the IC 100, and the plurality of external terminals include an enable terminal EN, a terminal SS, a feedback terminal FB, a bootstrap terminal BOOT, and an input terminal VIN, which are shown in FIG. , a switch terminal SW and a ground terminal GND. Terminals other than these may also be included in the plurality of external terminals. It should be noted that the number of external terminals of IC 100 shown in FIG. 2 is merely an example.

First, the external configuration of the switching power supply IC 100 will be described. An input voltage Vin is supplied to the input terminal VIN from the outside of the IC 100, and the input terminal VIN is connected to the ground through the capacitor C1. The switch terminal SW is connected to one end of the inductor L1, and the other end of the inductor L1 is connected to the output terminal OUT of the switching power supply AA. The output terminal OUT is connected to one end of the resistor R1, and the other end of the resistor R1 is grounded through the resistor R2. Also, the output terminal OUT is connected to the ground via the output capacitor C3. A bootstrap terminal BOOT is connected to the switch terminal SW via a capacitor C2. Terminal SS is connected to ground through a capacitor C _EXT , and ground terminal GND is directly connected to ground. A connection node between the resistors R1 and R2 is connected to the feedback terminal FB. Ground refers to a conductive part having a reference potential of 0 V (zero volts) or refers to the reference potential itself. In this embodiment, voltages shown without any particular reference represent potentials as seen from ground.

Next, the internal configuration of the switching power supply IC 100 will be described. The switching power supply IC 100 includes transistors 1a and 1b configured as N-channel MOSFETs (Metal Oxide Semiconductor Field effect transistors), drivers 2a and 2b, a main control circuit 3, an internal power supply voltage generation circuit 4, and a diode 5. , SS circuit 6, reference voltage generation circuit 7, error amplifier 8, ripple voltage generation circuit 9, addition circuit 10, main comparator 11, overcurrent protection circuit 12, short circuit protection circuit 13, overvoltage It comprises a protection circuit 14 , an undervoltage lockout circuit 15 , a thermal shutdown circuit 16 and an enable circuit 17 . The main control circuit 3 includes an on-timer circuit 21 and a drive logic circuit 22 .

The transistors 1a and 1b are a pair of switching elements connected in series between the input terminal VIN and the ground terminal GND (in other words, the ground). A rectangular wave switch voltage Vsw appears at the terminal SW. A transistor 1a is provided on the high side, and a transistor 1b is provided on the low side. Specifically, the drain of the transistor 1a is connected to the input terminal VIN, the source of the transistor 1a and the drain of the transistor 1b are commonly connected to the switch terminal SW, and the source of the transistor 1b is grounded.

Transistor 1a functions as an output transistor and transistor 1b functions as a synchronous rectification transistor. The inductor L1 and the output capacitor C3 constitute a rectifying/smoothing circuit that rectifies and smoothes the square-wave switch voltage Vsw appearing at the switch terminal SW to generate the output voltage Vout. Resistors R1 and R2 form a voltage dividing circuit that divides the output voltage Vout. By connecting the connection node between the resistors R1 and R2 to the feedback terminal FB, the divided voltage appearing at the connection node between the resistors R1 and R2 is input to the feedback terminal FB as the feedback voltage Vfb. Capacitor C2 forms a bootstrap circuit together with diode 5 built into IC100. Although the switching power supply IC 100 employs a synchronous rectification method, a diode rectification method may be employed. In this case, the transistor 1b and the driver 2b may be eliminated from the IC100, and instead, a rectifying diode (not shown) may be provided inside or outside the IC100. In the rectifier diode, the cathode will be connected to the switch terminal SW and the anode will be connected to the ground.

The driver 2 a controls the gate voltage Ga of the transistor 1 a based on the control signal Cnta input from the main control circuit 3 . Driver 2 b controls gate voltage Gb of transistor 1 b based on control signal Cntb input from main control circuit 3 . The control signals Cnta and Cntb and the gate voltages Ga and Gb each have a high-level or low-level potential. For any signal or voltage, a high level has a higher potential than a low level. The driver 2a sets the gate voltage Ga to high level and low level when the control signal Cnta is high level and low level, respectively. The driver 2b sets the gate voltage Gb to a high level and a low level when the control signal Cntb is at a high level and a low level, respectively. The transistor 1a is turned on (that is, conductive between the drain and source) when the gate voltage Ga is high level, and turned off (that is, non-conductive between the drain and source) when it is low level. Similarly, the transistor 1b is turned on when the gate voltage Gb is high level and turned off when it is low level.

A drive voltage Vboot (for example, 17 V) higher than the input voltage Vin (here, 12 V) is applied to the upper power supply terminal of the driver 2a, and the lower power supply terminal of the driver 2a is connected to the switch terminal SW. The high level and low level of the gate voltage Ga output from 2a become the drive voltage Vboot and the switch voltage Vsw, respectively. A level shifter provided in the driver 2a performs level shifting to raise the voltage level of the control signal Cnta, and the gate voltage Ga is generated from the voltage obtained by level-shifting the control signal Cnta. It should be noted that the level shifter may be considered to be inserted between the driver 2a and the main control circuit 3. FIG. An internal power supply voltage Vreg (for example, 5 V) is applied to the upper power supply terminal of the driver 2b, and the lower power supply terminal of the driver 2b is connected to the ground. The low level is the internal power supply voltage Vreg and the ground voltage, respectively.

Based on the comparison result signal CMP from the main comparator 11, the main control circuit 3 uses the on-timer circuit 21 and the drive logic circuit 22 to generate and output control signals Cnta and Cntb. At this time, the transistor 1b is turned off during the period during which the transistor 1a is turned on (hereinafter referred to as the output on period), and the transistor 1b is turned on during the period during which the transistor 1a is turned off (hereinafter referred to as the output off period). Also, the control signal Cntb is an inverted signal of the control signal Cnta. However, in order to reliably prevent the transistors 1a and 1b from being turned on at the same time, a dead time period during which the transistors 1a and 1b are turned off at the same time is appropriately inserted. Although the detailed operation will be described later, the IC 100 employs a constant on-time control method. Therefore, by alternately switching between a fixed-length output-on period during which the transistor 1a is turned on and a variable-length output-off period during which the transistor 1a is turned off, a current is caused to flow through the inductor L1. Vout will be generated.

The internal power supply voltage generating circuit 4 generates a direct current positive internal power supply voltage Vreg (eg, 5V) from the input voltage Vin. The internal power supply voltage Vreg is supplied to each part in the IC 100 as a drive voltage.

The anode of diode 5 is supplied with internal power supply voltage Vreg, and the cathode of diode 5 is connected to bootstrap terminal BOOT. A bootstrap circuit is formed by the diode 5 and the capacitor C2, and a drive voltage Vboot higher than the input voltage Vin is drawn from the cathode of the diode 5. FIG.

The SS circuit 6 includes a soft start circuit. The soft-start circuit generates a slope-shaped soft-start voltage that gradually rises from 0 V (volt) when the switching power supply AA is activated (in other words, when the switching power supply IC 100 is activated). Output to the main comparator 11 as Vss. As a result, when the switching power supply AA is started, output feedback control is performed by comparing the gently rising voltage Vss with a feedback voltage Vfb' with ripple, which will be described later, so that the output voltage Vout gradually rises. As a result, it is possible to suppress the overshoot of the output voltage Vout and the inrush current.

The operation of gradually increasing the output voltage Vout using the voltage Vss as the soft start voltage is called a soft start operation. Here, it is considered that the soft-start operation is mainly performed by the soft-start circuit, but the soft-start circuit in the SS circuit 6 cooperates with other circuits (including the main comparator 11 and the main control circuit 3) responsible for output feedback control. It can also be considered that the soft-start operation is realized by working.

The SS circuit 6 further includes a soft stop circuit. When stopping the operation of the switching power supply AA (in other words, when stopping the operation of the switching power supply IC 100), the soft stop circuit provides a slope-shaped soft stop voltage that gradually drops from a positive predetermined voltage toward 0V. and outputs the soft stop voltage to the main comparator 11 as the voltage Vss. As a result, when stopping the operation of the switching power supply AA, the output feedback control is performed by comparing the gradually falling voltage Vss with a feedback voltage Vfb' with ripple, which will be described later. ) is obtained. There are cases in which a sharp drop in the output voltage Vout is not desired due to the abrupt discharge of the output capacitor C3, and there are cases in which a steep drop in the output voltage Vout is not desired depending on the load connected to the output terminal OUT. A soft-stop circuit works beneficially in such cases.

The operation of gradually lowering the output voltage Vout using the voltage Vss as the soft stop voltage is called a soft stop operation. Here, it is considered that the soft stop operation is mainly performed by the soft stop circuit. It can also be considered that the soft stop operation is realized by working.

The soft start voltage and soft stop voltage may be generated from the terminal voltage of a capacitor C _EXT externally connected to the power supply IC 100, or from the terminal voltage of a capacitor (not shown in FIG. 1) built into the power supply IC 100. The circuit and method for generating the soft start voltage and soft stop voltage will be described in detail later.

Reference voltage generating circuit 7 generates a predetermined reference voltage Vref using internal power supply voltage Vreg. Reference voltage Vref is a positive DC voltage having a predetermined voltage value.

The error amplifier 8 receives the reference voltage Vref and the feedback voltage Vfb applied to the feedback terminal FB. The error amplifier 8 outputs to the main comparator 11 an error voltage Verr corresponding to the error between the feedback voltage Vfb and the reference voltage Vref. The error amplifier 8 generates an error voltage Verr so that the feedback voltage Vfb matches the reference voltage Vref, and when the feedback voltage Vfb drops relative to the reference voltage Vref, the error voltage Verr increases while the feedback voltage Vfb increases. When it does, it operates to lower the error voltage Verr.

The ripple voltage generation circuit 9 generates a ripple voltage Vrip that is a triangular pulsating voltage.

The adder circuit 10 adds the ripple voltage Vrip to the feedback voltage Vfb applied to the feedback terminal FB, and converts the voltage obtained by this addition (that is, the composite voltage having the voltage value of the sum of the feedback voltage Vfb and the ripple voltage Vrip). , to the main comparator 11 as a feedback voltage Vfb' with ripple.

The main comparator 11 has first and second non-inverting input terminals and an inverting input terminal. Verr and feedback voltage Vfb' with ripple are input. The main comparator 11 uses the lower voltage of the input voltages to the first and second non-inverting input terminals as the first comparison voltage, and the input voltage to the inverting input terminal as the second comparison voltage. The voltage and the second comparison voltage are compared, and a comparison result signal CMP indicating the comparison result is output. The comparison result signal CMP becomes high level when the first comparison voltage is higher than the second comparison voltage, and becomes low level when the second comparison voltage is higher than the first comparison voltage. When the first and second comparison voltages exactly match, the comparison result signal CMP becomes either low level or high level.

When the soft start operation is performed, the voltage Vss is lower than the error voltage Verr, the voltage Vss becomes the first comparison voltage, and the comparison result between the voltage Vss and the feedback voltage Vfb' with ripple is the comparison result signal. Appears in CMP.
After that, in a steady state after the soft start operation is finished, the voltage Vss is kept higher than the error voltage Verr (because the SS circuit 6 operates in this way), so the error voltage Verr and the feedback voltage with ripple The comparison result with Vfb' appears in the comparison result signal CMP. The steady state refers to a state after the end of the soft-start operation and before the start of the soft-stop operation, in which an abnormality including short-circuiting of the output terminal OUT does not occur. A state in which a cool-down operation, which will be described later, is performed does not belong to the steady state. In a steady state, the error amplifier 8 adjusts the error voltage Verr so that the feedback voltage Vfb matches the reference voltage Vref, whereby the output voltage Vout is a constant voltage corresponding to the voltage dividing ratio by the resistors R1 and R2 and the reference voltage Vref. will be stabilized at

When the soft stop operation is performed through the steady state, the voltage Vss drops toward 0 V and becomes lower than the error voltage Verr. A comparison result between the voltage Vss and the feedback voltage Vfb' with ripple appears in the comparison result signal CMP.

The overcurrent protection circuit 12 detects whether overcurrent is flowing through the transistors 1a and 1b. The short circuit protection circuit 13 detects whether there is an abnormal drop in the feedback voltage Vfb. The overvoltage protection circuit 14 detects whether or not there is an abnormal rise in the feedback voltage Vfb. The low voltage lockout circuit 15 detects whether or not the input voltage Vin has abnormally decreased. The thermal shutdown circuit 16 detects whether the temperature inside the IC 100 has risen abnormally. The main control circuit 3 forcibly turns off the transistors 1a and 1b or shuts down the IC 100 as necessary based on the detection results of the circuits 12-16. The enable circuit 17 outputs an enable output signal EN _OUT to the main control circuit 3 according to the level of the enable _input signal EN _IN supplied to the enable terminal EN. Activate or shutdown IC 100. Only when IC 100 is active is switching of transistors 1a and 1b as described above to produce output voltage Vout.

The operation of the constant on-time control method will be described with reference to FIG. FIG. 3 shows each signal waveform in a steady state where "Vss>Verr" and the output voltage Vout is stabilized. At this time, the feedback voltage Vfb is also substantially constant, and the rippled feedback voltage Vfb' obtained by injecting the triangular ripple voltage Vrip into the feedback voltage Vfb is a pulsating voltage.

Consider the state where the control signal Cnta is at low level and "Vfb'>Verr" as a starting point. When "Vfb'<Verr" at timing t1 from this state, the level of the comparison result signal CMP from the main comparator 11 switches from low level to high level. When the comparison result signal CMP switches from the low level to the high level, at the switching timing t1, the drive logic circuit 22 switches the level of the control signal Cnta from the low level to the high level. Elapsed time measurement is started, and a one-shot pulse signal (single pulse signal) is output to the drive logic circuit 22 at timing t2 when a predetermined ON time Ton has elapsed from timing t1. When the drive logic circuit 22 receives the one-shot pulse signal, it switches the level of the control signal Cnta from high level to low level. Thereafter, similar operations are repeated. The ON time Ton is a predetermined fixed time. The ON time Ton may be determined based on the input voltage Vin and the output voltage Vout (in this case, the IC 100 should be provided with an external terminal for receiving the output voltage Vout).

After the timing t2, the timing t3 is the timing at which the control signal Cnta switches from the low level to the high level by switching from the state of "Vfb'>Verr" to "Vfb'<Verr" next time. and t2 is an output ON period, and between timings t2 and t3 is an output OFF period. Output-on periods and output-off periods alternately occur, and a rectangular-wave switching voltage Vsw is generated at the switch terminal SW, and the switching voltage Vsw is rectified and smoothed to obtain the output voltage Vout. The ratio of the on-time Ton to the total time of the on-time Ton, which is the length of the output-on period, and the off-time Toff, which is the length of the output-off period, is called the output duty. The on-time Ton has a fixed length, while the off-time Toff varies.

According to the constant on-time control method using the injection of ripple voltage as described above, stable switching control can be performed even if the ripple component of the output voltage Vout is not so large. It is possible to use a multilayer ceramic capacitor with a small equivalent series resistance (ESR).

A predetermined lower limit is set for the length of the output OFF period, and after the timing t2, an output OFF period equal to or longer than the lower limit is ensured regardless of the level of the comparison result signal CMP. Therefore, for example, even if the comparison result signal CMP is high level at the timing t2, or if the comparison result signal CMP is low level at the timing t2, the comparison result is not obtained before the above lower limit length elapses from the timing t2. Even if the signal CMP becomes high level, the control signal Cnta is maintained at low level until the above lower limit length elapses from timing t2, and the control signal Cnta is kept high after the above lower limit length elapses from timing t2. considered to be a level.

An example of the ripple voltage generation circuit 9 is shown in FIG. The ripple voltage generating circuit 9 of FIG. 4(a) is composed of resistors 101 to 103 and a capacitor 104. In FIG. A switching voltage _VSW is divided by a series circuit of resistors 101 and 102, a node 105 to which the divided voltage is applied is connected to one end of a capacitor 104 via a resistor 103, and the other end of the capacitor 104 is grounded. . A voltage at a connection node between the capacitor 104 and the resistor 103 becomes a triangular ripple voltage Vrip. FIG. 4(b) shows waveforms of the voltage at the node 105 and the ripple voltage _Vrip along with the waveform of the switching voltage VSW.

FIG. 5 shows an internal configuration diagram of the SS circuit 6. As shown in FIG. The SS circuit 6 includes slope voltage generation circuits 110 and 120 , an SS control circuit 130 , an SS selection circuit 140 and an SS setting circuit 150 . These circuits implement the soft-start circuit and the soft-stop circuit described above, and the details thereof will become apparent from the description given later.

The slope voltage generating circuit 110 includes a charging constant current source 111, a discharging constant current source 112, a charging switch 113, a discharging switch 114, and a strong discharging switch. 115 and a capacitor _{C_INT} . In this embodiment, an arbitrary switch is composed of one or more FETs (Field Effect Transistors). Sometimes there is no conduction between the terminals of the switch.

A capacitor C _INT is a capacitor built in the power supply IC 100 . One end of the capacitor _CINT is commonly connected to one end of each of the switches 113 to 115 at the node 116, and the other ends of the switches 113, 114 and 115 are respectively connected to the constant current source 111, the constant current source 112 and the ground. . The other end of capacitor _CINT is connected to ground. The voltage at node 116 corresponding to the voltage across capacitor C _INT (in other words, the voltage across capacitor C _INT ) is referred to as voltage SS_INT.

Constant current source 111 operates based on internal power supply voltage Vreg, and outputs constant current _II1 toward node 116 from a terminal to which internal power supply voltage Vreg is applied. However, a switch 113 is interposed between the constant current source 111 and the node 116, and the constant current _II1 from the constant current source 111 flows toward the node 116 only when the switch 113 is on. Constant current _II1 does not flow when switch 113 is off.

Constant current source 112 operates based on internal power supply voltage Vreg and outputs constant current _II2 from node 116 toward the ground. However, a switch 114 is interposed between the node 116 and the constant current source 112, and the constant current _II2 from the constant current source 112 flows from the node 116 toward the ground only when the switch 114 is on. , the constant current _II2 does not flow when the switch 114 is off. The values of the constant currents _I11 and _I22 may match each other or may differ from each other.

The switches 113 to 115 are controlled to be on and off by the SS control circuit 130 . The SS control circuit 130 never turns on two or more of the switches 113 to 115 at the same time. Under the control of the SS control circuit 130, SS_INT soft rising operation, SS_INT soft falling operation, and SS_INT strong falling operation are realized.
As shown in FIG. 6(a), in the _{SS_INT} soft rise operation, switch 113 is turned on and switches 114 and 115 are turned off, and constant current II1 from constant current source 111 is applied to switch 113 and node 116 as a charging constant current. , and the voltage _{SS_INT} gradually rises. However, the increase in voltage _{SS_INT} is limited to a positive predetermined voltage VUL lower than the internal reference voltage Vreg, and voltage _{SS_INT} never rises above the predetermined voltage VUL.
As shown in FIG. 6(b), in the SS_INT soft-fall operation, switch 114 is turned on and switches 113 and 115 are turned off, and if voltage SS_INT is higher than 0V, the stored charge on capacitor _{C_INT} will flow at constant current _II2 . It is discharged and the voltage SS_INT gradually drops. However, the drop of the voltage SS_INT is limited to 0V (zero volts), and the voltage SS_INT never falls below 0V.
As shown in FIG. 6(c), in the SS_INT strong falling operation, the switch 115 is turned on and the switches 113 and 114 are turned off, and the accumulated charge of the capacitor _{C_INT} is rapidly discharged through the switch 115, and the capacitor _{C_INT} The voltage SS_INT, which is the terminal voltage of , drops rapidly toward 0V.

The slope voltage generation circuit 120 includes a charging constant current source 121, a discharging constant current source 122, a charging switch 123, a discharging switch 124, and a strong discharging switch. 125 and a capacitor C _EXT .

However, the capacitor C _EXT is a capacitor that can be externally connected to the power supply IC 100, and it is possible that the capacitor C _EXT is not connected to the terminal SS. Also, while the capacitance value of the capacitor _{C_INT} is fixed, capacitors having various capacitance values can be connected to the terminal SS as the capacitor _{C_EXT} , so that the capacitance of the capacitor _{C_EXT} is Value is variable. Therefore, it can be said that the capacitor C _INT functions as a first capacitor with a fixed capacitance value, and the capacitor C _EXT functions as a second capacitor with a variable capacitance value _. , the second capacitance is understood to be the intrinsic capacitance that exists between the terminal SS and ground even if the terminal SS is not connected to the capacitor _{C_EXT} . The inherent capacitance includes the parasitic capacitance between the terminal SS and the ground, and includes the minute capacitance if a minute capacitance is intentionally formed between the terminal SS and the ground inside the power supply IC 100 . In the following description, it is assumed that the capacitor _{C_EXT} is connected to the terminal SS unless otherwise specified.

One end of the capacitor C _EXT is commonly connected to one end of each of the switches 123 to 125 at the node 126, and the other ends of the switches 123, 124 and 125 are respectively connected to the constant current sources 121, 122 and ground. . The other end of capacitor C _EXT is connected to ground. The voltage at node 126 corresponding to the voltage across capacitor C _EXT (in other words, the voltage across capacitor C _EXT ) is referred to as voltage SS_EXT. Node 126 and terminal SS refer to the same thing.

Constant current source 121 operates based on internal power supply voltage Vreg, and outputs constant current _IE1 toward node 126 from a terminal to which internal power supply voltage Vreg is applied. However, a switch 123 is interposed between the constant current source 121 and the node 126, and the constant current _IE1 from the constant current source 121 flows toward the node 126 only when the switch 123 is on. Constant current _IE1 does not flow when switch 123 is off.

Constant current source 122 operates based on internal power supply voltage Vreg and outputs constant current _IE2 from node 126 to the ground. However, a switch 124 is interposed between the node 126 and the constant current source 122, and the constant current _IE2 from the constant current source 122 flows from the node 126 to the ground only when the switch 124 is on. , the constant current _IE2 does not flow when the switch 124 is off. The values of the constant currents I _E1 and I _E2 may match each other or may differ from each other.

The switches 123 to 125 are controlled to be on or off by the SS control circuit 130 . The SS control circuit 130 never turns on two or more of the switches 123 to 125 at the same time. Under the control of the SS control circuit 130, SS_EXT soft rising operation, SS_EXT soft falling operation, and SS_EXT strong falling operation are realized.
As shown in FIG. 7(a), in the _{SS_EXT} soft rise operation, switch 123 is turned on and switches 124 and 125 are turned off, and constant current IE1 from constant current source 121 is applied to switch 123 and node 126 as a charging constant current. , and the voltage _{SS_EXT} gradually rises. However, the rise of voltage _{SS_EXT} is limited to a positive predetermined voltage VUL lower than internal reference voltage Vreg, and voltage _{SS_EXT} does not rise beyond predetermined voltage VUL.
As shown in FIG. 7(b), in the SS_EXT soft fall operation, switch 124 is turned on and switches 123 and 125 are turned off, and if voltage _{SS_EXT} is higher than 0V, the stored charge on capacitor C _EXT is It is discharged and the voltage SS_EXT gradually drops. However, the drop of the voltage SS_EXT is limited to 0V (zero volts), and the voltage SS_EXT never falls below 0V.
As shown in FIG. 7(c), in the SS_EXT strong falling operation, the switch 125 is turned on and the switches 123 and 124 are turned off, so that the accumulated charge on the capacitor C _EXT is rapidly discharged through the switch 125, and the capacitor C _EXT The voltage SS_EXT, which is the terminal voltage of , drops rapidly toward 0V.

The constant currents _I11 and _IE1 can be different, but here the constant currents _I11 and _IE1 are assumed to match each other. Similarly, the constant currents _I12 and _IE2 can be different, but here the constant currents _I12 and _IE2 are assumed to match each other.

The SS control circuit 130 implements various operations including soft start operation, soft stop operation and cool down operation through on/off control of switches 113-115 and 123-125. At this time, signals SS_INT_MASK and SS_EXT_MASK can be referred to (details will be described later).

The SS selection circuit 140 has a function of comparing the voltages SS_INT and SS_EXT, and outputs the lower one of the voltages SS_INT and SS_EXT to the main comparator 11 as the voltage Vss.

The SS setting circuit 150 includes comparators 151 and 152, a one-shot pulse circuit 153, and holding circuits 154 and 155. The comparators 151 and 152 effectively operate when the signal PROTON, which will be described later, is at low level. A signal PROTON is generated by the main control circuit 3 and has a potential of high level or low level. As noted above, for any signal or voltage, a high level has a higher potential than a low level. In any signal or voltage, switching from low level to high level is called up edge, and timing of switching from low level to high level is called up edge timing. Similarly, in any signal or voltage, the switching from high level to low level is called down edge, and the timing of switching from high level to low level is called down edge timing.

The comparator 151 compares the voltages SS_INT and SS_EXT and outputs a signal SS_CMP indicating the comparison result. At this time, if the voltage SS_INT is higher than the voltage SS_EXT, a high level signal SS_CMP is output, and if the voltage SS_INT is lower than the voltage SS_EXT, a low level signal SS_CMP is output. When "SS_EXT=SS_INT", the level of the signal SS_CMP is either high level or low level. However, the signal SS_END_oneshot, which will be described later, is input to the comparator 151 as a control signal, and after the down edge of the signal SS_END_oneshot occurs, the level of the signal SS_CMP is maintained at the low level regardless of the voltages SS_INT and SS_EXT. do.

The comparator 152 receives inputs of the voltages SS_INT and SS_EXT and the positive reference voltage SS_REF, and treats the lower one of the voltages SS_INT and SS_EXT as the non-inverting voltage and the reference voltage SS_REF as the inverting voltage. If the voltage is higher than the inverting side voltage, a high level signal SS_END is output, and if the non-inverting side voltage is lower than the inverting side voltage, a low level signal SS_END is output. When the non-inverting side voltage matches the inverting side voltage, the level of the signal SS_END becomes either high level or low level.

The reference voltage SS_REF includes a reference voltage SS_REF _H (eg, 690 mV) and a reference voltage SS_REF _L (eg, 50 mV) lower than the reference voltage SS_REF _H. The reference voltage SS_REF _H functions as a threshold for judging whether or not the voltages SS_INT and SS_EXT have sufficiently increased in the process of increasing. Therefore, when the SS_INT soft rise operation and the SS_EXT soft rise operation are performed, the reference voltage SS_REF _H is input to the comparator 152 as the reference voltage SS_REF. On the other hand, the reference voltage SS_REF _L functions as a threshold for judging whether or not the voltages SS_INT and SS_EXT have sufficiently decreased in the process of decreasing. Therefore, when the SS_INT soft fall operation, the SS_EXT soft fall operation, the SS_INT strong fall operation, and the SS_EXT strong fall operation are performed, the reference voltage SS_REF _L is input to the comparator 152 as the reference voltage SS_REF. Which of the reference voltages SS_REF _H and SS_REF _L is supplied to the comparator 152 as the reference voltage SS_REF may be controlled by the SS control circuit 130 .

The one-shot pulse circuit 153 outputs a signal SS_END_oneshot corresponding to the signal SS_END. Specifically, in principle, the signal SS_END_oneshot is maintained at a low level, and when an up edge occurs in the signal SS_END, a single pulse signal that is at a high level for a predetermined time at the timing at which the up edge occurs is generated as the signal SS_END_oneshot. include in and output. After outputting the single pulse signal, the signal SS_END_oneshot is maintained at a low level.

The holding circuit 154 includes an RS flip-flop 154a (hereinafter referred to as FF 154a) having a set terminal, a reset terminal and an output terminal, and an AND circuit 154b, and the output signal from the output terminal of FF 154a functions as the signal SS_INT_MASK. In FF 154a, the AND of signal SS_CMP and signal SS_END_oneshot is input to the set terminal, and signal PROTON is input to the reset terminal. Therefore, the FF 154a latches the level of the signal SS_CMP when the signal SS_END_oneshot is at high level under the condition that the signal PROTON is at low level, and outputs it from the output terminal.

The holding circuit 155 includes an RS flip-flop 155a (hereinafter referred to as FF 155a) having a set terminal, a reset terminal and an output terminal, an AND circuit 155b, and an inverter circuit 155c. It functions as a signal SS_EXT_MASK. In the FF 155a, the AND of the inverted signal of the signal SS_CMP and the signal SS_END_oneshot is input to the set terminal, and the signal PROTON is input to the reset terminal. Therefore, under the condition that the signal PROTON is at low level, the FF 155a latches the level of the inverted signal of the signal SS_CMP when the signal SS_END_oneshot is at high level and outputs it from the output terminal.

More specifically, under the condition that the signal PROTON is at low level, if the signal SS_CMP is at high level while the signal SS_END_oneshot is at high level, the FF 154a holds the logical value of "1". The FF 155a holds the logical value of "0", and if the signal SS_CMP is at the low level while the signal SS_END_oneshot is at the high level, the FF 154a holds the logical value of "0" while the FF 155a holds the logical value of "1". Holds the logical value of The FF 154a outputs a high level signal SS_INT_MASK when holding a logic value of "1", and outputs a low level signal SS_INT_MASK when holding a logic value of "0". The FF 155a outputs a high level signal SS_EXT_MASK when holding a logic value of "1", and outputs a low level signal SS_EXT_MASK when holding a logic value of "0". The holding state of the logical value in the FFs 154a and 155a is maintained until the signal PROTON becomes high level, when the signal PROTON becomes high level, the held logical value is discarded and the signals SS_INT_MASK and SS_EXT_MASK become low level.

The information held by the holding circuits 154 and 155 is called mask information. Mask information is represented by the levels of signals SS_INT_MASK and SS_EXT_MASK. Mask information is transmitted to the SS control circuit 130 . The high level of the signal SS_INT_MASK has the meaning of masking the use of the capacitor C _INT in subsequent operations, and the high level of the signal SS_EXT_MASK has the meaning of masking the use of the capacitor C _EXT in the subsequent operations.

The soft start operation and the mask information generation operation will be described with reference to FIGS. 8 and 9. FIG. 8 and 9 are timing charts regarding each signal waveform of the switching power supply AA. However, in FIG. 8, the capacitor C _EXT is not connected to the terminal SS, or the capacitance value of the capacitor C _EXT is equal to the capacitance value of the capacitor C _INT even though the capacitor C _EXT is connected to the terminal SS. A smaller case (hereinafter referred to as case CS1) is assumed. In contrast, FIG. 9 assumes a case (hereinafter referred to as case CS2) in which the capacitance value of the capacitor C _EXT connected to the terminal SS is larger than the capacitance value of the capacitor C _INT . Also, FIGS. 8 and 9 are for explaining the soft start operation and the mask information generation operation, and it is assumed in FIGS. 8 and 9 that the soft stop operation is not performed.

First, the relationship between signals EN _IN , EN _OUT and PROTON and timings t _A1 to t _A4 common to cases CS1 and CS2 will be described. Assume that timings t _A1 , t _A2 , t _A3 , and t _A4 come in this order as time elapses. The voltage value of the enable input signal EN _IN begins to rise from 0 V to 5 V immediately before timing t _A1 , and at timing t _A1 , the voltage value of signal EN _IN reaches a predetermined enable determination threshold value of less than 5 V. The voltage value of signal EN _IN rises to reach 5V. After that, the voltage value of the signal EN _IN is maintained at 5 V, and _starts falling from 5 V to 0 V immediately before the timing t _{A4 .} After that, the voltage value of the signal EN _IN also drops to 0V. The enable circuit 17 outputs a high level enable output signal EN _OUT when the voltage value of the signal EN _IN is higher than the enable determination threshold, and outputs a low level enable output signal when the voltage value of the signal EN _IN is lower than the enable determination threshold. It outputs the signal EN _OUT .

Then, in response to the voltage value of the signal EN _IN exceeding the enable determination threshold, the level of the signal EN _OUT switches from low level to high level at timing t _A1 , and the voltage value of the signal EN _IN falls below the enable determination threshold. In response to this, the level of the signal EN _OUT is switched from high level to low level at timing t _A4 . However, it is preferable to provide a hysteresis characteristic to the enable determination threshold. The signal EN _OUT is maintained at a high level between timings t _A1 and t _A4 .

The main control circuit 3 switches the level of the signal PROTON from the high level to the low level at the timing tA2 when a predetermined activation delay time has elapsed from the rising edge timing _tA1 of the signal EN _OUT (before the timing _tA2 , the signal _PROTON is (maintained at high level), and thereafter, when a predetermined stop delay time elapses from the down edge timing _tA4 of the signal EN _OUT , the level of the signal PROTON is switched from low level to high level. The period during which the signal PROTON is at low level corresponds to the period during which various protective functions in the IC 100 are effective, and the main control circuit 3 switches the transistors 1a and 1b when the signal PROTON is at low level. When it operates and the signal PROTON is at a high level, it stops the switching operation of the transistors 1a and 1b. The switching operation refers to the operation of alternately turning on and off the transistors 1a and 1b, and the stopping of the switching operation refers to keeping the transistors 1a and 1b off regardless of the comparison result signal CMP or the like.

Waveforms such as voltages SS_INT and SS_EXT in case CS1 of FIG. 8 will be described. In FIG. 8, a polygonal-line waveform 610 _INT with a solid line and a polygonal-line waveform 610 _EXT with a broken line respectively represent the waveforms of the voltages SS_INT and SS_EXT in case CS1. It is assumed that the voltages SS_INT and _{SS_EXT} are 0V at the timing tA2. In FIG. 8, waveforms 610 _INT and 610 _EXT before timing t _A2 and after t _A4 overlap.

In case CS1, the SS control circuit 130 receives the down edge of signal PROTON and starts the SS_INT soft rise operation and the SS_EXT soft rise operation from timing _tA2 . The SS_INT soft rise operation continues until the voltage _{SS_INT} reaches the predetermined voltage VUL, and the SS_EXT soft rise operation continues until the voltage _{SS_EXT} reaches the predetermined voltage VUL. In case CS1, voltage SS_INT rises at a smaller slope than voltage SS_EXT, so that "SS_INT<SS_EXT" is established, and voltage SS_INT becomes reference voltage SS_REF _H (soft-start completion determination voltage) in comparator 152 of FIG. will be compared. Then, in case CS1, the voltage SS_INT rises from the state of "SS_INT<SS_REF _H " and exceeds the reference voltage SS_REF _H at timing _tA3 . Then, an up edge occurs in the signal _{SS_END} at the timing tA3, and in response to this, the signal SS_END_oneshot includes a single pulse signal that stays high for a predetermined period of time. At this time, in case CS1, since "SS_INT<SS_EXT" holds, the signal SS_CMP is at a low level. will hold the value. That is, after timing _tA3 , the signals SS_INT_MASK and SS_EXT_MASK become low level and high level, respectively. Before timing _tA3 , both signals SS_INT_MASK and SS_EXT_MASK are at low level. This is because the FFs 154a and 155a are reset by the high level of the signal _PROTON before timing tA2.

In case CS1, even after the voltage SS_INT reaches the reference voltage SS_REF _H , the state of the switch 113 being on and the switches 114 and 115 being off continues, after timing _tA3 and before timing _tA4 . , the voltage _{SS_INT} reaches a predetermined voltage VUL higher than the reference voltage _{SS_REFH} . In case CS1, voltage _{SS_EXT} reaches predetermined voltage VUL before timing _tA3 .

Since the SS selection circuit 140 outputs the lower voltage of the voltages SS_INT and SS_EXT to the main comparator 11 as the voltage Vss, in case CS1, a soft start operation is performed using the voltage SS_INT as the soft start voltage. . In the case CS1, the voltage SS_INT as the soft start voltage is lower than the error signal Verr from the timing _tA2 to the specific timing between the timings _tA2 and _tA3 . It gradually increases based on the starting voltage. However, the output voltage Vout reaches the target output voltage at a specific timing, and after that, even if the voltage SS_INT has not reached the reference voltage SS_REF _H , "Verr<SS_INT" is established, and the error voltage Verr and the feedback voltage with ripple The comparison result of Vfb' appears in the signal CMP. The target output voltage is a voltage determined by the reference voltage Vref and the voltage division ratio by the resistors R1 and R2, and is the voltage at which the output voltage Vout should be stabilized.

In case CS1, the rising edge of signal _PROTON after timing tA4 is received, mask information is discarded, and signals SS_INT_MASK and SS_EXT_MASK both go low. Also, as described above, it is assumed in FIG. 8 that the soft stop operation is not performed, and the voltages SS_INT and SS_EXT rapidly drop to 0V upon receiving the rising edge of the signal PROTON.

Waveforms such as voltages SS_INT and SS_EXT in case CS2 of FIG. 9 will be described. In FIG. 9, a polygonal-line waveform 620 _INT with a solid line and a polygonal-line waveform 620 _EXT with a broken line represent waveforms of voltages SS_INT and SS_EXT in case CS2, respectively. It is assumed that the voltages SS_INT and _{SS_EXT} are 0V at the timing tA2. In FIG. 9, waveforms 620 _INT and 620 _EXT before timing t _A2 and after t _A4 overlap.

In case CS2, the SS control circuit 130 receives the down edge of signal PROTON and starts the SS_INT soft rise operation and the SS_EXT soft rise operation from timing _tA2 . The SS_INT soft rise operation continues until the voltage _{SS_INT} reaches the predetermined voltage VUL, and the SS_EXT soft rise operation continues until the voltage _{SS_EXT} reaches the predetermined voltage VUL. In case CS2, since the slope of the rise of voltage SS_EXT is smaller than that of voltage _{SS_INT} , "SS_INT>SS_EXT" is established, and in comparator 152 of FIG. will be compared. Then, in case CS2, the voltage SS_EXT rises from the state of "SS_EXT<SS_REF _H " and exceeds the reference voltage SS_REF _H at timing _tA3 . Then, an up edge occurs in the signal _{SS_END} at the timing tA3, and in response to this, the signal SS_END_oneshot includes a single pulse signal that stays high for a predetermined period of time. At this time, in case CS2, since "SS_INT>SS_EXT", the signal SS_CMP is at a high level. will hold the value. That is, after timing _tA3 , the signals SS_INT_MASK and SS_EXT_MASK become high level and low level, respectively. Before timing _tA3 , both signals SS_INT_MASK and SS_EXT_MASK are at low level. This is because the FFs 154a and 155a are reset by the high level of the signal _PROTON before timing tA2. As described above, the comparator 151 maintains the level of the signal SS_CMP at low level regardless of the voltages SS_INT and SS_EXT after the falling edge of the signal SS_END_oneshot occurs.

In case CS2, even after the voltage _{SS_EXT} reaches the reference voltage _{SS_REF H} , the switch 123 is kept on and the switches 124 and 125 are kept off. , the voltage _{SS_EXT} reaches a predetermined voltage VUL higher than the reference voltage _{SS_REFH} . In case CS2, voltage _{SS_INT} reaches predetermined voltage VUL before timing _tA3 .

Since the SS selection circuit 140 outputs the lower voltage of the voltages SS_INT and SS_EXT to the main comparator 11 as the voltage Vss, in case CS2, the soft start operation is performed with the voltage SS_EXT as the soft start voltage. . In the case CS2, the voltage SS_EXT as the soft start voltage is lower than the error signal Verr from the timing _tA2 to the specific timing between the timings _tA2 and _tA3 . It gradually increases based on the starting voltage. However, the output voltage Vout reaches the target output voltage at a specific timing, and after that, even if the voltage SS_EXT has not reached the reference voltage _{SS_REFH} , "Verr<SS_EXT" is established, and the error voltage Verr and the feedback voltage with ripple The comparison result of Vfb' appears in the signal CMP.

In case CS2, the rising edge of signal _PROTON after timing tA4 is received, the mask information is discarded, and both signals SS_INT_MASK and SS_EXT_MASK become low level. Also, as described above, it is assumed in FIG. 9 that the soft stop operation is not performed, and the voltages SS_INT and SS_EXT rapidly drop to 0V in response to the rising edge of signal PROTON.

The soft start circuit _included in the _SS circuit 6 of FIG. 140 (although capacitor C _EXT may not be provided).

The soft start circuit sets the capacitors _CINT and _CEXT individually by the SS_INT soft rise operation and the SS_EXT soft rise operation at the time of starting the switching power supply AA (in the process of making the output voltage Vout go from 0V to the target output voltage). It is charged with the current (I _I1 , I _E1 ), and the soft start operation is performed using the lower one of the voltages SS_INT and SS_EXT as the soft start voltage. However, it can also be considered that the soft start circuit cooperates with other circuits (including the main comparator 11 and the main control circuit 3) responsible for output feedback control to realize the soft start operation. When the soft start operation is executed, the transistors 1a and 1b are controlled on/off based on the feedback voltage Vfb and the soft start voltage Vss without depending on the reference voltage Vref.

A designer of the switching power supply AA can adjust the rising slope of the output voltage Vout during the soft start operation by adjusting the capacitance value of the capacitor _CEXT connected to the terminal SS. _{Capacitor C_INT maintains} the minimum soft-start time (when switching power supply AA starts, output voltage Vout is It is built into the IC 100 to ensure the time required for the output voltage to rise from 0V to the target output voltage.

At the start of the soft-start operation when the switching power supply AA is started, the presence or absence of connection of the capacitor C _EXT and the magnitude relationship between the capacitance values of the capacitors C _INT and C _EXT are unknown. Both SS_EXT soft rise operations are performed, and the lower voltage of the voltages SS_INT and SS_EXT is used as the soft start voltage. However, after the mask information is obtained through the soft start operation, the presence or absence of connection of the capacitor C _EXT and the magnitude relationship between the capacitance values of the capacitors C _INT and C _EXT are known. Either one of C _INT and C _EXT can be treated as a target capacitor (target capacitance), and the target capacitor can be used for various operations.

Here, the target capacitor is the capacitor with the lower terminal voltage among the capacitors C _INT and C _EXT in the soft start operation executed between the timings t _A2 and t _A3 . Therefore, in case CS1 of FIG. 8, the capacitor _{C-- INT} is the target capacitor, and in case CS2 of FIG. 9, the capacitor _{C-- EXT} is the target capacitor. Of the capacitors _{C_INT} and _{C_EXT} , the one that is not the target capacitor is referred to as the asymmetric capacitor (asymmetric capacitance). As in case CS1 of FIG. 8, when the mask information is obtained that the signal SS_INT_MASK is at a low level and the signal SS_EXT_MASK is at a high level, the SS control circuit 130 sets the capacitor C _INT as the target capacitor and the capacitor C Set _EXT to be an asymmetric capacitor. Conversely, when mask information is obtained in which the signal SS_INT_MASK is at a high level and the signal _{SS_EXT_MASK} is at a low level, as in case CS2 in FIG. and set the capacitor _{C_EXT} as the target capacitor.

Detailed operation examples, application examples, and modification examples of the switching power supply AA based on the above contents will be described in the following first to ninth embodiments. Unless otherwise stated and inconsistent, the matters described above in this embodiment are applied to the first to ninth embodiments described later. Priority is given to the descriptions in the to ninth embodiments. In addition, as long as there is no contradiction, the matters described in any of the first to ninth embodiments described below can also be applied to any other embodiment (that is, the It is also possible to combine any two or more examples within).

[First embodiment]
A first embodiment will be described. In the first embodiment, a mode in which mask information is used for soft stop operation will be described.

10 and 11 show various signal waveforms and the like focusing on the soft stop operation. However, FIG. 10 assumes the above-described case CS1, and FIG. 11 assumes the above-described case CS2. It can be said that in case CS1, the capacitor _{C_INT is set as the target capacitor and the capacitor C_EXT is} set as the non-target capacitor at timing t _A3 in FIG. 8, and in case CS2, at timing t _A3 in FIG. It can be said that capacitor C _{- - EXT} is set to be the target capacitor and capacitor C _{- - INT} is set to be the non-target capacitor. Asymmetric capacitors correspond to capacitors whose use is masked.

After the enable input signal EN _IN is set to high level to start the switching power supply AA, the low level enable input signal EN _IN functions as a stop instruction signal that instructs to stop the operation of the switching power supply AA. At time t _A4 , there is a falling edge on signal EN _OUT as a result of signal EN _IN falling. Stopping the operation of the switching power supply AA means stopping the switching operation of the transistors 1a and 1b to stop the operation of generating the output voltage Vout from the input voltage Vin.

The soft stop operation in case CS1 will be described with reference to FIG. In FIG. 10, a polygonal-line waveform 630 _INT with a solid line and a polygonal-line waveform 630 _EXT with a broken line represent waveforms of the voltages SS_INT and SS_EXT in the case CS1, respectively. In case CS1, each operation and each signal state up to timing t _A4 are as described above with reference to FIG. It is assumed that the voltages SS_INT and _{SS_EXT} reach the predetermined voltage VUL through the soft start operation starting at timing _tA2 (see FIG. 8), and that the voltages _{SS_INT} and _{SS_EXT} match the predetermined voltage VUL at timing tA4.

Receiving the falling edge of the signal EN _OUT at timing t _A4 , the SS control circuit 130 performs a soft stop that discharges only the accumulated charge in the target capacitor among the target capacitor and the non-target capacitor at a constant current based on the mask information. take action. Therefore, in case CS1 of FIG. 10, the SS control circuit 130 starts the SS_INT soft-fall operation at timing t _A4 while turning off all the switches 123 to 125 connected to the capacitor C _EXT as the asymmetric capacitor ( However, the switch 123 may be on).

Therefore, in case CS1, the voltage _{SS_INT} gradually decreases from the predetermined voltage VUL starting at the timing _tA4 , and the voltage _{SS_INT} drops below the reference voltage _{SS_REFL} at the timing tA5. is not discharged between timings _tA4 and _tA5 , the voltage _{SS_EXT} is maintained at the predetermined voltage _VUL . In case CS1, since "SS_INT<SS_EXT" between timings _tA4 and _tA5 , the SS selection circuit 140 outputs the voltage _{SS_INT} that gradually decreases with a slope depending on the capacitance value of the capacitor CINT. is output to the main comparator 11 as the soft stop voltage Vss. At this time, since "SS_INT=Vss<Verr", the output voltage Vout gradually decreases from the target output voltage toward 0 V as the soft stop voltage Vss decreases. (However, immediately after timing _tA4 , the output voltage Vout matches the target output voltage during the period in which “SS_INT=Vss<Verr” is not yet established).

At timing _tA5 of case CS1, the voltage SS_INT, which is the lower voltage between the voltages SS_INT and SS_EXT, falls below the reference voltage _{SS_REFL} , so that the signal SS_END has a falling edge. The SS control circuit 130 receives the falling edge of the signal SS_END, determines that the output voltage Vout has sufficiently decreased, and switches the level of the signal PROTON from low level to high level. In conjunction with this, the SS_INT strong-falling operation and the SS_EXT strong-falling operation are also executed by turning on the switches 115 and 125, and the voltages SS_INT and SS_EXT quickly go to 0V. The main control circuit 3 stops the switching operations of the transistors 1a and 1b in response to the high level of the signal PROTON.

The soft stop operation in case CS2 will be described with reference to FIG. In FIG. 11, a polygonal-line waveform 640 _INT with a solid line and a polygonal-line waveform 640 _EXT with a broken line represent waveforms of voltages SS_INT and SS_EXT in case CS2, respectively. In case CS2, each operation and each signal state up to timing t _A4 are as described above with reference to FIG. It is assumed that the voltages SS_INT and _{SS_EXT} reach the predetermined voltage VUL through the soft start operation starting at timing _tA2 (see FIG. 9), and that the voltages _{SS_INT} and _{SS_EXT} match the predetermined voltage VUL at timing tA4.

Receiving the falling edge of the signal EN _OUT at timing t _A4 , the SS control circuit 130 performs a soft stop that discharges only the accumulated charge in the target capacitor among the target capacitor and the non-target capacitor at a constant current based on the mask information. take action. Therefore, in case CS2 of FIG. 11, the SS control circuit 130 starts the SS_EXT soft fall operation at timing t _A4 while turning off all the switches 113 to 115 connected to the capacitor C _INT as the asymmetric capacitor ( However, the switch 113 may be on).

Therefore, in case CS2, the voltage _{SS_EXT} gradually decreases from the predetermined voltage VUL starting at the timing _tA4 , and the voltage _{SS_EXT} falls below the reference voltage _{SS_REFL} at the timing tA5. is not discharged between timings _tA4 and _tA5 , the voltage _{SS_INT} is maintained at the predetermined voltage _VUL . In case CS2, since “SS_INT>SS_EXT” between timings _tA4 and _tA5 , the SS selection circuit 140 outputs the voltage SS_EXT that gradually decreases with a slope depending on the capacitance value of the capacitor _CEXT . is output to the main comparator 11 as the soft stop voltage Vss. At this time, since "SS_EXT=Vss<Verr", the output voltage Vout gradually decreases from the target output voltage toward 0 V as the soft stop voltage Vss decreases. (However, immediately after the timing _tA4 , the output voltage Vout matches the target output voltage during the period in which "SS_EXT=Vss<Verr" is not yet established).

At timing _tA5 of case CS2, the voltage SS_EXT, which is the lower voltage between the voltages SS_INT and SS_EXT, falls below the reference voltage _{SS_REFL} , so that the signal SS_END has a falling edge. The SS control circuit 130 receives the falling edge of the signal SS_END, determines that the output voltage Vout has sufficiently decreased, and switches the level of the signal PROTON from low level to high level. In conjunction with this, the SS_INT strong-falling operation and the SS_EXT strong-falling operation are also executed by turning on the switches 115 and 125, and the voltages SS_INT and SS_EXT quickly go to 0V. The main control circuit 3 stops the switching operations of the transistors 1a and 1b in response to the high level of the signal PROTON.

As described above, in case CS1 of FIG. 10, the soft stop operation is performed using the voltage _{SS_INT} as the soft stop voltage _Vss between timings _tA4 and _tA5 , and in case CS2 of FIG. , a soft stop operation is performed using the voltage SS_EXT as the soft stop voltage Vss.

The soft stop _{circuits included} in the SS circuit 6 of FIG. 140 (although capacitor C _EXT may not be provided).

In the soft-stop operation, the soft-stop circuit discharges the charge accumulated in the target capacitor by the soft-start operation with a constant discharge current ( _II2 or _IE2 ), and the voltage is related to the terminal voltage of the non-target capacitor. Instead, the terminal voltage of the target capacitor in the discharging process is used as the soft stop voltage Vss. In the method of FIGS. 10 and 11, in the soft stop operation, only the target capacitor among the target capacitor and the non-target capacitor is discharged with a constant discharge current.

When the soft stop operation is performed, the transistors 1a and 1b are controlled on/off based on the feedback voltage Vfb and the soft stop voltage Vss without depending on the reference voltage Vref. On the other hand, in a steady state (that is, after the soft start operation is completed and the soft stop operation is not being executed), on/off control of the transistors 1a and 1b is performed based on the feedback voltage Vfb and the reference voltage Vref. is done.

Consider a reference power supply for comparison with the switching power supply AA of the present embodiment. The reference power supply is a switching power supply AA from which the function of acquiring and holding mask information is removed. When attempting to perform a soft stop operation in the reference power supply, since the magnitude relationship between the capacitance values of the capacitors C _INT and C _EXT is unknown, there is no choice but to turn on both the switches 114 and 124. Depending on the function, the lower one of the voltages SS_INT and SS_EXT is output to the main comparator 11 as the soft stop voltage Vss. Then, for example, when the capacitor _CEXT is not connected to the terminal SS, the soft stop voltage Vss sharply drops to 0V after the timing _tA4 , so the output voltage Vout also drops sharply to 0V. Become. This does not provide the desired soft stop operation.

In the switching power supply AA according to the present embodiment, the mask information is acquired at the stage of the soft start operation at startup, and the mask information can be used to set the target capacitor and the non- _target capacitor. A desired soft stop operation can be obtained regardless of the presence or absence of the capacitor _{C_EXT} and the magnitude of the capacitance value of the capacitor C_EXT.

[Second embodiment]
A second embodiment will be described. In the second embodiment, a technique modified from the first embodiment will be described. In the first embodiment, the asymmetric capacitor may also be discharged during the soft stop operation. Specifically, based on the matters described in the first embodiment, the second embodiment is as follows.

First, consider case CS1 in FIG. In case CS1 according to the second embodiment, the SS control circuit 130 starts the SS_INT soft-falling operation and the SS_EXT soft-falling operation at timing _tA4 . Then, both the voltages _{SS_INT} and _{SS_EXT} gradually decrease from the predetermined voltage VUL starting at the timing _tA4 . Therefore, the voltage SS_INT, which is the terminal voltage of the target capacitor, is always treated as the non-inverting side voltage of the comparator 152 without depending on the voltage _{SS_EXT} , which is the terminal voltage of the non-target capacitor. Appears in the signal SS_END, or controls the input voltage to the comparator 152, and based on the mask information, the terminal voltage of the target capacitor independent of the voltage SS_EXT, which is the terminal voltage of the non-target capacitor. The SS selection circuit 140 is controlled or the input voltage to the SS selection circuit 140 is controlled so that the voltage SS_INT is output from the SS selection circuit 140 as the soft stop voltage Vss.

Then, the voltage _{SS_INT} gradually decreasing with a slope depending on the capacitance value of the capacitor CINT is supplied to the main comparator 11 as the soft stop voltage Vss, and the output voltage Vout increases as the soft stop voltage Vss decreases. Gradually decreases from the target output voltage toward 0 V (However, immediately after timing _tA4 , during the period in which “SS_INT=Vss<Verr” is not established, the output voltage Vout matches the target output voltage. ). In the case CS1 according to the second embodiment, the voltage SS_INT falls below the reference voltage _{SS_REFL} at timing _tA5 , and a down edge occurs in the signal SS_END. The operation after timing t _A5 including timing t _A5 is the same as in the first embodiment.

Next, consider case CS2 in FIG. In case CS2 according to the second embodiment, the SS control circuit 130 starts the SS_INT soft-falling operation and the SS_EXT soft-falling operation at timing _tA4 . Then, both the voltages _{SS_INT} and _{SS_EXT} gradually decrease from the predetermined voltage VUL starting at the timing _tA4 . Therefore, the voltage SS_EXT, which is the terminal voltage of the target capacitor, is always treated as the non-inverting side voltage of the comparator 152 without depending on the voltage _{SS_INT} , which is the terminal voltage of the non-target capacitor. appears in the signal SS_END, and based on the mask information, the terminal voltage of the target capacitor is independent of the voltage SS_INT, which is the terminal voltage of the non-target capacitor. The SS selection circuit 140 is controlled or the input voltage to the SS selection circuit 140 is controlled so that the voltage SS_EXT is output from the SS selection circuit 140 as the soft stop voltage Vss.

Then, the voltage SS_EXT gradually decreasing with a slope dependent on the capacitance value of the capacitor C _EXT is supplied to the main comparator 11 as the soft stop voltage Vss, and the output voltage Vout increases as the soft stop voltage Vss decreases. Gradually decreases from the target output voltage toward 0 V (however, immediately after timing _tA4 , during the period in which “SS_EXT=Vss<Verr” is not established, the output voltage Vout matches the target output voltage. ). In case CS2 according to the second embodiment, the voltage SS_EXT falls below the reference voltage _{SS_REFL} at timing _tA5 , and a down edge occurs in the signal SS_END. The operation after timing t _A5 including timing t _A5 is the same as in the first embodiment.

In this way, the soft stop circuit according to the second embodiment discharges the accumulated charges in both the target capacitor and the non-target capacitor individually with the constant discharge currents (I _I2 , I _E2 ) in the soft stop operation. However, regardless of the terminal voltage of the non-target capacitor, the terminal voltage of the target capacitor in the discharge process is used as the soft stop voltage. This method can also provide the same functions and effects as those of the first embodiment.

[Third embodiment]
A third embodiment will be described. The switching power supply IC 100 has a hiccup type short circuit protection function. In the hiccup-type short-circuit protection function, when the feedback voltage Vfb is lower than the predetermined protection determination voltage _VSCP for a predetermined protection determination time _TSCP or longer, the switching operation is performed for a period of time called a cool-down time. After stopping, the switching power supply AA is restarted with a soft start operation.

FIG. 12 shows an operation flow chart of the IC 100 involved in the hiccup type short circuit protection function. After the signal EN _OUT becomes high level, the level of the signal PROTON is checked in step S11, and if the signal PROTON is low level, the process proceeds from step S11 to step S12. Although the process may shift from step S21 to step S12, which will be described later, the timing of the first shift to step S12 (that is, the shift from step S11 to step S12) corresponds to timing _tA2 (see FIGS. 8 and 9). .

At step S12, the SS control circuit 130 starts the above-described soft start operation, and at the subsequent step S13, the level of the signal SS_END is confirmed. Then, when the rising edge of signal SS_END occurs, the process proceeds to step S14. In step S14, the main control circuit 3 starts a switching operation in a steady state.

After step S14, while continuing the switching operation, the main control circuit 3 cooperates with the short circuit protection circuit 13 to perform the short circuit detection operation of step S15. In the short-circuit detection process of step S15, the feedback voltage Vfb is compared with the predetermined protection determination voltage _VSCP , and if a state in which the feedback voltage Vfb is lower than the protection determination voltage _VSCP is detected, the duration of that state is set by a timer. clock. Only when it is detected that the feedback voltage Vfb is lower than the protection determination voltage _VSCP for a predetermined protection determination time _TSCP (for example, 320 microseconds) or longer, the process proceeds to step S16. . Even if it is detected that the feedback voltage Vfb is lower than the protection determination voltage _VSCP , the timer is reset if the state is resolved before the protection determination time _TSCP elapses. The protection judgment voltage _VSCP is a threshold voltage for judging whether or not the output voltage Vout is abnormally lowered due to a short circuit of the output terminal OUT or the like, and is a predetermined positive voltage value lower than the reference voltage Vref. have

At step S16, the switching operations of the transistors 1a and 1b are stopped by the main control circuit 3 and the SS count value is set to zero. After that, the process proceeds to step S17, and the SS circuit 6 performs a cool-down operation consisting of steps S17 to S20. Once the cool-down operation is started, the switching operation remains stopped until the process returns to step S12 via step S21, which will be described later. The SS count value is a variable managed by the SS control circuit 130 (or main control circuit 3).

At step S17, an SS discharging operation is performed. In the SS discharge operation, the SS_INT strong fall operation or the SS_EXT strong fall operation is performed, and the down edge of the signal SS_END after the start of the SS discharge operation triggers the shift to step S18. At step S18, the SS charging operation is performed. In the SS charging operation, the SS_INT soft rising operation or the SS_EXT soft rising operation is performed, and the rising edge of the signal SS_END after the start of the SS charging operation triggers a transition to step S19. In step S19, 1 is added to the SS count value, and in subsequent step S20, it is confirmed whether or not the SS count value has reached a predetermined value _nCL . If the SS count value has not reached the predetermined value _nCL , the process returns from step _S20 to step S17, and the processing after step S17 is repeated. Proceed to S21. The value n _CL has an arbitrary integer greater than or equal to 1 (eg 16).

In step S21, the same SS discharging operation as in step S17 is performed, and with the falling edge of the signal SS_END after the start of the SS discharging operation as a trigger, the process returns to step S12, and the processing of the steps after step S12 described above is executed. be. When the process returns to step S12 via step S21, the switching power supply AA is restarted with another soft start operation.

The time during which the cool-down operation in steps S17 to S20 is performed is the cool-down time. Since the time required for the SS discharging operation is sufficiently shorter than the time required for the SS charging operation, n _CL times the time required for the SS charging operation substantially corresponds to the cooldown time. When the output terminal OUT is short-circuited, the soft-start operation, the short-circuit detection operation, and the cool-down operation are repeated. It is possible to suppress a temperature rise that would lead to damage to the .

A cool-down circuit that performs a cool-down operation has a constant current source 111, a switch 113, a switch 115, a capacitor _{C_INT} , a constant current source 121, a switch 123, a switch 125, a capacitor _{C_EXT} , and an SS control circuit 130. (although capacitor _{C_EXT} may not be provided).

In the third embodiment, mask information is used for cooldown operation. The mask information should be acquired and held at the rising edge timing of the signal SS_END based on the soft start operation in step S12, and should be updated in synchronization with the rising edge of the signal SS_END during the cool-down operation. is not. For this reason, for example, the one-shot pulse circuit 153 outputs a pulse signal included in the signal SS_END_oneshot in synchronization only with the first rising edge of the signal SS_END after the falling edge of the signal PROTON. It may be a circuit that maintains the signal SS_END_oneshot at a low level regardless of the level. In addition, any configuration can be adopted that prevents the mask information from being updated in synchronization with the rising edge of the signal SS_END during the cooldown operation. In any case, after the falling edge of the signal PROTON, the target capacitor and the non-target capacitor once set are not updated or changed, and the setting contents (held mask information) are reset by the rising edge of the signal PROTON. be done.

Before describing the details of the use of the mask information for the cool-down operation, the cool-down operation in the above-described reference power supply that does not have the function of acquiring and holding the mask information will be described. Now consider case CS2, ie, the case where the capacitance value of capacitor C _EXT is greater than the capacitance value of capacitor C _INT . FIG. 13 shows the waveform 660 _INT of the voltage SS_INT (corresponding to the solid line broken line in FIG. 13) and the waveform 660 _EXT of the voltage SS_EXT (corresponding to the broken line broken line in FIG. 13) during the cool-down operation in the reference power supply in this case. ).

In the reference electrical equipment, when the cool-down operation is started, the SS discharge operation is first performed by turning on the switches 115 and 125. At this time, the slope of the voltage SS_INT falling is equal to the capacitance value of the capacitor _CINT . The falling slope of the voltage _{SS_EXT} depends on the product of the on-resistance value of the switch 115 and the on-resistance value of the switch 115 . Here, it is assumed that the switches 115 and 125 have the same structure and have a common on-resistance value. Then, when the capacitance value of the capacitor C _EXT is larger than the capacitance value of the capacitor C _INT , in the SS discharge operation, the slope of the drop of the voltage SS_INT becomes larger than the slope of the drop of the voltage SS_EXT, and the voltage When SS_EXT is higher than the reference voltage _{SS_REFL} , the voltage SS_INT falls below the reference voltage _{SS_REFL} , causing a down edge in the signal SS_END, and as a result, the SS discharging operation ends and the SS charging operation starts at that point. The SS charge operation is started based on the voltages SS_INT and SS_EXT at the end of the SS discharge operation, and continues until the lower voltage of the voltages SS_INT and _{SS_EXT} reaches the reference voltage SS_REFH. Then, when the lower voltage reaches the reference voltage SS_REF _H , the unit processing consisting of one SS discharging operation and one SS charging operation is completed, and thereafter the SS count value reaches the predetermined value _nCL . The unit processing is repeated until

In case CS2, the capacitance value of the capacitor _{C_EXT} is larger than the capacitance value of the capacitor _{C_INT} . It is based on the capacitance value of the capacitor _{C_INT} , which has a relatively small capacitance. That is, the time required for the SS charging operation is the time until the terminal voltage of the capacitor _CINT , which has a relatively small capacity, rises from the reference voltage SS_REF _L to the reference voltage SS_REF _H by the SS_INT soft rising operation. Conversely, although not shown, in the reference power supply, the time required for the SS charging operation in the case CS1 is based on the capacitance value of the capacitor C _EXT , which has a relatively small capacity.

14(a) and 14(b) show waveforms of the gate voltage Ga of the transistor 1a in cases CS1 and CS2 under short-circuit conditions of the output terminal OUT. In both the reference power supply, the switching power supply AA, and both cases CS1 and CS2, when the output terminal OUT is short-circuited, the switching operation is performed for the sum of the soft start time and the protection determination time _TSCP . A switching period and a cool-down period during which the switching operation is stopped for the cool-down time alternately come. The soft-start time refers to the time from when the soft-start operation is started until the rising edge of the signal SS_END occurs (that is, the time between timings _tA2 and _tA3 ; see FIG. 8, etc.). , the short detection operation is not performed until the rising edge of signal SS_END occurs.

In case CS1, the soft start time is based on the capacitance value of the capacitor _{C_INT} and is relatively short, and in case CS2 it is based on the capacitance value of the capacitor _{C_EXT} and is relatively short. significantly longer. This applies both to the reference power supply and to the switching power supply AA. On the other hand, when the output terminal OUT is short-circuited, a large amount of heat is generated by the sum of the soft start time and the protection determination time _TSCP . Lengthened is preferred. However, in the reference power supply, when the output terminal OUT is short-circuited, the time required for the SS charging operation (thus the cool-down time) is based on the capacitance value of the relatively small capacitor, so the switching power supply There is a risk that the components of the apparatus AA will not be able to dissipate the heat in time, and that the components will be damaged.

Taking this into consideration, the switching power supply AA uses the mask information for cool-down operation. That is, in the SS discharge operation of step S17, the SS control circuit 130 discharges only the accumulated charge of the target capacitor among the target capacitor and the non-target capacitor through the switch connected in parallel to the target capacitor based on the mask information. , in the SS charging operation of step S18, only the target capacitor among the target capacitor and the non-target capacitor is charged with a constant current based on the mask information.

Therefore, in case CS1, the capacitor C _INT is set as the target capacitor, so in the SS discharge operation of step S17, the SS control circuit 130 performs the SS_INT strong fall operation, while the capacitor C _EXT as the non-target capacitor All the connected switches 123 to 125 are turned off (however, the switch 123 may be on). In the SS charge operation of step S18 in case CS1, the SS control circuit 130 performs only the SS_INT soft rise operation among the SS_INT soft rise operation and the SS_EXT soft rise operation.

As a result, in case CS1 as shown in FIG. 15(a), in the SS discharge operation, the terminal voltage (SS_INT) of the capacitor C _INT falls below the reference voltage _{SS_REF} (discharge completion voltage) due to the _{SS_INT} strong fall operation. is discharged, and in the following SS charging operation, the capacitor C _INT is charged at a constant current I _I1 until the terminal voltage (SS_INT) of the capacitor C _INT exceeds the reference voltage SS_REF _H (charging completion voltage) due to the SS_INT soft rising operation. will be charged and the time for the SS charge operation will be based on the capacitance value of capacitor _{C_INT} . In FIG. 15A, a waveform 670 _INT with a solid line and a waveform 670 _EXT with a broken line respectively represent waveforms of voltages SS_INT and SS_EXT during cool-down operation in case CS1 in switching power supply AA.

Conversely, in case CS2, the capacitor C _EXT is set as the target capacitor, so in the SS discharge operation of step S17, the SS control circuit 130 performs the SS_EXT strong fall operation, while the capacitor C _INT as the non-target capacitor. All the switches 113 to 115 connected to are turned off (however, the switch 113 may be on). In the SS charge operation of step S18 in case CS2, the SS control circuit 130 performs only the SS_EXT soft rise operation among the SS_INT soft rise operation and the SS_EXT soft rise operation.

As a result, in case CS2 as shown in FIG. 15(b), in the SS discharge operation, the capacitor C _EXT is discharged until the terminal voltage (SS_EXT) of the capacitor C _EXT falls below the reference voltage _{SS_REF} (discharge completion voltage) due to the SS_EXT strong fall operation. is discharged, and in the subsequent SS charging operation, the capacitor C _EXT is charged at a constant current I _E1 until the terminal voltage (SS_EXT) of the capacitor C _EXT exceeds the reference voltage SS_REF _H (charging completion voltage) due to the SS_EXT soft rise operation. will be charged and the time for the SS charge operation will be based on the capacitance value of capacitor _{C_EXT} , which is longer than that based on the capacitance value of capacitor _{C_INT} . In FIG. 15B, a waveform 680 _INT with a solid line and a waveform 680 _EXT with a broken line respectively represent waveforms of voltages SS_INT and SS_EXT during cool-down operation in case CS2 in switching power supply AA.

The SS discharge operation in step S21 is the same as the SS discharge operation in step S17 in order to determine whether the discharge is completed based on the terminal voltage of the target capacitor and to sufficiently discharge the target capacitor.

According to the switching power supply AA according to the present embodiment, when the capacitor C _EXT having a larger capacitance value than the capacitor C _INT is connected to the terminal SS, the soft start time becomes longer, but the output terminal Since the cool-down time becomes longer when OUT is short-circuited, it is possible to ensure a sufficient heat dissipation time. That is, in both cases CS1 and CS2, highly reliable hiccup-type short-circuit protection can be realized.

[Fourth embodiment]
A fourth embodiment will be described. In the fourth embodiment, a technique modified from the third embodiment will be described. In the third embodiment, the asymmetric capacitor may be discharged during the SS discharging operation, or the asymmetric capacitor may be charged during the SS charging operation. Specifically, based on the matters described in the third embodiment, the fourth embodiment is as follows. Equivalent functions and effects to those of the third embodiment can be obtained by the fourth embodiment as well.

First, consider case CS1 in which capacitor C _INT is set as the target capacitor. In case CS1 according to the fourth embodiment, the SS control circuit 130 performs both the SS_INT strong-falling operation and the SS_EXT strong-falling operation in the SS discharge operation of step S17. Then, both the voltages SS_INT and SS_EXT will drop toward 0V. The comparator 152 is controlled so that the voltage SS_INT, which is the terminal voltage of the target capacitor, is always treated as the non-inverting side voltage of the comparator 152, and the comparison result between the voltage _{SS_INT} and the reference voltage SS_REFL appears in the signal SS_END. Or it controls the input voltage to the comparator 152 . As a result, in the SS discharge operation of step S17 in case CS1, the terminal voltage (SS_INT) of the capacitor C _INT drops to the reference voltage _{SS_REF} (discharge completion voltage) due to the SS_INT strong fall operation regardless of the terminal voltage (SS_EXT) of the capacitor C _EXT . The charge stored in the capacitor _{C-- INT} is discharged until it falls below the level, and the process proceeds to step S18 upon completion of the discharge.

In case CS1 according to the fourth embodiment, the SS control circuit 130 performs both the SS_INT soft rise operation and the SS_EXT soft rise operation in the SS charging operation of step S18. Then, both the voltages SS_INT and SS_EXT will rise, but the SS control circuit 130 depends on the voltage SS_EXT, which is the terminal voltage of the asymmetric capacitor, based on the mask information in the SS charging operation of step S18. The comparator 152 is controlled so that the voltage SS_INT, which is the terminal voltage of the target capacitor, is always treated as the non-inverting side voltage of the comparator 152 and the comparison result between the voltage SS_INT and the reference voltage SS_REF _H appears in the signal SS_END. controls the input voltage of the As a result, in the SS charging operation of step S18 in case CS1, the terminal voltage (SS_INT) of the capacitor C _INT rises to the reference voltage SS_REF _H (charging completion voltage) by the SS_INT soft rising operation regardless of the terminal voltage (SS_EXT) of the capacitor C _EXT . Capacitor _{C-- INT} is charged with constant current _II1 until it exceeds C-- INT.

However, in case CS1 according to the fourth embodiment, "C _INT >C _EXT " holds, so basically "SS_INT <SS_EXT" is obtained in the SS charging operation in step S18 without using the mask information. That is, in the SS charging operation of step S18, the comparator 152 compares the lower one of the voltages SS_INT and SS_EXT as the non-inverted voltage with the reference voltage _{SS_REFH} , and outputs the comparison result as the signal SS_END. You can do it.

Next, consider case CS2 in which capacitor C _EXT is set as the target capacitor. In case CS2 according to the fourth embodiment, the SS control circuit 130 performs both the SS_INT strong-falling operation and the SS_EXT strong-falling operation in the SS discharge operation of step S17. Then, both the voltages SS_INT and SS_EXT will drop toward 0V. The comparator 152 is controlled so that the voltage SS_EXT, which is the terminal voltage of the target capacitor, is always treated as the non-inverting side voltage of the comparator 152 and the result of comparison between the voltage _{SS_EXT} and the reference voltage SS_REFL appears in the signal SS_END. Or it controls the input voltage to the comparator 152 . As a result, in the SS discharge operation of step S17 in case CS2, the terminal voltage (SS_EXT) of the capacitor C _EXT becomes the reference voltage _{SS_REF} (discharge completion voltage) due to the SS_EXT strongly falling operation regardless of the terminal voltage (SS_INT) of the capacitor C _INT . The charge accumulated in the capacitor C - - _EXT is discharged until it falls below the level, and the process proceeds to step S18 upon completion of the discharge.

In case CS2 according to the fourth embodiment, the SS control circuit 130 performs both the SS_INT soft rise operation and the SS_EXT soft rise operation in the SS charging operation of step S18. Then, both the voltages SS_INT and SS_EXT will rise, but the SS control circuit 130 depends on the voltage SS_INT, which is the terminal voltage of the asymmetric capacitor, based on the mask information in the SS charging operation of step S18. The comparator 152 is controlled so that the voltage SS_EXT, which is the terminal voltage of the target capacitor, is always treated as the non-inverting side voltage of the comparator 152, and the comparison result between the voltage SS_EXT and the reference voltage SS_REF _H appears in the signal SS_END. controls the input voltage of the As a result, in the SS charging operation of step S18 in case CS2, the terminal voltage (SS_EXT) of the capacitor C _EXT rises to the reference voltage SS_REF _H (charging completion voltage) by the SS_EXT soft rise operation regardless of the terminal voltage (SS_INT) of the capacitor C _INT . The capacitor C - - _EXT is charged with the constant current I - - _E1 until it exceeds, and upon completion of the charging, the process proceeds to step S19.

However, in case CS2 according to the fourth embodiment, since "C _INT <C _EXT ", basically "SS_INT>SS_EXT" is satisfied in the SS charging operation in step S18 without using the mask information. That is, in the SS charging operation of step S18, the comparator 152 compares the lower voltage of the voltages SS_INT and SS_EXT with the reference voltage _{SS_REFH} as the non-inverted voltage, and outputs the comparison result as the signal SS_END. You can do it.

The SS discharging operation in step S21 is the same as the SS discharging operation in step S17. That is, in the SS discharge operation of step S21 in case CS1, the terminal voltage (SS_INT) of the capacitor C _INT is lowered to the reference voltage _{SS_REF} (discharge completion voltage) by the SS_INT strong drop operation regardless of the terminal voltage (SS_EXT) of the capacitor C _EXT . The charge accumulated in the capacitor _{C-- INT} is discharged until it falls below C-- INT, and upon completion of the discharge, the process returns to step S12. In the SS discharging operation of step S21 in case CS2, regardless of the terminal voltage (SS_INT) of the capacitor C _INT , the SS_EXT strong falling operation causes the terminal voltage (SS_EXT) of the capacitor C _EXT to drop below the reference voltage _{SS_REF} (discharge completion voltage). The charge accumulated in the capacitor _{C-- EXT} is discharged, and upon completion of the discharge, the process returns to step S12.

[Fifth embodiment]
A fifth embodiment will be described. The switching power supply IC 100 according to the fifth embodiment does not perform the soft stop operation described above. That is, for example, when the operation of the switching power supply AA is stopped after the output voltage Vout is stabilized at the target output voltage through the soft start operation (in other words, when the operation of the switching power supply IC 100 is stopped), the SS circuit 6 may drop the voltage Vss abruptly from a positive predetermined voltage (eg V _UL ; see FIGS. 10 and 11) to 0V. Further, in the fifth embodiment, the mask information described above is not used in the cool-down operation. Therefore, the holding circuits 154 and 155 (see FIG. 5) for generating and holding mask information are unnecessary.

Instead, in the fifth embodiment, the SS circuit 6 is provided with a cool-down judgment circuit 160 shown in FIG. In the fifth embodiment, the cool-down circuits that perform the cool-down operation are the constant current source 111, switch 113, switch 115 and capacitor C _INT shown in FIG. In addition to _EXT and the SS control circuit 130, it can be considered that the cooling-down determination circuit 160 of FIG. 16 is provided (however, the capacitor C _EXT may not be provided).

The cool-down determination circuit 160 includes comparators 161 and 162 , a switch circuit 163 and a comparison result integration circuit 164 . A voltage SS_INT and a reference voltage SS_REF are input to the non-inverting input terminal and the inverting input terminal of the comparator 161, respectively. The comparator 161 compares the input voltage SS_INT and the reference voltage SS_REF and outputs a signal CMP_INT indicating the comparison result. At this time, if the voltage SS_INT is higher than the reference voltage SS_REF, a high level signal CMP_INT is output, and if the voltage SS_INT is lower than the reference voltage SS_REF, a low level signal CMP_INT is output. When "SS_INT=SS_REF", the level of signal CMP_INT is either high level or low level.

A voltage SS_EXT and a reference voltage SS_REF are input to the non-inverting input terminal and the inverting input terminal of the comparator 162, respectively. The comparator 162 compares the voltage SS_EXT and the reference voltage SS_REF input thereto and outputs a signal CMP_EXT indicating the comparison result. At this time, if the voltage SS_EXT is higher than the reference voltage SS_REF, a high level signal CMP_EXT is output, and if the voltage SS_EXT is lower than the reference voltage SS_REF, a low level signal CMP_EXT is output. When "SS_EXT=SS_REF", the level of the signal CMP_EXT is either high level or low level.

The reference voltage SS_REF input to each inverting input terminal of the comparators 161 and 162 is the reference voltage SS_REF _H (eg, 690 mV) or the reference voltage SS_REF _L (eg, 50 mV) lower than the reference voltage SS_REF _H. The switch circuit 163 selectively supplies one of the reference voltages SS_REF _H and SS_REF _L to the inverting input terminals of the comparators 161 and 162 as the reference voltage SS_REF. Which of the reference voltages SS_REF _H and SS_REF _L is supplied to the comparators 161 and 162 as the reference voltage SS_REF may be controlled by the SS control circuit 130 (see FIG. 5). The switch circuit 163 can be configured with a plurality of FETs.

The reference voltage SS_REF _H functions as a threshold for judging whether or not the voltages SS_INT and SS_EXT have sufficiently increased in the process of increasing. Therefore, when the SS_INT soft rise operation and the SS_EXT soft rise operation (see FIGS. 6(a) and 7(a)) are performed, the reference voltage SS_REF _H is input to the comparators 161 and 162 as the reference voltage SS_REF. On the other hand, the reference voltage SS_REF _L functions as a threshold for judging whether or not the voltages SS_INT and SS_EXT have sufficiently decreased in the process of decreasing. Therefore, when the SS_INT strong falling operation and the SS_EXT strong falling operation (see FIGS. 6(c) and 7(c)) are performed, the reference voltage SS_REF _L is input to the comparators 161 and 162 as the reference voltage SS_REF.

The comparison result integration circuit 164 outputs signals CHG_END and DISCHG_END based on the signals CMP_INT and CMP_EXT from the comparators 161 and 162 . The comparison result integrating circuit 164 sets the signal CHG_END to a high level only when both the signals CMP_INT and CMP_EXT are at a high level, and otherwise sets the signal CHG_END to a low level. The comparison result integrating circuit 164 sets the signal DISCHG_END to high level only when both the signals CMP_INT and CMP_EXT are at low level, and otherwise sets the signal DISCHG_END to low level.

As described above, the switching power supply IC 100 has a hiccup type short circuit protection function. In the hiccup-type short-circuit protection function, when the feedback voltage Vfb is lower than the predetermined protection determination voltage _VSCP for a predetermined protection determination time _TSCP or longer, the switching operation is performed for a period of time called a cool-down time. After stopping, the switching power supply AA is restarted with a soft start operation.

FIG. 17 shows an operation flowchart of the IC 100 relating to the hiccup-type short-circuit protection function according to the fifth embodiment. The processes of steps S11 to S16 shown in FIG. 17 are the same as those described in the third embodiment (see FIG. 12). That is, after the processing of steps S11 to S13 described above, when the switching operation in the steady state is started by the main control circuit 3 in step S14, the main control circuit 3 continues the switching operation while the short circuit protection circuit 13, the short-circuit detection operation of step S15 is executed. Only when it is detected that the feedback voltage Vfb is lower than the protection determination voltage _VSCP for a predetermined protection determination time _TSCP (for example, 320 microseconds) or longer, the process proceeds to step S16. . At step S16, the switching operations of the transistors 1a and 1b are stopped by the main control circuit 3 and zero is substituted for the SS count value.

In the third embodiment corresponding to FIG. 12, after step S16, the process proceeds to step S17. On the other hand, in the fifth embodiment corresponding to FIG. 17, after step S16, the SS circuit 6 proceeds to step S17a instead of step S17 and performs a cool-down operation consisting of steps S17a to S20a. Once the cool-down operation is started, the switching operation remains stopped until the process returns to step S12 via step S21a, which will be described later. The SS count value is a variable managed by the SS control circuit 130 (or main control circuit 3).

At step S17a, the SS discharging operation is performed. In the SS discharging operation of step S17a, the SS_INT strong falling operation and the SS_EXT strong falling operation are performed with the reference voltage SS_REF _L (for example, 50 mV) supplied to the inverting input terminals of the comparators 161 and 162. Triggered by the rising edge of the signal DISCHG_END after the start, the process proceeds to step S18a. That is, in the SS discharging operation in step S17a, the switch 115 connected in parallel to the capacitor _{C_INT} and the switch 125 (see FIG. 5) connected in parallel to the capacitor _{C_EXT} are turned on, thereby reducing the voltage SS_INT (that is, the capacitor C _INT terminal voltage) and _{SS_EXT} (that is, the terminal voltage of the capacitor C _EXT ) both become lower than a predetermined reference voltage _{SS_REF L} (discharge completion voltage). After the discharge is completed, the process proceeds to step S18a.

At step S18a, the SS charging operation is performed. In the SS charging operation of step S18a, the SS_INT soft rising operation and the SS_EXT soft rising operation are performed while the reference voltage SS_REF _H (for example, 690 mV) is supplied to the inverting input terminals of the comparators 161 and 162. Triggered by the rising edge of the signal CHG_END after the start, the process proceeds to step S19a. That is, in the SS charging operation of step S18a, both the voltage SS_INT (that is, the terminal voltage of the capacitor _{C_INT} ) and the voltage SS_EXT (that is, the terminal voltage of the capacitor _{C_EXT} ) are maintained while the switches 115 and 125 (see FIG. 5) are turned off. is higher than a predetermined reference voltage _{SS_REFH} (charging completion voltage), the capacitors C _INT and C _EXT are charged with constant charging currents (I _I1 , I _E1 ), respectively. Transition.

In step S19a, 1 is added to the SS count value, and in subsequent step S20a, it is confirmed whether or not the SS count value has reached a predetermined value n _CL . If the SS count value has not reached the predetermined value _nCL , the process returns from step _S20a to step S17a, and the processing after step S17a is repeated. Proceed to S21a. The value n _CL has an arbitrary integer greater than or equal to 1 (eg 16).

In step S21a, an SS discharging operation similar to that in step S17a is performed, and with the rising edge of the signal DISCHG_END after the start of the SS discharging operation as a trigger, the process returns to step S12, and the processing of the steps after step S12 described above is executed. be. When the process returns to step S12 via step S21a, the switching power supply AA is restarted with another soft start operation.

The time during which the cool-down operations in steps S17a to S20a are performed is the cool-down time. Since the time required for the SS discharging operation is sufficiently shorter than the time required for the SS charging operation, n _CL times the time required for the SS charging operation substantially corresponds to the cooldown time. When the output terminal OUT is short-circuited, the soft-start operation, the short-circuit detection operation, and the cool-down operation are repeated. It is possible to suppress a temperature rise that would lead to damage to the .

According to the switching power supply AA according to the present embodiment, when the capacitor C _EXT having a larger capacitance value than the capacitor C _INT is connected to the terminal SS, the cool-down time is equal to the capacitance value of the capacitor C _EXT . is relatively long corresponding to , a sufficient heat dissipation time can be secured. In addition, even if the capacitance value of the capacitor C _EXT is smaller than that of the capacitor C _INT , or if the capacitor C _EXT is not connected to the terminal SS, the cool down time corresponding to the capacitor C _INT is ensured. can. That is, in either case, highly reliable hiccup-type short-circuit protection can be realized.

[Sixth embodiment]
A sixth embodiment will be described. After the power supply IC 100 starts the switching operation in the steady state in step S14 through steps S12 and S13 of FIGS. . In the third to fifth embodiments, the short-circuit detection operation is given as an example of the abnormality detection operation. In the short-circuit detection operation, the state in which the feedback voltage Vfb is lower than the protection determination voltage V _SCP is equal to or longer than the predetermined protection determination time T _SCP . It detects the presence or absence of an abnormality that continues. Incidentally, the abnormality detection circuit for the abnormality is configured including the short circuit protection circuit 13 . However, after step S14, the predetermined abnormality to be detected in step S15 (hereinafter referred to as abnormality J for convenience), which triggers the shift to step S16, is not detected by the short-circuit detection operation. Not limited. However, it is assumed that abnormality J is an abnormality that causes a large amount of heat in components (particularly, for example, transistor 1a) in switching power supply AA through current flow through output transistor 1a or 1b (thus, cool-down operation is beneficial. function).

For example, the anomaly J may be an anomaly in which an overcurrent flows through the transistor 1a or 1b. In this case, for example, the overcurrent protection circuit 12, which is an example of an abnormality detection circuit, is provided with a circuit for detecting the magnitude _IQ of the current flowing through the transistor 1a or 1b. A method of generating a transition from step S15 to step S16 assuming that an abnormality J is detected when _IQ is detected, or a method of generating a transition from step S15 to step S16, or a method in which the average value of the magnitude _IQ in a unit interval having a constant time length is a predetermined overcurrent It is also possible to adopt a method of generating a transition from step S15 to step S16 assuming that an abnormality J is detected when the threshold value is exceeded (the former method can be particularly useful in a series power supply device, which will be described later).

Further, for example, the abnormality J may be an abnormality that the temperature to be monitored is too high. In this case, for example, the thermal shutdown circuit 16, which is an example of an abnormality detection circuit, has a function of detecting the temperature to be monitored, which is the temperature of a predetermined location in the power supply IC 100, so that when the temperature to be monitored is equal to or higher than a predetermined temperature TMP _TH , A method of generating a transition from step S15 to step S16 assuming that an abnormality J is detected when this occurs, or a method of generating an abnormality when the temperature to be monitored continues to be equal to or higher than a predetermined temperature TMP _TH for a predetermined time or longer. It is also possible to adopt a method of causing a shift from step S15 to step S16 on the assumption that J is detected. However, when the monitored temperature reaches the shutdown temperature higher than the temperature TMP _TH , the power supply IC 100 may be shut down instead of proceeding from step S15 to step S16. When the power supply IC 100 is shut down, the supply of the input voltage Vin to the input terminal VIN is cut off once and then the input voltage Vin is supplied again, or the signal EN _IN is lowered to low level and then the signal EN _IN is raised again. The power supply IC 100 will not be restarted unless the

[Seventh embodiment]
A seventh embodiment will be described. The configuration in which the present invention relating to the SS circuit 6 is applied to the switching power supply AA adopting the constant on-time control method has been described above, but the present invention is applicable to the switching power supply adopting any control method. Applicable. That is, for example, the present invention may be applied to a switching power supply device that employs a voltage mode control method or a current mode control method method. To give an example with reference to the above contents, as shown in FIG. 18, the control circuit 3a corresponding to the main control circuit 3 divides the lower one of the reference voltage Vref and the voltage Vss and the feedback voltage Vfb. A pulse width modulation signal may be generated by comparing the voltage corresponding to the difference between them with the triangular wave, and the pulse width modulation signal may be used as the control signal Cnta.

In addition, for a series power supply device in which an output transistor (1a) interposed in series between a terminal to which an input voltage Vin is applied and a terminal to which an output voltage Vout is applied is operated not as a switching element but in a linear region (active region). It is also possible to apply the present invention. As an example with reference to the above contents, in the series power supply, as shown in FIG. 19, the terminal SW is directly connected to the output terminal OUT through the elimination of the inductor L1 based on the configuration of FIG. is deleted, and the control circuit 3b corresponding to the main control circuit 3 compares the lower voltage of the reference voltage Vref and the voltage Vss with the feedback voltage Vfb, and outputs a voltage corresponding to the difference between them, which is the voltage of the transistor 1a. to operate in the linear region to the gate of the transistor 1a. At this time, a drain current corresponding to the difference will continuously flow through the transistor 1a.

[Eighth embodiment]
An eighth embodiment will be described. The power supply according to the present invention, including the switching power supply AA, can be mounted on any type of electrical equipment, and the output voltage Vout of the power supply can be used as the drive voltage for any functional circuit in the electrical equipment.

FIG. 20 shows an external view of a copier as an example of electrical equipment in which the power supply device according to the present invention is mounted. In addition, for example, electrical equipment equipped with the power supply device according to the present invention includes mobile phones (including mobile phones classified as smart phones), personal digital assistants, tablet personal computers, television receivers, projectors, digital It can be a camera, an MP3 player, a pedometer, or a Bluetooth headset.

[Ninth embodiment]
A ninth embodiment will be described.

Each component of the switching power supply IC 100 is formed in the form of a semiconductor integrated circuit, and the semiconductor device is configured by enclosing the semiconductor integrated circuit in a housing (package) made of resin. However, a circuit equivalent to the circuit in the switching power supply IC 100 may be configured using a plurality of discrete components.

For any signal or voltage that indicates a logic value, the relationship between high and low levels may be reversed (i.e., a logic "1" assigned a high level or a low level may be assigned arbitrarily).

The transistor 1a may be composed of a P-channel type MOSFET. In this case, the voltage level supplied to the gate of the transistor 1a is modified from that described above so as to realize the switching control described above. be done. It is also possible to make the transistor 1b a P-channel MOSFET.

Each transistor described above may be any type of transistor. For example, the transistors described above as MOSFETs can be replaced with junction FETs, IGBTs (Insulated Gate Bipolar Transistors) or bipolar transistors. Any transistor has a first electrode, a second electrode and a control electrode. In a FET, one of the first and second electrodes is the drain and the other is the source, and the control electrode is the gate. In an IGBT, one of the first and second electrodes is the collector and the other is the emitter, and the control electrode is the gate. In a bipolar transistor not belonging to an IGBT, one of the first and second electrodes is the collector and the other is the emitter and the control electrode is the base.

<<Consideration of the present invention>>
Consider the invention as embodied in the embodiments described above.

A power supply device W1 according to one aspect of the present invention includes an output transistor (1a) for generating an output voltage from an input voltage, a feedback voltage (Vfb) corresponding to the output voltage, and a predetermined reference voltage (Vref). a control circuit for controlling the output transistor based on the power supply device; wherein the soft start circuit includes a first capacitor (C _INT ) with a fixed capacitance value and a second capacitor (C INT ) with a variable capacitance value at the start of the power supply device _EXT ) is individually charged with a constant charging current, and the terminal voltage of the first capacitor (that is, the voltage between the electrodes of the first capacitor due to the accumulated charge in the first capacitor) and the terminal voltage of the second capacitor (that is, the second The soft start operation is performed using the lower terminal voltage of the voltage between the electrodes of the second capacitor due to the accumulated charge of the capacitor as the soft start voltage, and after the soft start operation is completed, the power supply device: a specific circuit that performs a predetermined operation using either one of the terminal voltage (SS_INT) of the first capacitor and the terminal voltage (SS_EXT) of the second capacitor when a predetermined condition is satisfied; a target capacity setting circuit for setting a target capacity to a capacity corresponding to the lower terminal voltage, wherein the specific circuit selects one of the first capacity and the second capacity as the target capacity. The predetermined operation is performed using the terminal voltage of the capacitor.

The terminal voltage of the first capacitor and the terminal voltage of the second capacitor when the first capacitor with a fixed capacitance value and the second capacitor with a variable capacitance value are individually charged with a constant charging current. By executing the soft-start operation using the lower terminal voltage as the soft-start voltage, it is possible to realize the soft-start operation according to the relationship between the first capacitance and the second capacitance. That is, for example, when the electrostatic capacitance value of the second capacitor is relatively large, the soft start operation is performed using the terminal voltage of the second capacitor as the soft start voltage, thereby sufficiently corresponding to the second capacitor. A gradual rise in output voltage can be realized. On the other hand, even when the capacitance value of the second capacitor is very small, the soft-start operation is executed using the terminal voltage of the first capacitor as the soft-start voltage. An upper limit can be set.

After the soft start operation is completed, it is conceivable to perform a predetermined operation using the terminal voltage of the first or second capacitor. In this case, it is important which capacitor should be used to perform the predetermined operation. There is also According to the power supply device W1, the target capacitance is set according to the relationship between the first and second capacitances through the soft start operation, and the predetermined operation is performed using the capacitance having a relatively large capacitance value. becomes possible. As a result, it is possible to optimize the predetermined operation.

Examples of the predetermined operation include a soft-stop operation and a cool-down operation, and examples of the specific circuit include a soft-stop circuit responsible for the soft-stop operation and a cool-down circuit responsible for the cool-down operation. The operation is not limited to the soft stop operation and the cool down operation as long as the operation is performed by selectively using the first capacity or the second capacity. The target capacitance setting circuit is formed by the SS control circuit 130 and the holding circuits 154 and 155 in the above embodiments.

Specifically, for example, in the power supply W1, the predetermined operation is executed when the power supply W1 receives a stop instruction signal instructing the power supply to stop operating. and the specific circuit includes a soft stop circuit for executing the soft stop operation, and the soft stop circuit performs the soft stop operation during the soft stop operation. It is preferable to discharge the charge accumulated in the target capacitor with a constant discharge current, and use the terminal voltage of the target capacitor in the process of discharging as the soft stop voltage.

According to this, in a case where the capacitance value of the second capacitor is relatively small and the first capacitor is set as the target capacitor, the soft start operation and the soft stop operation are performed according to the first capacitor, In a case where the capacitance value of the second capacitor is relatively large and the second capacitor is set as the target capacitor, the soft start operation and the soft stop operation are performed according to the second capacitor. In other words, in the configuration in which the soft start operation is performed according to the setting state of the second capacitor, the soft stop operation can also be appropriate according to the setting state of the second capacitor.

More specifically, in the case where the capacitance value of the second capacitor is relatively small, and as a result the rising slope of the output voltage in the soft-start operation becomes relatively large, the falling slope of the output voltage in the soft-stop operation also increases. relatively large, the capacitance value of the second capacitor is relatively large, and as a result the rising slope of the output voltage in the soft-start operation becomes relatively small, the falling slope of the output voltage in the soft-stop operation also becomes relatively small.

In the above configuration, receiving the stop instruction signal corresponds to establishment of the predetermined condition.

Alternatively, for example, an abnormality detection circuit for detecting the presence or absence of a predetermined abnormality may be further provided in the power supply W1, and after the end of the soft start operation executed when starting up the power supply, the When the abnormality is detected, a cool-down operation is performed to keep the output transistor off, and then the power supply device is restarted with the soft-start operation again, and the predetermined operation is the cool-down operation. operation, wherein the specific circuit includes a cool-down circuit for performing the cool-down operation, the cool-down circuit comprising a first parallel switch (115) connected in parallel to the first capacitor, and the second It has a second parallel switch (125) connected in parallel to the capacitor, and in the cool-down operation, a unit operation is repeatedly executed a predetermined number of times, one or more times, and each unit operation is performed by the first parallel switch and the second parallel switch. Of the two parallel switches, the parallel switch connected in parallel to the target capacitor is turned on to discharge the charge accumulated in the target capacitor until the terminal voltage of the target capacitor becomes lower than a predetermined discharge completion voltage (SS_REF _L ). discharge operation (SS discharge operation in step S17), and through the discharge operation, the parallel switch connected in parallel to the target capacitor is turned off while the terminal voltage of the target capacitor is higher than a predetermined charge completion voltage (SS_REF _H ) and a charging operation (SS charging operation in step S18) of charging the target capacity with the charging constant current until the target capacity is reached.

According to this, in the case where the capacitance value of the second capacitor is relatively small and the first capacitor becomes the target capacitor and the time required for the soft start operation is relatively short, the capacitance of the first capacitor A cool-down operation is performed for a relatively short time based on the capacitance value, and conversely, the capacitance value of the second capacitor is relatively large, and the second capacitor becomes the target capacitance, which is the time required for the soft-start operation. is relatively long, the cool-down operation is performed for a relatively long time based on the capacitance value of the second capacitor. If the time required for the soft-start operation becomes longer, there is a high possibility that the temperature of the parts will rise due to an abnormality. According to the configuration, a cool-down operation is performed that allows heat to be dissipated for a necessary and sufficient time when the temperature rise of the parts due to an abnormality is performed, and damage to the components of the power supply device can be appropriately prevented.

In the above configuration, the detection of the abnormality after the end of the soft start operation executed when the power supply device is started corresponds to the establishment of the predetermined condition.

A power supply device W2 according to one aspect of the present invention includes an output transistor (1a) for generating an output voltage from an input voltage, a feedback voltage (Vfb) corresponding to the output voltage, and a predetermined reference voltage (Vref). a control circuit for controlling the output transistor based on the power supply, a soft start circuit for executing a soft start operation for gradually increasing the output voltage using a gradually increasing soft start voltage when the power supply device is started, and a predetermined and a cool-down circuit that performs a cool-down operation to keep the output transistor off when the abnormality is detected, wherein the soft-start circuit When the power supply device is started, the first capacitor (C _INT ) having a fixed capacitance value and the second capacitor (C _EXT ) having a variable capacitance value are individually charged with a constant charging current, The terminal voltage of the first capacitor (that is, the voltage across the first capacitor due to the accumulated charge in the first capacitor; SS_INT) and the terminal voltage of the second capacitor (that is, the voltage across the second capacitor due to the accumulated charge in the second capacitor) SS_EXT), the soft-start operation is performed using the lower terminal voltage as the soft-start voltage, and the cool-down operation is performed when the abnormality is detected after starting the power supply device. After that, the power supply device is restarted with the soft start operation again, and the cool-down circuit is connected in parallel to the first parallel switch (115) connected in parallel to the first capacitor and the second capacitor. a second parallel switch (125) configured to perform a unit operation in the cool-down operation a predetermined number of times, one or more times, each unit operation being performed by the first parallel switch and the second parallel switch By turning on the respective terminals, the accumulated charges of the first capacitor and the second capacitor are discharged until both the terminal voltage of the first capacitor and the terminal voltage of the second capacitor become lower than a predetermined discharge completion voltage (SS_REF _L ). (SS discharging operation in step S17a), and through the discharging operation, the terminal voltage of the first capacitor and the terminal voltage of the second capacitor while turning off the first parallel switch and the second parallel switch respectively. a charging operation (SS charging operation in step S18a) of charging each of the first capacitor and the second capacitor with the charging constant current until both of the terminal voltages become higher than a predetermined charge completion voltage (SS_REF _H ); ,

In the power supply W2, if the second capacitor has a relatively large capacitance value, the cool-down operation is performed for a relatively long time corresponding to the capacitance value of the second capacitor. Even if the capacitance values of the two capacitors are relatively small, the cool-down operation time is ensured for the time corresponding to the capacitance value of the first capacitor. Therefore, in any case, it is possible to secure at least the minimum heat radiation time for the parts that accompany temperature rise due to the abnormality, and to appropriately prevent damage to the components of the power supply device.

The embodiments of the present invention can be appropriately modified in various ways within the scope of the technical idea indicated in the scope of claims. The above embodiments are merely examples of the embodiments of the present invention, and the meanings of the terms of the present invention and each constituent element are not limited to those described in the above embodiments. The specific numerical values given in the above description are merely examples and can of course be changed to various numerical values.

100 switching power supply IC
AA Switching power supply Vin Input voltage Vout Output voltage Vsw Switching voltage Vfb Feedback voltage Vref Reference voltage Verr Error voltage Vrip Ripple voltage Vfb' Feedback voltage with ripple CMP Comparison result signal C _INT capacitor (built-in capacitor)
C _EXT capacitor (external capacitor)
1a, 1b transistor 3 main control circuit 6 SS circuit 8 error amplifier 11 main comparators 110, 120 slope voltage generation circuit 130 SS control circuit 140 SS selection circuit 150 SS setting circuit

Claims (15)

an output transistor for generating an output voltage from an input voltage;
a control circuit for controlling the output transistor based on a feedback voltage corresponding to the output voltage and a predetermined reference voltage;
a soft-start circuit that performs a soft-start operation of gradually increasing the output voltage using a gradually increasing soft-start voltage at startup , wherein:
The soft-start circuit separately charges a first capacitor having a fixed capacitance value and a second capacitor having a variable capacitance value with a constant charging current when the power supply device is started. executing the soft start operation using the lower terminal voltage of the terminal voltage of one capacitor and the terminal voltage of the second capacitor as the soft start voltage;
The power supply is
a specific circuit that executes a predetermined operation using either one of the terminal voltage of the first capacitor and the terminal voltage of the second capacitor when a predetermined condition is satisfied after the soft start operation is completed;
a target capacity setting circuit that sets a target capacity to a capacity corresponding to the lower terminal voltage in the soft start operation,
The specific circuit performs the predetermined operation using a terminal voltage of a capacitor set as the target capacitor, out of the first capacitor and the second capacitor.
, power supply. The predetermined operation includes a soft stop operation of gradually decreasing the output voltage using a gradually decreasing soft stop voltage, which is executed when receiving a stop instruction signal instructing to stop the operation of the power supply device,
The specific circuit includes a soft stop circuit that performs the soft stop operation,
In the soft stop operation, the soft stop circuit discharges the charge accumulated in the target capacitor by the soft start operation with a constant discharge current, and the terminal voltage of the target capacitor in the process of discharging is reduced. used as the soft stop voltage
The power supply of claim 1. The soft stop circuit discharges only the capacity set as the target capacity, out of the first capacity and the second capacity, at the constant discharge current in the soft stop operation.
3. The power supply of claim 2. In the soft stop operation, the soft stop circuit discharges the accumulated charges of both the first capacitor and the second capacitor individually with the discharge constant current. Among them, the terminal voltage of the target capacity in the process of discharging is used as the soft stop voltage regardless of the terminal voltage of the non-target capacity different from the capacity set as the target capacity.
3. The power supply of claim 2. The control circuit controls the output transistor based on the feedback voltage and the soft stop voltage when the soft stop operation is being performed, and the soft stop operation is performed after the soft start operation is completed. when not, controlling the output transistor based on the feedback voltage and the reference voltage
The power supply device according to any one of claims 2 to 4. Further comprising an abnormality detection circuit for detecting the presence or absence of a predetermined abnormality,
When the abnormality is detected after the end of the soft start operation executed when starting up the power supply device, a cool down operation is executed to keep the output transistor off, and then the soft start operation is performed again. The power supply is restarted with a start operation,
The predetermined action includes the cool-down action,
the specific circuit includes a cool-down circuit that performs the cool-down operation;
The cool-down circuit is
A first parallel switch connected in parallel to the first capacitor, and a second parallel switch connected in parallel to the second capacitor,
In the cool-down operation, the unit operation is repeatedly performed a predetermined number of times, which is one or more times;
In each unit operation, among the first parallel switch and the second parallel switch, by turning on the parallel switch connected in parallel to the target capacitor, the terminal voltage of the target capacitor becomes lower than a predetermined discharge completion voltage. until the terminal voltage of the target capacitor becomes higher than a predetermined charge completion voltage while turning off a parallel switch connected in parallel to the target capacitor through the discharging operation. and a charging operation of charging the target capacity with the charging constant current.
The power supply of claim 1. The cool-down circuit discharges and charges only the capacity set as the target capacity, out of the first capacity and the second capacity, in the discharging operation and the charging operation during the cool-down operation.
7. The power supply of claim 6. The cool-down circuit turns on both the first parallel switch and the second parallel switch in the discharge operation during the cool-down operation, but the target Regardless of the terminal voltage of a non-target capacitor that is different from the capacity set in the capacitor, the accumulated charge of the target capacitor is discharged until the terminal voltage of the target capacitor becomes lower than the discharge completion voltage.
7. The power supply of claim 6. The abnormality detection circuit detects the abnormality when the feedback voltage continues to be lower than a predetermined protection determination voltage for a predetermined time after the soft start operation executed when the power supply is started. detect there is
The power supply device according to any one of claims 6 to 8. The control circuit controls the output transistor based on the feedback voltage and the soft start voltage when the soft start operation is performed.
The power supply device according to any one of claims 1 to 9. The target capacity setting circuit sets the terminal voltage of the lower one of the terminal voltage of the first capacitor and the terminal voltage of the second capacitor to a predetermined soft-start completion judgment voltage in the process of charging with the charging constant current. and setting the target capacitance based on the comparison result of the terminal voltage of the first capacitance and the terminal voltage of the second capacitance when the lower terminal voltage becomes higher than the soft start completion determination voltage.
11. The power supply of claim 10. an output transistor for generating an output voltage from an input voltage;
a control circuit for controlling the output transistor based on a feedback voltage corresponding to the output voltage and a predetermined reference voltage;
a soft-start circuit for executing a soft-start operation of gradually increasing the output voltage using a gradually increasing soft-start voltage at startup ;
an abnormality detection circuit for detecting the presence or absence of a predetermined abnormality;
a cool-down circuit that performs a cool-down operation to keep the output transistor off when the abnormality is detected,
The soft-start circuit separately charges a first capacitor having a fixed capacitance value and a second capacitor having a variable capacitance value with a constant charging current when the power supply device is started. executing the soft start operation using the lower terminal voltage of the terminal voltage of one capacitor and the terminal voltage of the second capacitor as the soft start voltage;
When the abnormality is detected after starting the power supply device, the power supply device is restarted with the soft-start operation again after the cool-down operation,
The cool-down circuit is
A first parallel switch connected in parallel to the first capacitor, and a second parallel switch connected in parallel to the second capacitor,
In the cool-down operation, the unit operation is repeatedly performed a predetermined number of times, which is one or more times;
In each unit operation, both the terminal voltage of the first capacitor and the terminal voltage of the second capacitor become lower than a predetermined discharge completion voltage by turning on the first parallel switch and the second parallel switch, respectively. a discharge operation for discharging the accumulated charges in the first capacitor and the second capacitor up to the terminal voltage of the first capacitor and the terminal voltage of the first capacitor and a charging operation of charging each of the first capacitor and the second capacitor with the charging constant current until both terminal voltages of the second capacitor become higher than a predetermined charging completion voltage.
, power supply. The abnormality detection circuit detects the abnormality when the feedback voltage continues to be lower than a predetermined protection determination voltage for a predetermined time after the soft start operation executed when the power supply is started. detect there is
13. The power supply of claim 12. The control circuit controls the output transistor based on the feedback voltage and the soft start voltage when the soft start operation is performed.
14. A power supply device according to claim 12 or 13. The power supply device is configured using a power supply IC formed by enclosing a semiconductor integrated circuit in a housing,
The power supply IC has an external terminal to which an external capacitor can be connected,
the first capacitor is formed by a capacitor built into the power supply IC,
When the external capacitor is connected to the external terminal, the external capacitor forms the second capacitance, and the output voltage in the soft start operation is adjusted through adjustment of the capacitance value of the external capacitor. The slope of the rise of is adjustable
The power supply device according to any one of claims 1 to 14.

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