JP5275608B2 - 半導体基板の作製方法 - Google Patents

半導体基板の作製方法 Download PDF

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Publication number
JP5275608B2
JP5275608B2 JP2007272297A JP2007272297A JP5275608B2 JP 5275608 B2 JP5275608 B2 JP 5275608B2 JP 2007272297 A JP2007272297 A JP 2007272297A JP 2007272297 A JP2007272297 A JP 2007272297A JP 5275608 B2 JP5275608 B2 JP 5275608B2
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Japan
Prior art keywords
layer
substrate
semiconductor
circuit
semiconductor substrate
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Expired - Fee Related
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JP2007272297A
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English (en)
Japanese (ja)
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JP2009099900A5 (https=
JP2009099900A (ja
Inventor
哲弥 掛端
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to JP2007272297A priority Critical patent/JP5275608B2/ja
Priority to US12/249,437 priority patent/US7994022B2/en
Publication of JP2009099900A publication Critical patent/JP2009099900A/ja
Publication of JP2009099900A5 publication Critical patent/JP2009099900A5/ja
Priority to US13/168,155 priority patent/US8227866B2/en
Application granted granted Critical
Publication of JP5275608B2 publication Critical patent/JP5275608B2/ja
Expired - Fee Related legal-status Critical Current
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0214—Manufacture or treatment of multiple TFTs using temporary substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon

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  • Thin Film Transistor (AREA)
JP2007272297A 2007-10-19 2007-10-19 半導体基板の作製方法 Expired - Fee Related JP5275608B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2007272297A JP5275608B2 (ja) 2007-10-19 2007-10-19 半導体基板の作製方法
US12/249,437 US7994022B2 (en) 2007-10-19 2008-10-10 Semiconductor substrate and semiconductor device and manufacturing method of the same
US13/168,155 US8227866B2 (en) 2007-10-19 2011-06-24 Semiconductor substrate and semiconductor device and manufacturing method of the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007272297A JP5275608B2 (ja) 2007-10-19 2007-10-19 半導体基板の作製方法

Publications (3)

Publication Number Publication Date
JP2009099900A JP2009099900A (ja) 2009-05-07
JP2009099900A5 JP2009099900A5 (https=) 2010-09-09
JP5275608B2 true JP5275608B2 (ja) 2013-08-28

Family

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Family Applications (1)

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JP2007272297A Expired - Fee Related JP5275608B2 (ja) 2007-10-19 2007-10-19 半導体基板の作製方法

Country Status (2)

Country Link
US (2) US7994022B2 (https=)
JP (1) JP5275608B2 (https=)

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US20090186237A1 (en) * 2008-01-18 2009-07-23 Rolls-Royce Corp. CMAS-Resistant Thermal Barrier Coatings
US7820527B2 (en) * 2008-02-20 2010-10-26 Varian Semiconductor Equipment Associates, Inc. Cleave initiation using varying ion implant dose
KR100989125B1 (ko) * 2008-07-16 2010-10-20 삼성모바일디스플레이주식회사 원장기판 절단 장치 및 이에 의하여 절단된 유기발광표시장치
WO2010039699A2 (en) * 2008-09-30 2010-04-08 Rolls-Royce Corporation Coating including a rare earth silicate-based layer including a second phase
US8470460B2 (en) * 2008-11-25 2013-06-25 Rolls-Royce Corporation Multilayer thermal barrier coatings
CN101762922B (zh) * 2008-12-24 2012-05-30 京东方科技集团股份有限公司 触摸式电子纸及其制造方法
US20110033630A1 (en) * 2009-08-05 2011-02-10 Rolls-Royce Corporation Techniques for depositing coating on ceramic substrate
JP5620577B2 (ja) 2010-07-23 2014-11-05 ロールス−ロイス コーポレイション Ｃｍａｓ耐性遮熱コーティング層を含む遮熱コーティング
US20140261080A1 (en) 2010-08-27 2014-09-18 Rolls-Royce Corporation Rare earth silicate environmental barrier coatings
JP5729097B2 (ja) * 2011-04-07 2015-06-03 Jsr株式会社 基材の処理方法、仮固定材および電子部品
KR20120129592A (ko) 2011-05-20 2012-11-28 삼성디스플레이 주식회사 평판 표시 장치용 백플레인, 이를 포함하는 평판 표시 장치, 및 그 제조 방법
FR2985370A1 (fr) 2011-12-29 2013-07-05 Commissariat Energie Atomique Procede de fabrication d'une structure multicouche sur un support
CN102701569B (zh) * 2012-01-12 2015-01-07 上海华力微电子有限公司 改善高密度等离子体化学气相淀积的磷硅玻璃形貌的方法
US9390942B2 (en) * 2012-11-30 2016-07-12 Peregrine Semiconductor Corporation Method, system, and apparatus for preparing substrates and bonding semiconductor layers to substrates
WO2014174902A1 (ja) * 2013-04-25 2014-10-30 シャープ株式会社 半導体装置および半導体装置の製造方法
KR20140140416A (ko) * 2013-05-29 2014-12-09 삼성디스플레이 주식회사 유기발광 디스플레이 장치 제조방법 및 이에 따라 제조된 유기발광 디스플레이 장치
CN103345390A (zh) * 2013-06-17 2013-10-09 北京金山安全软件有限公司 用于移动终端的图片输出方法、装置和移动终端
US10329205B2 (en) 2014-11-24 2019-06-25 Rolls-Royce Corporation Bond layer for silicon-containing substrates
EP3234991B1 (en) * 2014-12-18 2021-07-07 Entegris, Inc. Wafer container with shock condition protection
EP3427293B1 (en) * 2016-03-07 2021-05-05 Globalwafers Co., Ltd. Semiconductor on insulator structure comprising a low temperature flowable oxide layer and method of manufacture thereof
US20190017177A1 (en) 2017-07-17 2019-01-17 Rolls-Royce Corporation Thermal barrier coatings for components in high-temperature mechanical systems
US11655543B2 (en) 2017-08-08 2023-05-23 Rolls-Royce Corporation CMAS-resistant barrier coatings
US10851656B2 (en) 2017-09-27 2020-12-01 Rolls-Royce Corporation Multilayer environmental barrier coating
US11251406B2 (en) 2019-03-07 2022-02-15 Vitro Flat Glass Llc Borosilicate light extraction region
CN110299427A (zh) * 2019-05-06 2019-10-01 上海空间电源研究所 一种空间用刚性太阳电池弯曲度调控方法
CN119008364B (zh) * 2024-07-05 2025-09-23 上海集成电路材料研究院有限公司 一种电子源结构及制作方法

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JP3237888B2 (ja) * 1992-01-31 2001-12-10 キヤノン株式会社 半導体基体及びその作製方法
JPH08255762A (ja) * 1995-03-17 1996-10-01 Nec Corp 半導体デバイスの製造方法
US6599574B1 (en) * 1996-04-04 2003-07-29 Applied Materials Inc. Method and apparatus for forming a dielectric film using helium as a carrier gas
US7470598B2 (en) * 2004-06-21 2008-12-30 Sang-Yun Lee Semiconductor layer structure and method of making the same
JPH11163363A (ja) 1997-11-22 1999-06-18 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法
US6433841B1 (en) 1997-12-19 2002-08-13 Seiko Epson Corporation Electro-optical apparatus having faces holding electro-optical material in between flattened by using concave recess, manufacturing method thereof, and electronic device using same
JP2000077287A (ja) * 1998-08-26 2000-03-14 Nissin Electric Co Ltd 結晶薄膜基板の製造方法
JP2000124092A (ja) 1998-10-16 2000-04-28 Shin Etsu Handotai Co Ltd 水素イオン注入剥離法によってｓｏｉウエーハを製造する方法およびこの方法で製造されたｓｏｉウエーハ
US6850292B1 (en) 1998-12-28 2005-02-01 Seiko Epson Corporation Electric-optic device, method of fabricating the same, and electronic apparatus
JP3636641B2 (ja) 1999-08-20 2005-04-06 セイコーエプソン株式会社 電気光学装置
JP3864678B2 (ja) 2000-07-28 2007-01-10 セイコーエプソン株式会社 電気光学装置の製造方法及び電気光学装置
US7018909B2 (en) * 2003-02-28 2006-03-28 S.O.I.Tec Silicon On Insulator Technologies S.A. Forming structures that include a relaxed or pseudo-relaxed layer on a substrate
JP4319078B2 (ja) * 2004-03-26 2009-08-26 シャープ株式会社 半導体装置の製造方法
EP1993128A3 (en) * 2007-05-17 2010-03-24 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing soi substrate
US9059247B2 (en) * 2007-05-18 2015-06-16 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate and method for manufacturing semiconductor device
US7781306B2 (en) * 2007-06-20 2010-08-24 Semiconductor Energy Laboratory Co., Ltd. Semiconductor substrate and method for manufacturing the same

Also Published As

Publication number Publication date
US20110248377A1 (en) 2011-10-13
US8227866B2 (en) 2012-07-24
US20090102008A1 (en) 2009-04-23
US7994022B2 (en) 2011-08-09
JP2009099900A (ja) 2009-05-07

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